+4 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c

reviewed

··· 553 553 entry = (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *) 554 554 ((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record)); 555 555 } 556 556 - for (i = 0; i < states->numEntries; i++) { 557 557 - if (i >= AMD_MAX_VCE_LEVELS) 558 558 - break; 556 556 + adev->pm.dpm.num_of_vce_states = 557 557 + states->numEntries > AMD_MAX_VCE_LEVELS ? 558 558 + AMD_MAX_VCE_LEVELS : states->numEntries; 559 559 + for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 559 560 vce_clk = (VCEClockInfo *) 560 561 ((u8 *)&array->entries[0] + 561 562 (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo)));

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

reviewed

··· 387 387 /* default uvd power state */ 388 388 struct amdgpu_ps *uvd_ps; 389 389 /* vce requirements */ 390 390 + u32 num_of_vce_states; 390 391 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 391 392 enum amd_vce_level vce_level; 392 393 enum amd_pm_state_type state;

+1 -1

drivers/gpu/drm/amd/amdgpu/ci_dpm.c

reviewed

··· 5689 5689 adev->pm.dpm.num_ps = state_array->ucNumEntries; 5690 5690 5691 5691 /* fill in the vce power states */ 5692 5692 - for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) { 5692 5692 + for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 5693 5693 u32 sclk, mclk; 5694 5694 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 5695 5695 clock_info = (union pplib_clock_info *)

+1 -1

drivers/gpu/drm/amd/amdgpu/kv_dpm.c

reviewed

··· 2796 2796 adev->pm.dpm.num_ps = state_array->ucNumEntries; 2797 2797 2798 2798 /* fill in the vce power states */ 2799 2799 - for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) { 2799 2799 + for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 2800 2800 u32 sclk; 2801 2801 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 2802 2802 clock_info = (union pplib_clock_info *)

+1 -1

drivers/gpu/drm/amd/amdgpu/si_dpm.c

reviewed

··· 7320 7320 adev->pm.dpm.num_ps = state_array->ucNumEntries; 7321 7321 7322 7322 /* fill in the vce power states */ 7323 7323 - for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) { 7323 7323 + for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 7324 7324 u32 sclk, mclk; 7325 7325 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 7326 7326 clock_info = (union pplib_clock_info *)