Merge tag 'pwm/for-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

+2 -2

Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt

··· 6 6 - clocks: This clock defines the base clock frequency of the PWM hardware 7 7 system, the period and the duty_cycle of the PWM signal is a multiple of 8 8 the base period. 9 - - #pwm-cells: Should be 2. See pwm.txt in this directory for a description of 9 + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of 10 10 the cells format. 11 11 12 12 Examples: ··· 15 15 compatible = "brcm,bcm2835-pwm"; 16 16 reg = <0x2020c000 0x28>; 17 17 clocks = <&clk_pwm>; 18 - #pwm-cells = <2>; 18 + #pwm-cells = <3>; 19 19 }; 20 20 21 21 clocks {

+5 -1

Documentation/devicetree/bindings/pwm/pwm-mediatek.txt

··· 2 2 3 3 Required properties: 4 4 - compatible: should be "mediatek,<name>-pwm": 5 + - "mediatek,mt2712-pwm": found on mt2712 SoC. 6 + - "mediatek,mt7622-pwm": found on mt7622 SoC. 5 7 - "mediatek,mt7623-pwm": found on mt7623 SoC. 6 8 - reg: physical base address and length of the controller's registers. 7 9 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of ··· 12 10 - clock-names: must contain the following: 13 11 - "top": the top clock generator 14 12 - "main": clock used by the PWM core 15 - - "pwm1-5": the five per PWM clocks 13 + - "pwm1-8": the eight per PWM clocks for mt2712 14 + - "pwm1-6": the six per PWM clocks for mt7622 15 + - "pwm1-5": the five per PWM clocks for mt7623 16 16 - pinctrl-names: Must contain a "default" entry. 17 17 - pinctrl-0: One property must exist for each entry in pinctrl-names. 18 18 See pinctrl/pinctrl-bindings.txt for details of the property values.

+9 -2

Documentation/devicetree/bindings/pwm/pwm-rockchip.txt

··· 3 3 Required properties: 4 4 - compatible: should be "rockchip,<name>-pwm" 5 5 "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs 6 - "rockchip,rk3288-pwm": found on RK3288 SoC 6 + "rockchip,rk3288-pwm": found on RK3288 SOC 7 + "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC 7 8 "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC 8 9 - reg: physical base address and length of the controller's registers 9 - - clocks: phandle and clock specifier of the PWM reference clock 10 + - clocks: See ../clock/clock-bindings.txt 11 + - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399): 12 + - There is one clock that's used both to derive the functional clock 13 + for the device and as the bus clock. 14 + - For newer hardware (rk3328 and future socs): specified by name 15 + - "pwm": This is used to derive the functional clock. 16 + - "pclk": This is the APB bus clock. 10 17 - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory 11 18 for a description of the cell format. 12 19

+1

Documentation/devicetree/bindings/pwm/pwm-tiecap.txt

··· 6 6 for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; 7 7 for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; 8 8 for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap"; 9 + for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap"; 9 10 - #pwm-cells: should be 3. See pwm.txt in this directory for a description of 10 11 the cells format. The PWM channel index ranges from 0 to 4. The only third 11 12 cell flag supported by this binding is PWM_POLARITY_INVERTED.

+22

Documentation/devicetree/bindings/pwm/pwm-zx.txt

··· 1 + ZTE ZX PWM controller 2 + 3 + Required properties: 4 + - compatible: Should be "zte,zx296718-pwm". 5 + - reg: Physical base address and length of the controller's registers. 6 + - clocks : The phandle and specifier referencing the controller's clocks. 7 + - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The 8 + PCLK is for register access, while WCLK is the reference clock for 9 + calculating period and duty cycles. 10 + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of 11 + the cells format. 12 + 13 + Example: 14 + 15 + pwm: pwm@1439000 { 16 + compatible = "zte,zx296718-pwm"; 17 + reg = <0x1439000 0x1000>; 18 + clocks = <&lsp1crm LSP1_PWM_PCLK>, 19 + <&lsp1crm LSP1_PWM_WCLK>; 20 + clock-names = "pclk", "wclk"; 21 + #pwm-cells = <3>; 22 + };

-1

Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt

··· 6 6 - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller. 7 7 - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller. 8 8 - "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller. 9 - - "renesas,tpu-sh7372": for SH7372 (SH-Mobile AP4) compatible PWM controller. 10 9 - "renesas,tpu": for generic R-Car TPU PWM controller. 11 10 12 11 - reg: Base address and length of each memory resource used by the PWM

+11 -2

drivers/pwm/Kconfig

··· 300 300 Generic PWM framework driver for Mediatek ARM SoC. 301 301 302 302 To compile this driver as a module, choose M here: the module 303 - will be called pwm-mxs. 303 + will be called pwm-mediatek. 304 304 305 305 config PWM_MXS 306 306 tristate "Freescale MXS PWM support" ··· 456 456 457 457 config PWM_TIECAP 458 458 tristate "ECAP PWM support" 459 - depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX 459 + depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX || ARCH_KEYSTONE 460 460 help 461 461 PWM driver support for the ECAP APWM controller found on AM33XX 462 462 TI SOC ··· 509 509 510 510 To compile this driver as a module, choose M here: the module 511 511 will be called pwm-vt8500. 512 + 513 + config PWM_ZX 514 + tristate "ZTE ZX PWM support" 515 + depends on ARCH_ZX 516 + help 517 + Generic PWM framework driver for ZTE ZX family SoCs. 518 + 519 + To compile this driver as a module, choose M here: the module 520 + will be called pwm-zx. 512 521 513 522 endif

+1

drivers/pwm/Makefile

··· 50 50 obj-$(CONFIG_PWM_TWL) += pwm-twl.o 51 51 obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o 52 52 obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o 53 + obj-$(CONFIG_PWM_ZX) += pwm-zx.o

+2

drivers/pwm/pwm-bcm2835.c

··· 167 167 pc->chip.dev = &pdev->dev; 168 168 pc->chip.ops = &bcm2835_pwm_ops; 169 169 pc->chip.npwm = 2; 170 + pc->chip.of_xlate = of_pwm_xlate_with_flags; 171 + pc->chip.of_pwm_n_cells = 3; 170 172 171 173 platform_set_drvdata(pdev, pc); 172 174

+1 -1

drivers/pwm/pwm-hibvt.c

··· 208 208 if (ret < 0) 209 209 return ret; 210 210 211 - pwm_chip->rstc = devm_reset_control_get(&pdev->dev, NULL); 211 + pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 212 212 if (IS_ERR(pwm_chip->rstc)) { 213 213 clk_disable_unprepare(pwm_chip->clk); 214 214 return PTR_ERR(pwm_chip->rstc);

+54 -24

drivers/pwm/pwm-mediatek.c

··· 2 2 * Mediatek Pulse Width Modulator driver 3 3 * 4 4 * Copyright (C) 2015 John Crispin <blogic@openwrt.org> 5 + * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> 5 6 * 6 7 * This file is licensed under the terms of the GNU General Public 7 8 * License version 2. This program is licensed "as is" without any ··· 29 28 #define PWMWAVENUM 0x28 30 29 #define PWMDWIDTH 0x2c 31 30 #define PWMTHRES 0x30 31 + 32 + #define PWM_CLK_DIV_MAX 7 32 33 33 34 enum { 34 35 MTK_CLK_MAIN = 0, ··· 64 61 return container_of(chip, struct mtk_pwm_chip, chip); 65 62 } 66 63 64 + static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm) 65 + { 66 + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); 67 + int ret; 68 + 69 + ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]); 70 + if (ret < 0) 71 + return ret; 72 + 73 + ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]); 74 + if (ret < 0) 75 + goto disable_clk_top; 76 + 77 + ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); 78 + if (ret < 0) 79 + goto disable_clk_main; 80 + 81 + return 0; 82 + 83 + disable_clk_main: 84 + clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]); 85 + disable_clk_top: 86 + clk_disable_unprepare(pc->clks[MTK_CLK_TOP]); 87 + 88 + return ret; 89 + } 90 + 91 + static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) 92 + { 93 + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); 94 + 95 + clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); 96 + clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]); 97 + clk_disable_unprepare(pc->clks[MTK_CLK_TOP]); 98 + } 99 + 67 100 static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, 68 101 unsigned int offset) 69 102 { ··· 119 80 struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); 120 81 struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]; 121 82 u32 resolution, clkdiv = 0; 83 + int ret; 84 + 85 + ret = mtk_pwm_clk_enable(chip, pwm); 86 + if (ret < 0) 87 + return ret; 122 88 123 89 resolution = NSEC_PER_SEC / clk_get_rate(clk); 124 90 ··· 132 88 clkdiv++; 133 89 } 134 90 135 - if (clkdiv > 7) 91 + if (clkdiv > PWM_CLK_DIV_MAX) { 92 + mtk_pwm_clk_disable(chip, pwm); 93 + dev_err(chip->dev, "period %d not supported\n", period_ns); 136 94 return -EINVAL; 95 + } 137 96 138 - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); 97 + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); 139 98 mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); 140 99 mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution); 100 + 101 + mtk_pwm_clk_disable(chip, pwm); 141 102 142 103 return 0; 143 104 } ··· 153 104 u32 value; 154 105 int ret; 155 106 156 - ret = clk_prepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); 107 + ret = mtk_pwm_clk_enable(chip, pwm); 157 108 if (ret < 0) 158 109 return ret; 159 110 ··· 173 124 value &= ~BIT(pwm->hwpwm); 174 125 writel(value, pc->regs); 175 126 176 - clk_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); 127 + mtk_pwm_clk_disable(chip, pwm); 177 128 } 178 129 179 130 static const struct pwm_ops mtk_pwm_ops = { ··· 205 156 return PTR_ERR(pc->clks[i]); 206 157 } 207 158 208 - ret = clk_prepare(pc->clks[MTK_CLK_TOP]); 209 - if (ret < 0) 210 - return ret; 211 - 212 - ret = clk_prepare(pc->clks[MTK_CLK_MAIN]); 213 - if (ret < 0) 214 - goto disable_clk_top; 215 - 216 159 platform_set_drvdata(pdev, pc); 217 160 218 161 pc->chip.dev = &pdev->dev; ··· 215 174 ret = pwmchip_add(&pc->chip); 216 175 if (ret < 0) { 217 176 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 218 - goto disable_clk_main; 177 + return ret; 219 178 } 220 179 221 180 return 0; 222 - 223 - disable_clk_main: 224 - clk_unprepare(pc->clks[MTK_CLK_MAIN]); 225 - disable_clk_top: 226 - clk_unprepare(pc->clks[MTK_CLK_TOP]); 227 - 228 - return ret; 229 181 } 230 182 231 183 static int mtk_pwm_remove(struct platform_device *pdev) 232 184 { 233 185 struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); 234 - unsigned int i; 235 - 236 - for (i = 0; i < pc->chip.npwm; i++) 237 - pwm_disable(&pc->chip.pwms[i]); 238 186 239 187 return pwmchip_remove(&pc->chip); 240 188 }

+1 -1

drivers/pwm/pwm-meson.c

··· 441 441 for (i = 0; i < meson->chip.npwm; i++) { 442 442 struct meson_pwm_channel *channel = &channels[i]; 443 443 444 - snprintf(name, sizeof(name), "%s#mux%u", np->full_name, i); 444 + snprintf(name, sizeof(name), "%pOF#mux%u", np, i); 445 445 446 446 init.name = name; 447 447 init.ops = &clk_mux_ops;

+7 -7

drivers/pwm/pwm-pca9685.c

··· 241 241 } 242 242 #endif 243 243 244 - static void pca9685_set_sleep_mode(struct pca9685 *pca, int sleep) 244 + static void pca9685_set_sleep_mode(struct pca9685 *pca, bool enable) 245 245 { 246 246 regmap_update_bits(pca->regmap, PCA9685_MODE1, 247 - MODE1_SLEEP, sleep ? MODE1_SLEEP : 0); 248 - if (!sleep) { 247 + MODE1_SLEEP, enable ? MODE1_SLEEP : 0); 248 + if (!enable) { 249 249 /* Wait 500us for the oscillator to be back up */ 250 250 udelay(500); 251 251 } ··· 272 272 * state is guaranteed active here. 273 273 */ 274 274 /* Put chip into sleep mode */ 275 - pca9685_set_sleep_mode(pca, 1); 275 + pca9685_set_sleep_mode(pca, true); 276 276 277 277 /* Change the chip-wide output frequency */ 278 278 regmap_write(pca->regmap, PCA9685_PRESCALE, prescale); 279 279 280 280 /* Wake the chip up */ 281 - pca9685_set_sleep_mode(pca, 0); 281 + pca9685_set_sleep_mode(pca, false); 282 282 283 283 pca->period_ns = period_ns; 284 284 } else { ··· 534 534 struct i2c_client *client = to_i2c_client(dev); 535 535 struct pca9685 *pca = i2c_get_clientdata(client); 536 536 537 - pca9685_set_sleep_mode(pca, 1); 537 + pca9685_set_sleep_mode(pca, true); 538 538 return 0; 539 539 } 540 540 ··· 543 543 struct i2c_client *client = to_i2c_client(dev); 544 544 struct pca9685 *pca = i2c_get_clientdata(client); 545 545 546 - pca9685_set_sleep_mode(pca, 0); 546 + pca9685_set_sleep_mode(pca, false); 547 547 return 0; 548 548 } 549 549 #endif

-1

drivers/pwm/pwm-renesas-tpu.c

··· 455 455 { .compatible = "renesas,tpu-r8a73a4", }, 456 456 { .compatible = "renesas,tpu-r8a7740", }, 457 457 { .compatible = "renesas,tpu-r8a7790", }, 458 - { .compatible = "renesas,tpu-sh7372", }, 459 458 { .compatible = "renesas,tpu", }, 460 459 { }, 461 460 };

+147 -134

drivers/pwm/pwm-rockchip.c

··· 27 27 #define PWM_DUTY_NEGATIVE (0 << 3) 28 28 #define PWM_INACTIVE_NEGATIVE (0 << 4) 29 29 #define PWM_INACTIVE_POSITIVE (1 << 4) 30 + #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE) 30 31 #define PWM_OUTPUT_LEFT (0 << 5) 32 + #define PWM_LOCK_EN (1 << 6) 31 33 #define PWM_LP_DISABLE (0 << 8) 32 34 33 35 struct rockchip_pwm_chip { 34 36 struct pwm_chip chip; 35 37 struct clk *clk; 38 + struct clk *pclk; 36 39 const struct rockchip_pwm_data *data; 37 40 void __iomem *base; 38 41 }; ··· 51 48 struct rockchip_pwm_regs regs; 52 49 unsigned int prescaler; 53 50 bool supports_polarity; 54 - const struct pwm_ops *ops; 55 - 56 - void (*set_enable)(struct pwm_chip *chip, 57 - struct pwm_device *pwm, bool enable, 58 - enum pwm_polarity polarity); 59 - void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, 60 - struct pwm_state *state); 51 + bool supports_lock; 52 + u32 enable_conf; 61 53 }; 62 54 63 55 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) ··· 60 62 return container_of(c, struct rockchip_pwm_chip, chip); 61 63 } 62 64 63 - static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, 64 - struct pwm_device *pwm, bool enable, 65 - enum pwm_polarity polarity) 66 - { 67 - struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 68 - u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; 69 - u32 val; 70 - 71 - val = readl_relaxed(pc->base + pc->data->regs.ctrl); 72 - 73 - if (enable) 74 - val |= enable_conf; 75 - else 76 - val &= ~enable_conf; 77 - 78 - writel_relaxed(val, pc->base + pc->data->regs.ctrl); 79 - } 80 - 81 - static void rockchip_pwm_get_state_v1(struct pwm_chip *chip, 82 - struct pwm_device *pwm, 83 - struct pwm_state *state) 84 - { 85 - struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 86 - u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; 87 - u32 val; 88 - 89 - val = readl_relaxed(pc->base + pc->data->regs.ctrl); 90 - if ((val & enable_conf) == enable_conf) 91 - state->enabled = true; 92 - } 93 - 94 - static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, 95 - struct pwm_device *pwm, bool enable, 96 - enum pwm_polarity polarity) 97 - { 98 - struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 99 - u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 100 - PWM_CONTINUOUS; 101 - u32 val; 102 - 103 - if (polarity == PWM_POLARITY_INVERSED) 104 - enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; 105 - else 106 - enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; 107 - 108 - val = readl_relaxed(pc->base + pc->data->regs.ctrl); 109 - 110 - if (enable) 111 - val |= enable_conf; 112 - else 113 - val &= ~enable_conf; 114 - 115 - writel_relaxed(val, pc->base + pc->data->regs.ctrl); 116 - } 117 - 118 - static void rockchip_pwm_get_state_v2(struct pwm_chip *chip, 119 - struct pwm_device *pwm, 120 - struct pwm_state *state) 121 - { 122 - struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 123 - u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 124 - PWM_CONTINUOUS; 125 - u32 val; 126 - 127 - val = readl_relaxed(pc->base + pc->data->regs.ctrl); 128 - if ((val & enable_conf) != enable_conf) 129 - return; 130 - 131 - state->enabled = true; 132 - 133 - if (!(val & PWM_DUTY_POSITIVE)) 134 - state->polarity = PWM_POLARITY_INVERSED; 135 - } 136 - 137 65 static void rockchip_pwm_get_state(struct pwm_chip *chip, 138 66 struct pwm_device *pwm, 139 67 struct pwm_state *state) 140 68 { 141 69 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 70 + u32 enable_conf = pc->data->enable_conf; 142 71 unsigned long clk_rate; 143 72 u64 tmp; 73 + u32 val; 144 74 int ret; 145 75 146 - ret = clk_enable(pc->clk); 76 + ret = clk_enable(pc->pclk); 147 77 if (ret) 148 78 return; 149 79 ··· 83 157 84 158 tmp = readl_relaxed(pc->base + pc->data->regs.duty); 85 159 tmp *= pc->data->prescaler * NSEC_PER_SEC; 86 - state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 160 + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 87 161 88 - pc->data->get_state(chip, pwm, state); 162 + val = readl_relaxed(pc->base + pc->data->regs.ctrl); 163 + if (pc->data->supports_polarity) 164 + state->enabled = ((val & enable_conf) != enable_conf) ? 165 + false : true; 166 + else 167 + state->enabled = ((val & enable_conf) == enable_conf) ? 168 + true : false; 89 169 90 - clk_disable(pc->clk); 170 + if (pc->data->supports_polarity) { 171 + if (!(val & PWM_DUTY_POSITIVE)) 172 + state->polarity = PWM_POLARITY_INVERSED; 173 + } 174 + 175 + clk_disable(pc->pclk); 91 176 } 92 177 93 - static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 94 - int duty_ns, int period_ns) 178 + static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 179 + struct pwm_state *state) 95 180 { 96 181 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 97 182 unsigned long period, duty; 98 183 u64 clk_rate, div; 184 + u32 ctrl; 99 185 100 186 clk_rate = clk_get_rate(pc->clk); 101 187 ··· 116 178 * bits, every possible input period can be obtained using the 117 179 * default prescaler value for all practical clock rate values. 118 180 */ 119 - div = clk_rate * period_ns; 181 + div = clk_rate * state->period; 120 182 period = DIV_ROUND_CLOSEST_ULL(div, 121 183 pc->data->prescaler * NSEC_PER_SEC); 122 184 123 - div = clk_rate * duty_ns; 185 + div = clk_rate * state->duty_cycle; 124 186 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); 187 + 188 + /* 189 + * Lock the period and duty of previous configuration, then 190 + * change the duty and period, that would not be effective. 191 + */ 192 + ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); 193 + if (pc->data->supports_lock) { 194 + ctrl |= PWM_LOCK_EN; 195 + writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl); 196 + } 125 197 126 198 writel(period, pc->base + pc->data->regs.period); 127 199 writel(duty, pc->base + pc->data->regs.duty); 128 200 129 - return 0; 201 + if (pc->data->supports_polarity) { 202 + ctrl &= ~PWM_POLARITY_MASK; 203 + if (state->polarity == PWM_POLARITY_INVERSED) 204 + ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; 205 + else 206 + ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; 207 + } 208 + 209 + /* 210 + * Unlock and set polarity at the same time, 211 + * the configuration of duty, period and polarity 212 + * would be effective together at next period. 213 + */ 214 + if (pc->data->supports_lock) 215 + ctrl &= ~PWM_LOCK_EN; 216 + 217 + writel(ctrl, pc->base + pc->data->regs.ctrl); 130 218 } 131 219 132 220 static int rockchip_pwm_enable(struct pwm_chip *chip, 133 - struct pwm_device *pwm, 134 - bool enable, 135 - enum pwm_polarity polarity) 221 + struct pwm_device *pwm, 222 + bool enable) 136 223 { 137 224 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 225 + u32 enable_conf = pc->data->enable_conf; 138 226 int ret; 227 + u32 val; 139 228 140 229 if (enable) { 141 230 ret = clk_enable(pc->clk); ··· 170 205 return ret; 171 206 } 172 207 173 - pc->data->set_enable(chip, pwm, enable, polarity); 208 + val = readl_relaxed(pc->base + pc->data->regs.ctrl); 209 + 210 + if (enable) 211 + val |= enable_conf; 212 + else 213 + val &= ~enable_conf; 214 + 215 + writel_relaxed(val, pc->base + pc->data->regs.ctrl); 174 216 175 217 if (!enable) 176 218 clk_disable(pc->clk); ··· 191 219 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 192 220 struct pwm_state curstate; 193 221 bool enabled; 194 - int ret; 222 + int ret = 0; 223 + 224 + ret = clk_enable(pc->pclk); 225 + if (ret) 226 + return ret; 195 227 196 228 pwm_get_state(pwm, &curstate); 197 229 enabled = curstate.enabled; 198 230 199 - ret = clk_enable(pc->clk); 200 - if (ret) 201 - return ret; 202 - 203 - if (state->polarity != curstate.polarity && enabled) { 204 - ret = rockchip_pwm_enable(chip, pwm, false, state->polarity); 231 + if (state->polarity != curstate.polarity && enabled && 232 + !pc->data->supports_lock) { 233 + ret = rockchip_pwm_enable(chip, pwm, false); 205 234 if (ret) 206 235 goto out; 207 236 enabled = false; 208 237 } 209 238 210 - ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period); 211 - if (ret) { 212 - if (enabled != curstate.enabled) 213 - rockchip_pwm_enable(chip, pwm, !enabled, 214 - state->polarity); 215 - goto out; 216 - } 217 - 239 + rockchip_pwm_config(chip, pwm, state); 218 240 if (state->enabled != enabled) { 219 - ret = rockchip_pwm_enable(chip, pwm, state->enabled, 220 - state->polarity); 241 + ret = rockchip_pwm_enable(chip, pwm, state->enabled); 221 242 if (ret) 222 243 goto out; 223 244 } ··· 222 257 rockchip_pwm_get_state(chip, pwm, state); 223 258 224 259 out: 225 - clk_disable(pc->clk); 260 + clk_disable(pc->pclk); 226 261 227 262 return ret; 228 263 } 229 264 230 - static const struct pwm_ops rockchip_pwm_ops_v1 = { 231 - .get_state = rockchip_pwm_get_state, 232 - .apply = rockchip_pwm_apply, 233 - .owner = THIS_MODULE, 234 - }; 235 - 236 - static const struct pwm_ops rockchip_pwm_ops_v2 = { 265 + static const struct pwm_ops rockchip_pwm_ops = { 237 266 .get_state = rockchip_pwm_get_state, 238 267 .apply = rockchip_pwm_apply, 239 268 .owner = THIS_MODULE, ··· 241 282 .ctrl = 0x0c, 242 283 }, 243 284 .prescaler = 2, 244 - .ops = &rockchip_pwm_ops_v1, 245 - .set_enable = rockchip_pwm_set_enable_v1, 246 - .get_state = rockchip_pwm_get_state_v1, 285 + .supports_polarity = false, 286 + .supports_lock = false, 287 + .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN, 247 288 }; 248 289 249 290 static const struct rockchip_pwm_data pwm_data_v2 = { ··· 255 296 }, 256 297 .prescaler = 1, 257 298 .supports_polarity = true, 258 - .ops = &rockchip_pwm_ops_v2, 259 - .set_enable = rockchip_pwm_set_enable_v2, 260 - .get_state = rockchip_pwm_get_state_v2, 299 + .supports_lock = false, 300 + .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 301 + PWM_CONTINUOUS, 261 302 }; 262 303 263 304 static const struct rockchip_pwm_data pwm_data_vop = { ··· 269 310 }, 270 311 .prescaler = 1, 271 312 .supports_polarity = true, 272 - .ops = &rockchip_pwm_ops_v2, 273 - .set_enable = rockchip_pwm_set_enable_v2, 274 - .get_state = rockchip_pwm_get_state_v2, 313 + .supports_lock = false, 314 + .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 315 + PWM_CONTINUOUS, 316 + }; 317 + 318 + static const struct rockchip_pwm_data pwm_data_v3 = { 319 + .regs = { 320 + .duty = 0x08, 321 + .period = 0x04, 322 + .cntr = 0x00, 323 + .ctrl = 0x0c, 324 + }, 325 + .prescaler = 1, 326 + .supports_polarity = true, 327 + .supports_lock = true, 328 + .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 329 + PWM_CONTINUOUS, 275 330 }; 276 331 277 332 static const struct of_device_id rockchip_pwm_dt_ids[] = { 278 333 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, 279 334 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, 280 335 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, 336 + { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3}, 281 337 { /* sentinel */ } 282 338 }; 283 339 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); ··· 302 328 const struct of_device_id *id; 303 329 struct rockchip_pwm_chip *pc; 304 330 struct resource *r; 305 - int ret; 331 + int ret, count; 306 332 307 333 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); 308 334 if (!id) ··· 317 343 if (IS_ERR(pc->base)) 318 344 return PTR_ERR(pc->base); 319 345 320 - pc->clk = devm_clk_get(&pdev->dev, NULL); 321 - if (IS_ERR(pc->clk)) 322 - return PTR_ERR(pc->clk); 346 + pc->clk = devm_clk_get(&pdev->dev, "pwm"); 347 + if (IS_ERR(pc->clk)) { 348 + pc->clk = devm_clk_get(&pdev->dev, NULL); 349 + if (IS_ERR(pc->clk)) { 350 + ret = PTR_ERR(pc->clk); 351 + if (ret != -EPROBE_DEFER) 352 + dev_err(&pdev->dev, "Can't get bus clk: %d\n", 353 + ret); 354 + return ret; 355 + } 356 + } 357 + 358 + count = of_count_phandle_with_args(pdev->dev.of_node, 359 + "clocks", "#clock-cells"); 360 + if (count == 2) 361 + pc->pclk = devm_clk_get(&pdev->dev, "pclk"); 362 + else 363 + pc->pclk = pc->clk; 364 + 365 + if (IS_ERR(pc->pclk)) { 366 + ret = PTR_ERR(pc->pclk); 367 + if (ret != -EPROBE_DEFER) 368 + dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret); 369 + return ret; 370 + } 323 371 324 372 ret = clk_prepare_enable(pc->clk); 325 - if (ret) 373 + if (ret) { 374 + dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret); 326 375 return ret; 376 + } 377 + 378 + ret = clk_prepare(pc->pclk); 379 + if (ret) { 380 + dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret); 381 + goto err_clk; 382 + } 327 383 328 384 platform_set_drvdata(pdev, pc); 329 385 330 386 pc->data = id->data; 331 387 pc->chip.dev = &pdev->dev; 332 - pc->chip.ops = pc->data->ops; 388 + pc->chip.ops = &rockchip_pwm_ops; 333 389 pc->chip.base = -1; 334 390 pc->chip.npwm = 1; 335 391 ··· 372 368 if (ret < 0) { 373 369 clk_unprepare(pc->clk); 374 370 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 371 + goto err_pclk; 375 372 } 376 373 377 374 /* Keep the PWM clk enabled if the PWM appears to be up and running. */ 378 375 if (!pwm_is_enabled(pc->chip.pwms)) 379 376 clk_disable(pc->clk); 377 + 378 + return 0; 379 + 380 + err_pclk: 381 + clk_unprepare(pc->pclk); 382 + err_clk: 383 + clk_disable_unprepare(pc->clk); 380 384 381 385 return ret; 382 386 } ··· 407 395 if (pwm_is_enabled(pc->chip.pwms)) 408 396 clk_disable(pc->clk); 409 397 398 + clk_unprepare(pc->pclk); 410 399 clk_unprepare(pc->clk); 411 400 412 401 return pwmchip_remove(&pc->chip);

+35 -35

drivers/pwm/pwm-samsung.c

··· 3 3 * Copyright (c) 2008 Simtec Electronics 4 4 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> 5 5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> 6 + * Copyright (c) 2017 Samsung Electronics Co., Ltd. 6 7 * 7 8 * PWM driver for Samsung SoCs 8 9 * ··· 75 74 * @chip: generic PWM chip 76 75 * @variant: local copy of hardware variant data 77 76 * @inverter_mask: inverter status for all channels - one bit per channel 77 + * @disabled_mask: disabled status for all channels - one bit per channel 78 78 * @base: base address of mapped PWM registers 79 79 * @base_clk: base clock used to drive the timers 80 80 * @tclk0: external clock 0 (can be ERR_PTR if not present) ··· 85 83 struct pwm_chip chip; 86 84 struct samsung_pwm_variant variant; 87 85 u8 inverter_mask; 86 + u8 disabled_mask; 88 87 89 88 void __iomem *base; 90 89 struct clk *base_clk; ··· 260 257 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan); 261 258 writel(tcon, our_chip->base + REG_TCON); 262 259 260 + our_chip->disabled_mask &= ~BIT(pwm->hwpwm); 261 + 263 262 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 264 263 265 264 return 0; ··· 279 274 tcon = readl(our_chip->base + REG_TCON); 280 275 tcon &= ~TCON_AUTORELOAD(tcon_chan); 281 276 writel(tcon, our_chip->base + REG_TCON); 277 + 278 + our_chip->disabled_mask |= BIT(pwm->hwpwm); 282 279 283 280 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 284 281 } ··· 304 297 spin_unlock_irqrestore(&samsung_pwm_lock, flags); 305 298 } 306 299 307 - static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, 308 - int duty_ns, int period_ns) 300 + static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, 301 + int duty_ns, int period_ns, bool force_period) 309 302 { 310 303 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); 311 304 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); ··· 319 312 if (period_ns > NSEC_PER_SEC) 320 313 return -ERANGE; 321 314 322 - if (period_ns == chan->period_ns && duty_ns == chan->duty_ns) 323 - return 0; 324 - 325 315 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); 326 316 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); 327 317 ··· 326 322 ++tcnt; 327 323 328 324 /* Check to see if we are changing the clock rate of the PWM. */ 329 - if (chan->period_ns != period_ns) { 325 + if (chan->period_ns != period_ns || force_period) { 330 326 unsigned long tin_rate; 331 327 u32 period; 332 328 ··· 383 379 chan->duty_ns = duty_ns; 384 380 385 381 return 0; 382 + } 383 + 384 + static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, 385 + int duty_ns, int period_ns) 386 + { 387 + return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false); 386 388 } 387 389 388 390 static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip, ··· 602 592 } 603 593 604 594 #ifdef CONFIG_PM_SLEEP 605 - static int pwm_samsung_suspend(struct device *dev) 595 + static int pwm_samsung_resume(struct device *dev) 606 596 { 607 - struct samsung_pwm_chip *chip = dev_get_drvdata(dev); 597 + struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev); 598 + struct pwm_chip *chip = &our_chip->chip; 608 599 unsigned int i; 609 600 610 - /* 611 - * No one preserves these values during suspend so reset them. 612 - * Otherwise driver leaves PWM unconfigured if same values are 613 - * passed to pwm_config() next time. 614 - */ 615 - for (i = 0; i < SAMSUNG_PWM_NUM; ++i) { 616 - struct pwm_device *pwm = &chip->chip.pwms[i]; 601 + for (i = 0; i < SAMSUNG_PWM_NUM; i++) { 602 + struct pwm_device *pwm = &chip->pwms[i]; 617 603 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); 618 604 619 605 if (!chan) 620 606 continue; 621 607 622 - chan->period_ns = 0; 623 - chan->duty_ns = 0; 624 - } 608 + if (our_chip->variant.output_mask & BIT(i)) 609 + pwm_samsung_set_invert(our_chip, i, 610 + our_chip->inverter_mask & BIT(i)); 625 611 626 - return 0; 627 - } 612 + if (chan->period_ns) { 613 + __pwm_samsung_config(chip, pwm, chan->duty_ns, 614 + chan->period_ns, true); 615 + /* needed to make PWM disable work on Odroid-XU3 */ 616 + pwm_samsung_manual_update(our_chip, pwm); 617 + } 628 618 629 - static int pwm_samsung_resume(struct device *dev) 630 - { 631 - struct samsung_pwm_chip *chip = dev_get_drvdata(dev); 632 - unsigned int chan; 633 - 634 - /* 635 - * Inverter setting must be preserved across suspend/resume 636 - * as nobody really seems to configure it more than once. 637 - */ 638 - for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) { 639 - if (chip->variant.output_mask & BIT(chan)) 640 - pwm_samsung_set_invert(chip, chan, 641 - chip->inverter_mask & BIT(chan)); 619 + if (our_chip->disabled_mask & BIT(i)) 620 + pwm_samsung_disable(chip, pwm); 621 + else 622 + pwm_samsung_enable(chip, pwm); 642 623 } 643 624 644 625 return 0; 645 626 } 646 627 #endif 647 628 648 - static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, pwm_samsung_suspend, 649 - pwm_samsung_resume); 629 + static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume); 650 630 651 631 static struct platform_driver pwm_samsung_driver = { 652 632 .driver = {

+1 -1

drivers/pwm/pwm-tegra.c

··· 218 218 */ 219 219 pwm->clk_rate = clk_get_rate(pwm->clk); 220 220 221 - pwm->rst = devm_reset_control_get(&pdev->dev, "pwm"); 221 + pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); 222 222 if (IS_ERR(pwm->rst)) { 223 223 ret = PTR_ERR(pwm->rst); 224 224 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);

+48 -42

drivers/pwm/pwm-tiecap.c

··· 39 39 #define ECCTL2_TSCTR_FREERUN BIT(4) 40 40 41 41 struct ecap_context { 42 - u32 cap3; 43 - u32 cap4; 44 - u16 ecctl2; 42 + u32 cap3; 43 + u32 cap4; 44 + u16 ecctl2; 45 45 }; 46 46 47 47 struct ecap_pwm_chip { 48 - struct pwm_chip chip; 49 - unsigned int clk_rate; 50 - void __iomem *mmio_base; 48 + struct pwm_chip chip; 49 + unsigned int clk_rate; 50 + void __iomem *mmio_base; 51 51 struct ecap_context ctx; 52 52 }; 53 53 ··· 64 64 int duty_ns, int period_ns) 65 65 { 66 66 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); 67 + u32 period_cycles, duty_cycles; 67 68 unsigned long long c; 68 - unsigned long period_cycles, duty_cycles; 69 - unsigned int reg_val; 69 + u16 value; 70 70 71 71 if (period_ns > NSEC_PER_SEC) 72 72 return -ERANGE; ··· 74 74 c = pc->clk_rate; 75 75 c = c * period_ns; 76 76 do_div(c, NSEC_PER_SEC); 77 - period_cycles = (unsigned long)c; 77 + period_cycles = (u32)c; 78 78 79 79 if (period_cycles < 1) { 80 80 period_cycles = 1; ··· 83 83 c = pc->clk_rate; 84 84 c = c * duty_ns; 85 85 do_div(c, NSEC_PER_SEC); 86 - duty_cycles = (unsigned long)c; 86 + duty_cycles = (u32)c; 87 87 } 88 88 89 89 pm_runtime_get_sync(pc->chip.dev); 90 90 91 - reg_val = readw(pc->mmio_base + ECCTL2); 91 + value = readw(pc->mmio_base + ECCTL2); 92 92 93 93 /* Configure APWM mode & disable sync option */ 94 - reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA; 94 + value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA; 95 95 96 - writew(reg_val, pc->mmio_base + ECCTL2); 96 + writew(value, pc->mmio_base + ECCTL2); 97 97 98 98 if (!pwm_is_enabled(pwm)) { 99 99 /* Update active registers if not running */ ··· 110 110 } 111 111 112 112 if (!pwm_is_enabled(pwm)) { 113 - reg_val = readw(pc->mmio_base + ECCTL2); 113 + value = readw(pc->mmio_base + ECCTL2); 114 114 /* Disable APWM mode to put APWM output Low */ 115 - reg_val &= ~ECCTL2_APWM_MODE; 116 - writew(reg_val, pc->mmio_base + ECCTL2); 115 + value &= ~ECCTL2_APWM_MODE; 116 + writew(value, pc->mmio_base + ECCTL2); 117 117 } 118 118 119 119 pm_runtime_put_sync(pc->chip.dev); 120 + 120 121 return 0; 121 122 } 122 123 123 124 static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, 124 - enum pwm_polarity polarity) 125 + enum pwm_polarity polarity) 125 126 { 126 127 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); 127 - unsigned short reg_val; 128 + u16 value; 128 129 129 130 pm_runtime_get_sync(pc->chip.dev); 130 - reg_val = readw(pc->mmio_base + ECCTL2); 131 + 132 + value = readw(pc->mmio_base + ECCTL2); 133 + 131 134 if (polarity == PWM_POLARITY_INVERSED) 132 135 /* Duty cycle defines LOW period of PWM */ 133 - reg_val |= ECCTL2_APWM_POL_LOW; 136 + value |= ECCTL2_APWM_POL_LOW; 134 137 else 135 138 /* Duty cycle defines HIGH period of PWM */ 136 - reg_val &= ~ECCTL2_APWM_POL_LOW; 139 + value &= ~ECCTL2_APWM_POL_LOW; 137 140 138 - writew(reg_val, pc->mmio_base + ECCTL2); 141 + writew(value, pc->mmio_base + ECCTL2); 142 + 139 143 pm_runtime_put_sync(pc->chip.dev); 144 + 140 145 return 0; 141 146 } 142 147 143 148 static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 144 149 { 145 150 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); 146 - unsigned int reg_val; 151 + u16 value; 147 152 148 153 /* Leave clock enabled on enabling PWM */ 149 154 pm_runtime_get_sync(pc->chip.dev); ··· 157 152 * Enable 'Free run Time stamp counter mode' to start counter 158 153 * and 'APWM mode' to enable APWM output 159 154 */ 160 - reg_val = readw(pc->mmio_base + ECCTL2); 161 - reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE; 162 - writew(reg_val, pc->mmio_base + ECCTL2); 155 + value = readw(pc->mmio_base + ECCTL2); 156 + value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE; 157 + writew(value, pc->mmio_base + ECCTL2); 158 + 163 159 return 0; 164 160 } 165 161 166 162 static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 167 163 { 168 164 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); 169 - unsigned int reg_val; 165 + u16 value; 170 166 171 167 /* 172 168 * Disable 'Free run Time stamp counter mode' to stop counter 173 169 * and 'APWM mode' to put APWM output to low 174 170 */ 175 - reg_val = readw(pc->mmio_base + ECCTL2); 176 - reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE); 177 - writew(reg_val, pc->mmio_base + ECCTL2); 171 + value = readw(pc->mmio_base + ECCTL2); 172 + value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE); 173 + writew(value, pc->mmio_base + ECCTL2); 178 174 179 175 /* Disable clock on PWM disable */ 180 176 pm_runtime_put_sync(pc->chip.dev); ··· 190 184 } 191 185 192 186 static const struct pwm_ops ecap_pwm_ops = { 193 - .free = ecap_pwm_free, 194 - .config = ecap_pwm_config, 195 - .set_polarity = ecap_pwm_set_polarity, 196 - .enable = ecap_pwm_enable, 197 - .disable = ecap_pwm_disable, 198 - .owner = THIS_MODULE, 187 + .free = ecap_pwm_free, 188 + .config = ecap_pwm_config, 189 + .set_polarity = ecap_pwm_set_polarity, 190 + .enable = ecap_pwm_enable, 191 + .disable = ecap_pwm_disable, 192 + .owner = THIS_MODULE, 199 193 }; 200 194 201 195 static const struct of_device_id ecap_of_match[] = { ··· 208 202 static int ecap_pwm_probe(struct platform_device *pdev) 209 203 { 210 204 struct device_node *np = pdev->dev.of_node; 211 - int ret; 205 + struct ecap_pwm_chip *pc; 212 206 struct resource *r; 213 207 struct clk *clk; 214 - struct ecap_pwm_chip *pc; 208 + int ret; 215 209 216 210 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 217 211 if (!pc) ··· 254 248 return ret; 255 249 } 256 250 251 + platform_set_drvdata(pdev, pc); 257 252 pm_runtime_enable(&pdev->dev); 258 253 259 - platform_set_drvdata(pdev, pc); 260 254 return 0; 261 255 } 262 256 ··· 265 259 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev); 266 260 267 261 pm_runtime_disable(&pdev->dev); 262 + 268 263 return pwmchip_remove(&pc->chip); 269 264 } 270 265 ··· 318 311 319 312 static struct platform_driver ecap_pwm_driver = { 320 313 .driver = { 321 - .name = "ecap", 314 + .name = "ecap", 322 315 .of_match_table = ecap_of_match, 323 - .pm = &ecap_pwm_pm_ops, 316 + .pm = &ecap_pwm_pm_ops, 324 317 }, 325 318 .probe = ecap_pwm_probe, 326 319 .remove = ecap_pwm_remove, 327 320 }; 328 - 329 321 module_platform_driver(ecap_pwm_driver); 330 322 331 323 MODULE_DESCRIPTION("ECAP PWM driver");

+69 -53

drivers/pwm/pwm-tiehrpwm.c

··· 122 122 }; 123 123 124 124 struct ehrpwm_pwm_chip { 125 - struct pwm_chip chip; 126 - unsigned int clk_rate; 127 - void __iomem *mmio_base; 125 + struct pwm_chip chip; 126 + unsigned long clk_rate; 127 + void __iomem *mmio_base; 128 128 unsigned long period_cycles[NUM_PWM_CHANNEL]; 129 129 enum pwm_polarity polarity[NUM_PWM_CHANNEL]; 130 - struct clk *tbclk; 130 + struct clk *tbclk; 131 131 struct ehrpwm_context ctx; 132 132 }; 133 133 ··· 136 136 return container_of(chip, struct ehrpwm_pwm_chip, chip); 137 137 } 138 138 139 - static inline u16 ehrpwm_read(void __iomem *base, int offset) 139 + static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset) 140 140 { 141 141 return readw(base + offset); 142 142 } 143 143 144 - static inline void ehrpwm_write(void __iomem *base, int offset, unsigned int val) 144 + static inline void ehrpwm_write(void __iomem *base, unsigned int offset, 145 + u16 value) 145 146 { 146 - writew(val & 0xFFFF, base + offset); 147 + writew(value, base + offset); 147 148 } 148 149 149 - static void ehrpwm_modify(void __iomem *base, int offset, 150 - unsigned short mask, unsigned short val) 150 + static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask, 151 + u16 value) 151 152 { 152 - unsigned short regval; 153 + unsigned short val; 153 154 154 - regval = readw(base + offset); 155 - regval &= ~mask; 156 - regval |= val & mask; 157 - writew(regval, base + offset); 155 + val = readw(base + offset); 156 + val &= ~mask; 157 + val |= value & mask; 158 + writew(val, base + offset); 158 159 } 159 160 160 161 /** ··· 164 163 * @prescale_div: prescaler value set 165 164 * @tb_clk_div: Time Base Control prescaler bits 166 165 */ 167 - static int set_prescale_div(unsigned long rqst_prescaler, 168 - unsigned short *prescale_div, unsigned short *tb_clk_div) 166 + static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, 167 + u16 *tb_clk_div) 169 168 { 170 169 unsigned int clkdiv, hspclkdiv; 171 170 172 171 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { 173 172 for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) { 174 - 175 173 /* 176 174 * calculations for prescaler value : 177 175 * prescale_div = HSPCLKDIVIDER * CLKDIVIDER. ··· 191 191 } 192 192 } 193 193 } 194 + 194 195 return 1; 195 196 } 196 197 197 198 static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan) 198 199 { 199 - int aqctl_reg; 200 - unsigned short aqctl_val, aqctl_mask; 200 + u16 aqctl_val, aqctl_mask; 201 + unsigned int aqctl_reg; 201 202 202 203 /* 203 204 * Configure PWM output to HIGH/LOW level on counter ··· 233 232 * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE 234 233 */ 235 234 static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 236 - int duty_ns, int period_ns) 235 + int duty_ns, int period_ns) 237 236 { 238 237 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); 238 + u32 period_cycles, duty_cycles; 239 + u16 ps_divval, tb_divval; 240 + unsigned int i, cmp_reg; 239 241 unsigned long long c; 240 - unsigned long period_cycles, duty_cycles; 241 - unsigned short ps_divval, tb_divval; 242 - int i, cmp_reg; 243 242 244 243 if (period_ns > NSEC_PER_SEC) 245 244 return -ERANGE; ··· 273 272 if (i == pwm->hwpwm) 274 273 continue; 275 274 276 - dev_err(chip->dev, "Period value conflicts with channel %d\n", 277 - i); 275 + dev_err(chip->dev, 276 + "period value conflicts with channel %u\n", 277 + i); 278 278 return -EINVAL; 279 279 } 280 280 } ··· 284 282 285 283 /* Configure clock prescaler to support Low frequency PWM wave */ 286 284 if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval, 287 - &tb_divval)) { 285 + &tb_divval)) { 288 286 dev_err(chip->dev, "Unsupported values\n"); 289 287 return -EINVAL; 290 288 } ··· 305 303 306 304 /* Configure ehrpwm counter for up-count mode */ 307 305 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, 308 - TBCTL_CTRMODE_UP); 306 + TBCTL_CTRMODE_UP); 309 307 310 308 if (pwm->hwpwm == 1) 311 309 /* Channel 1 configured with compare B register */ ··· 317 315 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); 318 316 319 317 pm_runtime_put_sync(chip->dev); 318 + 320 319 return 0; 321 320 } 322 321 323 322 static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip, 324 - struct pwm_device *pwm, enum pwm_polarity polarity) 323 + struct pwm_device *pwm, 324 + enum pwm_polarity polarity) 325 325 { 326 326 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); 327 327 328 328 /* Configuration of polarity in hardware delayed, do at enable */ 329 329 pc->polarity[pwm->hwpwm] = polarity; 330 + 330 331 return 0; 331 332 } 332 333 333 334 static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 334 335 { 335 336 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); 336 - unsigned short aqcsfrc_val, aqcsfrc_mask; 337 + u16 aqcsfrc_val, aqcsfrc_mask; 337 338 int ret; 338 339 339 340 /* Leave clock enabled on enabling PWM */ ··· 353 348 354 349 /* Changes to shadow mode */ 355 350 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, 356 - AQSFRC_RLDCSF_ZRO); 351 + AQSFRC_RLDCSF_ZRO); 357 352 358 353 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); 359 354 ··· 363 358 /* Enable TBCLK before enabling PWM device */ 364 359 ret = clk_enable(pc->tbclk); 365 360 if (ret) { 366 - dev_err(chip->dev, "Failed to enable TBCLK for %s\n", 367 - dev_name(pc->chip.dev)); 361 + dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n", 362 + dev_name(pc->chip.dev), ret); 368 363 return ret; 369 364 } 370 365 371 366 /* Enable time counter for free_run */ 372 367 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); 368 + 373 369 return 0; 374 370 } 375 371 376 372 static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 377 373 { 378 374 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); 379 - unsigned short aqcsfrc_val, aqcsfrc_mask; 375 + u16 aqcsfrc_val, aqcsfrc_mask; 380 376 381 377 /* Action Qualifier puts PWM output low forcefully */ 382 378 if (pwm->hwpwm) { ··· 393 387 * Action Qualifier control on PWM output from next TBCLK 394 388 */ 395 389 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, 396 - AQSFRC_RLDCSF_IMDT); 390 + AQSFRC_RLDCSF_IMDT); 397 391 398 392 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); 399 393 ··· 421 415 } 422 416 423 417 static const struct pwm_ops ehrpwm_pwm_ops = { 424 - .free = ehrpwm_pwm_free, 425 - .config = ehrpwm_pwm_config, 426 - .set_polarity = ehrpwm_pwm_set_polarity, 427 - .enable = ehrpwm_pwm_enable, 428 - .disable = ehrpwm_pwm_disable, 429 - .owner = THIS_MODULE, 418 + .free = ehrpwm_pwm_free, 419 + .config = ehrpwm_pwm_config, 420 + .set_polarity = ehrpwm_pwm_set_polarity, 421 + .enable = ehrpwm_pwm_enable, 422 + .disable = ehrpwm_pwm_disable, 423 + .owner = THIS_MODULE, 430 424 }; 431 425 432 426 static const struct of_device_id ehrpwm_of_match[] = { 433 - { .compatible = "ti,am3352-ehrpwm" }, 434 - { .compatible = "ti,am33xx-ehrpwm" }, 427 + { .compatible = "ti,am3352-ehrpwm" }, 428 + { .compatible = "ti,am33xx-ehrpwm" }, 435 429 {}, 436 430 }; 437 431 MODULE_DEVICE_TABLE(of, ehrpwm_of_match); ··· 439 433 static int ehrpwm_pwm_probe(struct platform_device *pdev) 440 434 { 441 435 struct device_node *np = pdev->dev.of_node; 442 - int ret; 436 + struct ehrpwm_pwm_chip *pc; 443 437 struct resource *r; 444 438 struct clk *clk; 445 - struct ehrpwm_pwm_chip *pc; 439 + int ret; 446 440 447 441 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 448 442 if (!pc) ··· 495 489 ret = pwmchip_add(&pc->chip); 496 490 if (ret < 0) { 497 491 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 498 - return ret; 492 + goto err_clk_unprepare; 499 493 } 500 494 495 + platform_set_drvdata(pdev, pc); 501 496 pm_runtime_enable(&pdev->dev); 502 497 503 - platform_set_drvdata(pdev, pc); 504 498 return 0; 499 + 500 + err_clk_unprepare: 501 + clk_unprepare(pc->tbclk); 502 + 503 + return ret; 505 504 } 506 505 507 506 static int ehrpwm_pwm_remove(struct platform_device *pdev) ··· 515 504 516 505 clk_unprepare(pc->tbclk); 517 506 518 - pm_runtime_put_sync(&pdev->dev); 519 507 pm_runtime_disable(&pdev->dev); 508 + 520 509 return pwmchip_remove(&pc->chip); 521 510 } 522 511 ··· 524 513 static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc) 525 514 { 526 515 pm_runtime_get_sync(pc->chip.dev); 516 + 527 517 pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL); 528 518 pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD); 529 519 pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA); ··· 533 521 pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB); 534 522 pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC); 535 523 pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC); 524 + 536 525 pm_runtime_put_sync(pc->chip.dev); 537 526 } 538 527 ··· 552 539 static int ehrpwm_pwm_suspend(struct device *dev) 553 540 { 554 541 struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); 555 - int i; 542 + unsigned int i; 556 543 557 544 ehrpwm_pwm_save_context(pc); 545 + 558 546 for (i = 0; i < pc->chip.npwm; i++) { 559 547 struct pwm_device *pwm = &pc->chip.pwms[i]; 560 548 ··· 565 551 /* Disable explicitly if PWM is running */ 566 552 pm_runtime_put_sync(dev); 567 553 } 554 + 568 555 return 0; 569 556 } 570 557 571 558 static int ehrpwm_pwm_resume(struct device *dev) 572 559 { 573 560 struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); 574 - int i; 561 + unsigned int i; 575 562 576 563 for (i = 0; i < pc->chip.npwm; i++) { 577 564 struct pwm_device *pwm = &pc->chip.pwms[i]; ··· 583 568 /* Enable explicitly if PWM was running */ 584 569 pm_runtime_get_sync(dev); 585 570 } 571 + 586 572 ehrpwm_pwm_restore_context(pc); 573 + 587 574 return 0; 588 575 } 589 576 #endif 590 577 591 578 static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend, 592 - ehrpwm_pwm_resume); 579 + ehrpwm_pwm_resume); 593 580 594 581 static struct platform_driver ehrpwm_pwm_driver = { 595 582 .driver = { 596 - .name = "ehrpwm", 583 + .name = "ehrpwm", 597 584 .of_match_table = ehrpwm_of_match, 598 - .pm = &ehrpwm_pwm_pm_ops, 585 + .pm = &ehrpwm_pwm_pm_ops, 599 586 }, 600 587 .probe = ehrpwm_pwm_probe, 601 588 .remove = ehrpwm_pwm_remove, 602 589 }; 603 - 604 590 module_platform_driver(ehrpwm_pwm_driver); 605 591 606 592 MODULE_DESCRIPTION("EHRPWM PWM driver");

+1

drivers/pwm/pwm-vt8500.c

··· 241 241 ret = pwmchip_add(&chip->chip); 242 242 if (ret < 0) { 243 243 dev_err(&pdev->dev, "failed to add PWM chip\n"); 244 + clk_unprepare(chip->clk); 244 245 return ret; 245 246 } 246 247

+282

drivers/pwm/pwm-zx.c

··· 1 + /* 2 + * Copyright (C) 2017 Sanechips Technology Co., Ltd. 3 + * Copyright 2017 Linaro Ltd. 4 + * 5 + * This program is free software; you can redistribute it and/or modify 6 + * it under the terms of the GNU General Public License version 2 as 7 + * published by the Free Software Foundation. 8 + */ 9 + 10 + #include <linux/clk.h> 11 + #include <linux/err.h> 12 + #include <linux/io.h> 13 + #include <linux/kernel.h> 14 + #include <linux/module.h> 15 + #include <linux/platform_device.h> 16 + #include <linux/pwm.h> 17 + #include <linux/slab.h> 18 + 19 + #define ZX_PWM_MODE 0x0 20 + #define ZX_PWM_CLKDIV_SHIFT 2 21 + #define ZX_PWM_CLKDIV_MASK GENMASK(11, 2) 22 + #define ZX_PWM_CLKDIV(x) (((x) << ZX_PWM_CLKDIV_SHIFT) & \ 23 + ZX_PWM_CLKDIV_MASK) 24 + #define ZX_PWM_POLAR BIT(1) 25 + #define ZX_PWM_EN BIT(0) 26 + #define ZX_PWM_PERIOD 0x4 27 + #define ZX_PWM_DUTY 0x8 28 + 29 + #define ZX_PWM_CLKDIV_MAX 1023 30 + #define ZX_PWM_PERIOD_MAX 65535 31 + 32 + struct zx_pwm_chip { 33 + struct pwm_chip chip; 34 + struct clk *pclk; 35 + struct clk *wclk; 36 + void __iomem *base; 37 + }; 38 + 39 + static inline struct zx_pwm_chip *to_zx_pwm_chip(struct pwm_chip *chip) 40 + { 41 + return container_of(chip, struct zx_pwm_chip, chip); 42 + } 43 + 44 + static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm, 45 + unsigned int offset) 46 + { 47 + return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); 48 + } 49 + 50 + static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm, 51 + unsigned int offset, u32 value) 52 + { 53 + writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset); 54 + } 55 + 56 + static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm, 57 + unsigned int offset, u32 mask, u32 value) 58 + { 59 + u32 data; 60 + 61 + data = zx_pwm_readl(zpc, hwpwm, offset); 62 + data &= ~mask; 63 + data |= value & mask; 64 + zx_pwm_writel(zpc, hwpwm, offset, data); 65 + } 66 + 67 + static void zx_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 68 + struct pwm_state *state) 69 + { 70 + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); 71 + unsigned long rate; 72 + unsigned int div; 73 + u32 value; 74 + u64 tmp; 75 + 76 + value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); 77 + 78 + if (value & ZX_PWM_POLAR) 79 + state->polarity = PWM_POLARITY_NORMAL; 80 + else 81 + state->polarity = PWM_POLARITY_INVERSED; 82 + 83 + if (value & ZX_PWM_EN) 84 + state->enabled = true; 85 + else 86 + state->enabled = false; 87 + 88 + div = (value & ZX_PWM_CLKDIV_MASK) >> ZX_PWM_CLKDIV_SHIFT; 89 + rate = clk_get_rate(zpc->wclk); 90 + 91 + tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD); 92 + tmp *= div * NSEC_PER_SEC; 93 + state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); 94 + 95 + tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUTY); 96 + tmp *= div * NSEC_PER_SEC; 97 + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); 98 + } 99 + 100 + static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 101 + unsigned int duty_ns, unsigned int period_ns) 102 + { 103 + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); 104 + unsigned int period_cycles, duty_cycles; 105 + unsigned long long c; 106 + unsigned int div = 1; 107 + unsigned long rate; 108 + 109 + /* Find out the best divider */ 110 + rate = clk_get_rate(zpc->wclk); 111 + 112 + while (1) { 113 + c = rate / div; 114 + c = c * period_ns; 115 + do_div(c, NSEC_PER_SEC); 116 + 117 + if (c < ZX_PWM_PERIOD_MAX) 118 + break; 119 + 120 + div++; 121 + 122 + if (div > ZX_PWM_CLKDIV_MAX) 123 + return -ERANGE; 124 + } 125 + 126 + /* Calculate duty cycles */ 127 + period_cycles = c; 128 + c *= duty_ns; 129 + do_div(c, period_ns); 130 + duty_cycles = c; 131 + 132 + /* 133 + * If the PWM is being enabled, we have to temporarily disable it 134 + * before configuring the registers. 135 + */ 136 + if (pwm_is_enabled(pwm)) 137 + zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_EN, 0); 138 + 139 + /* Set up registers */ 140 + zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_CLKDIV_MASK, 141 + ZX_PWM_CLKDIV(div)); 142 + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles); 143 + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles); 144 + 145 + /* Re-enable the PWM if needed */ 146 + if (pwm_is_enabled(pwm)) 147 + zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, 148 + ZX_PWM_EN, ZX_PWM_EN); 149 + 150 + return 0; 151 + } 152 + 153 + static int zx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 154 + struct pwm_state *state) 155 + { 156 + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); 157 + struct pwm_state cstate; 158 + int ret; 159 + 160 + pwm_get_state(pwm, &cstate); 161 + 162 + if (state->polarity != cstate.polarity) 163 + zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_POLAR, 164 + (state->polarity == PWM_POLARITY_INVERSED) ? 165 + 0 : ZX_PWM_POLAR); 166 + 167 + if (state->period != cstate.period || 168 + state->duty_cycle != cstate.duty_cycle) { 169 + ret = zx_pwm_config(chip, pwm, state->duty_cycle, 170 + state->period); 171 + if (ret) 172 + return ret; 173 + } 174 + 175 + if (state->enabled != cstate.enabled) { 176 + if (state->enabled) { 177 + ret = clk_prepare_enable(zpc->wclk); 178 + if (ret) 179 + return ret; 180 + 181 + zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, 182 + ZX_PWM_EN, ZX_PWM_EN); 183 + } else { 184 + zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, 185 + ZX_PWM_EN, 0); 186 + clk_disable_unprepare(zpc->wclk); 187 + } 188 + } 189 + 190 + return 0; 191 + } 192 + 193 + static const struct pwm_ops zx_pwm_ops = { 194 + .apply = zx_pwm_apply, 195 + .get_state = zx_pwm_get_state, 196 + .owner = THIS_MODULE, 197 + }; 198 + 199 + static int zx_pwm_probe(struct platform_device *pdev) 200 + { 201 + struct zx_pwm_chip *zpc; 202 + struct resource *res; 203 + unsigned int i; 204 + int ret; 205 + 206 + zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL); 207 + if (!zpc) 208 + return -ENOMEM; 209 + 210 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 211 + zpc->base = devm_ioremap_resource(&pdev->dev, res); 212 + if (IS_ERR(zpc->base)) 213 + return PTR_ERR(zpc->base); 214 + 215 + zpc->pclk = devm_clk_get(&pdev->dev, "pclk"); 216 + if (IS_ERR(zpc->pclk)) 217 + return PTR_ERR(zpc->pclk); 218 + 219 + zpc->wclk = devm_clk_get(&pdev->dev, "wclk"); 220 + if (IS_ERR(zpc->wclk)) 221 + return PTR_ERR(zpc->wclk); 222 + 223 + ret = clk_prepare_enable(zpc->pclk); 224 + if (ret) 225 + return ret; 226 + 227 + zpc->chip.dev = &pdev->dev; 228 + zpc->chip.ops = &zx_pwm_ops; 229 + zpc->chip.base = -1; 230 + zpc->chip.npwm = 4; 231 + zpc->chip.of_xlate = of_pwm_xlate_with_flags; 232 + zpc->chip.of_pwm_n_cells = 3; 233 + 234 + /* 235 + * PWM devices may be enabled by firmware, and let's disable all of 236 + * them initially to save power. 237 + */ 238 + for (i = 0; i < zpc->chip.npwm; i++) 239 + zx_pwm_set_mask(zpc, i, ZX_PWM_MODE, ZX_PWM_EN, 0); 240 + 241 + ret = pwmchip_add(&zpc->chip); 242 + if (ret < 0) { 243 + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); 244 + return ret; 245 + } 246 + 247 + platform_set_drvdata(pdev, zpc); 248 + 249 + return 0; 250 + } 251 + 252 + static int zx_pwm_remove(struct platform_device *pdev) 253 + { 254 + struct zx_pwm_chip *zpc = platform_get_drvdata(pdev); 255 + int ret; 256 + 257 + ret = pwmchip_remove(&zpc->chip); 258 + clk_disable_unprepare(zpc->pclk); 259 + 260 + return ret; 261 + } 262 + 263 + static const struct of_device_id zx_pwm_dt_ids[] = { 264 + { .compatible = "zte,zx296718-pwm", }, 265 + { /* sentinel */ } 266 + }; 267 + MODULE_DEVICE_TABLE(of, zx_pwm_dt_ids); 268 + 269 + static struct platform_driver zx_pwm_driver = { 270 + .driver = { 271 + .name = "zx-pwm", 272 + .of_match_table = zx_pwm_dt_ids, 273 + }, 274 + .probe = zx_pwm_probe, 275 + .remove = zx_pwm_remove, 276 + }; 277 + module_platform_driver(zx_pwm_driver); 278 + 279 + MODULE_ALIAS("platform:zx-pwm"); 280 + MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 281 + MODULE_DESCRIPTION("ZTE ZX PWM Driver"); 282 + MODULE_LICENSE("GPL v2");

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