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phy: rockchip: samsung-hdptx: Drop hw_rate driver data

The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep
track of the clock rate programmed in hardware and support implementing
the ->recalc_rate() callback in hdptx_phy_clk_ops.

Computing the clock rate from the actual PHY PLL configuration seems to
work reliably, hence remove the now redundant struct member.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-8-8d5f97419c0b@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Cristian Ciocaltea and committed by
Vinod Koul 66d76b6d 3481fc04

+2 -11
+2 -11
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
··· 387 387 388 388 /* clk provider */ 389 389 struct clk_hw hw; 390 - unsigned long hw_rate; 391 390 bool restrict_rate_change; 392 391 393 392 atomic_t usage_count; ··· 930 931 { 931 932 const struct ropll_config *cfg = NULL; 932 933 struct ropll_config rc = {0}; 933 - int ret, i; 934 + int i; 934 935 935 936 if (!hdptx->hdmi_cfg.tmds_char_rate) 936 937 return 0; ··· 992 993 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, 993 994 FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); 994 995 995 - ret = rk_hdptx_post_enable_pll(hdptx); 996 - if (!ret) 997 - hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, 998 - hdptx->hdmi_cfg.bpc); 999 - 1000 - return ret; 996 + return rk_hdptx_post_enable_pll(hdptx); 1001 997 } 1002 998 1003 999 static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) ··· 1896 1902 u32 status; 1897 1903 u64 rate; 1898 1904 int ret; 1899 - 1900 - if (hdptx->hw_rate) 1901 - return hdptx->hw_rate; 1902 1905 1903 1906 ret = regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status); 1904 1907 if (ret || !(status & HDPTX_I_PLL_EN))