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dmaengine: fsl-edma: read/write multiple registers in cyclic transactions

Add support for reading multiple registers in DEV_TO_MEM transactions and
for writing multiple registers in MEM_TO_DEV transactions.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Co-developed-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
Link: https://lore.kernel.org/r/20241219102415.1208328-6-larisa.grigore@oss.nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Larisa Grigore and committed by
Vinod Koul 66d88e16 2500243e

+27 -9
+27 -9
drivers/dma/fsl-edma-common.c
··· 480 480 bool disable_req, bool enable_sg) 481 481 { 482 482 struct dma_slave_config *cfg = &fsl_chan->cfg; 483 + u32 burst = 0; 483 484 u16 csr = 0; 484 - u32 burst; 485 485 486 486 /* 487 487 * eDMA hardware SGs require the TCDs to be stored in little ··· 496 496 497 497 fsl_edma_set_tcd_to_le(fsl_chan, tcd, soff, soff); 498 498 499 - if (fsl_chan->is_multi_fifo) { 500 - /* set mloff to support multiple fifo */ 501 - burst = cfg->direction == DMA_DEV_TO_MEM ? 502 - cfg->src_maxburst : cfg->dst_maxburst; 503 - nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4)); 504 - /* enable DMLOE/SMLOE */ 505 - if (cfg->direction == DMA_MEM_TO_DEV) { 499 + /* If we expect to have either multi_fifo or a port window size, 500 + * we will use minor loop offset, meaning bits 29-10 will be used for 501 + * address offset, while bits 9-0 will be used to tell DMA how much 502 + * data to read from addr. 503 + * If we don't have either of those, will use a major loop reading from addr 504 + * nbytes (29bits). 505 + */ 506 + if (cfg->direction == DMA_MEM_TO_DEV) { 507 + if (fsl_chan->is_multi_fifo) 508 + burst = cfg->dst_maxburst * 4; 509 + if (cfg->dst_port_window_size) 510 + burst = cfg->dst_port_window_size * cfg->dst_addr_width; 511 + if (burst) { 512 + nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-burst); 506 513 nbytes |= EDMA_V3_TCD_NBYTES_DMLOE; 507 514 nbytes &= ~EDMA_V3_TCD_NBYTES_SMLOE; 508 - } else { 515 + } 516 + } else { 517 + if (fsl_chan->is_multi_fifo) 518 + burst = cfg->src_maxburst * 4; 519 + if (cfg->src_port_window_size) 520 + burst = cfg->src_port_window_size * cfg->src_addr_width; 521 + if (burst) { 522 + nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-burst); 509 523 nbytes |= EDMA_V3_TCD_NBYTES_SMLOE; 510 524 nbytes &= ~EDMA_V3_TCD_NBYTES_DMLOE; 511 525 } ··· 637 623 dst_addr = fsl_chan->dma_dev_addr; 638 624 soff = fsl_chan->cfg.dst_addr_width; 639 625 doff = fsl_chan->is_multi_fifo ? 4 : 0; 626 + if (fsl_chan->cfg.dst_port_window_size) 627 + doff = fsl_chan->cfg.dst_addr_width; 640 628 } else if (direction == DMA_DEV_TO_MEM) { 641 629 src_addr = fsl_chan->dma_dev_addr; 642 630 dst_addr = dma_buf_next; 643 631 soff = fsl_chan->is_multi_fifo ? 4 : 0; 644 632 doff = fsl_chan->cfg.src_addr_width; 633 + if (fsl_chan->cfg.src_port_window_size) 634 + soff = fsl_chan->cfg.src_addr_width; 645 635 } else { 646 636 /* DMA_DEV_TO_DEV */ 647 637 src_addr = fsl_chan->cfg.src_addr;