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mfd: cros_ec: Add SCP Core-1 as a new CrOS EC MCU

MT8195 System Companion Processors(SCP) is a dual-core RISC-V MCU.
Add a new CrOS feature ID to represent the SCP's 2nd core.

The 1st core is referred to as 'core 0', and the 2nd core is referred
to as 'core 1'.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220601112201.15510-16-tinghan.shen@mediatek.com

authored by

Tinghan Shen and committed by
Lee Jones 66ee379d 738654be

+8
+5
drivers/mfd/cros_ec_dev.c
··· 65 65 .desc = "System Control Processor", 66 66 }, 67 67 { 68 + .id = EC_FEATURE_SCP_C1, 69 + .name = CROS_EC_DEV_SCP_C1_NAME, 70 + .desc = "System Control Processor 2nd Core", 71 + }, 72 + { 68 73 .id = EC_FEATURE_TOUCHPAD, 69 74 .name = CROS_EC_DEV_TP_NAME, 70 75 .desc = "Touchpad",
+2
include/linux/platform_data/cros_ec_commands.h
··· 1300 1300 * mux. 1301 1301 */ 1302 1302 EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, 1303 + /* The MCU is a System Companion Processor (SCP) 2nd Core. */ 1304 + EC_FEATURE_SCP_C1 = 45, 1303 1305 }; 1304 1306 1305 1307 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
+1
include/linux/platform_data/cros_ec_proto.h
··· 19 19 #define CROS_EC_DEV_ISH_NAME "cros_ish" 20 20 #define CROS_EC_DEV_PD_NAME "cros_pd" 21 21 #define CROS_EC_DEV_SCP_NAME "cros_scp" 22 + #define CROS_EC_DEV_SCP_C1_NAME "cros_scp_c1" 22 23 #define CROS_EC_DEV_TP_NAME "cros_tp" 23 24 24 25 /*