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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
interconnect: qcom: sm8150: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-17-c03aaeffc769@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Konrad Dybcio
and committed by
Georgi Djakov
670699a4
ab2c1cb5
+255
-28
+255
-28
drivers/interconnect/qcom/sm8150.c
+255
-28
drivers/interconnect/qcom/sm8150.c
···
1280
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.buswidth = 8,
1281
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};
1282
1282
1283
-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1284
-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1285
-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1286
-
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
1287
-
DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
1288
-
DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
1289
-
DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
1290
-
DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
1291
-
DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
1292
-
DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
1293
-
DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
1294
-
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
1295
-
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
1296
-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1297
-
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
1298
-
DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
1299
-
DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
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-
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
1301
-
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
1302
-
DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
1303
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DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
1304
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DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
1305
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DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
1306
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DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
1307
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DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
1308
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DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
1309
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DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
1310
-
DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);
1283
+
static struct qcom_icc_bcm bcm_acv = {
1284
+
.name = "ACV",
1285
+
.keepalive = false,
1286
+
.num_nodes = 1,
1287
+
.nodes = { &ebi },
1288
+
};
1289
+
1290
+
static struct qcom_icc_bcm bcm_mc0 = {
1291
+
.name = "MC0",
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+
.keepalive = true,
1293
+
.num_nodes = 1,
1294
+
.nodes = { &ebi },
1295
+
};
1296
+
1297
+
static struct qcom_icc_bcm bcm_sh0 = {
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+
.name = "SH0",
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+
.keepalive = true,
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+
.num_nodes = 1,
1301
+
.nodes = { &qns_llcc },
1302
+
};
1303
+
1304
+
static struct qcom_icc_bcm bcm_mm0 = {
1305
+
.name = "MM0",
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+
.keepalive = true,
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+
.num_nodes = 1,
1308
+
.nodes = { &qns_mem_noc_hf },
1309
+
};
1310
+
1311
+
static struct qcom_icc_bcm bcm_mm1 = {
1312
+
.name = "MM1",
1313
+
.keepalive = false,
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+
.num_nodes = 7,
1315
+
.nodes = { &qxm_camnoc_hf0_uncomp,
1316
+
&qxm_camnoc_hf1_uncomp,
1317
+
&qxm_camnoc_sf_uncomp,
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+
&qxm_camnoc_hf0,
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&qxm_camnoc_hf1,
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&qxm_mdp0,
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&qxm_mdp1
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+
},
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+
};
1324
+
1325
+
static struct qcom_icc_bcm bcm_sh2 = {
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+
.name = "SH2",
1327
+
.keepalive = false,
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+
.num_nodes = 1,
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+
.nodes = { &qns_gem_noc_snoc },
1330
+
};
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+
1332
+
static struct qcom_icc_bcm bcm_mm2 = {
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+
.name = "MM2",
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+
.keepalive = false,
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+
.num_nodes = 2,
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.nodes = { &qxm_camnoc_sf, &qns2_mem_noc },
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+
};
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+
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+
static struct qcom_icc_bcm bcm_sh3 = {
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.name = "SH3",
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+
.keepalive = false,
1342
+
.num_nodes = 2,
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+
.nodes = { &acm_gpu_tcu, &acm_sys_tcu },
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+
};
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+
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static struct qcom_icc_bcm bcm_mm3 = {
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.name = "MM3",
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.keepalive = false,
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+
.num_nodes = 4,
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.nodes = { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
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+
};
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+
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static struct qcom_icc_bcm bcm_sh4 = {
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.name = "SH4",
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+
.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_cmpnoc },
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};
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+
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static struct qcom_icc_bcm bcm_sh5 = {
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.name = "SH5",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &acm_apps },
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};
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+
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static struct qcom_icc_bcm bcm_sn0 = {
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.name = "SN0",
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.keepalive = true,
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+
.num_nodes = 1,
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+
.nodes = { &qns_gemnoc_sf },
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+
};
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+
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static struct qcom_icc_bcm bcm_co0 = {
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.name = "CO0",
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+
.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qns_cdsp_mem_noc },
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};
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+
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static struct qcom_icc_bcm bcm_ce0 = {
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.name = "CE0",
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+
.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qxm_crypto },
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+
};
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+
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static struct qcom_icc_bcm bcm_sn1 = {
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.name = "SN1",
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.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qxs_imem },
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+
};
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+
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static struct qcom_icc_bcm bcm_co1 = {
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.name = "CO1",
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.keepalive = false,
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+
.num_nodes = 1,
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.nodes = { &qnm_npu },
1400
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};
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+
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static struct qcom_icc_bcm bcm_cn0 = {
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.name = "CN0",
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.keepalive = true,
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.num_nodes = 53,
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.nodes = { &qhm_spdm,
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&qnm_snoc,
1408
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&qhs_a1_noc_cfg,
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&qhs_a2_noc_cfg,
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&qhs_ahb2phy_south,
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&qhs_aop,
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&qhs_aoss,
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&qhs_camera_cfg,
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&qhs_clk_ctl,
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&qhs_compute_dsp,
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&qhs_cpr_cx,
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&qhs_cpr_mmcx,
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&qhs_cpr_mx,
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&qhs_crypto0_cfg,
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&qhs_ddrss_cfg,
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&qhs_display_cfg,
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&qhs_emac_cfg,
1423
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&qhs_glm,
1424
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&qhs_gpuss_cfg,
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&qhs_imem_cfg,
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&qhs_ipa,
1427
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&qhs_mnoc_cfg,
1428
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&qhs_npu_cfg,
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&qhs_pcie0_cfg,
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&qhs_pcie1_cfg,
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&qhs_phy_refgen_north,
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&qhs_pimem_cfg,
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&qhs_prng,
1434
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&qhs_qdss_cfg,
1435
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&qhs_qspi,
1436
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&qhs_qupv3_east,
1437
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&qhs_qupv3_north,
1438
+
&qhs_qupv3_south,
1439
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&qhs_sdc2,
1440
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&qhs_sdc4,
1441
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&qhs_snoc_cfg,
1442
+
&qhs_spdm,
1443
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&qhs_spss_cfg,
1444
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&qhs_ssc_cfg,
1445
+
&qhs_tcsr,
1446
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&qhs_tlmm_east,
1447
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&qhs_tlmm_north,
1448
+
&qhs_tlmm_south,
1449
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&qhs_tlmm_west,
1450
+
&qhs_tsif,
1451
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&qhs_ufs_card_cfg,
1452
+
&qhs_ufs_mem_cfg,
1453
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&qhs_usb3_0,
1454
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&qhs_usb3_1,
1455
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&qhs_venus_cfg,
1456
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&qhs_vsense_ctrl_cfg,
1457
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&qns_cnoc_a2noc,
1458
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&srvc_cnoc
1459
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},
1460
+
};
1461
+
1462
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static struct qcom_icc_bcm bcm_qup0 = {
1463
+
.name = "QUP0",
1464
+
.keepalive = false,
1465
+
.num_nodes = 3,
1466
+
.nodes = { &qhm_qup0, &qhm_qup1, &qhm_qup2 },
1467
+
};
1468
+
1469
+
static struct qcom_icc_bcm bcm_sn2 = {
1470
+
.name = "SN2",
1471
+
.keepalive = false,
1472
+
.num_nodes = 1,
1473
+
.nodes = { &qns_gemnoc_gc },
1474
+
};
1475
+
1476
+
static struct qcom_icc_bcm bcm_sn3 = {
1477
+
.name = "SN3",
1478
+
.keepalive = false,
1479
+
.num_nodes = 3,
1480
+
.nodes = { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc },
1481
+
};
1482
+
1483
+
static struct qcom_icc_bcm bcm_sn4 = {
1484
+
.name = "SN4",
1485
+
.keepalive = false,
1486
+
.num_nodes = 1,
1487
+
.nodes = { &qxs_pimem },
1488
+
};
1489
+
1490
+
static struct qcom_icc_bcm bcm_sn5 = {
1491
+
.name = "SN5",
1492
+
.keepalive = false,
1493
+
.num_nodes = 1,
1494
+
.nodes = { &xs_qdss_stm },
1495
+
};
1496
+
1497
+
static struct qcom_icc_bcm bcm_sn8 = {
1498
+
.name = "SN8",
1499
+
.keepalive = false,
1500
+
.num_nodes = 2,
1501
+
.nodes = { &xs_pcie_0, &xs_pcie_1 },
1502
+
};
1503
+
1504
+
static struct qcom_icc_bcm bcm_sn9 = {
1505
+
.name = "SN9",
1506
+
.keepalive = false,
1507
+
.num_nodes = 1,
1508
+
.nodes = { &qnm_aggre1_noc },
1509
+
};
1510
+
1511
+
static struct qcom_icc_bcm bcm_sn11 = {
1512
+
.name = "SN11",
1513
+
.keepalive = false,
1514
+
.num_nodes = 1,
1515
+
.nodes = { &qnm_aggre2_noc },
1516
+
};
1517
+
1518
+
static struct qcom_icc_bcm bcm_sn12 = {
1519
+
.name = "SN12",
1520
+
.keepalive = false,
1521
+
.num_nodes = 2,
1522
+
.nodes = { &qxm_pimem, &xm_gic },
1523
+
};
1524
+
1525
+
static struct qcom_icc_bcm bcm_sn14 = {
1526
+
.name = "SN14",
1527
+
.keepalive = false,
1528
+
.num_nodes = 1,
1529
+
.nodes = { &qns_pcie_mem_noc },
1530
+
};
1531
+
1532
+
static struct qcom_icc_bcm bcm_sn15 = {
1533
+
.name = "SN15",
1534
+
.keepalive = false,
1535
+
.num_nodes = 1,
1536
+
.nodes = { &qnm_gemnoc },
1537
+
};
1311
1538
1312
1539
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1313
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&bcm_qup0,