clk: qcom: mmcc-msm8960: handle LVDS clock

On APQ8064 the DSI2_PIXEL_SRC clock can be used either to drive the
second DSI host or to drive the LCDC controller. Add LVDS PLL as
possible source to the clock and LVDS output clock. The DSI2_PIXEL_SRC
clock has separate path to be used for the LVDS clock. To represent
both DSI and LVDS clocks properly, add intermediate clock which toggles
the enable bit and make DSI2_PIXEL_CLK clock just check for the HALT
bit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-4-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Dmitry Baryshkov and committed by

Bjorn Andersson 1 year ago 672daf24 a34d21d8

+57 -4

1 changed file

expand all

drivers

clk

qcom

mmcc-msm8960.c

+57 -4

drivers/clk/qcom/mmcc-msm8960.c

··· 37 37 P_DSI2_PLL_DSICLK, 38 38 P_DSI1_PLL_BYTECLK, 39 39 P_DSI2_PLL_BYTECLK, 40 + P_LVDS_PLL, 40 41 }; 41 42 42 43 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } ··· 141 140 static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = { 142 141 { .fw_name = "pxo", .name = "pxo_board" }, 143 142 { .fw_name = "dsi2pll", .name = "dsi2pll" }, 143 + { .fw_name = "dsi1pll", .name = "dsi1pll" }, 144 + }; 145 + 146 + static const struct parent_map mmcc_pxo_dsi2_dsi1_lvds_map[] = { 147 + { P_PXO, 0 }, 148 + { P_DSI2_PLL_DSICLK, 1 }, 149 + { P_LVDS_PLL, 2 }, 150 + { P_DSI1_PLL_DSICLK, 3 }, 151 + }; 152 + 153 + static const struct clk_parent_data mmcc_pxo_dsi2_dsi1_lvds[] = { 154 + { .fw_name = "pxo", .name = "pxo_board" }, 155 + { .fw_name = "dsi2pll", .name = "dsi2pll" }, 156 + { .fw_name = "lvdspll", .name = "mpd4_lvds_pll" }, 144 157 { .fw_name = "dsi1pll", .name = "dsi1pll" }, 145 158 }; 146 159 ··· 2454 2439 }, 2455 2440 .s = { 2456 2441 .src_sel_shift = 0, 2457 - .parent_map = mmcc_pxo_dsi2_dsi1_map, 2442 + .parent_map = mmcc_pxo_dsi2_dsi1_lvds_map, 2458 2443 }, 2459 2444 .clkr = { 2460 2445 .enable_reg = 0x0094, 2461 2446 .enable_mask = BIT(2), 2462 2447 .hw.init = &(struct clk_init_data){ 2463 2448 .name = "dsi2_pixel_src", 2464 - .parent_data = mmcc_pxo_dsi2_dsi1, 2465 - .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2449 + .parent_data = mmcc_pxo_dsi2_dsi1_lvds, 2450 + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1_lvds), 2466 2451 .ops = &clk_rcg_pixel_ops, 2452 + }, 2453 + }, 2454 + }; 2455 + 2456 + static struct clk_branch dsi2_pixel_lvds_src = { 2457 + .clkr = { 2458 + .enable_reg = 0x0094, 2459 + .enable_mask = BIT(0), 2460 + .hw.init = &(struct clk_init_data){ 2461 + .name = "dsi2_pixel_lvds_src", 2462 + .parent_hws = (const struct clk_hw*[]){ 2463 + &dsi2_pixel_src.clkr.hw 2464 + }, 2465 + .num_parents = 1, 2466 + .ops = &clk_branch_simple_ops, 2467 + .flags = CLK_SET_RATE_PARENT, 2467 2468 }, 2468 2469 }, 2469 2470 }; ··· 2489 2458 .halt_bit = 19, 2490 2459 .clkr = { 2491 2460 .enable_reg = 0x0094, 2492 - .enable_mask = BIT(0), 2461 + .enable_mask = 0, 2493 2462 .hw.init = &(struct clk_init_data){ 2494 2463 .name = "mdp_pclk2_clk", 2495 2464 .parent_hws = (const struct clk_hw*[]){ 2496 2465 &dsi2_pixel_src.clkr.hw 2466 + }, 2467 + .num_parents = 1, 2468 + .ops = &clk_branch_ops, 2469 + .flags = CLK_SET_RATE_PARENT, 2470 + }, 2471 + }, 2472 + }; 2473 + 2474 + static struct clk_branch lvds_clk = { 2475 + .halt_reg = 0x024c, 2476 + .halt_bit = 6, 2477 + .clkr = { 2478 + .enable_reg = 0x0264, 2479 + .enable_mask = BIT(1), 2480 + .hw.init = &(struct clk_init_data){ 2481 + .name = "mdp_lvds_clk", 2482 + .parent_hws = (const struct clk_hw*[]){ 2483 + &dsi2_pixel_lvds_src.clkr.hw 2497 2484 }, 2498 2485 .num_parents = 1, 2499 2486 .ops = &clk_branch_ops, ··· 2848 2799 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, 2849 2800 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, 2850 2801 [PLL2] = &pll2.clkr, 2802 + [DSI2_PIXEL_LVDS_SRC] = &dsi2_pixel_lvds_src.clkr, 2803 + [LVDS_CLK] = &lvds_clk.clkr, 2851 2804 }; 2852 2805 2853 2806 static const struct qcom_reset_map mmcc_msm8960_resets[] = { ··· 3034 2983 [VCAP_CLK] = &vcap_clk.clkr, 3035 2984 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr, 3036 2985 [PLL15] = &pll15.clkr, 2986 + [DSI2_PIXEL_LVDS_SRC] = &dsi2_pixel_lvds_src.clkr, 2987 + [LVDS_CLK] = &lvds_clk.clkr, 3037 2988 }; 3038 2989 3039 2990 static const struct qcom_reset_map mmcc_apq8064_resets[] = {

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