+5

drivers/gpu/drm/msm/Makefile

reviewed

··· 195 195 generated/a4xx.xml.h \ 196 196 generated/a5xx.xml.h \ 197 197 generated/a6xx.xml.h \ 198 198 + generated/a6xx_descriptors.xml.h \ 199 199 + generated/a6xx_enums.xml.h \ 200 200 + generated/a6xx_perfcntrs.xml.h \ 201 201 + generated/a7xx_enums.xml.h \ 202 202 + generated/a7xx_perfcntrs.xml.h \ 198 203 generated/a6xx_gmu.xml.h \ 199 204 generated/adreno_common.xml.h \ 200 205 generated/adreno_pm4.xml.h \

+1 -1

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

reviewed

··· 1335 1335 REG_A6XX_RB_NC_MODE_CNTL, 1336 1336 REG_A6XX_RB_CMP_DBG_ECO_CNTL, 1337 1337 REG_A7XX_GRAS_NC_MODE_CNTL, 1338 1338 - REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 1338 1338 + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 1339 1339 REG_A6XX_UCHE_GBIF_GX_CONFIG, 1340 1340 REG_A6XX_UCHE_CLIENT_PF, 1341 1341 REG_A6XX_TPL1_DBG_ECO_CNTL1,

+4

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

reviewed

··· 6 6 7 7 8 8 #include "adreno_gpu.h" 9 9 + #include "a6xx_enums.xml.h" 10 10 + #include "a7xx_enums.xml.h" 11 11 + #include "a6xx_perfcntrs.xml.h" 12 12 + #include "a7xx_perfcntrs.xml.h" 9 13 #include "a6xx.xml.h" 10 14 11 15 #include "a6xx_gmu.h"

+1 -1

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

reviewed

··· 158 158 /* Make sure all pending memory writes are posted */ 159 159 wmb(); 160 160 161 161 - gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE, dumper->iova); 161 161 + gpu_write64(gpu, REG_A6XX_CP_CRASH_DUMP_SCRIPT_BASE, dumper->iova); 162 162 163 163 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); 164 164

+1 -1

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

reviewed

··· 212 212 SHADER(A6XX_SP_LB_5_DATA, 0x200), 213 213 SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800), 214 214 SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280), 215 215 - SHADER(A6XX_SP_UAV_DATA, 0x80), 215 215 + SHADER(A6XX_SP_GFX_UAV_BASE_DATA, 0x80), 216 216 SHADER(A6XX_SP_INST_TAG, 0x80), 217 217 SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80), 218 218 SHADER(A6XX_SP_TMO_UMO_TAG, 0x80),

+1 -1

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

reviewed

··· 210 210 gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0); 211 211 212 212 /* Enable the GMEM save/restore feature for preemption */ 213 213 - gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x1); 213 213 + gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0x1); 214 214 215 215 /* Reset the preemption state */ 216 216 set_preempt_state(a6xx_gpu, PREEMPT_NONE);

+2 -2

drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h

reviewed

··· 1311 1311 REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000}, 1312 1312 { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR, 1313 1313 REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040}, 1314 1314 - { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR, 1315 1315 - REG_A7XX_CP_RESOURCE_TBL_DBG_DATA, 0x04100}, 1314 1314 + { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR, 1315 1315 + REG_A7XX_CP_RESOURCE_TABLE_DBG_DATA, 0x04100}, 1316 1316 { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 1317 1317 REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200}, 1318 1318 { "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR,

+647 -2929

drivers/gpu/drm/msm/registers/adreno/a6xx.xml

reviewed

··· 5 5 <import file="freedreno_copyright.xml"/> 6 6 <import file="adreno/adreno_common.xml"/> 7 7 <import file="adreno/adreno_pm4.xml"/> 8 8 + <import file="adreno/a6xx_enums.xml"/> 9 9 + <import file="adreno/a7xx_enums.xml"/> 10 10 + <import file="adreno/a6xx_perfcntrs.xml"/> 11 11 + <import file="adreno/a7xx_perfcntrs.xml"/> 12 12 + <import file="adreno/a6xx_descriptors.xml"/> 8 13 9 14 <!-- 10 15 Each register that is actually being used by driver should have "usage" defined, ··· 24 19 is either overwritten by renderpass/blit (ib2) or not used if not overwritten 25 20 by a particular renderpass/blit. 26 21 --> 27 27 - 28 28 - <!-- these might be same as a5xx --> 29 29 - <enum name="a6xx_tile_mode"> 30 30 - <value name="TILE6_LINEAR" value="0"/> 31 31 - <value name="TILE6_2" value="2"/> 32 32 - <value name="TILE6_3" value="3"/> 33 33 - </enum> 34 34 - 35 35 - <enum name="a6xx_format"> 36 36 - <value value="0x02" name="FMT6_A8_UNORM"/> 37 37 - <value value="0x03" name="FMT6_8_UNORM"/> 38 38 - <value value="0x04" name="FMT6_8_SNORM"/> 39 39 - <value value="0x05" name="FMT6_8_UINT"/> 40 40 - <value value="0x06" name="FMT6_8_SINT"/> 41 41 - 42 42 - <value value="0x08" name="FMT6_4_4_4_4_UNORM"/> 43 43 - <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/> 44 44 - <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only --> 45 45 - <value value="0x0e" name="FMT6_5_6_5_UNORM"/> 46 46 - 47 47 - <value value="0x0f" name="FMT6_8_8_UNORM"/> 48 48 - <value value="0x10" name="FMT6_8_8_SNORM"/> 49 49 - <value value="0x11" name="FMT6_8_8_UINT"/> 50 50 - <value value="0x12" name="FMT6_8_8_SINT"/> 51 51 - <value value="0x13" name="FMT6_L8_A8_UNORM"/> 52 52 - 53 53 - <value value="0x15" name="FMT6_16_UNORM"/> 54 54 - <value value="0x16" name="FMT6_16_SNORM"/> 55 55 - <value value="0x17" name="FMT6_16_FLOAT"/> 56 56 - <value value="0x18" name="FMT6_16_UINT"/> 57 57 - <value value="0x19" name="FMT6_16_SINT"/> 58 58 - 59 59 - <value value="0x21" name="FMT6_8_8_8_UNORM"/> 60 60 - <value value="0x22" name="FMT6_8_8_8_SNORM"/> 61 61 - <value value="0x23" name="FMT6_8_8_8_UINT"/> 62 62 - <value value="0x24" name="FMT6_8_8_8_SINT"/> 63 63 - 64 64 - <value value="0x30" name="FMT6_8_8_8_8_UNORM"/> 65 65 - <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha --> 66 66 - <value value="0x32" name="FMT6_8_8_8_8_SNORM"/> 67 67 - <value value="0x33" name="FMT6_8_8_8_8_UINT"/> 68 68 - <value value="0x34" name="FMT6_8_8_8_8_SINT"/> 69 69 - 70 70 - <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/> 71 71 - 72 72 - <value value="0x36" name="FMT6_10_10_10_2_UNORM"/> 73 73 - <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/> 74 74 - <value value="0x39" name="FMT6_10_10_10_2_SNORM"/> 75 75 - <value value="0x3a" name="FMT6_10_10_10_2_UINT"/> 76 76 - <value value="0x3b" name="FMT6_10_10_10_2_SINT"/> 77 77 - 78 78 - <value value="0x42" name="FMT6_11_11_10_FLOAT"/> 79 79 - 80 80 - <value value="0x43" name="FMT6_16_16_UNORM"/> 81 81 - <value value="0x44" name="FMT6_16_16_SNORM"/> 82 82 - <value value="0x45" name="FMT6_16_16_FLOAT"/> 83 83 - <value value="0x46" name="FMT6_16_16_UINT"/> 84 84 - <value value="0x47" name="FMT6_16_16_SINT"/> 85 85 - 86 86 - <value value="0x48" name="FMT6_32_UNORM"/> 87 87 - <value value="0x49" name="FMT6_32_SNORM"/> 88 88 - <value value="0x4a" name="FMT6_32_FLOAT"/> 89 89 - <value value="0x4b" name="FMT6_32_UINT"/> 90 90 - <value value="0x4c" name="FMT6_32_SINT"/> 91 91 - <value value="0x4d" name="FMT6_32_FIXED"/> 92 92 - 93 93 - <value value="0x58" name="FMT6_16_16_16_UNORM"/> 94 94 - <value value="0x59" name="FMT6_16_16_16_SNORM"/> 95 95 - <value value="0x5a" name="FMT6_16_16_16_FLOAT"/> 96 96 - <value value="0x5b" name="FMT6_16_16_16_UINT"/> 97 97 - <value value="0x5c" name="FMT6_16_16_16_SINT"/> 98 98 - 99 99 - <value value="0x60" name="FMT6_16_16_16_16_UNORM"/> 100 100 - <value value="0x61" name="FMT6_16_16_16_16_SNORM"/> 101 101 - <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/> 102 102 - <value value="0x63" name="FMT6_16_16_16_16_UINT"/> 103 103 - <value value="0x64" name="FMT6_16_16_16_16_SINT"/> 104 104 - 105 105 - <value value="0x65" name="FMT6_32_32_UNORM"/> 106 106 - <value value="0x66" name="FMT6_32_32_SNORM"/> 107 107 - <value value="0x67" name="FMT6_32_32_FLOAT"/> 108 108 - <value value="0x68" name="FMT6_32_32_UINT"/> 109 109 - <value value="0x69" name="FMT6_32_32_SINT"/> 110 110 - <value value="0x6a" name="FMT6_32_32_FIXED"/> 111 111 - 112 112 - <value value="0x70" name="FMT6_32_32_32_UNORM"/> 113 113 - <value value="0x71" name="FMT6_32_32_32_SNORM"/> 114 114 - <value value="0x72" name="FMT6_32_32_32_UINT"/> 115 115 - <value value="0x73" name="FMT6_32_32_32_SINT"/> 116 116 - <value value="0x74" name="FMT6_32_32_32_FLOAT"/> 117 117 - <value value="0x75" name="FMT6_32_32_32_FIXED"/> 118 118 - 119 119 - <value value="0x80" name="FMT6_32_32_32_32_UNORM"/> 120 120 - <value value="0x81" name="FMT6_32_32_32_32_SNORM"/> 121 121 - <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/> 122 122 - <value value="0x83" name="FMT6_32_32_32_32_UINT"/> 123 123 - <value value="0x84" name="FMT6_32_32_32_32_SINT"/> 124 124 - <value value="0x85" name="FMT6_32_32_32_32_FIXED"/> 125 125 - 126 126 - <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY --> 127 127 - <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV --> 128 128 - <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 --> 129 129 - <value value="0x8f" name="FMT6_NV21"/> 130 130 - <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 --> 131 131 - 132 132 - <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/> 133 133 - 134 134 - <!-- Note: tiling/UBWC for these may be different from equivalent formats 135 135 - For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM 136 136 - --> 137 137 - <value value="0x94" name="FMT6_NV12_Y"/> 138 138 - <value value="0x95" name="FMT6_NV12_UV"/> 139 139 - <value value="0x96" name="FMT6_NV12_VU"/> 140 140 - <value value="0x97" name="FMT6_NV12_4R"/> 141 141 - <value value="0x98" name="FMT6_NV12_4R_Y"/> 142 142 - <value value="0x99" name="FMT6_NV12_4R_UV"/> 143 143 - <value value="0x9a" name="FMT6_P010"/> 144 144 - <value value="0x9b" name="FMT6_P010_Y"/> 145 145 - <value value="0x9c" name="FMT6_P010_UV"/> 146 146 - <value value="0x9d" name="FMT6_TP10"/> 147 147 - <value value="0x9e" name="FMT6_TP10_Y"/> 148 148 - <value value="0x9f" name="FMT6_TP10_UV"/> 149 149 - 150 150 - <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/> 151 151 - 152 152 - <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/> 153 153 - <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/> 154 154 - <value value="0xad" name="FMT6_ETC2_R11_UNORM"/> 155 155 - <value value="0xae" name="FMT6_ETC2_R11_SNORM"/> 156 156 - <value value="0xaf" name="FMT6_ETC1"/> 157 157 - <value value="0xb0" name="FMT6_ETC2_RGB8"/> 158 158 - <value value="0xb1" name="FMT6_ETC2_RGBA8"/> 159 159 - <value value="0xb2" name="FMT6_ETC2_RGB8A1"/> 160 160 - <value value="0xb3" name="FMT6_DXT1"/> 161 161 - <value value="0xb4" name="FMT6_DXT3"/> 162 162 - <value value="0xb5" name="FMT6_DXT5"/> 163 163 - <value value="0xb7" name="FMT6_RGTC1_UNORM"/> 164 164 - <value value="0xb8" name="FMT6_RGTC1_SNORM"/> 165 165 - <value value="0xbb" name="FMT6_RGTC2_UNORM"/> 166 166 - <value value="0xbc" name="FMT6_RGTC2_SNORM"/> 167 167 - <value value="0xbe" name="FMT6_BPTC_UFLOAT"/> 168 168 - <value value="0xbf" name="FMT6_BPTC_FLOAT"/> 169 169 - <value value="0xc0" name="FMT6_BPTC"/> 170 170 - <value value="0xc1" name="FMT6_ASTC_4x4"/> 171 171 - <value value="0xc2" name="FMT6_ASTC_5x4"/> 172 172 - <value value="0xc3" name="FMT6_ASTC_5x5"/> 173 173 - <value value="0xc4" name="FMT6_ASTC_6x5"/> 174 174 - <value value="0xc5" name="FMT6_ASTC_6x6"/> 175 175 - <value value="0xc6" name="FMT6_ASTC_8x5"/> 176 176 - <value value="0xc7" name="FMT6_ASTC_8x6"/> 177 177 - <value value="0xc8" name="FMT6_ASTC_8x8"/> 178 178 - <value value="0xc9" name="FMT6_ASTC_10x5"/> 179 179 - <value value="0xca" name="FMT6_ASTC_10x6"/> 180 180 - <value value="0xcb" name="FMT6_ASTC_10x8"/> 181 181 - <value value="0xcc" name="FMT6_ASTC_10x10"/> 182 182 - <value value="0xcd" name="FMT6_ASTC_12x10"/> 183 183 - <value value="0xce" name="FMT6_ASTC_12x12"/> 184 184 - 185 185 - <!-- for sampling stencil (integer, 2nd channel), not available on a630 --> 186 186 - <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/> 187 187 - 188 188 - <!-- Not a hw enum, used internally in driver --> 189 189 - <value value="0xff" name="FMT6_NONE"/> 190 190 - 191 191 - </enum> 192 192 - 193 193 - <!-- probably same as a5xx --> 194 194 - <enum name="a6xx_polygon_mode"> 195 195 - <value name="POLYMODE6_POINTS" value="1"/> 196 196 - <value name="POLYMODE6_LINES" value="2"/> 197 197 - <value name="POLYMODE6_TRIANGLES" value="3"/> 198 198 - </enum> 199 199 - 200 200 - <enum name="a6xx_depth_format"> 201 201 - <value name="DEPTH6_NONE" value="0"/> 202 202 - <value name="DEPTH6_16" value="1"/> 203 203 - <value name="DEPTH6_24_8" value="2"/> 204 204 - <value name="DEPTH6_32" value="4"/> 205 205 - </enum> 206 206 - 207 207 - <bitset name="a6x_cp_protect" inline="yes"> 208 208 - <bitfield name="BASE_ADDR" low="0" high="17"/> 209 209 - <bitfield name="MASK_LEN" low="18" high="30"/> 210 210 - <bitfield name="READ" pos="31" type="boolean"/> 211 211 - </bitset> 212 212 - 213 213 - <enum name="a6xx_shader_id"> 214 214 - <value value="0x9" name="A6XX_TP0_TMO_DATA"/> 215 215 - <value value="0xa" name="A6XX_TP0_SMO_DATA"/> 216 216 - <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/> 217 217 - <value value="0x19" name="A6XX_TP1_TMO_DATA"/> 218 218 - <value value="0x1a" name="A6XX_TP1_SMO_DATA"/> 219 219 - <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/> 220 220 - <value value="0x29" name="A6XX_SP_INST_DATA"/> 221 221 - <value value="0x2a" name="A6XX_SP_LB_0_DATA"/> 222 222 - <value value="0x2b" name="A6XX_SP_LB_1_DATA"/> 223 223 - <value value="0x2c" name="A6XX_SP_LB_2_DATA"/> 224 224 - <value value="0x2d" name="A6XX_SP_LB_3_DATA"/> 225 225 - <value value="0x2e" name="A6XX_SP_LB_4_DATA"/> 226 226 - <value value="0x2f" name="A6XX_SP_LB_5_DATA"/> 227 227 - <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/> 228 228 - <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/> 229 229 - <value value="0x32" name="A6XX_SP_UAV_DATA"/> 230 230 - <value value="0x33" name="A6XX_SP_INST_TAG"/> 231 231 - <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/> 232 232 - <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/> 233 233 - <value value="0x36" name="A6XX_SP_SMO_TAG"/> 234 234 - <value value="0x37" name="A6XX_SP_STATE_DATA"/> 235 235 - <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/> 236 236 - <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/> 237 237 - <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/> 238 238 - <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/> 239 239 - <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> 240 240 - <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> 241 241 - <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/> 242 242 - <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/> 243 243 - <value value="0x52" name="A6XX_HLSQ_INST_RAM"/> 244 244 - <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/> 245 245 - <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/> 246 246 - <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/> 247 247 - <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/> 248 248 - <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/> 249 249 - <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> 250 250 - <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> 251 251 - <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/> 252 252 - <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/> 253 253 - <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/> 254 254 - <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/> 255 255 - <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/> 256 256 - <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/> 257 257 - <value value="0x70" name="A6XX_SP_LB_6_DATA"/> 258 258 - <value value="0x71" name="A6XX_SP_LB_7_DATA"/> 259 259 - <value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/> 260 260 - </enum> 261 261 - 262 262 - <enum name="a7xx_statetype_id"> 263 263 - <value value="0" name="A7XX_TP0_NCTX_REG"/> 264 264 - <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/> 265 265 - <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/> 266 266 - <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/> 267 267 - <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/> 268 268 - <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/> 269 269 - <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/> 270 270 - <value value="9" name="A7XX_TP0_TMO_DATA"/> 271 271 - <value value="10" name="A7XX_TP0_SMO_DATA"/> 272 272 - <value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/> 273 273 - <value value="32" name="A7XX_SP_NCTX_REG"/> 274 274 - <value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/> 275 275 - <value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/> 276 276 - <value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/> 277 277 - <value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/> 278 278 - <value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/> 279 279 - <value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/> 280 280 - <value value="39" name="A7XX_SP_INST_DATA"/> 281 281 - <value value="40" name="A7XX_SP_INST_DATA_1"/> 282 282 - <value value="41" name="A7XX_SP_LB_0_DATA"/> 283 283 - <value value="42" name="A7XX_SP_LB_1_DATA"/> 284 284 - <value value="43" name="A7XX_SP_LB_2_DATA"/> 285 285 - <value value="44" name="A7XX_SP_LB_3_DATA"/> 286 286 - <value value="45" name="A7XX_SP_LB_4_DATA"/> 287 287 - <value value="46" name="A7XX_SP_LB_5_DATA"/> 288 288 - <value value="47" name="A7XX_SP_LB_6_DATA"/> 289 289 - <value value="48" name="A7XX_SP_LB_7_DATA"/> 290 290 - <value value="49" name="A7XX_SP_CB_RAM"/> 291 291 - <value value="50" name="A7XX_SP_LB_13_DATA"/> 292 292 - <value value="51" name="A7XX_SP_LB_14_DATA"/> 293 293 - <value value="52" name="A7XX_SP_INST_TAG"/> 294 294 - <value value="53" name="A7XX_SP_INST_DATA_2"/> 295 295 - <value value="54" name="A7XX_SP_TMO_TAG"/> 296 296 - <value value="55" name="A7XX_SP_SMO_TAG"/> 297 297 - <value value="56" name="A7XX_SP_STATE_DATA"/> 298 298 - <value value="57" name="A7XX_SP_HWAVE_RAM"/> 299 299 - <value value="58" name="A7XX_SP_L0_INST_BUF"/> 300 300 - <value value="59" name="A7XX_SP_LB_8_DATA"/> 301 301 - <value value="60" name="A7XX_SP_LB_9_DATA"/> 302 302 - <value value="61" name="A7XX_SP_LB_10_DATA"/> 303 303 - <value value="62" name="A7XX_SP_LB_11_DATA"/> 304 304 - <value value="63" name="A7XX_SP_LB_12_DATA"/> 305 305 - <value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/> 306 306 - <value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/> 307 307 - <value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/> 308 308 - <value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/> 309 309 - <value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/> 310 310 - <value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/> 311 311 - <value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/> 312 312 - <value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/> 313 313 - <value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/> 314 314 - <value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/> 315 315 - <value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/> 316 316 - <value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> 317 317 - <value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> 318 318 - <value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/> 319 319 - <value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/> 320 320 - <value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/> 321 321 - <value value="82" name="A7XX_HLSQ_INST_RAM"/> 322 322 - <value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/> 323 323 - <value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/> 324 324 - <value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/> 325 325 - <value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/> 326 326 - <value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/> 327 327 - <value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> 328 328 - <value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> 329 329 - <value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/> 330 330 - <value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/> 331 331 - <value value="92" name="A7XX_HLSQ_INST_RAM_1"/> 332 332 - <value value="93" name="A7XX_HLSQ_STPROC_META"/> 333 333 - <value value="94" name="A7XX_HLSQ_BV_BE_META"/> 334 334 - <value value="95" name="A7XX_HLSQ_INST_RAM_2"/> 335 335 - <value value="96" name="A7XX_HLSQ_DATAPATH_META"/> 336 336 - <value value="97" name="A7XX_HLSQ_FRONTEND_META"/> 337 337 - <value value="98" name="A7XX_HLSQ_INDIRECT_META"/> 338 338 - <value value="99" name="A7XX_HLSQ_BACKEND_META"/> 339 339 - </enum> 340 340 - 341 341 - <enum name="a6xx_debugbus_id"> 342 342 - <value value="0x1" name="A6XX_DBGBUS_CP"/> 343 343 - <value value="0x2" name="A6XX_DBGBUS_RBBM"/> 344 344 - <value value="0x3" name="A6XX_DBGBUS_VBIF"/> 345 345 - <value value="0x4" name="A6XX_DBGBUS_HLSQ"/> 346 346 - <value value="0x5" name="A6XX_DBGBUS_UCHE"/> 347 347 - <value value="0x6" name="A6XX_DBGBUS_DPM"/> 348 348 - <value value="0x7" name="A6XX_DBGBUS_TESS"/> 349 349 - <value value="0x8" name="A6XX_DBGBUS_PC"/> 350 350 - <value value="0x9" name="A6XX_DBGBUS_VFDP"/> 351 351 - <value value="0xa" name="A6XX_DBGBUS_VPC"/> 352 352 - <value value="0xb" name="A6XX_DBGBUS_TSE"/> 353 353 - <value value="0xc" name="A6XX_DBGBUS_RAS"/> 354 354 - <value value="0xd" name="A6XX_DBGBUS_VSC"/> 355 355 - <value value="0xe" name="A6XX_DBGBUS_COM"/> 356 356 - <value value="0x10" name="A6XX_DBGBUS_LRZ"/> 357 357 - <value value="0x11" name="A6XX_DBGBUS_A2D"/> 358 358 - <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/> 359 359 - <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/> 360 360 - <value value="0x14" name="A6XX_DBGBUS_RBP"/> 361 361 - <value value="0x15" name="A6XX_DBGBUS_DCS"/> 362 362 - <value value="0x16" name="A6XX_DBGBUS_DBGC"/> 363 363 - <value value="0x17" name="A6XX_DBGBUS_CX"/> 364 364 - <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/> 365 365 - <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/> 366 366 - <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/> 367 367 - <value value="0x1d" name="A6XX_DBGBUS_GPC"/> 368 368 - <value value="0x1e" name="A6XX_DBGBUS_LARC"/> 369 369 - <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/> 370 370 - <value value="0x20" name="A6XX_DBGBUS_RB_0"/> 371 371 - <value value="0x21" name="A6XX_DBGBUS_RB_1"/> 372 372 - <value value="0x22" name="A6XX_DBGBUS_RB_2"/> 373 373 - <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/> 374 374 - <value value="0x28" name="A6XX_DBGBUS_CCU_0"/> 375 375 - <value value="0x29" name="A6XX_DBGBUS_CCU_1"/> 376 376 - <value value="0x2a" name="A6XX_DBGBUS_CCU_2"/> 377 377 - <value value="0x38" name="A6XX_DBGBUS_VFD_0"/> 378 378 - <value value="0x39" name="A6XX_DBGBUS_VFD_1"/> 379 379 - <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/> 380 380 - <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/> 381 381 - <value value="0x3c" name="A6XX_DBGBUS_VFD_4"/> 382 382 - <value value="0x3d" name="A6XX_DBGBUS_VFD_5"/> 383 383 - <value value="0x40" name="A6XX_DBGBUS_SP_0"/> 384 384 - <value value="0x41" name="A6XX_DBGBUS_SP_1"/> 385 385 - <value value="0x42" name="A6XX_DBGBUS_SP_2"/> 386 386 - <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/> 387 387 - <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/> 388 388 - <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/> 389 389 - <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/> 390 390 - <value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/> 391 391 - <value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/> 392 392 - <value value="0x58" name="A6XX_DBGBUS_SPTP_0"/> 393 393 - <value value="0x59" name="A6XX_DBGBUS_SPTP_1"/> 394 394 - <value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/> 395 395 - <value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/> 396 396 - <value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/> 397 397 - <value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/> 398 398 - </enum> 399 399 - 400 400 - <enum name="a7xx_state_location"> 401 401 - <value value="0" name="A7XX_HLSQ_STATE"/> 402 402 - <value value="1" name="A7XX_HLSQ_DP"/> 403 403 - <value value="2" name="A7XX_SP_TOP"/> 404 404 - <value value="3" name="A7XX_USPTP"/> 405 405 - <value value="4" name="A7XX_HLSQ_DP_STR"/> 406 406 - </enum> 407 407 - 408 408 - <enum name="a7xx_pipe"> 409 409 - <value value="0" name="A7XX_PIPE_NONE"/> 410 410 - <value value="1" name="A7XX_PIPE_BR"/> 411 411 - <value value="2" name="A7XX_PIPE_BV"/> 412 412 - <value value="3" name="A7XX_PIPE_LPAC"/> 413 413 - </enum> 414 414 - 415 415 - <enum name="a7xx_cluster"> 416 416 - <value value="0" name="A7XX_CLUSTER_NONE"/> 417 417 - <value value="1" name="A7XX_CLUSTER_FE"/> 418 418 - <value value="2" name="A7XX_CLUSTER_SP_VS"/> 419 419 - <value value="3" name="A7XX_CLUSTER_PC_VS"/> 420 420 - <value value="4" name="A7XX_CLUSTER_GRAS"/> 421 421 - <value value="5" name="A7XX_CLUSTER_SP_PS"/> 422 422 - <value value="6" name="A7XX_CLUSTER_VPC_PS"/> 423 423 - <value value="7" name="A7XX_CLUSTER_PS"/> 424 424 - </enum> 425 425 - 426 426 - <enum name="a7xx_debugbus_id"> 427 427 - <value value="1" name="A7XX_DBGBUS_CP_0_0"/> 428 428 - <value value="2" name="A7XX_DBGBUS_CP_0_1"/> 429 429 - <value value="3" name="A7XX_DBGBUS_RBBM"/> 430 430 - <value value="5" name="A7XX_DBGBUS_GBIF_GX"/> 431 431 - <value value="6" name="A7XX_DBGBUS_GBIF_CX"/> 432 432 - <value value="7" name="A7XX_DBGBUS_HLSQ"/> 433 433 - <value value="9" name="A7XX_DBGBUS_UCHE_0"/> 434 434 - <value value="10" name="A7XX_DBGBUS_UCHE_1"/> 435 435 - <value value="13" name="A7XX_DBGBUS_TESS_BR"/> 436 436 - <value value="14" name="A7XX_DBGBUS_TESS_BV"/> 437 437 - <value value="17" name="A7XX_DBGBUS_PC_BR"/> 438 438 - <value value="18" name="A7XX_DBGBUS_PC_BV"/> 439 439 - <value value="21" name="A7XX_DBGBUS_VFDP_BR"/> 440 440 - <value value="22" name="A7XX_DBGBUS_VFDP_BV"/> 441 441 - <value value="25" name="A7XX_DBGBUS_VPC_BR"/> 442 442 - <value value="26" name="A7XX_DBGBUS_VPC_BV"/> 443 443 - <value value="29" name="A7XX_DBGBUS_TSE_BR"/> 444 444 - <value value="30" name="A7XX_DBGBUS_TSE_BV"/> 445 445 - <value value="33" name="A7XX_DBGBUS_RAS_BR"/> 446 446 - <value value="34" name="A7XX_DBGBUS_RAS_BV"/> 447 447 - <value value="37" name="A7XX_DBGBUS_VSC"/> 448 448 - <value value="39" name="A7XX_DBGBUS_COM_0"/> 449 449 - <value value="43" name="A7XX_DBGBUS_LRZ_BR"/> 450 450 - <value value="44" name="A7XX_DBGBUS_LRZ_BV"/> 451 451 - <value value="47" name="A7XX_DBGBUS_UFC_0"/> 452 452 - <value value="48" name="A7XX_DBGBUS_UFC_1"/> 453 453 - <value value="55" name="A7XX_DBGBUS_GMU_GX"/> 454 454 - <value value="59" name="A7XX_DBGBUS_DBGC"/> 455 455 - <value value="60" name="A7XX_DBGBUS_CX"/> 456 456 - <value value="61" name="A7XX_DBGBUS_GMU_CX"/> 457 457 - <value value="62" name="A7XX_DBGBUS_GPC_BR"/> 458 458 - <value value="63" name="A7XX_DBGBUS_GPC_BV"/> 459 459 - <value value="66" name="A7XX_DBGBUS_LARC"/> 460 460 - <value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/> 461 461 - <value value="70" name="A7XX_DBGBUS_RB_0"/> 462 462 - <value value="71" name="A7XX_DBGBUS_RB_1"/> 463 463 - <value value="72" name="A7XX_DBGBUS_RB_2"/> 464 464 - <value value="73" name="A7XX_DBGBUS_RB_3"/> 465 465 - <value value="74" name="A7XX_DBGBUS_RB_4"/> 466 466 - <value value="75" name="A7XX_DBGBUS_RB_5"/> 467 467 - <value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/> 468 468 - <value value="106" name="A7XX_DBGBUS_CCU_0"/> 469 469 - <value value="107" name="A7XX_DBGBUS_CCU_1"/> 470 470 - <value value="108" name="A7XX_DBGBUS_CCU_2"/> 471 471 - <value value="109" name="A7XX_DBGBUS_CCU_3"/> 472 472 - <value value="110" name="A7XX_DBGBUS_CCU_4"/> 473 473 - <value value="111" name="A7XX_DBGBUS_CCU_5"/> 474 474 - <value value="138" name="A7XX_DBGBUS_VFD_BR_0"/> 475 475 - <value value="139" name="A7XX_DBGBUS_VFD_BR_1"/> 476 476 - <value value="140" name="A7XX_DBGBUS_VFD_BR_2"/> 477 477 - <value value="141" name="A7XX_DBGBUS_VFD_BR_3"/> 478 478 - <value value="142" name="A7XX_DBGBUS_VFD_BR_4"/> 479 479 - <value value="143" name="A7XX_DBGBUS_VFD_BR_5"/> 480 480 - <value value="144" name="A7XX_DBGBUS_VFD_BR_6"/> 481 481 - <value value="145" name="A7XX_DBGBUS_VFD_BR_7"/> 482 482 - <value value="202" name="A7XX_DBGBUS_VFD_BV_0"/> 483 483 - <value value="203" name="A7XX_DBGBUS_VFD_BV_1"/> 484 484 - <value value="204" name="A7XX_DBGBUS_VFD_BV_2"/> 485 485 - <value value="205" name="A7XX_DBGBUS_VFD_BV_3"/> 486 486 - <value value="234" name="A7XX_DBGBUS_USP_0"/> 487 487 - <value value="235" name="A7XX_DBGBUS_USP_1"/> 488 488 - <value value="236" name="A7XX_DBGBUS_USP_2"/> 489 489 - <value value="237" name="A7XX_DBGBUS_USP_3"/> 490 490 - <value value="238" name="A7XX_DBGBUS_USP_4"/> 491 491 - <value value="239" name="A7XX_DBGBUS_USP_5"/> 492 492 - <value value="266" name="A7XX_DBGBUS_TP_0"/> 493 493 - <value value="267" name="A7XX_DBGBUS_TP_1"/> 494 494 - <value value="268" name="A7XX_DBGBUS_TP_2"/> 495 495 - <value value="269" name="A7XX_DBGBUS_TP_3"/> 496 496 - <value value="270" name="A7XX_DBGBUS_TP_4"/> 497 497 - <value value="271" name="A7XX_DBGBUS_TP_5"/> 498 498 - <value value="272" name="A7XX_DBGBUS_TP_6"/> 499 499 - <value value="273" name="A7XX_DBGBUS_TP_7"/> 500 500 - <value value="274" name="A7XX_DBGBUS_TP_8"/> 501 501 - <value value="275" name="A7XX_DBGBUS_TP_9"/> 502 502 - <value value="276" name="A7XX_DBGBUS_TP_10"/> 503 503 - <value value="277" name="A7XX_DBGBUS_TP_11"/> 504 504 - <value value="330" name="A7XX_DBGBUS_USPTP_0"/> 505 505 - <value value="331" name="A7XX_DBGBUS_USPTP_1"/> 506 506 - <value value="332" name="A7XX_DBGBUS_USPTP_2"/> 507 507 - <value value="333" name="A7XX_DBGBUS_USPTP_3"/> 508 508 - <value value="334" name="A7XX_DBGBUS_USPTP_4"/> 509 509 - <value value="335" name="A7XX_DBGBUS_USPTP_5"/> 510 510 - <value value="336" name="A7XX_DBGBUS_USPTP_6"/> 511 511 - <value value="337" name="A7XX_DBGBUS_USPTP_7"/> 512 512 - <value value="338" name="A7XX_DBGBUS_USPTP_8"/> 513 513 - <value value="339" name="A7XX_DBGBUS_USPTP_9"/> 514 514 - <value value="340" name="A7XX_DBGBUS_USPTP_10"/> 515 515 - <value value="341" name="A7XX_DBGBUS_USPTP_11"/> 516 516 - <value value="396" name="A7XX_DBGBUS_CCHE_0"/> 517 517 - <value value="397" name="A7XX_DBGBUS_CCHE_1"/> 518 518 - <value value="398" name="A7XX_DBGBUS_CCHE_2"/> 519 519 - <value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/> 520 520 - <value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/> 521 521 - <value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/> 522 522 - <value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/> 523 523 - <value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/> 524 524 - <value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/> 525 525 - <value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/> 526 526 - <value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/> 527 527 - <value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/> 528 528 - <value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/> 529 529 - <value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/> 530 530 - <value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/> 531 531 - <value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/> 532 532 - <value value="447" name="A7XX_DBGBUS_CGC_CORE"/> 533 533 - </enum> 534 534 - 535 535 - <enum name="a6xx_cp_perfcounter_select"> 536 536 - <value value="0" name="PERF_CP_ALWAYS_COUNT"/> 537 537 - <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> 538 538 - <value value="2" name="PERF_CP_BUSY_CYCLES"/> 539 539 - <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> 540 540 - <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> 541 541 - <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 542 542 - <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 543 543 - <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 544 544 - <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> 545 545 - <value value="9" name="PERF_CP_MODE_SWITCH"/> 546 546 - <value value="10" name="PERF_CP_ZPASS_DONE"/> 547 547 - <value value="11" name="PERF_CP_CONTEXT_DONE"/> 548 548 - <value value="12" name="PERF_CP_CACHE_FLUSH"/> 549 549 - <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/> 550 550 - <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/> 551 551 - <value value="15" name="PERF_CP_SQE_IDLE"/> 552 552 - <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/> 553 553 - <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/> 554 554 - <value value="18" name="PERF_CP_SQE_MRB_STARVE"/> 555 555 - <value value="19" name="PERF_CP_SQE_RRB_STARVE"/> 556 556 - <value value="20" name="PERF_CP_SQE_VSD_STARVE"/> 557 557 - <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/> 558 558 - <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/> 559 559 - <value value="23" name="PERF_CP_SQE_SYNC_STALL"/> 560 560 - <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/> 561 561 - <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/> 562 562 - <value value="26" name="PERF_CP_SQE_T4_EXEC"/> 563 563 - <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/> 564 564 - <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/> 565 565 - <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/> 566 566 - <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> 567 567 - <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/> 568 568 - <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/> 569 569 - <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/> 570 570 - <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> 571 571 - <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> 572 572 - <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/> 573 573 - <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/> 574 574 - <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/> 575 575 - <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/> 576 576 - <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/> 577 577 - <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/> 578 578 - <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/> 579 579 - <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/> 580 580 - <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/> 581 581 - <value value="45" name="PERF_CP_PM4_DATA"/> 582 582 - <value value="46" name="PERF_CP_PM4_HEADERS"/> 583 583 - <value value="47" name="PERF_CP_VBIF_READ_BEATS"/> 584 584 - <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/> 585 585 - <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/> 586 586 - </enum> 587 587 - 588 588 - <enum name="a6xx_rbbm_perfcounter_select"> 589 589 - <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> 590 590 - <value value="1" name="PERF_RBBM_ALWAYS_ON"/> 591 591 - <value value="2" name="PERF_RBBM_TSE_BUSY"/> 592 592 - <value value="3" name="PERF_RBBM_RAS_BUSY"/> 593 593 - <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> 594 594 - <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> 595 595 - <value value="6" name="PERF_RBBM_STATUS_MASKED"/> 596 596 - <value value="7" name="PERF_RBBM_COM_BUSY"/> 597 597 - <value value="8" name="PERF_RBBM_DCOM_BUSY"/> 598 598 - <value value="9" name="PERF_RBBM_VBIF_BUSY"/> 599 599 - <value value="10" name="PERF_RBBM_VSC_BUSY"/> 600 600 - <value value="11" name="PERF_RBBM_TESS_BUSY"/> 601 601 - <value value="12" name="PERF_RBBM_UCHE_BUSY"/> 602 602 - <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> 603 603 - </enum> 604 604 - 605 605 - <enum name="a6xx_pc_perfcounter_select"> 606 606 - <value value="0" name="PERF_PC_BUSY_CYCLES"/> 607 607 - <value value="1" name="PERF_PC_WORKING_CYCLES"/> 608 608 - <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> 609 609 - <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> 610 610 - <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> 611 611 - <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> 612 612 - <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> 613 613 - <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> 614 614 - <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> 615 615 - <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> 616 616 - <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> 617 617 - <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> 618 618 - <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> 619 619 - <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> 620 620 - <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> 621 621 - <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> 622 622 - <value value="16" name="PERF_PC_INSTANCES"/> 623 623 - <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> 624 624 - <value value="18" name="PERF_PC_DEAD_PRIM"/> 625 625 - <value value="19" name="PERF_PC_LIVE_PRIM"/> 626 626 - <value value="20" name="PERF_PC_VERTEX_HITS"/> 627 627 - <value value="21" name="PERF_PC_IA_VERTICES"/> 628 628 - <value value="22" name="PERF_PC_IA_PRIMITIVES"/> 629 629 - <value value="23" name="PERF_PC_GS_PRIMITIVES"/> 630 630 - <value value="24" name="PERF_PC_HS_INVOCATIONS"/> 631 631 - <value value="25" name="PERF_PC_DS_INVOCATIONS"/> 632 632 - <value value="26" name="PERF_PC_VS_INVOCATIONS"/> 633 633 - <value value="27" name="PERF_PC_GS_INVOCATIONS"/> 634 634 - <value value="28" name="PERF_PC_DS_PRIMITIVES"/> 635 635 - <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> 636 636 - <value value="30" name="PERF_PC_3D_DRAWCALLS"/> 637 637 - <value value="31" name="PERF_PC_2D_DRAWCALLS"/> 638 638 - <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> 639 639 - <value value="33" name="PERF_TESS_BUSY_CYCLES"/> 640 640 - <value value="34" name="PERF_TESS_WORKING_CYCLES"/> 641 641 - <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> 642 642 - <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> 643 643 - <value value="37" name="PERF_PC_TSE_TRANSACTION"/> 644 644 - <value value="38" name="PERF_PC_TSE_VERTEX"/> 645 645 - <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/> 646 646 - <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/> 647 647 - <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/> 648 648 - </enum> 649 649 - 650 650 - <enum name="a6xx_vfd_perfcounter_select"> 651 651 - <value value="0" name="PERF_VFD_BUSY_CYCLES"/> 652 652 - <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> 653 653 - <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> 654 654 - <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> 655 655 - <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> 656 656 - <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/> 657 657 - <value value="6" name="PERF_VFD_RBUFFER_FULL"/> 658 658 - <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> 659 659 - <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> 660 660 - <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/> 661 661 - <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/> 662 662 - <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/> 663 663 - <value value="12" name="PERF_VFD_MODE_0_FIBERS"/> 664 664 - <value value="13" name="PERF_VFD_MODE_1_FIBERS"/> 665 665 - <value value="14" name="PERF_VFD_MODE_2_FIBERS"/> 666 666 - <value value="15" name="PERF_VFD_MODE_3_FIBERS"/> 667 667 - <value value="16" name="PERF_VFD_MODE_4_FIBERS"/> 668 668 - <value value="17" name="PERF_VFD_TOTAL_VERTICES"/> 669 669 - <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/> 670 670 - <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> 671 671 - <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> 672 672 - <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/> 673 673 - <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/> 674 674 - </enum> 675 675 - 676 676 - <enum name="a6xx_hlsq_perfcounter_select"> 677 677 - <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> 678 678 - <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> 679 679 - <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> 680 680 - <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> 681 681 - <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> 682 682 - <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> 683 683 - <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/> 684 684 - <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/> 685 685 - <value value="8" name="PERF_HLSQ_QUADS"/> 686 686 - <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/> 687 687 - <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> 688 688 - <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> 689 689 - <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> 690 690 - <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> 691 691 - <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> 692 692 - <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> 693 693 - <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> 694 694 - <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> 695 695 - <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/> 696 696 - <value value="19" name="PERF_HLSQ_PIXELS"/> 697 697 - <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> 698 698 - </enum> 699 699 - 700 700 - <enum name="a6xx_vpc_perfcounter_select"> 701 701 - <value value="0" name="PERF_VPC_BUSY_CYCLES"/> 702 702 - <value value="1" name="PERF_VPC_WORKING_CYCLES"/> 703 703 - <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> 704 704 - <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> 705 705 - <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> 706 706 - <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> 707 707 - <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> 708 708 - <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/> 709 709 - <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/> 710 710 - <value value="9" name="PERF_VPC_PC_PRIMITIVES"/> 711 711 - <value value="10" name="PERF_VPC_SP_COMPONENTS"/> 712 712 - <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> 713 713 - <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> 714 714 - <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/> 715 715 - <value value="14" name="PERF_VPC_LM_TRANSACTION"/> 716 716 - <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/> 717 717 - <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/> 718 718 - <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/> 719 719 - <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/> 720 720 - <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/> 721 721 - <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/> 722 722 - <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/> 723 723 - <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/> 724 724 - <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/> 725 725 - <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> 726 726 - <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/> 727 727 - <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/> 728 728 - <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/> 729 729 - </enum> 730 730 - 731 731 - <enum name="a6xx_tse_perfcounter_select"> 732 732 - <value value="0" name="PERF_TSE_BUSY_CYCLES"/> 733 733 - <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> 734 734 - <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> 735 735 - <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> 736 736 - <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> 737 737 - <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> 738 738 - <value value="6" name="PERF_TSE_INPUT_PRIM"/> 739 739 - <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> 740 740 - <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> 741 741 - <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> 742 742 - <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> 743 743 - <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> 744 744 - <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> 745 745 - <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> 746 746 - <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> 747 747 - <value value="15" name="PERF_TSE_CINVOCATION"/> 748 748 - <value value="16" name="PERF_TSE_CPRIMITIVES"/> 749 749 - <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> 750 750 - <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/> 751 751 - <value value="19" name="PERF_TSE_CLIP_PLANES"/> 752 752 - </enum> 753 753 - 754 754 - <enum name="a6xx_ras_perfcounter_select"> 755 755 - <value value="0" name="PERF_RAS_BUSY_CYCLES"/> 756 756 - <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> 757 757 - <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> 758 758 - <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> 759 759 - <value value="4" name="PERF_RAS_SUPER_TILES"/> 760 760 - <value value="5" name="PERF_RAS_8X4_TILES"/> 761 761 - <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> 762 762 - <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> 763 763 - <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> 764 764 - <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> 765 765 - <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> 766 766 - <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> 767 767 - <value value="12" name="PERF_RAS_BLOCKS"/> 768 768 - </enum> 769 769 - 770 770 - <enum name="a6xx_uche_perfcounter_select"> 771 771 - <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> 772 772 - <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/> 773 773 - <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> 774 774 - <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> 775 775 - <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> 776 776 - <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> 777 777 - <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> 778 778 - <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> 779 779 - <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> 780 780 - <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> 781 781 - <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> 782 782 - <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> 783 783 - <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> 784 784 - <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> 785 785 - <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> 786 786 - <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> 787 787 - <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> 788 788 - <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> 789 789 - <value value="18" name="PERF_UCHE_EVICTS"/> 790 790 - <value value="19" name="PERF_UCHE_BANK_REQ0"/> 791 791 - <value value="20" name="PERF_UCHE_BANK_REQ1"/> 792 792 - <value value="21" name="PERF_UCHE_BANK_REQ2"/> 793 793 - <value value="22" name="PERF_UCHE_BANK_REQ3"/> 794 794 - <value value="23" name="PERF_UCHE_BANK_REQ4"/> 795 795 - <value value="24" name="PERF_UCHE_BANK_REQ5"/> 796 796 - <value value="25" name="PERF_UCHE_BANK_REQ6"/> 797 797 - <value value="26" name="PERF_UCHE_BANK_REQ7"/> 798 798 - <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> 799 799 - <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> 800 800 - <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> 801 801 - <value value="30" name="PERF_UCHE_TPH_REF_FULL"/> 802 802 - <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/> 803 803 - <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/> 804 804 - <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/> 805 805 - <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/> 806 806 - <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/> 807 807 - <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/> 808 808 - <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/> 809 809 - <value value="38" name="PERF_UCHE_RAM_READ_REQ"/> 810 810 - <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/> 811 811 - </enum> 812 812 - 813 813 - <enum name="a6xx_tp_perfcounter_select"> 814 814 - <value value="0" name="PERF_TP_BUSY_CYCLES"/> 815 815 - <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> 816 816 - <value value="2" name="PERF_TP_LATENCY_CYCLES"/> 817 817 - <value value="3" name="PERF_TP_LATENCY_TRANS"/> 818 818 - <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> 819 819 - <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> 820 820 - <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> 821 821 - <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> 822 822 - <value value="8" name="PERF_TP_SP_TP_TRANS"/> 823 823 - <value value="9" name="PERF_TP_TP_SP_TRANS"/> 824 824 - <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> 825 825 - <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> 826 826 - <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> 827 827 - <value value="13" name="PERF_TP_QUADS_RECEIVED"/> 828 828 - <value value="14" name="PERF_TP_QUADS_OFFSET"/> 829 829 - <value value="15" name="PERF_TP_QUADS_SHADOW"/> 830 830 - <value value="16" name="PERF_TP_QUADS_ARRAY"/> 831 831 - <value value="17" name="PERF_TP_QUADS_GRADIENT"/> 832 832 - <value value="18" name="PERF_TP_QUADS_1D"/> 833 833 - <value value="19" name="PERF_TP_QUADS_2D"/> 834 834 - <value value="20" name="PERF_TP_QUADS_BUFFER"/> 835 835 - <value value="21" name="PERF_TP_QUADS_3D"/> 836 836 - <value value="22" name="PERF_TP_QUADS_CUBE"/> 837 837 - <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> 838 838 - <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> 839 839 - <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/> 840 840 - <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> 841 841 - <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/> 842 842 - <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> 843 843 - <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> 844 844 - <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/> 845 845 - <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/> 846 846 - <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/> 847 847 - <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/> 848 848 - <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> 849 849 - <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> 850 850 - <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> 851 851 - <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> 852 852 - <value value="38" name="PERF_TP_TPA2TPC_TRANS"/> 853 853 - <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/> 854 854 - <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/> 855 855 - <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/> 856 856 - <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/> 857 857 - <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/> 858 858 - <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/> 859 859 - <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> 860 860 - <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/> 861 861 - <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> 862 862 - <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/> 863 863 - <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/> 864 864 - <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> 865 865 - <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> 866 866 - <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/> 867 867 - <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/> 868 868 - <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> 869 869 - <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/> 870 870 - <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/> 871 871 - </enum> 872 872 - 873 873 - <enum name="a6xx_sp_perfcounter_select"> 874 874 - <value value="0" name="PERF_SP_BUSY_CYCLES"/> 875 875 - <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> 876 876 - <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> 877 877 - <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> 878 878 - <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> 879 879 - <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> 880 880 - <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> 881 881 - <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/> 882 882 - <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> 883 883 - <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> 884 884 - <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> 885 885 - <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> 886 886 - <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> 887 887 - <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> 888 888 - <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> 889 889 - <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> 890 890 - <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> 891 891 - <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> 892 892 - <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> 893 893 - <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> 894 894 - <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> 895 895 - <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> 896 896 - <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> 897 897 - <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> 898 898 - <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> 899 899 - <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> 900 900 - <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> 901 901 - <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> 902 902 - <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> 903 903 - <value value="29" name="PERF_SP_LM_ATOMICS"/> 904 904 - <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> 905 905 - <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> 906 906 - <value value="32" name="PERF_SP_GM_ATOMICS"/> 907 907 - <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> 908 908 - <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> 909 909 - <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> 910 910 - <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> 911 911 - <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> 912 912 - <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> 913 913 - <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> 914 914 - <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> 915 915 - <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> 916 916 - <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> 917 917 - <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/> 918 918 - <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/> 919 919 - <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/> 920 920 - <value value="46" name="PERF_SP_UCHE_READ_TRANS"/> 921 921 - <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/> 922 922 - <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/> 923 923 - <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/> 924 924 - <value value="50" name="PERF_SP_PIXELS_KILLED"/> 925 925 - <value value="51" name="PERF_SP_ICL1_REQUESTS"/> 926 926 - <value value="52" name="PERF_SP_ICL1_MISSES"/> 927 927 - <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/> 928 928 - <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/> 929 929 - <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/> 930 930 - <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/> 931 931 - <value value="57" name="PERF_SP_GPR_READ"/> 932 932 - <value value="58" name="PERF_SP_GPR_WRITE"/> 933 933 - <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> 934 934 - <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> 935 935 - <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/> 936 936 - <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> 937 937 - <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> 938 938 - <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> 939 939 - <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/> 940 940 - <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/> 941 941 - <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/> 942 942 - <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> 943 943 - <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/> 944 944 - <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/> 945 945 - <value value="71" name="PERF_SP_WORKING_EU"/> 946 946 - <value value="72" name="PERF_SP_ANY_EU_WORKING"/> 947 947 - <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/> 948 948 - <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/> 949 949 - <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/> 950 950 - <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/> 951 951 - <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/> 952 952 - <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/> 953 953 - <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/> 954 954 - <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/> 955 955 - <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/> 956 956 - <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/> 957 957 - <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> 958 958 - <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/> 959 959 - </enum> 960 960 - 961 961 - <enum name="a6xx_rb_perfcounter_select"> 962 962 - <value value="0" name="PERF_RB_BUSY_CYCLES"/> 963 963 - <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/> 964 964 - <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> 965 965 - <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> 966 966 - <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> 967 967 - <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/> 968 968 - <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> 969 969 - <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/> 970 970 - <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> 971 971 - <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> 972 972 - <value value="10" name="PERF_RB_Z_WORKLOAD"/> 973 973 - <value value="11" name="PERF_RB_HLSQ_ACTIVE"/> 974 974 - <value value="12" name="PERF_RB_Z_READ"/> 975 975 - <value value="13" name="PERF_RB_Z_WRITE"/> 976 976 - <value value="14" name="PERF_RB_C_READ"/> 977 977 - <value value="15" name="PERF_RB_C_WRITE"/> 978 978 - <value value="16" name="PERF_RB_TOTAL_PASS"/> 979 979 - <value value="17" name="PERF_RB_Z_PASS"/> 980 980 - <value value="18" name="PERF_RB_Z_FAIL"/> 981 981 - <value value="19" name="PERF_RB_S_FAIL"/> 982 982 - <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> 983 983 - <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> 984 984 - <value value="22" name="PERF_RB_PS_INVOCATIONS"/> 985 985 - <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/> 986 986 - <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/> 987 987 - <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> 988 988 - <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/> 989 989 - <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/> 990 990 - <value value="28" name="PERF_RB_2D_VALID_PIXELS"/> 991 991 - <value value="29" name="PERF_RB_3D_PIXELS"/> 992 992 - <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/> 993 993 - <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/> 994 994 - <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/> 995 995 - <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/> 996 996 - <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> 997 997 - <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> 998 998 - <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> 999 999 - <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> 1000 1000 - <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/> 1001 1001 - <value value="39" name="PERF_RB_2D_INPUT_TRANS"/> 1002 1002 - <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> 1003 1003 - <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> 1004 1004 - <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/> 1005 1005 - <value value="43" name="PERF_RB_COLOR_PIX_TILES"/> 1006 1006 - <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/> 1007 1007 - <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/> 1008 1008 - <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/> 1009 1009 - <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/> 1010 1010 - </enum> 1011 1011 - 1012 1012 - <enum name="a6xx_vsc_perfcounter_select"> 1013 1013 - <value value="0" name="PERF_VSC_BUSY_CYCLES"/> 1014 1014 - <value value="1" name="PERF_VSC_WORKING_CYCLES"/> 1015 1015 - <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> 1016 1016 - <value value="3" name="PERF_VSC_EOT_NUM"/> 1017 1017 - <value value="4" name="PERF_VSC_INPUT_TILES"/> 1018 1018 - </enum> 1019 1019 - 1020 1020 - <enum name="a6xx_ccu_perfcounter_select"> 1021 1021 - <value value="0" name="PERF_CCU_BUSY_CYCLES"/> 1022 1022 - <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> 1023 1023 - <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> 1024 1024 - <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> 1025 1025 - <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> 1026 1026 - <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> 1027 1027 - <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> 1028 1028 - <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> 1029 1029 - <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> 1030 1030 - <value value="9" name="PERF_CCU_GMEM_READ"/> 1031 1031 - <value value="10" name="PERF_CCU_GMEM_WRITE"/> 1032 1032 - <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> 1033 1033 - <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> 1034 1034 - <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> 1035 1035 - <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> 1036 1036 - <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> 1037 1037 - <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/> 1038 1038 - <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/> 1039 1039 - <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/> 1040 1040 - <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> 1041 1041 - <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> 1042 1042 - <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> 1043 1043 - <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> 1044 1044 - <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> 1045 1045 - <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/> 1046 1046 - <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/> 1047 1047 - <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/> 1048 1048 - <value value="27" name="PERF_CCU_2D_RD_REQ"/> 1049 1049 - <value value="28" name="PERF_CCU_2D_WR_REQ"/> 1050 1050 - </enum> 1051 1051 - 1052 1052 - <enum name="a6xx_lrz_perfcounter_select"> 1053 1053 - <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> 1054 1054 - <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> 1055 1055 - <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> 1056 1056 - <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> 1057 1057 - <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> 1058 1058 - <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> 1059 1059 - <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> 1060 1060 - <value value="7" name="PERF_LRZ_LRZ_READ"/> 1061 1061 - <value value="8" name="PERF_LRZ_LRZ_WRITE"/> 1062 1062 - <value value="9" name="PERF_LRZ_READ_LATENCY"/> 1063 1063 - <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> 1064 1064 - <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> 1065 1065 - <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> 1066 1066 - <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> 1067 1067 - <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> 1068 1068 - <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> 1069 1069 - <value value="16" name="PERF_LRZ_TILE_KILLED"/> 1070 1070 - <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> 1071 1071 - <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> 1072 1072 - <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/> 1073 1073 - <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/> 1074 1074 - <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/> 1075 1075 - <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/> 1076 1076 - <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/> 1077 1077 - <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> 1078 1078 - <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> 1079 1079 - <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/> 1080 1080 - <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/> 1081 1081 - </enum> 1082 1082 - 1083 1083 - <enum name="a6xx_cmp_perfcounter_select"> 1084 1084 - <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/> 1085 1085 - <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> 1086 1086 - <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> 1087 1087 - <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> 1088 1088 - <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> 1089 1089 - <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> 1090 1090 - <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> 1091 1091 - <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> 1092 1092 - <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> 1093 1093 - <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> 1094 1094 - <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> 1095 1095 - <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> 1096 1096 - <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> 1097 1097 - <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> 1098 1098 - <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> 1099 1099 - <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> 1100 1100 - <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> 1101 1101 - <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> 1102 1102 - <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> 1103 1103 - <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> 1104 1104 - <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> 1105 1105 - <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> 1106 1106 - <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> 1107 1107 - <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> 1108 1108 - <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> 1109 1109 - <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> 1110 1110 - <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> 1111 1111 - <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> 1112 1112 - <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/> 1113 1113 - <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/> 1114 1114 - <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> 1115 1115 - <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> 1116 1116 - <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/> 1117 1117 - <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> 1118 1118 - <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> 1119 1119 - <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> 1120 1120 - <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> 1121 1121 - <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/> 1122 1122 - <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/> 1123 1123 - <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/> 1124 1124 - </enum> 1125 1125 - 1126 1126 - <!-- 1127 1127 - Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the 1128 1128 - component type/size, so I think it relates to internal format used for 1129 1129 - blending? The one exception is that 16b unorm and 32b float use the 1130 1130 - same value... maybe 16b unorm is uncommon enough that it was just easier 1131 1131 - to upconvert to 32b float internally? 1132 1132 - 1133 1133 - 8b unorm: 10 (sometimes 0, is the high bit part of something else?) 1134 1134 - 16b unorm: 4 1135 1135 - 1136 1136 - 32b int: 7 1137 1137 - 16b int: 6 1138 1138 - 8b int: 5 1139 1139 - 1140 1140 - 32b float: 4 1141 1141 - 16b float: 3 1142 1142 - --> 1143 1143 - <enum name="a6xx_2d_ifmt"> 1144 1144 - <value value="0x10" name="R2D_UNORM8"/> 1145 1145 - <value value="0x7" name="R2D_INT32"/> 1146 1146 - <value value="0x6" name="R2D_INT16"/> 1147 1147 - <value value="0x5" name="R2D_INT8"/> 1148 1148 - <value value="0x4" name="R2D_FLOAT32"/> 1149 1149 - <value value="0x3" name="R2D_FLOAT16"/> 1150 1150 - <value value="0x1" name="R2D_UNORM8_SRGB"/> 1151 1151 - <value value="0x0" name="R2D_RAW"/> 1152 1152 - </enum> 1153 1153 - 1154 1154 - <enum name="a6xx_ztest_mode"> 1155 1155 - <doc>Allow early z-test and early-lrz (if applicable)</doc> 1156 1156 - <value value="0x0" name="A6XX_EARLY_Z"/> 1157 1157 - <doc>Disable early z-test and early-lrz test (if applicable)</doc> 1158 1158 - <value value="0x1" name="A6XX_LATE_Z"/> 1159 1159 - <doc> 1160 1160 - A special mode that allows early-lrz test but disables 1161 1161 - early-z test. Which might sound a bit funny, since 1162 1162 - lrz-test happens before z-test. But as long as a couple 1163 1163 - conditions are maintained this allows using lrz-test in 1164 1164 - cases where fragment shader has kill/discard: 1165 1165 - 1166 1166 - 1) Disable lrz-write in cases where it is uncertain during 1167 1167 - binning pass that a fragment will pass. Ie. if frag 1168 1168 - shader has-kill, writes-z, or alpha/stencil test is 1169 1169 - enabled. (For correctness, lrz-write must be disabled 1170 1170 - when blend is enabled.) This is analogous to how a 1171 1171 - z-prepass works. 1172 1172 - 1173 1173 - 2) Disable lrz-write and test if a depth-test direction 1174 1174 - reversal is detected. Due to condition (1), the contents 1175 1175 - of the lrz buffer are a conservative estimation of the 1176 1176 - depth buffer during the draw pass. Meaning that geometry 1177 1177 - that we know for certain will not be visible will not pass 1178 1178 - lrz-test. But geometry which may be (or contributes to 1179 1179 - blend) will pass the lrz-test. 1180 1180 - 1181 1181 - This allows us to keep early-lrz-test in cases where the frag 1182 1182 - shader does not write-z (ie. we know the z-value before FS) 1183 1183 - and does not have side-effects (image/ssbo writes, etc), but 1184 1184 - does have kill/discard. Which turns out to be a common 1185 1185 - enough case that it is useful to keep early-lrz test against 1186 1186 - the conservative lrz buffer to discard fragments that we 1187 1187 - know will definitely not be visible. 1188 1188 - </doc> 1189 1189 - <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/> 1190 1190 - <doc>Not a real hw value, used internally by mesa</doc> 1191 1191 - <value value="0x3" name="A6XX_INVALID_ZTEST"/> 1192 1192 - </enum> 1193 1193 - 1194 1194 - <enum name="a6xx_tess_spacing"> 1195 1195 - <value value="0x0" name="TESS_EQUAL"/> 1196 1196 - <value value="0x2" name="TESS_FRACTIONAL_ODD"/> 1197 1197 - <value value="0x3" name="TESS_FRACTIONAL_EVEN"/> 1198 1198 - </enum> 1199 1199 - <enum name="a6xx_tess_output"> 1200 1200 - <value value="0x0" name="TESS_POINTS"/> 1201 1201 - <value value="0x1" name="TESS_LINES"/> 1202 1202 - <value value="0x2" name="TESS_CW_TRIS"/> 1203 1203 - <value value="0x3" name="TESS_CCW_TRIS"/> 1204 1204 - </enum> 1205 1205 - 1206 1206 - <enum name="a7xx_cp_perfcounter_select"> 1207 1207 - <value value="0" name="A7XX_PERF_CP_ALWAYS_COUNT"/> 1208 1208 - <value value="1" name="A7XX_PERF_CP_BUSY_GFX_CORE_IDLE"/> 1209 1209 - <value value="2" name="A7XX_PERF_CP_BUSY_CYCLES"/> 1210 1210 - <value value="3" name="A7XX_PERF_CP_NUM_PREEMPTIONS"/> 1211 1211 - <value value="4" name="A7XX_PERF_CP_PREEMPTION_REACTION_DELAY"/> 1212 1212 - <value value="5" name="A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 1213 1213 - <value value="6" name="A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 1214 1214 - <value value="7" name="A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 1215 1215 - <value value="8" name="A7XX_PERF_CP_PREDICATED_DRAWS_KILLED"/> 1216 1216 - <value value="9" name="A7XX_PERF_CP_MODE_SWITCH"/> 1217 1217 - <value value="10" name="A7XX_PERF_CP_ZPASS_DONE"/> 1218 1218 - <value value="11" name="A7XX_PERF_CP_CONTEXT_DONE"/> 1219 1219 - <value value="12" name="A7XX_PERF_CP_CACHE_FLUSH"/> 1220 1220 - <value value="13" name="A7XX_PERF_CP_LONG_PREEMPTIONS"/> 1221 1221 - <value value="14" name="A7XX_PERF_CP_SQE_I_CACHE_STARVE"/> 1222 1222 - <value value="15" name="A7XX_PERF_CP_SQE_IDLE"/> 1223 1223 - <value value="16" name="A7XX_PERF_CP_SQE_PM4_STARVE_RB_IB"/> 1224 1224 - <value value="17" name="A7XX_PERF_CP_SQE_PM4_STARVE_SDS"/> 1225 1225 - <value value="18" name="A7XX_PERF_CP_SQE_MRB_STARVE"/> 1226 1226 - <value value="19" name="A7XX_PERF_CP_SQE_RRB_STARVE"/> 1227 1227 - <value value="20" name="A7XX_PERF_CP_SQE_VSD_STARVE"/> 1228 1228 - <value value="21" name="A7XX_PERF_CP_VSD_DECODE_STARVE"/> 1229 1229 - <value value="22" name="A7XX_PERF_CP_SQE_PIPE_OUT_STALL"/> 1230 1230 - <value value="23" name="A7XX_PERF_CP_SQE_SYNC_STALL"/> 1231 1231 - <value value="24" name="A7XX_PERF_CP_SQE_PM4_WFI_STALL"/> 1232 1232 - <value value="25" name="A7XX_PERF_CP_SQE_SYS_WFI_STALL"/> 1233 1233 - <value value="26" name="A7XX_PERF_CP_SQE_T4_EXEC"/> 1234 1234 - <value value="27" name="A7XX_PERF_CP_SQE_LOAD_STATE_EXEC"/> 1235 1235 - <value value="28" name="A7XX_PERF_CP_SQE_SAVE_SDS_STATE"/> 1236 1236 - <value value="29" name="A7XX_PERF_CP_SQE_DRAW_EXEC"/> 1237 1237 - <value value="30" name="A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> 1238 1238 - <value value="31" name="A7XX_PERF_CP_SQE_EXEC_PROFILED"/> 1239 1239 - <value value="32" name="A7XX_PERF_CP_MEMORY_POOL_EMPTY"/> 1240 1240 - <value value="33" name="A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL"/> 1241 1241 - <value value="34" name="A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> 1242 1242 - <value value="35" name="A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> 1243 1243 - <value value="36" name="A7XX_PERF_CP_AHB_STALL_SQE_GMU"/> 1244 1244 - <value value="37" name="A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER"/> 1245 1245 - <value value="38" name="A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER"/> 1246 1246 - <value value="39" name="A7XX_PERF_CP_CLUSTER0_EMPTY"/> 1247 1247 - <value value="40" name="A7XX_PERF_CP_CLUSTER1_EMPTY"/> 1248 1248 - <value value="41" name="A7XX_PERF_CP_CLUSTER2_EMPTY"/> 1249 1249 - <value value="42" name="A7XX_PERF_CP_CLUSTER3_EMPTY"/> 1250 1250 - <value value="43" name="A7XX_PERF_CP_CLUSTER4_EMPTY"/> 1251 1251 - <value value="44" name="A7XX_PERF_CP_CLUSTER5_EMPTY"/> 1252 1252 - <value value="45" name="A7XX_PERF_CP_PM4_DATA"/> 1253 1253 - <value value="46" name="A7XX_PERF_CP_PM4_HEADERS"/> 1254 1254 - <value value="47" name="A7XX_PERF_CP_VBIF_READ_BEATS"/> 1255 1255 - <value value="48" name="A7XX_PERF_CP_VBIF_WRITE_BEATS"/> 1256 1256 - <value value="49" name="A7XX_PERF_CP_SQE_INSTR_COUNTER"/> 1257 1257 - <value value="50" name="A7XX_PERF_CP_RESERVED_50"/> 1258 1258 - <value value="51" name="A7XX_PERF_CP_RESERVED_51"/> 1259 1259 - <value value="52" name="A7XX_PERF_CP_RESERVED_52"/> 1260 1260 - <value value="53" name="A7XX_PERF_CP_RESERVED_53"/> 1261 1261 - <value value="54" name="A7XX_PERF_CP_RESERVED_54"/> 1262 1262 - <value value="55" name="A7XX_PERF_CP_RESERVED_55"/> 1263 1263 - <value value="56" name="A7XX_PERF_CP_RESERVED_56"/> 1264 1264 - <value value="57" name="A7XX_PERF_CP_RESERVED_57"/> 1265 1265 - <value value="58" name="A7XX_PERF_CP_RESERVED_58"/> 1266 1266 - <value value="59" name="A7XX_PERF_CP_RESERVED_59"/> 1267 1267 - <value value="60" name="A7XX_PERF_CP_CLUSTER0_FULL"/> 1268 1268 - <value value="61" name="A7XX_PERF_CP_CLUSTER1_FULL"/> 1269 1269 - <value value="62" name="A7XX_PERF_CP_CLUSTER2_FULL"/> 1270 1270 - <value value="63" name="A7XX_PERF_CP_CLUSTER3_FULL"/> 1271 1271 - <value value="64" name="A7XX_PERF_CP_CLUSTER4_FULL"/> 1272 1272 - <value value="65" name="A7XX_PERF_CP_CLUSTER5_FULL"/> 1273 1273 - <value value="66" name="A7XX_PERF_CP_CLUSTER6_FULL"/> 1274 1274 - <value value="67" name="A7XX_PERF_CP_CLUSTER6_EMPTY"/> 1275 1275 - <value value="68" name="A7XX_PERF_CP_ICACHE_MISSES"/> 1276 1276 - <value value="69" name="A7XX_PERF_CP_ICACHE_HITS"/> 1277 1277 - <value value="70" name="A7XX_PERF_CP_ICACHE_STALL"/> 1278 1278 - <value value="71" name="A7XX_PERF_CP_DCACHE_MISSES"/> 1279 1279 - <value value="72" name="A7XX_PERF_CP_DCACHE_HITS"/> 1280 1280 - <value value="73" name="A7XX_PERF_CP_DCACHE_STALLS"/> 1281 1281 - <value value="74" name="A7XX_PERF_CP_AQE_SQE_STALL"/> 1282 1282 - <value value="75" name="A7XX_PERF_CP_SQE_AQE_STARVE"/> 1283 1283 - <value value="76" name="A7XX_PERF_CP_PREEMPT_LATENCY"/> 1284 1284 - <value value="77" name="A7XX_PERF_CP_SQE_MD8_STALL_CYCLES"/> 1285 1285 - <value value="78" name="A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES"/> 1286 1286 - <value value="79" name="A7XX_PERF_CP_AQE_NUM_AS_CHUNKS"/> 1287 1287 - <value value="80" name="A7XX_PERF_CP_AQE_NUM_MS_CHUNKS"/> 1288 1288 - </enum> 1289 1289 - 1290 1290 - <enum name="a7xx_rbbm_perfcounter_select"> 1291 1291 - <value value="0" name="A7XX_PERF_RBBM_ALWAYS_COUNT"/> 1292 1292 - <value value="1" name="A7XX_PERF_RBBM_ALWAYS_ON"/> 1293 1293 - <value value="2" name="A7XX_PERF_RBBM_TSE_BUSY"/> 1294 1294 - <value value="3" name="A7XX_PERF_RBBM_RAS_BUSY"/> 1295 1295 - <value value="4" name="A7XX_PERF_RBBM_PC_DCALL_BUSY"/> 1296 1296 - <value value="5" name="A7XX_PERF_RBBM_PC_VSD_BUSY"/> 1297 1297 - <value value="6" name="A7XX_PERF_RBBM_STATUS_MASKED"/> 1298 1298 - <value value="7" name="A7XX_PERF_RBBM_COM_BUSY"/> 1299 1299 - <value value="8" name="A7XX_PERF_RBBM_DCOM_BUSY"/> 1300 1300 - <value value="9" name="A7XX_PERF_RBBM_VBIF_BUSY"/> 1301 1301 - <value value="10" name="A7XX_PERF_RBBM_VSC_BUSY"/> 1302 1302 - <value value="11" name="A7XX_PERF_RBBM_TESS_BUSY"/> 1303 1303 - <value value="12" name="A7XX_PERF_RBBM_UCHE_BUSY"/> 1304 1304 - <value value="13" name="A7XX_PERF_RBBM_HLSQ_BUSY"/> 1305 1305 - </enum> 1306 1306 - 1307 1307 - <enum name="a7xx_pc_perfcounter_select"> 1308 1308 - <value value="0" name="A7XX_PERF_PC_BUSY_CYCLES"/> 1309 1309 - <value value="1" name="A7XX_PERF_PC_WORKING_CYCLES"/> 1310 1310 - <value value="2" name="A7XX_PERF_PC_STALL_CYCLES_VFD"/> 1311 1311 - <value value="3" name="A7XX_PERF_PC_RESERVED"/> 1312 1312 - <value value="4" name="A7XX_PERF_PC_STALL_CYCLES_VPC"/> 1313 1313 - <value value="5" name="A7XX_PERF_PC_STALL_CYCLES_UCHE"/> 1314 1314 - <value value="6" name="A7XX_PERF_PC_STALL_CYCLES_TESS"/> 1315 1315 - <value value="7" name="A7XX_PERF_PC_STALL_CYCLES_VFD_ONLY"/> 1316 1316 - <value value="8" name="A7XX_PERF_PC_STALL_CYCLES_VPC_ONLY"/> 1317 1317 - <value value="9" name="A7XX_PERF_PC_PASS1_TF_STALL_CYCLES"/> 1318 1318 - <value value="10" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_INDEX"/> 1319 1319 - <value value="11" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> 1320 1320 - <value value="12" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> 1321 1321 - <value value="13" name="A7XX_PERF_PC_STARVE_CYCLES_DI"/> 1322 1322 - <value value="14" name="A7XX_PERF_PC_VIS_STREAMS_LOADED"/> 1323 1323 - <value value="15" name="A7XX_PERF_PC_INSTANCES"/> 1324 1324 - <value value="16" name="A7XX_PERF_PC_VPC_PRIMITIVES"/> 1325 1325 - <value value="17" name="A7XX_PERF_PC_DEAD_PRIM"/> 1326 1326 - <value value="18" name="A7XX_PERF_PC_LIVE_PRIM"/> 1327 1327 - <value value="19" name="A7XX_PERF_PC_VERTEX_HITS"/> 1328 1328 - <value value="20" name="A7XX_PERF_PC_IA_VERTICES"/> 1329 1329 - <value value="21" name="A7XX_PERF_PC_IA_PRIMITIVES"/> 1330 1330 - <value value="22" name="A7XX_PERF_PC_RESERVED_22"/> 1331 1331 - <value value="23" name="A7XX_PERF_PC_HS_INVOCATIONS"/> 1332 1332 - <value value="24" name="A7XX_PERF_PC_DS_INVOCATIONS"/> 1333 1333 - <value value="25" name="A7XX_PERF_PC_VS_INVOCATIONS"/> 1334 1334 - <value value="26" name="A7XX_PERF_PC_GS_INVOCATIONS"/> 1335 1335 - <value value="27" name="A7XX_PERF_PC_DS_PRIMITIVES"/> 1336 1336 - <value value="28" name="A7XX_PERF_PC_3D_DRAWCALLS"/> 1337 1337 - <value value="29" name="A7XX_PERF_PC_2D_DRAWCALLS"/> 1338 1338 - <value value="30" name="A7XX_PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> 1339 1339 - <value value="31" name="A7XX_PERF_PC_TESS_BUSY_CYCLES"/> 1340 1340 - <value value="32" name="A7XX_PERF_PC_TESS_WORKING_CYCLES"/> 1341 1341 - <value value="33" name="A7XX_PERF_PC_TESS_STALL_CYCLES_PC"/> 1342 1342 - <value value="34" name="A7XX_PERF_PC_TESS_STARVE_CYCLES_PC"/> 1343 1343 - <value value="35" name="A7XX_PERF_PC_TESS_SINGLE_PRIM_CYCLES"/> 1344 1344 - <value value="36" name="A7XX_PERF_PC_TESS_PC_UV_TRANS"/> 1345 1345 - <value value="37" name="A7XX_PERF_PC_TESS_PC_UV_PATCHES"/> 1346 1346 - <value value="38" name="A7XX_PERF_PC_TESS_FACTOR_TRANS"/> 1347 1347 - <value value="39" name="A7XX_PERF_PC_TAG_CHECKED_VERTICES"/> 1348 1348 - <value value="40" name="A7XX_PERF_PC_MESH_VS_WAVES"/> 1349 1349 - <value value="41" name="A7XX_PERF_PC_MESH_DRAWS"/> 1350 1350 - <value value="42" name="A7XX_PERF_PC_MESH_DEAD_DRAWS"/> 1351 1351 - <value value="43" name="A7XX_PERF_PC_MESH_MVIS_EN_DRAWS"/> 1352 1352 - <value value="44" name="A7XX_PERF_PC_MESH_DEAD_PRIM"/> 1353 1353 - <value value="45" name="A7XX_PERF_PC_MESH_LIVE_PRIM"/> 1354 1354 - <value value="46" name="A7XX_PERF_PC_MESH_PA_EN_PRIM"/> 1355 1355 - <value value="47" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_MVIS_STREAM"/> 1356 1356 - <value value="48" name="A7XX_PERF_PC_STARVE_CYCLES_PREDRAW"/> 1357 1357 - <value value="49" name="A7XX_PERF_PC_STALL_CYCLES_COMPUTE_GFX"/> 1358 1358 - <value value="50" name="A7XX_PERF_PC_STALL_CYCLES_GFX_COMPUTE"/> 1359 1359 - <value value="51" name="A7XX_PERF_PC_TESS_PC_MULTI_PATCH_TRANS"/> 1360 1360 - </enum> 1361 1361 - 1362 1362 - <enum name="a7xx_vfd_perfcounter_select"> 1363 1363 - <value value="0" name="A7XX_PERF_VFD_BUSY_CYCLES"/> 1364 1364 - <value value="1" name="A7XX_PERF_VFD_STALL_CYCLES_UCHE"/> 1365 1365 - <value value="2" name="A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> 1366 1366 - <value value="3" name="A7XX_PERF_VFD_STALL_CYCLES_SP_INFO"/> 1367 1367 - <value value="4" name="A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR"/> 1368 1368 - <value value="5" name="A7XX_PERF_VFD_STARVE_CYCLES_UCHE"/> 1369 1369 - <value value="6" name="A7XX_PERF_VFD_RBUFFER_FULL"/> 1370 1370 - <value value="7" name="A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL"/> 1371 1371 - <value value="8" name="A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> 1372 1372 - <value value="9" name="A7XX_PERF_VFD_NUM_ATTRIBUTES"/> 1373 1373 - <value value="10" name="A7XX_PERF_VFD_UPPER_SHADER_FIBERS"/> 1374 1374 - <value value="11" name="A7XX_PERF_VFD_LOWER_SHADER_FIBERS"/> 1375 1375 - <value value="12" name="A7XX_PERF_VFD_MODE_0_FIBERS"/> 1376 1376 - <value value="13" name="A7XX_PERF_VFD_MODE_1_FIBERS"/> 1377 1377 - <value value="14" name="A7XX_PERF_VFD_MODE_2_FIBERS"/> 1378 1378 - <value value="15" name="A7XX_PERF_VFD_MODE_3_FIBERS"/> 1379 1379 - <value value="16" name="A7XX_PERF_VFD_MODE_4_FIBERS"/> 1380 1380 - <value value="17" name="A7XX_PERF_VFD_TOTAL_VERTICES"/> 1381 1381 - <value value="18" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD"/> 1382 1382 - <value value="19" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> 1383 1383 - <value value="20" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG"/> 1384 1384 - <value value="21" name="A7XX_PERF_VFDP_STARVE_CYCLES_PC"/> 1385 1385 - <value value="22" name="A7XX_PERF_VFDP_VS_STAGE_WAVES"/> 1386 1386 - <value value="23" name="A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE"/> 1387 1387 - <value value="24" name="A7XX_PERF_VFD_STALL_CYCLES_CBSYNC"/> 1388 1388 - </enum> 1389 1389 - 1390 1390 - <enum name="a7xx_hlsq_perfcounter_select"> 1391 1391 - <value value="0" name="A7XX_PERF_HLSQ_BUSY_CYCLES"/> 1392 1392 - <value value="1" name="A7XX_PERF_HLSQ_STALL_CYCLES_UCHE"/> 1393 1393 - <value value="2" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE"/> 1394 1394 - <value value="3" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> 1395 1395 - <value value="4" name="A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES"/> 1396 1396 - <value value="5" name="A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT"/> 1397 1397 - <value value="6" name="A7XX_PERF_HLSQ_RESERVED_6"/> 1398 1398 - <value value="7" name="A7XX_PERF_HLSQ_RESERVED_7"/> 1399 1399 - <value value="8" name="A7XX_PERF_HLSQ_RESERVED_8"/> 1400 1400 - <value value="9" name="A7XX_PERF_HLSQ_RESERVED_9"/> 1401 1401 - <value value="10" name="A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS"/> 1402 1402 - <value value="11" name="A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> 1403 1403 - <value value="12" name="A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> 1404 1404 - <value value="13" name="A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> 1405 1405 - <value value="14" name="A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> 1406 1406 - <value value="15" name="A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> 1407 1407 - <value value="16" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> 1408 1408 - <value value="17" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> 1409 1409 - <value value="18" name="A7XX_PERF_HLSQ_STALL_CYCLES_VPC"/> 1410 1410 - <value value="19" name="A7XX_PERF_HLSQ_RESERVED_19"/> 1411 1411 - <value value="20" name="A7XX_PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> 1412 1412 - <value value="21" name="A7XX_PERF_HLSQ_VSBR_STALL_CYCLES"/> 1413 1413 - <value value="22" name="A7XX_PERF_HLSQ_FS_STALL_CYCLES"/> 1414 1414 - <value value="23" name="A7XX_PERF_HLSQ_LPAC_STALL_CYCLES"/> 1415 1415 - <value value="24" name="A7XX_PERF_HLSQ_BV_STALL_CYCLES"/> 1416 1416 - <value value="25" name="A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES"/> 1417 1417 - <value value="26" name="A7XX_PERF_HLSQ_FS_DEREF_CYCLES"/> 1418 1418 - <value value="27" name="A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES"/> 1419 1419 - <value value="28" name="A7XX_PERF_HLSQ_BV_DEREF_CYCLES"/> 1420 1420 - <value value="29" name="A7XX_PERF_HLSQ_VSBR_S2W_CYCLES"/> 1421 1421 - <value value="30" name="A7XX_PERF_HLSQ_FS_S2W_CYCLES"/> 1422 1422 - <value value="31" name="A7XX_PERF_HLSQ_LPAC_S2W_CYCLES"/> 1423 1423 - <value value="32" name="A7XX_PERF_HLSQ_BV_S2W_CYCLES"/> 1424 1424 - <value value="33" name="A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W"/> 1425 1425 - <value value="34" name="A7XX_PERF_HLSQ_FS_WAIT_VS_S2W"/> 1426 1426 - <value value="35" name="A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W"/> 1427 1427 - <value value="36" name="A7XX_PERF_HLSQ_BV_WAIT_FS_S2W"/> 1428 1428 - <value value="37" name="A7XX_PERF_HLSQ_VS_WAIT_CONST_RESOURCE"/> 1429 1429 - <value value="38" name="A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W"/> 1430 1430 - <value value="39" name="A7XX_PERF_HLSQ_FS_STARVING_SP"/> 1431 1431 - <value value="40" name="A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING"/> 1432 1432 - <value value="41" name="A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING"/> 1433 1433 - <value value="42" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS"/> 1434 1434 - <value value="43" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS"/> 1435 1435 - <value value="44" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS"/> 1436 1436 - <value value="45" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS"/> 1437 1437 - <value value="46" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV"/> 1438 1438 - <value value="47" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV"/> 1439 1439 - <value value="48" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC"/> 1440 1440 - <value value="49" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC"/> 1441 1441 - <value value="50" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS"/> 1442 1442 - <value value="51" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS"/> 1443 1443 - <value value="52" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV"/> 1444 1444 - <value value="53" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC"/> 1445 1445 - <value value="54" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS"/> 1446 1446 - <value value="55" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS"/> 1447 1447 - <value value="56" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV"/> 1448 1448 - <value value="57" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC"/> 1449 1449 - </enum> 1450 1450 - 1451 1451 - <enum name="a7xx_vpc_perfcounter_select"> 1452 1452 - <value value="0" name="A7XX_PERF_VPC_BUSY_CYCLES"/> 1453 1453 - <value value="1" name="A7XX_PERF_VPC_WORKING_CYCLES"/> 1454 1454 - <value value="2" name="A7XX_PERF_VPC_STALL_CYCLES_UCHE"/> 1455 1455 - <value value="3" name="A7XX_PERF_VPC_STALL_CYCLES_VFD_WACK"/> 1456 1456 - <value value="4" name="A7XX_PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> 1457 1457 - <value value="5" name="A7XX_PERF_VPC_RESERVED_5"/> 1458 1458 - <value value="6" name="A7XX_PERF_VPC_STALL_CYCLES_SP_LM"/> 1459 1459 - <value value="7" name="A7XX_PERF_VPC_STARVE_CYCLES_SP"/> 1460 1460 - <value value="8" name="A7XX_PERF_VPC_STARVE_CYCLES_LRZ"/> 1461 1461 - <value value="9" name="A7XX_PERF_VPC_PC_PRIMITIVES"/> 1462 1462 - <value value="10" name="A7XX_PERF_VPC_SP_COMPONENTS"/> 1463 1463 - <value value="11" name="A7XX_PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> 1464 1464 - <value value="12" name="A7XX_PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> 1465 1465 - <value value="13" name="A7XX_PERF_VPC_RB_VISIBLE_PRIMITIVES"/> 1466 1466 - <value value="14" name="A7XX_PERF_VPC_LM_TRANSACTION"/> 1467 1467 - <value value="15" name="A7XX_PERF_VPC_STREAMOUT_TRANSACTION"/> 1468 1468 - <value value="16" name="A7XX_PERF_VPC_VS_BUSY_CYCLES"/> 1469 1469 - <value value="17" name="A7XX_PERF_VPC_PS_BUSY_CYCLES"/> 1470 1470 - <value value="18" name="A7XX_PERF_VPC_VS_WORKING_CYCLES"/> 1471 1471 - <value value="19" name="A7XX_PERF_VPC_PS_WORKING_CYCLES"/> 1472 1472 - <value value="20" name="A7XX_PERF_VPC_STARVE_CYCLES_RB"/> 1473 1473 - <value value="21" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_POS"/> 1474 1474 - <value value="22" name="A7XX_PERF_VPC_WIT_FULL_CYCLES"/> 1475 1475 - <value value="23" name="A7XX_PERF_VPC_VPCRAM_FULL_CYCLES"/> 1476 1476 - <value value="24" name="A7XX_PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> 1477 1477 - <value value="25" name="A7XX_PERF_VPC_NUM_VPCRAM_WRITE"/> 1478 1478 - <value value="26" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_SO"/> 1479 1479 - <value value="27" name="A7XX_PERF_VPC_NUM_ATTR_REQ_LM"/> 1480 1480 - <value value="28" name="A7XX_PERF_VPC_STALL_CYCLE_TSE"/> 1481 1481 - <value value="29" name="A7XX_PERF_VPC_TSE_PRIMITIVES"/> 1482 1482 - <value value="30" name="A7XX_PERF_VPC_GS_PRIMITIVES"/> 1483 1483 - <value value="31" name="A7XX_PERF_VPC_TSE_TRANSACTIONS"/> 1484 1484 - <value value="32" name="A7XX_PERF_VPC_STALL_CYCLES_CCU"/> 1485 1485 - <value value="33" name="A7XX_PERF_VPC_NUM_WM_HIT"/> 1486 1486 - <value value="34" name="A7XX_PERF_VPC_STALL_DQ_WACK"/> 1487 1487 - <value value="35" name="A7XX_PERF_VPC_STALL_CYCLES_CCHE"/> 1488 1488 - <value value="36" name="A7XX_PERF_VPC_STARVE_CYCLES_CCHE"/> 1489 1489 - <value value="37" name="A7XX_PERF_VPC_NUM_PA_REQ"/> 1490 1490 - <value value="38" name="A7XX_PERF_VPC_NUM_LM_REQ_HIT"/> 1491 1491 - <value value="39" name="A7XX_PERF_VPC_CCHE_REQBUF_FULL"/> 1492 1492 - <value value="40" name="A7XX_PERF_VPC_STALL_CYCLES_LM_ACK"/> 1493 1493 - <value value="41" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_FE"/> 1494 1494 - <value value="42" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_PCVS"/> 1495 1495 - <value value="43" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_VPCPS"/> 1496 1496 - </enum> 1497 1497 - 1498 1498 - <enum name="a7xx_tse_perfcounter_select"> 1499 1499 - <value value="0" name="A7XX_PERF_TSE_BUSY_CYCLES"/> 1500 1500 - <value value="1" name="A7XX_PERF_TSE_CLIPPING_CYCLES"/> 1501 1501 - <value value="2" name="A7XX_PERF_TSE_STALL_CYCLES_RAS"/> 1502 1502 - <value value="3" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> 1503 1503 - <value value="4" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> 1504 1504 - <value value="5" name="A7XX_PERF_TSE_STARVE_CYCLES_PC"/> 1505 1505 - <value value="6" name="A7XX_PERF_TSE_INPUT_PRIM"/> 1506 1506 - <value value="7" name="A7XX_PERF_TSE_INPUT_NULL_PRIM"/> 1507 1507 - <value value="8" name="A7XX_PERF_TSE_TRIVAL_REJ_PRIM"/> 1508 1508 - <value value="9" name="A7XX_PERF_TSE_CLIPPED_PRIM"/> 1509 1509 - <value value="10" name="A7XX_PERF_TSE_ZERO_AREA_PRIM"/> 1510 1510 - <value value="11" name="A7XX_PERF_TSE_FACENESS_CULLED_PRIM"/> 1511 1511 - <value value="12" name="A7XX_PERF_TSE_ZERO_PIXEL_PRIM"/> 1512 1512 - <value value="13" name="A7XX_PERF_TSE_OUTPUT_NULL_PRIM"/> 1513 1513 - <value value="14" name="A7XX_PERF_TSE_OUTPUT_VISIBLE_PRIM"/> 1514 1514 - <value value="15" name="A7XX_PERF_TSE_CINVOCATION"/> 1515 1515 - <value value="16" name="A7XX_PERF_TSE_CPRIMITIVES"/> 1516 1516 - <value value="17" name="A7XX_PERF_TSE_2D_INPUT_PRIM"/> 1517 1517 - <value value="18" name="A7XX_PERF_TSE_2D_ALIVE_CYCLES"/> 1518 1518 - <value value="19" name="A7XX_PERF_TSE_CLIP_PLANES"/> 1519 1519 - </enum> 1520 1520 - 1521 1521 - <enum name="a7xx_ras_perfcounter_select"> 1522 1522 - <value value="0" name="A7XX_PERF_RAS_BUSY_CYCLES"/> 1523 1523 - <value value="1" name="A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> 1524 1524 - <value value="2" name="A7XX_PERF_RAS_STALL_CYCLES_LRZ"/> 1525 1525 - <value value="3" name="A7XX_PERF_RAS_STARVE_CYCLES_TSE"/> 1526 1526 - <value value="4" name="A7XX_PERF_RAS_SUPER_TILES"/> 1527 1527 - <value value="5" name="A7XX_PERF_RAS_8X4_TILES"/> 1528 1528 - <value value="6" name="A7XX_PERF_RAS_MASKGEN_ACTIVE"/> 1529 1529 - <value value="7" name="A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES"/> 1530 1530 - <value value="8" name="A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES"/> 1531 1531 - <value value="9" name="A7XX_PERF_RAS_PRIM_KILLED_INVISILBE"/> 1532 1532 - <value value="10" name="A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> 1533 1533 - <value value="11" name="A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> 1534 1534 - <value value="12" name="A7XX_PERF_RAS_BLOCKS"/> 1535 1535 - <value value="13" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_l2"/> 1536 1536 - <value value="14" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_l2"/> 1537 1537 - <value value="15" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_l2"/> 1538 1538 - <value value="16" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_l2"/> 1539 1539 - <value value="17" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_l2"/> 1540 1540 - <value value="18" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_l2"/> 1541 1541 - <value value="19" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_l2"/> 1542 1542 - <value value="20" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_l2"/> 1543 1543 - <value value="21" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_l2"/> 1544 1544 - <value value="22" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_l2"/> 1545 1545 - <value value="23" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_l2"/> 1546 1546 - <value value="24" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_l2"/> 1547 1547 - <value value="25" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_l2"/> 1548 1548 - <value value="26" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_l2"/> 1549 1549 - <value value="27" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_l2"/> 1550 1550 - <value value="28" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_l2"/> 1551 1551 - <value value="29" name="A7XX_PERF_RAS_FALSE_PARTIAL_STILE"/> 1552 1552 - 1553 1553 - </enum> 1554 1554 - 1555 1555 - <enum name="a7xx_uche_perfcounter_select"> 1556 1556 - <value value="0" name="A7XX_PERF_UCHE_BUSY_CYCLES"/> 1557 1557 - <value value="1" name="A7XX_PERF_UCHE_STALL_CYCLES_ARBITER"/> 1558 1558 - <value value="2" name="A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES"/> 1559 1559 - <value value="3" name="A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES"/> 1560 1560 - <value value="4" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_TP"/> 1561 1561 - <value value="5" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD"/> 1562 1562 - <value value="6" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> 1563 1563 - <value value="7" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ"/> 1564 1564 - <value value="8" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_SP"/> 1565 1565 - <value value="9" name="A7XX_PERF_UCHE_READ_REQUESTS_TP"/> 1566 1566 - <value value="10" name="A7XX_PERF_UCHE_READ_REQUESTS_VFD"/> 1567 1567 - <value value="11" name="A7XX_PERF_UCHE_READ_REQUESTS_HLSQ"/> 1568 1568 - <value value="12" name="A7XX_PERF_UCHE_READ_REQUESTS_LRZ"/> 1569 1569 - <value value="13" name="A7XX_PERF_UCHE_READ_REQUESTS_SP"/> 1570 1570 - <value value="14" name="A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ"/> 1571 1571 - <value value="15" name="A7XX_PERF_UCHE_WRITE_REQUESTS_SP"/> 1572 1572 - <value value="16" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VPC"/> 1573 1573 - <value value="17" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VSC"/> 1574 1574 - <value value="18" name="A7XX_PERF_UCHE_EVICTS"/> 1575 1575 - <value value="19" name="A7XX_PERF_UCHE_BANK_REQ0"/> 1576 1576 - <value value="20" name="A7XX_PERF_UCHE_BANK_REQ1"/> 1577 1577 - <value value="21" name="A7XX_PERF_UCHE_BANK_REQ2"/> 1578 1578 - <value value="22" name="A7XX_PERF_UCHE_BANK_REQ3"/> 1579 1579 - <value value="23" name="A7XX_PERF_UCHE_BANK_REQ4"/> 1580 1580 - <value value="24" name="A7XX_PERF_UCHE_BANK_REQ5"/> 1581 1581 - <value value="25" name="A7XX_PERF_UCHE_BANK_REQ6"/> 1582 1582 - <value value="26" name="A7XX_PERF_UCHE_BANK_REQ7"/> 1583 1583 - <value value="27" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0"/> 1584 1584 - <value value="28" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1"/> 1585 1585 - <value value="29" name="A7XX_PERF_UCHE_GMEM_READ_BEATS"/> 1586 1586 - <value value="30" name="A7XX_PERF_UCHE_TPH_REF_FULL"/> 1587 1587 - <value value="31" name="A7XX_PERF_UCHE_TPH_VICTIM_FULL"/> 1588 1588 - <value value="32" name="A7XX_PERF_UCHE_TPH_EXT_FULL"/> 1589 1589 - <value value="33" name="A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA"/> 1590 1590 - <value value="34" name="A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES"/> 1591 1591 - <value value="35" name="A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES"/> 1592 1592 - <value value="36" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_PC"/> 1593 1593 - <value value="37" name="A7XX_PERF_UCHE_READ_REQUESTS_PC"/> 1594 1594 - <value value="38" name="A7XX_PERF_UCHE_RAM_READ_REQ"/> 1595 1595 - <value value="39" name="A7XX_PERF_UCHE_RAM_WRITE_REQ"/> 1596 1596 - <value value="40" name="A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP"/> 1597 1597 - <value value="41" name="A7XX_PERF_UCHE_STALL_CYCLES_DECMP"/> 1598 1598 - <value value="42" name="A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF"/> 1599 1599 - <value value="43" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC"/> 1600 1600 - <value value="44" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_NONUBWC"/> 1601 1601 - <value value="45" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM"/> 1602 1602 - <value value="46" name="A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS_KAILUA"/> 1603 1603 - <value value="47" name="A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS_KAILUA"/> 1604 1604 - <value value="48" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE"/> 1605 1605 - <value value="49" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER_KAILUA"/> 1606 1606 - <value value="50" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE"/> 1607 1607 - <value value="51" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS"/> 1608 1608 - <value value="52" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0"/> 1609 1609 - <value value="53" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1"/> 1610 1610 - <value value="54" name="A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL"/> 1611 1611 - <value value="55" name="A7XX_PERF_UCHE_CCHE_DPH_QUEUE_FULL"/> 1612 1612 - <value value="56" name="A7XX_PERF_UCHE_GMEM_WRITE_BEATS"/> 1613 1613 - <value value="57" name="A7XX_PERF_UCHE_UBWC_READ_BEATS"/> 1614 1614 - <value value="58" name="A7XX_PERF_UCHE_UBWC_WRITE_BEATS"/> 1615 1615 - </enum> 1616 1616 - 1617 1617 - <enum name="a7xx_tp_perfcounter_select"> 1618 1618 - <value value="0" name="A7XX_PERF_TP_BUSY_CYCLES"/> 1619 1619 - <value value="1" name="A7XX_PERF_TP_STALL_CYCLES_UCHE"/> 1620 1620 - <value value="2" name="A7XX_PERF_TP_LATENCY_CYCLES"/> 1621 1621 - <value value="3" name="A7XX_PERF_TP_LATENCY_TRANS"/> 1622 1622 - <value value="4" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES"/> 1623 1623 - <value value="5" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES"/> 1624 1624 - <value value="6" name="A7XX_PERF_TP_L1_CACHELINE_REQUESTS"/> 1625 1625 - <value value="7" name="A7XX_PERF_TP_L1_CACHELINE_MISSES"/> 1626 1626 - <value value="8" name="A7XX_PERF_TP_SP_TP_TRANS"/> 1627 1627 - <value value="9" name="A7XX_PERF_TP_TP_SP_TRANS"/> 1628 1628 - <value value="10" name="A7XX_PERF_TP_OUTPUT_PIXELS"/> 1629 1629 - <value value="11" name="A7XX_PERF_TP_FILTER_WORKLOAD_16BIT"/> 1630 1630 - <value value="12" name="A7XX_PERF_TP_FILTER_WORKLOAD_32BIT"/> 1631 1631 - <value value="13" name="A7XX_PERF_TP_QUADS_RECEIVED"/> 1632 1632 - <value value="14" name="A7XX_PERF_TP_QUADS_OFFSET"/> 1633 1633 - <value value="15" name="A7XX_PERF_TP_QUADS_SHADOW"/> 1634 1634 - <value value="16" name="A7XX_PERF_TP_QUADS_ARRAY"/> 1635 1635 - <value value="17" name="A7XX_PERF_TP_QUADS_GRADIENT"/> 1636 1636 - <value value="18" name="A7XX_PERF_TP_QUADS_1D"/> 1637 1637 - <value value="19" name="A7XX_PERF_TP_QUADS_2D"/> 1638 1638 - <value value="20" name="A7XX_PERF_TP_QUADS_BUFFER"/> 1639 1639 - <value value="21" name="A7XX_PERF_TP_QUADS_3D"/> 1640 1640 - <value value="22" name="A7XX_PERF_TP_QUADS_CUBE"/> 1641 1641 - <value value="23" name="A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED"/> 1642 1642 - <value value="24" name="A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS"/> 1643 1643 - <value value="25" name="A7XX_PERF_TP_OUTPUT_PIXELS_POINT"/> 1644 1644 - <value value="26" name="A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR"/> 1645 1645 - <value value="27" name="A7XX_PERF_TP_OUTPUT_PIXELS_MIP"/> 1646 1646 - <value value="28" name="A7XX_PERF_TP_OUTPUT_PIXELS_ANISO"/> 1647 1647 - <value value="29" name="A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> 1648 1648 - <value value="30" name="A7XX_PERF_TP_FLAG_CACHE_REQUESTS"/> 1649 1649 - <value value="31" name="A7XX_PERF_TP_FLAG_CACHE_MISSES"/> 1650 1650 - <value value="32" name="A7XX_PERF_TP_L1_5_L2_REQUESTS"/> 1651 1651 - <value value="33" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS"/> 1652 1652 - <value value="34" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT"/> 1653 1653 - <value value="35" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> 1654 1654 - <value value="36" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> 1655 1655 - <value value="37" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> 1656 1656 - <value value="38" name="A7XX_PERF_TP_TPA2TPC_TRANS"/> 1657 1657 - <value value="39" name="A7XX_PERF_TP_L1_MISSES_ASTC_1TILE"/> 1658 1658 - <value value="40" name="A7XX_PERF_TP_L1_MISSES_ASTC_2TILE"/> 1659 1659 - <value value="41" name="A7XX_PERF_TP_L1_MISSES_ASTC_4TILE"/> 1660 1660 - <value value="42" name="A7XX_PERF_TP_L1_5_COMPRESS_REQS"/> 1661 1661 - <value value="43" name="A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS"/> 1662 1662 - <value value="44" name="A7XX_PERF_TP_L1_BANK_CONFLICT"/> 1663 1663 - <value value="45" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> 1664 1664 - <value value="46" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS"/> 1665 1665 - <value value="47" name="A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> 1666 1666 - <value value="48" name="A7XX_PERF_TP_FRONTEND_WORKING_CYCLES"/> 1667 1667 - <value value="49" name="A7XX_PERF_TP_L1_TAG_WORKING_CYCLES"/> 1668 1668 - <value value="50" name="A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> 1669 1669 - <value value="51" name="A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> 1670 1670 - <value value="52" name="A7XX_PERF_TP_BACKEND_WORKING_CYCLES"/> 1671 1671 - <value value="53" name="A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> 1672 1672 - <value value="54" name="A7XX_PERF_TP_STARVE_CYCLES_SP"/> 1673 1673 - <value value="55" name="A7XX_PERF_TP_STARVE_CYCLES_UCHE"/> 1674 1674 - <value value="56" name="A7XX_PERF_TP_STALL_CYCLES_UFC"/> 1675 1675 - <value value="57" name="A7XX_PERF_TP_FORMAT_DECOMP"/> 1676 1676 - <value value="58" name="A7XX_PERF_TP_FILTER_POINT_FP16"/> 1677 1677 - <value value="59" name="A7XX_PERF_TP_FILTER_POINT_FP32"/> 1678 1678 - <value value="60" name="A7XX_PERF_TP_LATENCY_FIFO_FULL"/> 1679 1679 - <value value="61" name="A7XX_PERF_TP_RESERVED_61"/> 1680 1680 - <value value="62" name="A7XX_PERF_TP_RESERVED_62"/> 1681 1681 - <value value="63" name="A7XX_PERF_TP_RESERVED_63"/> 1682 1682 - <value value="64" name="A7XX_PERF_TP_RESERVED_64"/> 1683 1683 - <value value="65" name="A7XX_PERF_TP_RESERVED_65"/> 1684 1684 - <value value="66" name="A7XX_PERF_TP_RESERVED_66"/> 1685 1685 - <value value="67" name="A7XX_PERF_TP_RESERVED_67"/> 1686 1686 - <value value="68" name="A7XX_PERF_TP_RESERVED_68"/> 1687 1687 - <value value="69" name="A7XX_PERF_TP_RESERVED_69"/> 1688 1688 - <value value="70" name="A7XX_PERF_TP_RESERVED_70"/> 1689 1689 - <value value="71" name="A7XX_PERF_TP_RESERVED_71"/> 1690 1690 - <value value="72" name="A7XX_PERF_TP_RESERVED_72"/> 1691 1691 - <value value="73" name="A7XX_PERF_TP_RESERVED_73"/> 1692 1692 - <value value="74" name="A7XX_PERF_TP_RESERVED_74"/> 1693 1693 - <value value="75" name="A7XX_PERF_TP_RESERVED_75"/> 1694 1694 - <value value="76" name="A7XX_PERF_TP_RESERVED_76"/> 1695 1695 - <value value="77" name="A7XX_PERF_TP_RESERVED_77"/> 1696 1696 - <value value="78" name="A7XX_PERF_TP_RESERVED_78"/> 1697 1697 - <value value="79" name="A7XX_PERF_TP_RESERVED_79"/> 1698 1698 - <value value="80" name="A7XX_PERF_TP_RESERVED_80"/> 1699 1699 - <value value="81" name="A7XX_PERF_TP_RESERVED_81"/> 1700 1700 - <value value="82" name="A7XX_PERF_TP_RESERVED_82"/> 1701 1701 - <value value="83" name="A7XX_PERF_TP_RESERVED_83"/> 1702 1702 - <value value="84" name="A7XX_PERF_TP_RESERVED_84"/> 1703 1703 - <value value="85" name="A7XX_PERF_TP_RESERVED_85"/> 1704 1704 - <value value="86" name="A7XX_PERF_TP_RESERVED_86"/> 1705 1705 - <value value="87" name="A7XX_PERF_TP_RESERVED_87"/> 1706 1706 - <value value="88" name="A7XX_PERF_TP_RESERVED_88"/> 1707 1707 - <value value="89" name="A7XX_PERF_TP_RESERVED_89"/> 1708 1708 - <value value="90" name="A7XX_PERF_TP_RESERVED_90"/> 1709 1709 - <value value="91" name="A7XX_PERF_TP_RESERVED_91"/> 1710 1710 - <value value="92" name="A7XX_PERF_TP_RESERVED_92"/> 1711 1711 - <value value="93" name="A7XX_PERF_TP_RESERVED_93"/> 1712 1712 - <value value="94" name="A7XX_PERF_TP_RESERVED_94"/> 1713 1713 - <value value="95" name="A7XX_PERF_TP_RESERVED_95"/> 1714 1714 - <value value="96" name="A7XX_PERF_TP_RESERVED_96"/> 1715 1715 - <value value="97" name="A7XX_PERF_TP_RESERVED_97"/> 1716 1716 - <value value="98" name="A7XX_PERF_TP_RESERVED_98"/> 1717 1717 - <value value="99" name="A7XX_PERF_TP_RESERVED_99"/> 1718 1718 - <value value="100" name="A7XX_PERF_TP_RESERVED_100"/> 1719 1719 - <value value="101" name="A7XX_PERF_TP_RESERVED_101"/> 1720 1720 - <value value="102" name="A7XX_PERF_TP_RESERVED_102"/> 1721 1721 - <value value="103" name="A7XX_PERF_TP_RESERVED_103"/> 1722 1722 - <value value="104" name="A7XX_PERF_TP_RESERVED_104"/> 1723 1723 - <value value="105" name="A7XX_PERF_TP_RESERVED_105"/> 1724 1724 - <value value="106" name="A7XX_PERF_TP_RESERVED_106"/> 1725 1725 - <value value="107" name="A7XX_PERF_TP_RESERVED_107"/> 1726 1726 - <value value="108" name="A7XX_PERF_TP_RESERVED_108"/> 1727 1727 - <value value="109" name="A7XX_PERF_TP_RESERVED_109"/> 1728 1728 - <value value="110" name="A7XX_PERF_TP_RESERVED_110"/> 1729 1729 - <value value="111" name="A7XX_PERF_TP_RESERVED_111"/> 1730 1730 - <value value="112" name="A7XX_PERF_TP_RESERVED_112"/> 1731 1731 - <value value="113" name="A7XX_PERF_TP_RESERVED_113"/> 1732 1732 - <value value="114" name="A7XX_PERF_TP_RESERVED_114"/> 1733 1733 - <value value="115" name="A7XX_PERF_TP_RESERVED_115"/> 1734 1734 - <value value="116" name="A7XX_PERF_TP_RESERVED_116"/> 1735 1735 - <value value="117" name="A7XX_PERF_TP_RESERVED_117"/> 1736 1736 - <value value="118" name="A7XX_PERF_TP_RESERVED_118"/> 1737 1737 - <value value="119" name="A7XX_PERF_TP_RESERVED_119"/> 1738 1738 - <value value="120" name="A7XX_PERF_TP_RESERVED_120"/> 1739 1739 - <value value="121" name="A7XX_PERF_TP_RESERVED_121"/> 1740 1740 - <value value="122" name="A7XX_PERF_TP_RESERVED_122"/> 1741 1741 - <value value="123" name="A7XX_PERF_TP_RESERVED_123"/> 1742 1742 - <value value="124" name="A7XX_PERF_TP_RESERVED_124"/> 1743 1743 - <value value="125" name="A7XX_PERF_TP_RESERVED_125"/> 1744 1744 - <value value="126" name="A7XX_PERF_TP_RESERVED_126"/> 1745 1745 - <value value="127" name="A7XX_PERF_TP_RESERVED_127"/> 1746 1746 - <value value="128" name="A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR"/> 1747 1747 - <value value="129" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16"/> 1748 1748 - <value value="130" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16"/> 1749 1749 - <value value="131" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32"/> 1750 1750 - <value value="132" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32"/> 1751 1751 - </enum> 1752 1752 - 1753 1753 - <enum name="a7xx_sp_perfcounter_select"> 1754 1754 - <value value="0" name="A7XX_PERF_SP_BUSY_CYCLES"/> 1755 1755 - <value value="1" name="A7XX_PERF_SP_ALU_WORKING_CYCLES"/> 1756 1756 - <value value="2" name="A7XX_PERF_SP_EFU_WORKING_CYCLES"/> 1757 1757 - <value value="3" name="A7XX_PERF_SP_STALL_CYCLES_VPC"/> 1758 1758 - <value value="4" name="A7XX_PERF_SP_STALL_CYCLES_TP"/> 1759 1759 - <value value="5" name="A7XX_PERF_SP_STALL_CYCLES_UCHE"/> 1760 1760 - <value value="6" name="A7XX_PERF_SP_STALL_CYCLES_RB"/> 1761 1761 - <value value="7" name="A7XX_PERF_SP_NON_EXECUTION_CYCLES"/> 1762 1762 - <value value="8" name="A7XX_PERF_SP_WAVE_CONTEXTS"/> 1763 1763 - <value value="9" name="A7XX_PERF_SP_WAVE_CONTEXT_CYCLES"/> 1764 1764 - <value value="10" name="A7XX_PERF_SP_STAGE_WAVE_CYCLES"/> 1765 1765 - <value value="11" name="A7XX_PERF_SP_STAGE_WAVE_SAMPLES"/> 1766 1766 - <value value="12" name="A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES"/> 1767 1767 - <value value="13" name="A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES"/> 1768 1768 - <value value="14" name="A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES"/> 1769 1769 - <value value="15" name="A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES"/> 1770 1770 - <value value="16" name="A7XX_PERF_SP_WAVE_CTRL_CYCLES"/> 1771 1771 - <value value="17" name="A7XX_PERF_SP_WAVE_LOAD_CYCLES"/> 1772 1772 - <value value="18" name="A7XX_PERF_SP_WAVE_EMIT_CYCLES"/> 1773 1773 - <value value="19" name="A7XX_PERF_SP_WAVE_NOP_CYCLES"/> 1774 1774 - <value value="20" name="A7XX_PERF_SP_WAVE_WAIT_CYCLES"/> 1775 1775 - <value value="21" name="A7XX_PERF_SP_WAVE_FETCH_CYCLES"/> 1776 1776 - <value value="22" name="A7XX_PERF_SP_WAVE_IDLE_CYCLES"/> 1777 1777 - <value value="23" name="A7XX_PERF_SP_WAVE_END_CYCLES"/> 1778 1778 - <value value="24" name="A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES"/> 1779 1779 - <value value="25" name="A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> 1780 1780 - <value value="26" name="A7XX_PERF_SP_WAVE_JOIN_CYCLES"/> 1781 1781 - <value value="27" name="A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS"/> 1782 1782 - <value value="28" name="A7XX_PERF_SP_LM_STORE_INSTRUCTIONS"/> 1783 1783 - <value value="29" name="A7XX_PERF_SP_LM_ATOMICS"/> 1784 1784 - <value value="30" name="A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS"/> 1785 1785 - <value value="31" name="A7XX_PERF_SP_GM_STORE_INSTRUCTIONS"/> 1786 1786 - <value value="32" name="A7XX_PERF_SP_GM_ATOMICS"/> 1787 1787 - <value value="33" name="A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> 1788 1788 - <value value="34" name="A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> 1789 1789 - <value value="35" name="A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> 1790 1790 - <value value="36" name="A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> 1791 1791 - <value value="37" name="A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> 1792 1792 - <value value="38" name="A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> 1793 1793 - <value value="39" name="A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> 1794 1794 - <value value="40" name="A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> 1795 1795 - <value value="41" name="A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> 1796 1796 - <value value="42" name="A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> 1797 1797 - <value value="43" name="A7XX_PERF_SP_VS_INSTRUCTIONS"/> 1798 1798 - <value value="44" name="A7XX_PERF_SP_FS_INSTRUCTIONS"/> 1799 1799 - <value value="45" name="A7XX_PERF_SP_ADDR_LOCK_COUNT"/> 1800 1800 - <value value="46" name="A7XX_PERF_SP_UCHE_READ_TRANS"/> 1801 1801 - <value value="47" name="A7XX_PERF_SP_UCHE_WRITE_TRANS"/> 1802 1802 - <value value="48" name="A7XX_PERF_SP_EXPORT_VPC_TRANS"/> 1803 1803 - <value value="49" name="A7XX_PERF_SP_EXPORT_RB_TRANS"/> 1804 1804 - <value value="50" name="A7XX_PERF_SP_PIXELS_KILLED"/> 1805 1805 - <value value="51" name="A7XX_PERF_SP_ICL1_REQUESTS"/> 1806 1806 - <value value="52" name="A7XX_PERF_SP_ICL1_MISSES"/> 1807 1807 - <value value="53" name="A7XX_PERF_SP_HS_INSTRUCTIONS"/> 1808 1808 - <value value="54" name="A7XX_PERF_SP_DS_INSTRUCTIONS"/> 1809 1809 - <value value="55" name="A7XX_PERF_SP_GS_INSTRUCTIONS"/> 1810 1810 - <value value="56" name="A7XX_PERF_SP_CS_INSTRUCTIONS"/> 1811 1811 - <value value="57" name="A7XX_PERF_SP_GPR_READ"/> 1812 1812 - <value value="58" name="A7XX_PERF_SP_GPR_WRITE"/> 1813 1813 - <value value="59" name="A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> 1814 1814 - <value value="60" name="A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> 1815 1815 - <value value="61" name="A7XX_PERF_SP_LM_BANK_CONFLICTS"/> 1816 1816 - <value value="62" name="A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> 1817 1817 - <value value="63" name="A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> 1818 1818 - <value value="64" name="A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> 1819 1819 - <value value="65" name="A7XX_PERF_SP_LM_WORKING_CYCLES"/> 1820 1820 - <value value="66" name="A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES"/> 1821 1821 - <value value="67" name="A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES"/> 1822 1822 - <value value="68" name="A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> 1823 1823 - <value value="69" name="A7XX_PERF_SP_STARVE_CYCLES_HLSQ"/> 1824 1824 - <value value="70" name="A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES"/> 1825 1825 - <value value="71" name="A7XX_PERF_SP_WORKING_EU"/> 1826 1826 - <value value="72" name="A7XX_PERF_SP_ANY_EU_WORKING"/> 1827 1827 - <value value="73" name="A7XX_PERF_SP_WORKING_EU_FS_STAGE"/> 1828 1828 - <value value="74" name="A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE"/> 1829 1829 - <value value="75" name="A7XX_PERF_SP_WORKING_EU_VS_STAGE"/> 1830 1830 - <value value="76" name="A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE"/> 1831 1831 - <value value="77" name="A7XX_PERF_SP_WORKING_EU_CS_STAGE"/> 1832 1832 - <value value="78" name="A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE"/> 1833 1833 - <value value="79" name="A7XX_PERF_SP_GPR_READ_PREFETCH"/> 1834 1834 - <value value="80" name="A7XX_PERF_SP_GPR_READ_CONFLICT"/> 1835 1835 - <value value="81" name="A7XX_PERF_SP_GPR_WRITE_CONFLICT"/> 1836 1836 - <value value="82" name="A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES"/> 1837 1837 - <value value="83" name="A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> 1838 1838 - <value value="84" name="A7XX_PERF_SP_EXECUTABLE_WAVES"/> 1839 1839 - <value value="85" name="A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES"/> 1840 1840 - <value value="86" name="A7XX_PERF_SP_WORKING_EU_LPAC"/> 1841 1841 - <value value="87" name="A7XX_PERF_SP_BYPASS_BUSY_CYCLES"/> 1842 1842 - <value value="88" name="A7XX_PERF_SP_ANY_EU_WORKING_LPAC"/> 1843 1843 - <value value="89" name="A7XX_PERF_SP_WAVE_ALU_CYCLES"/> 1844 1844 - <value value="90" name="A7XX_PERF_SP_WAVE_EFU_CYCLES"/> 1845 1845 - <value value="91" name="A7XX_PERF_SP_WAVE_INT_CYCLES"/> 1846 1846 - <value value="92" name="A7XX_PERF_SP_WAVE_CSP_CYCLES"/> 1847 1847 - <value value="93" name="A7XX_PERF_SP_EWAVE_CONTEXTS"/> 1848 1848 - <value value="94" name="A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES"/> 1849 1849 - <value value="95" name="A7XX_PERF_SP_LPAC_BUSY_CYCLES"/> 1850 1850 - <value value="96" name="A7XX_PERF_SP_LPAC_INSTRUCTIONS"/> 1851 1851 - <value value="97" name="A7XX_PERF_SP_FS_STAGE_1X_WAVES"/> 1852 1852 - <value value="98" name="A7XX_PERF_SP_FS_STAGE_2X_WAVES"/> 1853 1853 - <value value="99" name="A7XX_PERF_SP_QUADS"/> 1854 1854 - <value value="100" name="A7XX_PERF_SP_CS_INVOCATIONS"/> 1855 1855 - <value value="101" name="A7XX_PERF_SP_PIXELS"/> 1856 1856 - <value value="102" name="A7XX_PERF_SP_LPAC_DRAWCALLS"/> 1857 1857 - <value value="103" name="A7XX_PERF_SP_PI_WORKING_CYCLES"/> 1858 1858 - <value value="104" name="A7XX_PERF_SP_WAVE_INPUT_CYCLES"/> 1859 1859 - <value value="105" name="A7XX_PERF_SP_WAVE_OUTPUT_CYCLES"/> 1860 1860 - <value value="106" name="A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES"/> 1861 1861 - <value value="107" name="A7XX_PERF_SP_WAVE_HWAVE_SYNC"/> 1862 1862 - <value value="108" name="A7XX_PERF_SP_OUTPUT_3D_PIXELS"/> 1863 1863 - <value value="109" name="A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS"/> 1864 1864 - <value value="110" name="A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS"/> 1865 1865 - <value value="111" name="A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS"/> 1866 1866 - <value value="112" name="A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS"/> 1867 1867 - <value value="113" name="A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS"/> 1868 1868 - <value value="114" name="A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS"/> 1869 1869 - <value value="115" name="A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS"/> 1870 1870 - <value value="116" name="A7XX_PERF_SP_ALU_GPR_READ_CYCLES"/> 1871 1871 - <value value="117" name="A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES"/> 1872 1872 - <value value="118" name="A7XX_PERF_SP_LM_FULL_CYCLES"/> 1873 1873 - <value value="119" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES"/> 1874 1874 - <value value="120" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES"/> 1875 1875 - <value value="121" name="A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION"/> 1876 1876 - <value value="122" name="A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS"/> 1877 1877 - <value value="123" name="A7XX_PERF_SP_RBRT_KICKOFF_FIBERS"/> 1878 1878 - <value value="124" name="A7XX_PERF_SP_RBRT_KICKOFF_DQUADS"/> 1879 1879 - <value value="125" name="A7XX_PERF_SP_RTU_BUSY_CYCLES"/> 1880 1880 - <value value="126" name="A7XX_PERF_SP_RTU_L0_HITS"/> 1881 1881 - <value value="127" name="A7XX_PERF_SP_RTU_L0_MISSES"/> 1882 1882 - <value value="128" name="A7XX_PERF_SP_RTU_L0_HIT_ON_MISS"/> 1883 1883 - <value value="129" name="A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE"/> 1884 1884 - <value value="130" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE"/> 1885 1885 - <value value="131" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE"/> 1886 1886 - <value value="132" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE"/> 1887 1887 - <value value="133" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA"/> 1888 1888 - <value value="134" name="A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT"/> 1889 1889 - <value value="135" name="A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT"/> 1890 1890 - <value value="136" name="A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE"/> 1891 1891 - <value value="137" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0"/> 1892 1892 - <value value="138" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO"/> 1893 1893 - <value value="139" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES"/> 1894 1894 - <value value="140" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES"/> 1895 1895 - <value value="141" name="A7XX_PERF_SP_STCHE_MISS_INC_VS"/> 1896 1896 - <value value="142" name="A7XX_PERF_SP_STCHE_MISS_INC_FS"/> 1897 1897 - <value value="143" name="A7XX_PERF_SP_STCHE_MISS_INC_BV"/> 1898 1898 - <value value="144" name="A7XX_PERF_SP_STCHE_MISS_INC_LPAC"/> 1899 1899 - <value value="145" name="A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS"/> 1900 1900 - <value value="146" name="A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS"/> 1901 1901 - <value value="147" name="A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS"/> 1902 1902 - <value value="148" name="A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS"/> 1903 1903 - <value value="149" name="A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS"/> 1904 1904 - <value value="150" name="A7XX_PERF_SP_SCH_STALL_CYCLES_RTU"/> 1905 1905 - </enum> 1906 1906 - 1907 1907 - <enum name="a7xx_rb_perfcounter_select"> 1908 1908 - <value value="0" name="A7XX_PERF_RB_BUSY_CYCLES"/> 1909 1909 - <value value="1" name="A7XX_PERF_RB_STALL_CYCLES_HLSQ"/> 1910 1910 - <value value="2" name="A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL"/> 1911 1911 - <value value="3" name="A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL"/> 1912 1912 - <value value="4" name="A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL"/> 1913 1913 - <value value="5" name="A7XX_PERF_RB_STARVE_CYCLES_SP"/> 1914 1914 - <value value="6" name="A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE"/> 1915 1915 - <value value="7" name="A7XX_PERF_RB_STARVE_CYCLES_CCU"/> 1916 1916 - <value value="8" name="A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE"/> 1917 1917 - <value value="9" name="A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE"/> 1918 1918 - <value value="10" name="A7XX_PERF_RB_Z_WORKLOAD"/> 1919 1919 - <value value="11" name="A7XX_PERF_RB_HLSQ_ACTIVE"/> 1920 1920 - <value value="12" name="A7XX_PERF_RB_Z_READ"/> 1921 1921 - <value value="13" name="A7XX_PERF_RB_Z_WRITE"/> 1922 1922 - <value value="14" name="A7XX_PERF_RB_C_READ"/> 1923 1923 - <value value="15" name="A7XX_PERF_RB_C_WRITE"/> 1924 1924 - <value value="16" name="A7XX_PERF_RB_TOTAL_PASS"/> 1925 1925 - <value value="17" name="A7XX_PERF_RB_Z_PASS"/> 1926 1926 - <value value="18" name="A7XX_PERF_RB_Z_FAIL"/> 1927 1927 - <value value="19" name="A7XX_PERF_RB_S_FAIL"/> 1928 1928 - <value value="20" name="A7XX_PERF_RB_BLENDED_FXP_COMPONENTS"/> 1929 1929 - <value value="21" name="A7XX_PERF_RB_BLENDED_FP16_COMPONENTS"/> 1930 1930 - <value value="22" name="A7XX_PERF_RB_PS_INVOCATIONS"/> 1931 1931 - <value value="23" name="A7XX_PERF_RB_2D_ALIVE_CYCLES"/> 1932 1932 - <value value="24" name="A7XX_PERF_RB_2D_STALL_CYCLES_A2D"/> 1933 1933 - <value value="25" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SRC"/> 1934 1934 - <value value="26" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SP"/> 1935 1935 - <value value="27" name="A7XX_PERF_RB_2D_STARVE_CYCLES_DST"/> 1936 1936 - <value value="28" name="A7XX_PERF_RB_2D_VALID_PIXELS"/> 1937 1937 - <value value="29" name="A7XX_PERF_RB_3D_PIXELS"/> 1938 1938 - <value value="30" name="A7XX_PERF_RB_BLENDER_WORKING_CYCLES"/> 1939 1939 - <value value="31" name="A7XX_PERF_RB_ZPROC_WORKING_CYCLES"/> 1940 1940 - <value value="32" name="A7XX_PERF_RB_CPROC_WORKING_CYCLES"/> 1941 1941 - <value value="33" name="A7XX_PERF_RB_SAMPLER_WORKING_CYCLES"/> 1942 1942 - <value value="34" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> 1943 1943 - <value value="35" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> 1944 1944 - <value value="36" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> 1945 1945 - <value value="37" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> 1946 1946 - <value value="38" name="A7XX_PERF_RB_STALL_CYCLES_VPC"/> 1947 1947 - <value value="39" name="A7XX_PERF_RB_2D_INPUT_TRANS"/> 1948 1948 - <value value="40" name="A7XX_PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> 1949 1949 - <value value="41" name="A7XX_PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> 1950 1950 - <value value="42" name="A7XX_PERF_RB_BLENDED_FP32_COMPONENTS"/> 1951 1951 - <value value="43" name="A7XX_PERF_RB_COLOR_PIX_TILES"/> 1952 1952 - <value value="44" name="A7XX_PERF_RB_STALL_CYCLES_CCU"/> 1953 1953 - <value value="45" name="A7XX_PERF_RB_EARLY_Z_ARB3_GRANT"/> 1954 1954 - <value value="46" name="A7XX_PERF_RB_LATE_Z_ARB3_GRANT"/> 1955 1955 - <value value="47" name="A7XX_PERF_RB_EARLY_Z_SKIP_GRANT"/> 1956 1956 - <value value="48" name="A7XX_PERF_RB_VRS_1x1_QUADS"/> 1957 1957 - <value value="49" name="A7XX_PERF_RB_VRS_2x1_QUADS"/> 1958 1958 - <value value="50" name="A7XX_PERF_RB_VRS_1x2_QUADS"/> 1959 1959 - <value value="51" name="A7XX_PERF_RB_VRS_2x2_QUADS"/> 1960 1960 - <value value="52" name="A7XX_PERF_RB_VRS_4x2_QUADS"/> 1961 1961 - <value value="53" name="A7XX_PERF_RB_VRS_4x4_QUADS"/> 1962 1962 - </enum> 1963 1963 - 1964 1964 - <enum name="a7xx_vsc_perfcounter_select"> 1965 1965 - <value value="0" name="A7XX_PERF_VSC_BUSY_CYCLES"/> 1966 1966 - <value value="1" name="A7XX_PERF_VSC_WORKING_CYCLES"/> 1967 1967 - <value value="2" name="A7XX_PERF_VSC_STALL_CYCLES_UCHE"/> 1968 1968 - <value value="3" name="A7XX_PERF_VSC_EOT_NUM"/> 1969 1969 - <value value="4" name="A7XX_PERF_VSC_INPUT_TILES"/> 1970 1970 - </enum> 1971 1971 - 1972 1972 - <enum name="a7xx_ccu_perfcounter_select"> 1973 1973 - <value value="0" name="A7XX_PERF_CCU_BUSY_CYCLES"/> 1974 1974 - <value value="1" name="A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> 1975 1975 - <value value="2" name="A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> 1976 1976 - <value value="3" name="A7XX_PERF_CCU_DEPTH_BLOCKS"/> 1977 1977 - <value value="4" name="A7XX_PERF_CCU_COLOR_BLOCKS"/> 1978 1978 - <value value="5" name="A7XX_PERF_CCU_DEPTH_BLOCK_HIT"/> 1979 1979 - <value value="6" name="A7XX_PERF_CCU_COLOR_BLOCK_HIT"/> 1980 1980 - <value value="7" name="A7XX_PERF_CCU_PARTIAL_BLOCK_READ"/> 1981 1981 - <value value="8" name="A7XX_PERF_CCU_GMEM_READ"/> 1982 1982 - <value value="9" name="A7XX_PERF_CCU_GMEM_WRITE"/> 1983 1983 - <value value="10" name="A7XX_PERF_CCU_2D_RD_REQ"/> 1984 1984 - <value value="11" name="A7XX_PERF_CCU_2D_WR_REQ"/> 1985 1985 - <value value="12" name="A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT"/> 1986 1986 - <value value="13" name="A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT"/> 1987 1987 - <value value="14" name="A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED"/> 1988 1988 - <value value="15" name="A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED"/> 1989 1989 - <value value="16" name="A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT"/> 1990 1990 - <value value="17" name="A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT"/> 1991 1991 - <value value="18" name="A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER"/> 1992 1992 - <value value="19" name="A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER"/> 1993 1993 - <value value="20" name="A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ"/> 1994 1994 - <value value="21" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA"/> 1995 1995 - <value value="22" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL"/> 1996 1996 - </enum> 1997 1997 - 1998 1998 - <enum name="a7xx_lrz_perfcounter_select"> 1999 1999 - <value value="0" name="A7XX_PERF_LRZ_BUSY_CYCLES"/> 2000 2000 - <value value="1" name="A7XX_PERF_LRZ_STARVE_CYCLES_RAS"/> 2001 2001 - <value value="2" name="A7XX_PERF_LRZ_STALL_CYCLES_RB"/> 2002 2002 - <value value="3" name="A7XX_PERF_LRZ_STALL_CYCLES_VSC"/> 2003 2003 - <value value="4" name="A7XX_PERF_LRZ_STALL_CYCLES_VPC"/> 2004 2004 - <value value="5" name="A7XX_PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> 2005 2005 - <value value="6" name="A7XX_PERF_LRZ_STALL_CYCLES_UCHE"/> 2006 2006 - <value value="7" name="A7XX_PERF_LRZ_LRZ_READ"/> 2007 2007 - <value value="8" name="A7XX_PERF_LRZ_LRZ_WRITE"/> 2008 2008 - <value value="9" name="A7XX_PERF_LRZ_READ_LATENCY"/> 2009 2009 - <value value="10" name="A7XX_PERF_LRZ_MERGE_CACHE_UPDATING"/> 2010 2010 - <value value="11" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> 2011 2011 - <value value="12" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ"/> 2012 2012 - <value value="13" name="A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> 2013 2013 - <value value="14" name="A7XX_PERF_LRZ_FULL_8X8_TILES"/> 2014 2014 - <value value="15" name="A7XX_PERF_LRZ_PARTIAL_8X8_TILES"/> 2015 2015 - <value value="16" name="A7XX_PERF_LRZ_TILE_KILLED"/> 2016 2016 - <value value="17" name="A7XX_PERF_LRZ_TOTAL_PIXEL"/> 2017 2017 - <value value="18" name="A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> 2018 2018 - <value value="19" name="A7XX_PERF_LRZ_FEEDBACK_ACCEPT"/> 2019 2019 - <value value="20" name="A7XX_PERF_LRZ_FEEDBACK_DISCARD"/> 2020 2020 - <value value="21" name="A7XX_PERF_LRZ_FEEDBACK_STALL"/> 2021 2021 - <value value="22" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> 2022 2022 - <value value="23" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> 2023 2023 - <value value="24" name="A7XX_PERF_LRZ_RAS_MASK_TRANS"/> 2024 2024 - <value value="25" name="A7XX_PERF_LRZ_STALL_CYCLES_MVC"/> 2025 2025 - <value value="26" name="A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS"/> 2026 2026 - <value value="27" name="A7XX_PERF_LRZ_TILE_KILLED_BY_Z"/> 2027 2027 - </enum> 2028 2028 - 2029 2029 - <enum name="a7xx_cmp_perfcounter_select"> 2030 2030 - <value value="0" name="A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB"/> 2031 2031 - <value value="1" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> 2032 2032 - <value value="2" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> 2033 2033 - <value value="3" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> 2034 2034 - <value value="4" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> 2035 2035 - <value value="5" name="A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST"/> 2036 2036 - <value value="6" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> 2037 2037 - <value value="7" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA"/> 2038 2038 - <value value="8" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA"/> 2039 2039 - <value value="9" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> 2040 2040 - <value value="10" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> 2041 2041 - <value value="11" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> 2042 2042 - <value value="12" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> 2043 2043 - <value value="13" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> 2044 2044 - <value value="14" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> 2045 2045 - <value value="15" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> 2046 2046 - <value value="16" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> 2047 2047 - <value value="17" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> 2048 2048 - <value value="18" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> 2049 2049 - <value value="19" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> 2050 2050 - <value value="20" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> 2051 2051 - <value value="21" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> 2052 2052 - <value value="22" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> 2053 2053 - <value value="23" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> 2054 2054 - <value value="24" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> 2055 2055 - <value value="25" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> 2056 2056 - <value value="26" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> 2057 2057 - <value value="27" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> 2058 2058 - <value value="28" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> 2059 2059 - <value value="29" name="A7XX_PERF_CMPDECMP_RESOLVE_EVENTS"/> 2060 2060 - <value value="30" name="A7XX_PERF_CMPDECMP_CONCURRENT_RESOLVE_EVENTS"/> 2061 2061 - <value value="31" name="A7XX_PERF_CMPDECMP_DROPPED_CLEAR_EVENTS"/> 2062 2062 - <value value="32" name="A7XX_PERF_CMPDECMP_ST_BLOCKS_CONCURRENT"/> 2063 2063 - <value value="33" name="A7XX_PERF_CMPDECMP_LRZ_ST_BLOCKS_CONCURRENT"/> 2064 2064 - <value value="34" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT"/> 2065 2065 - <value value="35" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT"/> 2066 2066 - <value value="36" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT"/> 2067 2067 - <value value="37" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT"/> 2068 2068 - <value value="38" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT"/> 2069 2069 - <value value="39" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT"/> 2070 2070 - <value value="40" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT"/> 2071 2071 - <value value="41" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT"/> 2072 2072 - <value value="42" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT"/> 2073 2073 - <value value="43" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT"/> 2074 2074 - <value value="44" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT"/> 2075 2075 - <value value="45" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT"/> 2076 2076 - <value value="46" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT"/> 2077 2077 - <value value="47" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT"/> 2078 2078 - <value value="48" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT"/> 2079 2079 - <value value="49" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT"/> 2080 2080 - </enum> 2081 2081 - 2082 2082 - <enum name="a7xx_gbif_perfcounter_select"> 2083 2083 - <value value="0" name="A7XX_PERF_GBIF_RESERVED_0"/> 2084 2084 - <value value="1" name="A7XX_PERF_GBIF_RESERVED_1"/> 2085 2085 - <value value="2" name="A7XX_PERF_GBIF_RESERVED_2"/> 2086 2086 - <value value="3" name="A7XX_PERF_GBIF_RESERVED_3"/> 2087 2087 - <value value="4" name="A7XX_PERF_GBIF_RESERVED_4"/> 2088 2088 - <value value="5" name="A7XX_PERF_GBIF_RESERVED_5"/> 2089 2089 - <value value="6" name="A7XX_PERF_GBIF_RESERVED_6"/> 2090 2090 - <value value="7" name="A7XX_PERF_GBIF_RESERVED_7"/> 2091 2091 - <value value="8" name="A7XX_PERF_GBIF_RESERVED_8"/> 2092 2092 - <value value="9" name="A7XX_PERF_GBIF_RESERVED_9"/> 2093 2093 - <value value="10" name="A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL"/> 2094 2094 - <value value="11" name="A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL"/> 2095 2095 - <value value="12" name="A7XX_PERF_GBIF_RESERVED_12"/> 2096 2096 - <value value="13" name="A7XX_PERF_GBIF_RESERVED_13"/> 2097 2097 - <value value="14" name="A7XX_PERF_GBIF_RESERVED_14"/> 2098 2098 - <value value="15" name="A7XX_PERF_GBIF_RESERVED_15"/> 2099 2099 - <value value="16" name="A7XX_PERF_GBIF_RESERVED_16"/> 2100 2100 - <value value="17" name="A7XX_PERF_GBIF_RESERVED_17"/> 2101 2101 - <value value="18" name="A7XX_PERF_GBIF_RESERVED_18"/> 2102 2102 - <value value="19" name="A7XX_PERF_GBIF_RESERVED_19"/> 2103 2103 - <value value="20" name="A7XX_PERF_GBIF_RESERVED_20"/> 2104 2104 - <value value="21" name="A7XX_PERF_GBIF_RESERVED_21"/> 2105 2105 - <value value="22" name="A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL"/> 2106 2106 - <value value="23" name="A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL"/> 2107 2107 - <value value="24" name="A7XX_PERF_GBIF_RESERVED_24"/> 2108 2108 - <value value="25" name="A7XX_PERF_GBIF_RESERVED_25"/> 2109 2109 - <value value="26" name="A7XX_PERF_GBIF_RESERVED_26"/> 2110 2110 - <value value="27" name="A7XX_PERF_GBIF_RESERVED_27"/> 2111 2111 - <value value="28" name="A7XX_PERF_GBIF_RESERVED_28"/> 2112 2112 - <value value="29" name="A7XX_PERF_GBIF_RESERVED_29"/> 2113 2113 - <value value="30" name="A7XX_PERF_GBIF_RESERVED_30"/> 2114 2114 - <value value="31" name="A7XX_PERF_GBIF_RESERVED_31"/> 2115 2115 - <value value="32" name="A7XX_PERF_GBIF_RESERVED_32"/> 2116 2116 - <value value="33" name="A7XX_PERF_GBIF_RESERVED_33"/> 2117 2117 - <value value="34" name="A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL"/> 2118 2118 - <value value="35" name="A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL"/> 2119 2119 - <value value="36" name="A7XX_PERF_GBIF_RESERVED_36"/> 2120 2120 - <value value="37" name="A7XX_PERF_GBIF_RESERVED_37"/> 2121 2121 - <value value="38" name="A7XX_PERF_GBIF_RESERVED_38"/> 2122 2122 - <value value="39" name="A7XX_PERF_GBIF_RESERVED_39"/> 2123 2123 - <value value="40" name="A7XX_PERF_GBIF_RESERVED_40"/> 2124 2124 - <value value="41" name="A7XX_PERF_GBIF_RESERVED_41"/> 2125 2125 - <value value="42" name="A7XX_PERF_GBIF_RESERVED_42"/> 2126 2126 - <value value="43" name="A7XX_PERF_GBIF_RESERVED_43"/> 2127 2127 - <value value="44" name="A7XX_PERF_GBIF_RESERVED_44"/> 2128 2128 - <value value="45" name="A7XX_PERF_GBIF_RESERVED_45"/> 2129 2129 - <value value="46" name="A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL"/> 2130 2130 - <value value="47" name="A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL"/> 2131 2131 - <value value="48" name="A7XX_PERF_GBIF_RESERVED_48"/> 2132 2132 - <value value="49" name="A7XX_PERF_GBIF_RESERVED_49"/> 2133 2133 - <value value="50" name="A7XX_PERF_GBIF_RESERVED_50"/> 2134 2134 - <value value="51" name="A7XX_PERF_GBIF_RESERVED_51"/> 2135 2135 - <value value="52" name="A7XX_PERF_GBIF_RESERVED_52"/> 2136 2136 - <value value="53" name="A7XX_PERF_GBIF_RESERVED_53"/> 2137 2137 - <value value="54" name="A7XX_PERF_GBIF_RESERVED_54"/> 2138 2138 - <value value="55" name="A7XX_PERF_GBIF_RESERVED_55"/> 2139 2139 - <value value="56" name="A7XX_PERF_GBIF_RESERVED_56"/> 2140 2140 - <value value="57" name="A7XX_PERF_GBIF_RESERVED_57"/> 2141 2141 - <value value="58" name="A7XX_PERF_GBIF_RESERVED_58"/> 2142 2142 - <value value="59" name="A7XX_PERF_GBIF_RESERVED_59"/> 2143 2143 - <value value="60" name="A7XX_PERF_GBIF_RESERVED_60"/> 2144 2144 - <value value="61" name="A7XX_PERF_GBIF_RESERVED_61"/> 2145 2145 - <value value="62" name="A7XX_PERF_GBIF_RESERVED_62"/> 2146 2146 - <value value="63" name="A7XX_PERF_GBIF_RESERVED_63"/> 2147 2147 - <value value="64" name="A7XX_PERF_GBIF_RESERVED_64"/> 2148 2148 - <value value="65" name="A7XX_PERF_GBIF_RESERVED_65"/> 2149 2149 - <value value="66" name="A7XX_PERF_GBIF_RESERVED_66"/> 2150 2150 - <value value="67" name="A7XX_PERF_GBIF_RESERVED_67"/> 2151 2151 - <value value="68" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL"/> 2152 2152 - <value value="69" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL"/> 2153 2153 - <value value="70" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL"/> 2154 2154 - <value value="71" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL"/> 2155 2155 - <value value="72" name="A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF"/> 2156 2156 - <value value="73" name="A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF"/> 2157 2157 - <value value="74" name="A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF"/> 2158 2158 - <value value="75" name="A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF"/> 2159 2159 - <value value="76" name="A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF"/> 2160 2160 - <value value="77" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF"/> 2161 2161 - <value value="78" name="A7XX_PERF_GBIF_AXI_ALL_READ_BEATS"/> 2162 2162 - <value value="79" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_BEATS"/> 2163 2163 - <value value="80" name="A7XX_PERF_GBIF_AXI_ALL_BEATS"/> 2164 2164 - </enum> 2165 2165 - 2166 2166 - <enum name="a7xx_ufc_perfcounter_select"> 2167 2167 - <value value="0" name="A7XX_PERF_UFC_BUSY_CYCLES"/> 2168 2168 - <value value="1" name="A7XX_PERF_UFC_READ_DATA_VBIF"/> 2169 2169 - <value value="2" name="A7XX_PERF_UFC_WRITE_DATA_VBIF"/> 2170 2170 - <value value="3" name="A7XX_PERF_UFC_READ_REQUEST_VBIF"/> 2171 2171 - <value value="4" name="A7XX_PERF_UFC_WRITE_REQUEST_VBIF"/> 2172 2172 - <value value="5" name="A7XX_PERF_UFC_LRZ_FILTER_HIT"/> 2173 2173 - <value value="6" name="A7XX_PERF_UFC_LRZ_FILTER_MISS"/> 2174 2174 - <value value="7" name="A7XX_PERF_UFC_CRE_FILTER_HIT"/> 2175 2175 - <value value="8" name="A7XX_PERF_UFC_CRE_FILTER_MISS"/> 2176 2176 - <value value="9" name="A7XX_PERF_UFC_SP_FILTER_HIT"/> 2177 2177 - <value value="10" name="A7XX_PERF_UFC_SP_FILTER_MISS"/> 2178 2178 - <value value="11" name="A7XX_PERF_UFC_SP_REQUESTS"/> 2179 2179 - <value value="12" name="A7XX_PERF_UFC_TP_FILTER_HIT"/> 2180 2180 - <value value="13" name="A7XX_PERF_UFC_TP_FILTER_MISS"/> 2181 2181 - <value value="14" name="A7XX_PERF_UFC_TP_REQUESTS"/> 2182 2182 - <value value="15" name="A7XX_PERF_UFC_MAIN_HIT_LRZ_PREFETCH"/> 2183 2183 - <value value="16" name="A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH"/> 2184 2184 - <value value="17" name="A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH"/> 2185 2185 - <value value="18" name="A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH"/> 2186 2186 - <value value="19" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_READ"/> 2187 2187 - <value value="20" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE"/> 2188 2188 - <value value="21" name="A7XX_PERF_UFC_MAIN_MISS_LRZ_PREFETCH"/> 2189 2189 - <value value="22" name="A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH"/> 2190 2190 - <value value="23" name="A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH"/> 2191 2191 - <value value="24" name="A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH"/> 2192 2192 - <value value="25" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_READ"/> 2193 2193 - <value value="26" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE"/> 2194 2194 - <value value="27" name="A7XX_PERF_UFC_UBWC_READ_UFC_TRANS"/> 2195 2195 - <value value="28" name="A7XX_PERF_UFC_UBWC_WRITE_UFC_TRANS"/> 2196 2196 - <value value="29" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD"/> 2197 2197 - <value value="30" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA"/> 2198 2198 - <value value="31" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA"/> 2199 2199 - <value value="32" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG"/> 2200 2200 - <value value="33" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN"/> 2201 2201 - <value value="34" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT"/> 2202 2202 - <value value="35" name="A7XX_PERF_UFC_LRZ_PREFETCH_STALLED_CYCLES"/> 2203 2203 - <value value="36" name="A7XX_PERF_UFC_CRE_PREFETCH_STALLED_CYCLES"/> 2204 2204 - <value value="37" name="A7XX_PERF_UFC_SPTP_PREFETCH_STALLED_CYCLES"/> 2205 2205 - <value value="38" name="A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES"/> 2206 2206 - <value value="39" name="A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES"/> 2207 2207 - <value value="40" name="A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES"/> 2208 2208 - <value value="41" name="A7XX_PERF_UFC_EVICTION_STALLED_CYCLES"/> 2209 2209 - <value value="42" name="A7XX_PERF_UFC_LOCK_STALLED_CYCLES"/> 2210 2210 - <value value="43" name="A7XX_PERF_UFC_MISS_LATENCY_CYCLES"/> 2211 2211 - <value value="44" name="A7XX_PERF_UFC_MISS_LATENCY_SAMPLES"/> 2212 2212 - <value value="45" name="A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES"/> 2213 2213 - <value value="46" name="A7XX_PERF_UFC_TP_HINT_TAG_MISS"/> 2214 2214 - <value value="47" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_RDY"/> 2215 2215 - <value value="48" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_NRDY"/> 2216 2216 - <value value="49" name="A7XX_PERF_UFC_TP_HINT_IS_FCLEAR"/> 2217 2217 - <value value="50" name="A7XX_PERF_UFC_TP_HINT_IS_ALPHA0"/> 2218 2218 - <value value="51" name="A7XX_PERF_UFC_SP_L1_FILTER_HIT"/> 2219 2219 - <value value="52" name="A7XX_PERF_UFC_SP_L1_FILTER_MISS"/> 2220 2220 - <value value="53" name="A7XX_PERF_UFC_SP_L1_FILTER_REQUESTS"/> 2221 2221 - <value value="54" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_RDY"/> 2222 2222 - <value value="55" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_NRDY"/> 2223 2223 - <value value="56" name="A7XX_PERF_UFC_TP_L1_TAG_MISS"/> 2224 2224 - <value value="57" name="A7XX_PERF_UFC_TP_L1_FILTER_REQUESTS"/> 2225 2225 - </enum> 2226 22 2227 23 <domain name="A6XX" width="32" prefix="variant" varset="chip"> 2228 24 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip"> ··· 177 2371 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/> 178 2372 <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/> 179 2373 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/> 180 180 - <reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/> 2374 2374 + <reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE"/> 181 2375 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/> 182 2376 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/> 183 2377 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/> ··· 206 2400 --> 207 2401 <reg64 offset="0x0934" name="CP_VSD_BASE"/> 208 2402 209 209 - <bitset name="a6xx_roq_stat" inline="yes"> 2403 2403 + <bitset name="a6xx_roq_status" inline="yes"> 210 2404 <bitfield name="RPTR" low="0" high="9"/> 211 2405 <bitfield name="WPTR" low="16" high="25"/> 212 2406 </bitset> 213 213 - <reg32 offset="0x0939" name="CP_ROQ_RB_STAT" type="a6xx_roq_stat"/> 214 214 - <reg32 offset="0x093a" name="CP_ROQ_IB1_STAT" type="a6xx_roq_stat"/> 215 215 - <reg32 offset="0x093b" name="CP_ROQ_IB2_STAT" type="a6xx_roq_stat"/> 216 216 - <reg32 offset="0x093c" name="CP_ROQ_SDS_STAT" type="a6xx_roq_stat"/> 217 217 - <reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/> 218 218 - <reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/> 2407 2407 + <reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status"/> 2408 2408 + <reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status"/> 2409 2409 + <reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status"/> 2410 2410 + <reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status"/> 2411 2411 + <reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status"/> 2412 2412 + <reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status"/> 219 2413 220 220 - <reg32 offset="0x0943" name="CP_IB1_DWORDS"/> 221 221 - <reg32 offset="0x0944" name="CP_IB2_DWORDS"/> 222 222 - <reg32 offset="0x0945" name="CP_SDS_DWORDS"/> 223 223 - <reg32 offset="0x0946" name="CP_MRB_DWORDS"/> 224 224 - <reg32 offset="0x0947" name="CP_VSD_DWORDS"/> 2414 2414 + <reg32 offset="0x0943" name="CP_IB1_INIT_SIZE"/> 2415 2415 + <reg32 offset="0x0944" name="CP_IB2_INIT_SIZE"/> 2416 2416 + <reg32 offset="0x0945" name="CP_SDS_INIT_SIZE"/> 2417 2417 + <reg32 offset="0x0946" name="CP_MRB_INIT_SIZE"/> 2418 2418 + <reg32 offset="0x0947" name="CP_VSD_INIT_SIZE"/> 225 2419 226 2420 <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB"> 227 2421 <doc>number of remaining dwords incl current dword being consumed?</doc> ··· 257 2451 <reg32 offset="0x098D" name="CP_AHB_CNTL"/> 258 2452 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/> 259 2453 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/> 2454 2454 + <reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/> 260 2455 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/> 261 2456 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/> 262 2457 ··· 275 2468 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/> 276 2469 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/> 277 2470 278 278 - <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/> 279 279 - <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/> 2471 2471 + <reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX-"/> 2472 2472 + <reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX-"/> 280 2473 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/> 281 2474 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/> 282 2475 ··· 426 2619 vertices in, number of primnitives assembled etc. 427 2620 --> 428 2621 429 429 - <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in --> 430 430 - <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/> 431 431 - <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out --> 432 432 - <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/> 433 433 - <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in --> 434 434 - <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/> 435 435 - <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out --> 436 436 - <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/> 437 437 - <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in --> 438 438 - <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/> 439 439 - <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out --> 440 440 - <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/> 441 441 - <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in --> 442 442 - <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/> 443 443 - <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out --> 444 444 - <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/> 445 445 - <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out --> 446 446 - <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/> 447 447 - <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in --> 448 448 - <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/> 449 449 - <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/> 450 450 - <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/> 2622 2622 + <reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES"/> 2623 2623 + <reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES"/> 2624 2624 + <reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS"/> 2625 2625 + <reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS"/> 2626 2626 + <reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS"/> 2627 2627 + <reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS"/> 2628 2628 + <reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES"/> 2629 2629 + <reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS"/> 2630 2630 + <reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES"/> 2631 2631 + <reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS"/> 2632 2632 + <reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS"/> 451 2633 452 2634 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> 453 2635 <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> ··· 575 2779 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/> 576 2780 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/> 577 2781 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/> 578 578 - <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/> 2782 2782 + <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE" variants="A6XX"/> 579 2783 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-"> 580 2784 <bitfield name="TXDONE" pos="0" type="boolean"/> 581 2785 </reg32> ··· 636 2840 </reg32> 637 2841 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> 638 2842 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> 639 639 - <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/> 2843 2843 + <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2" variants="A6XX"/> 640 2844 <reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX"> 641 2845 <doc> 642 2846 Set to true when binning, isn't changed afterwards ··· 732 2936 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> 733 2937 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/> 734 2938 </reg32> 735 735 - <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress" usage="cmd"/> 736 736 - <reg32 offset="0x0c06" name="VSC_BIN_COUNT" usage="rp_blit"> 2939 2939 + <reg64 offset="0x0c03" name="VSC_SIZE_BASE" type="waddress" usage="cmd"/> 2940 2940 + <reg32 offset="0x0c06" name="VSC_EXPANDED_BIN_CNTL" usage="rp_blit"> 737 2941 <bitfield name="NX" low="1" high="10" type="uint"/> 738 2942 <bitfield name="NY" low="11" high="20" type="uint"/> 739 2943 </reg32> ··· 763 2967 764 2968 LIMIT is set to PITCH - 64, to make room for a bit of overflow 765 2969 --> 766 766 - <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress" usage="cmd"/> 767 767 - <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH" usage="cmd"/> 768 768 - <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT" usage="cmd"/> 769 769 - <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress" usage="cmd"/> 770 770 - <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH" usage="cmd"/> 771 771 - <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT" usage="cmd"/> 2970 2970 + <reg64 offset="0x0c30" name="VSC_PIPE_DATA_PRIM_BASE" type="waddress" usage="cmd"/> 2971 2971 + <reg32 offset="0x0c32" name="VSC_PIPE_DATA_PRIM_STRIDE" usage="cmd"/> 2972 2972 + <reg32 offset="0x0c33" name="VSC_PIPE_DATA_PRIM_LENGTH" usage="cmd"/> 2973 2973 + <reg64 offset="0x0c34" name="VSC_PIPE_DATA_DRAW_BASE" type="waddress" usage="cmd"/> 2974 2974 + <reg32 offset="0x0c36" name="VSC_PIPE_DATA_DRAW_STRIDE" usage="cmd"/> 2975 2975 + <reg32 offset="0x0c37" name="VSC_PIPE_DATA_DRAW_LENGTH" usage="cmd"/> 772 2976 773 773 - <array offset="0x0c38" name="VSC_STATE" stride="1" length="32" usage="rp_blit"> 2977 2977 + <array offset="0x0c38" name="VSC_CHANNEL_VISIBILITY" stride="1" length="32" usage="rp_blit"> 774 2978 <doc> 775 2979 Seems to be a bitmap of which tiles mapped to the VSC 776 2980 pipe contain geometry. ··· 781 2985 <reg32 offset="0x0" name="REG"/> 782 2986 </array> 783 2987 784 784 - <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 2988 2988 + <array offset="0x0c58" name="VSC_PIPE_DATA_PRIM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 785 2989 <doc> 786 2990 Has the size of data written to corresponding VSC_PRIM_STRM 787 2991 buffer. ··· 789 2993 <reg32 offset="0x0" name="REG"/> 790 2994 </array> 791 2995 792 792 - <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 2996 2996 + <array offset="0x0c78" name="VSC_PIPE_DATA_DRAW_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 793 2997 <doc> 794 2998 Has the size of data written to corresponding VSC pipe, ie. 795 795 - same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI 2999 2999 + same thing that is written out to VSC_SIZE_BASE 796 3000 </doc> 797 3001 <reg32 offset="0x0" name="REG"/> 798 3002 </array> ··· 824 3028 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> 825 3029 </reg32> 826 3030 827 827 - <bitset name="a6xx_gras_xs_cl_cntl" inline="yes"> 3031 3031 + <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes"> 828 3032 <bitfield name="CLIP_MASK" low="0" high="7"/> 829 3033 <bitfield name="CULL_MASK" low="8" high="15"/> 830 3034 </bitset> 831 831 - <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> 832 832 - <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> 833 833 - <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> 834 834 - <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/> 3035 3035 + <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 3036 3036 + <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 3037 3037 + <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 3038 3038 + <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit"/> 835 3039 836 836 - <reg32 offset="0x8005" name="GRAS_CNTL" usage="rp_blit"> 837 837 - <!-- see also RB_RENDER_CONTROL0 --> 3040 3040 + <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" usage="rp_blit"> 3041 3041 + <!-- see also RB_INTERP_CNTL --> 838 3042 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 839 3043 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 840 3044 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> ··· 863 3067 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> --> 864 3068 865 3069 <!-- 0x8006-0x800f invalid --> 866 866 - <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16" usage="rp_blit"> 3070 3070 + <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" usage="rp_blit"> 867 3071 <reg32 offset="0" name="XOFFSET" type="float"/> 868 3072 <reg32 offset="1" name="XSCALE" type="float"/> 869 3073 <reg32 offset="2" name="YOFFSET" type="float"/> ··· 871 3075 <reg32 offset="4" name="ZOFFSET" type="float"/> 872 3076 <reg32 offset="5" name="ZSCALE" type="float"/> 873 3077 </array> 874 874 - <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16" usage="rp_blit"> 3078 3078 + <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" usage="rp_blit"> 875 3079 <reg32 offset="0" name="MIN" type="float"/> 876 3080 <reg32 offset="1" name="MAX" type="float"/> 877 3081 </array> ··· 920 3124 921 3125 <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd"> 922 3126 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 923 923 - <bitfield name="SHIFTAMOUNT" low="1" high="2"/> 3127 3127 + <enum name="a6xx_shift_amount"> 3128 3128 + <value value="0" name="NO_SHIFT"/> 3129 3129 + <value value="1" name="HALF_PIXEL_SHIFT"/> 3130 3130 + <value value="2" name="FULL_PIXEL_SHIFT"/> 3131 3131 + </enum> 3132 3132 + <bitfield name="SHIFTAMOUNT" low="1" high="2" type="a6xx_shift_amount"/> 924 3133 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> 925 3134 <bitfield name="UNK4" low="4" high="5"/> 926 3135 </reg32> ··· 934 3133 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> 935 3134 </reg32> 936 3135 937 937 - <bitset name="a6xx_gras_layer_cntl" inline="yes"> 3136 3136 + <bitset name="a6xx_gras_us_xs_siv_cntl" inline="yes"> 938 3137 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> 939 3138 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> 940 3139 </bitset> 941 941 - <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> 942 942 - <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> 943 943 - <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> 3140 3140 + <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 3141 3141 + <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 3142 3142 + <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 944 3143 <!-- 0x809e/0x809f invalid --> 945 3144 946 3145 <enum name="a6xx_sequenced_thread_dist"> ··· 1014 3213 <enum name="a6xx_lrz_feedback_mask"> 1015 3214 <value value="0x0" name="LRZ_FEEDBACK_NONE"/> 1016 3215 <value value="0x1" name="LRZ_FEEDBACK_EARLY_Z"/> 1017 1017 - <value value="0x2" name="LRZ_FEEDBACK_EARLY_LRZ_LATE_Z"/> 3216 3216 + <value value="0x2" name="LRZ_FEEDBACK_EARLY_Z_LATE_Z"/> 1018 3217 <!-- We don't have a flag type and this flags combination is often used --> 1019 1019 - <value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z"/> 3218 3218 + <value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z"/> 1020 3219 <value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/> 1021 3220 </enum> 1022 3221 1023 1023 - <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL" usage="rp_blit"> 3222 3222 + <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" usage="rp_blit"> 1024 3223 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1025 3224 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1026 3225 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> ··· 1036 3235 <bitfield name="UNK27" pos="27"/> 1037 3236 </reg32> 1038 3237 1039 1039 - <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL" usage="rp_blit"> 3238 3238 + <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" usage="rp_blit"> 1040 3239 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1041 3240 <bitfield name="UNK2" pos="2"/> 1042 3241 <bitfield name="UNK3" pos="3"/> 1043 3242 </reg32> 1044 1044 - <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL" usage="rp_blit"> 3243 3243 + <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" usage="rp_blit"> 1045 3244 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1046 3245 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1047 3246 </reg32> 1048 3247 1049 1049 - <bitset name="a6xx_sample_config" inline="yes"> 3248 3248 + <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes"> 1050 3249 <bitfield name="UNK0" pos="0"/> 1051 3250 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/> 1052 3251 </bitset> 1053 3252 1054 1054 - <bitset name="a6xx_sample_locations" inline="yes"> 3253 3253 + <bitset name="a6xx_programmable_msaa_pos" inline="yes"> 1055 3254 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/> 1056 3255 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/> 1057 3256 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/> ··· 1062 3261 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> 1063 3262 </bitset> 1064 3263 1065 1065 - <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> 1066 1066 - <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> 1067 1067 - <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> 3264 3264 + <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 3265 3265 + <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3266 3266 + <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1068 3267 1069 3268 <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/> 1070 3269 ··· 1087 3286 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1088 3287 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1089 3288 1090 1090 - <!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate --> 1091 1091 - <reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/> 1092 1092 - <reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/> 1093 1093 - <reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/> 1094 1094 - <reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/> 1095 1095 - <reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/> 1096 1096 - <reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/> 3289 3289 + <enum name="a6xx_fsr_combiner"> 3290 3290 + <value value="0" name="FSR_COMBINER_OP_KEEP"/> 3291 3291 + <value value="1" name="FSR_COMBINER_OP_REPLACE"/> 3292 3292 + <value value="2" name="FSR_COMBINER_OP_MIN"/> 3293 3293 + <value value="3" name="FSR_COMBINER_OP_MAX"/> 3294 3294 + <value value="4" name="FSR_COMBINER_OP_MUL"/> 3295 3295 + </enum> 3296 3296 + 3297 3297 + <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> 3298 3298 + <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 3299 3299 + <bitfield name="FRAG_SIZE_X" low="1" high="2" type="uint"/> 3300 3300 + <bitfield name="FRAG_SIZE_Y" low="3" high="4" type="uint"/> 3301 3301 + <bitfield name="COMBINER_OP_1" low="5" high="7" type="a6xx_fsr_combiner"/> 3302 3302 + <bitfield name="COMBINER_OP_2" low="8" high="10" type="a6xx_fsr_combiner"/> 3303 3303 + <bitfield name="ATTACHMENT_FSR_ENABLE" pos="13" type="boolean"/> 3304 3304 + <bitfield name="PRIMITIVE_FSR_ENABLE" pos="20" type="boolean"/> 3305 3305 + </reg32> 3306 3306 + <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 3307 3307 + <bitfield name="LAYERED" pos="0" type="boolean"/> 3308 3308 + <bitfield name="TILE_MODE" low="1" high="2" type="a6xx_tile_mode"/> 3309 3309 + </reg32> 3310 3310 + <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" variants="A7XX-" usage="rp_blit"> 3311 3311 + <bitfield name="WIDTH" low="0" high="15" type="uint"/> 3312 3312 + <bitfield name="HEIGHT" low="16" high="31" type="uint"/> 3313 3313 + </reg32> 3314 3314 + <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX-" type="waddress" usage="rp_blit"/> 3315 3315 + <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" variants="A7XX-" usage="rp_blit"> 3316 3316 + <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/> 3317 3317 + <bitfield name="ARRAY_PITCH" shr="6" low="10" high="28" type="uint"/> 3318 3318 + </reg32> 1097 3319 1098 3320 <enum name="a6xx_lrz_dir_status"> 1099 3321 <value value="0x1" name="LRZ_DIR_LE"/> ··· 1137 3313 </doc> 1138 3314 <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/> 1139 3315 <!-- set when depth-test + depth-write enabled --> 1140 1140 - <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/> 3316 3316 + <bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/> 1141 3317 <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/> 1142 3318 <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/> 1143 3319 <doc> ··· 1163 3339 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> 1164 3340 </reg32> 1165 3341 1166 1166 - <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0" usage="rp_blit"> 3342 3342 + <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" usage="rp_blit"> 1167 3343 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1168 3344 </reg32> 1169 3345 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/> 1170 3346 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit"> 1171 1171 - <!-- TODO: fix the shr fields --> 1172 3347 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> 1173 1173 - <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/> 3348 3348 + <bitfield name="ARRAY_PITCH" low="10" high="28" shr="8" type="uint"/> 1174 3349 </reg32> 1175 3350 1176 3351 <!-- ··· 1204 3381 --> 1205 3382 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/> 1206 3383 <!-- 0x8108 invalid --> 1207 1207 - <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL" usage="rp_blit"> 3384 3384 + <reg32 offset="0x8109" name="GRAS_LRZ_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 1208 3385 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 1209 3386 </reg32> 1210 3387 <!-- 1211 3388 LRZ buffer represents a single array layer + mip level, and there is 1212 3389 a single buffer per depth image. Thus to reuse LRZ between renderpasses 1213 3390 it is necessary to track the depth view used in the past renderpass, which 1214 1214 - GRAS_LRZ_DEPTH_VIEW is for. 1215 1215 - GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_DEPTH_VIEW is equal to 3391 3391 + GRAS_LRZ_VIEW_INFO is for. 3392 3392 + GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_VIEW_INFO is equal to 1216 3393 the value stored in the LRZ buffer, if not - LRZ is disabled. 1217 3394 --> 1218 1218 - <reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW" usage="cmd"> 3395 3395 + <reg32 offset="0x810a" name="GRAS_LRZ_VIEW_INFO" usage="cmd"> 1219 3396 <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/> 1220 3397 <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/> 1221 3398 <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/> ··· 1231 3408 <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/> 1232 3409 1233 3410 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> 1234 1234 - <reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/> 3411 3411 + <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX-"/> 1235 3412 1236 3413 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1237 3414 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> ··· 1253 3430 <value value="0x5" name="ROTATE_VFLIP"/> 1254 3431 </enum> 1255 3432 1256 1256 - <bitset name="a6xx_2d_blit_cntl" inline="yes"> 3433 3433 + <bitset name="a6xx_a2d_bit_cntl" inline="yes"> 1257 3434 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> 1258 3435 <bitfield name="OVERWRITEEN" pos="3" type="boolean"/> 1259 3436 <bitfield name="UNK4" low="4" high="6"/> ··· 1270 3447 <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/> 1271 3448 </bitset> 1272 3449 1273 1273 - <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/> 3450 3450 + <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> 1274 3451 <!-- note: the low 8 bits for src coords are valid, probably fixed point 1275 3452 it would be a bit weird though, since we subtract 1 from BR coords 1276 3453 apparently signed, gallium driver uses negative coords and it works? 1277 3454 --> 1278 1278 - <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/> 1279 1279 - <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/> 1280 1280 - <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/> 1281 1281 - <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/> 1282 1282 - <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1283 1283 - <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy" usage="rp_blit"/> 3455 3455 + <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" usage="rp_blit"/> 3456 3456 + <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" usage="rp_blit"/> 3457 3457 + <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" usage="rp_blit"/> 3458 3458 + <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" usage="rp_blit"/> 3459 3459 + <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" usage="rp_blit"/> 3460 3460 + <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1284 3461 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/> 1285 3462 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/> 1286 3463 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/> 1287 1287 - <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> 1288 1288 - <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> 3464 3464 + <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 3465 3465 + <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1289 3466 <!-- 0x840c-0x85ff invalid --> 1290 3467 1291 3468 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> ··· 1304 3481 --> 1305 3482 1306 3483 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 1307 1307 - <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A6XX" usage="rp_blit"> 3484 3484 + <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX" usage="rp_blit"> 1308 3485 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1309 3486 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1310 3487 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> ··· 1313 3490 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1314 3491 </reg32> 1315 3492 1316 1316 - <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit"> 3493 3493 + <reg32 offset="0x8800" name="RB_CNTL" variants="A7XX-" usage="rp_blit"> 1317 3494 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1318 3495 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1319 3496 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> ··· 1324 3501 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit"> 1325 3502 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> 1326 3503 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 1327 1327 - <!-- set during binning pass: --> 1328 1328 - <bitfield name="BINNING" pos="7" type="boolean"/> 3504 3504 + <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1329 3505 <bitfield name="UNK8" low="8" high="10"/> 1330 3506 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 1331 3507 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> ··· 1337 3515 </reg32> 1338 3516 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 1339 3517 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 1340 1340 - <!-- set during binning pass: --> 1341 1341 - <bitfield name="BINNING" pos="7" type="boolean"/> 3518 3518 + <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1342 3519 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 1343 3520 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 1344 3521 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 1345 3522 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 1346 3523 </reg32> 1347 3524 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 1348 1348 - <bitfield name="BINNING" pos="7" type="boolean"/> 3525 3525 + <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1349 3526 </reg32> 1350 3527 1351 3528 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit"> ··· 1357 3536 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1358 3537 </reg32> 1359 3538 1360 1360 - <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> 1361 1361 - <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> 1362 1362 - <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> 3539 3539 + <reg32 offset="0x8804" name="RB_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 3540 3540 + <reg32 offset="0x8805" name="RB_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3541 3541 + <reg32 offset="0x8806" name="RB_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1363 3542 <!-- 0x8807-0x8808 invalid --> 1364 3543 <!-- 1365 3544 note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL 1366 3545 name comes from kernel and is probably right) 1367 3546 --> 1368 1368 - <reg32 offset="0x8809" name="RB_RENDER_CONTROL0" usage="rp_blit"> 1369 1369 - <!-- see also GRAS_CNTL --> 3547 3547 + <reg32 offset="0x8809" name="RB_INTERP_CNTL" usage="rp_blit"> 3548 3548 + <!-- see also GRAS_CL_INTERP_CNTL --> 1370 3549 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 1371 3550 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 1372 3551 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> ··· 1376 3555 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 1377 3556 <bitfield name="UNK10" pos="10" type="boolean"/> 1378 3557 </reg32> 1379 1379 - <reg32 offset="0x880a" name="RB_RENDER_CONTROL1" usage="rp_blit"> 3558 3558 + <reg32 offset="0x880a" name="RB_PS_INPUT_CNTL" usage="rp_blit"> 1380 3559 <!-- enable bits for various FS sysvalue regs: --> 1381 3560 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> 1382 3561 <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/> ··· 1388 3567 <bitfield name="FOVEATION" pos="8" type="boolean"/> 1389 3568 </reg32> 1390 3569 1391 1391 - <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0" usage="rp_blit"> 3570 3570 + <reg32 offset="0x880b" name="RB_PS_OUTPUT_CNTL" usage="rp_blit"> 1392 3571 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 1393 3572 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> 1394 3573 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> 1395 3574 <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/> 1396 3575 </reg32> 1397 1397 - <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1" usage="rp_blit"> 3576 3576 + <reg32 offset="0x880c" name="RB_PS_MRT_CNTL" usage="rp_blit"> 1398 3577 <bitfield name="MRT" low="0" high="3" type="uint"/> 1399 3578 </reg32> 1400 1400 - <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS" usage="rp_blit"> 3579 3579 + <reg32 offset="0x880d" name="RB_PS_OUTPUT_MASK" usage="rp_blit"> 1401 3580 <bitfield name="RT0" low="0" high="3"/> 1402 3581 <bitfield name="RT1" low="4" high="7"/> 1403 3582 <bitfield name="RT2" low="8" high="11"/> ··· 1429 3608 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 1430 3609 </reg32> 1431 3610 1432 1432 - <reg32 offset="0x8810" name="RB_SAMPLE_CNTL" usage="rp_blit"> 3611 3611 + <reg32 offset="0x8810" name="RB_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 1433 3612 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 1434 3613 </reg32> 1435 3614 <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/> ··· 1493 3672 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/> 1494 3673 </array> 1495 3674 1496 1496 - <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float" usage="rp_blit"/> 1497 1497 - <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float" usage="rp_blit"/> 1498 1498 - <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float" usage="rp_blit"/> 1499 1499 - <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float" usage="rp_blit"/> 1500 1500 - <reg32 offset="0x8864" name="RB_ALPHA_CONTROL" usage="cmd"> 3675 3675 + <reg32 offset="0x8860" name="RB_BLEND_CONSTANT_RED_FP32" type="float" usage="rp_blit"/> 3676 3676 + <reg32 offset="0x8861" name="RB_BLEND_CONSTANT_GREEN_FP32" type="float" usage="rp_blit"/> 3677 3677 + <reg32 offset="0x8862" name="RB_BLEND_CONSTANT_BLUE_FP32" type="float" usage="rp_blit"/> 3678 3678 + <reg32 offset="0x8863" name="RB_BLEND_CONSTANT_ALPHA_FP32" type="float" usage="rp_blit"/> 3679 3679 + <reg32 offset="0x8864" name="RB_ALPHA_TEST_CNTL" usage="cmd"> 1501 3680 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> 1502 3681 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 1503 3682 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> 1504 3683 </reg32> 1505 3684 <reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit"> 1506 3685 <!-- per-mrt enable bit --> 1507 1507 - <bitfield name="ENABLE_BLEND" low="0" high="7"/> 3686 3686 + <bitfield name="BLEND_READS_DEST" low="0" high="7"/> 1508 3687 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> 1509 3688 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 1510 3689 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> ··· 1547 3726 <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/> 1548 3727 <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/> 1549 3728 <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1550 1550 - <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> 3729 3729 + <reg32 offset="0x8877" name="RB_DEPTH_GMEM_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 1551 3730 1552 1552 - <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float" usage="rp_blit"/> 1553 1553 - <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float" usage="rp_blit"/> 3731 3731 + <reg32 offset="0x8878" name="RB_DEPTH_BOUND_MIN" type="float" usage="rp_blit"/> 3732 3732 + <reg32 offset="0x8879" name="RB_DEPTH_BOUND_MAX" type="float" usage="rp_blit"/> 1554 3733 <!-- 0x887a-0x887f invalid --> 1555 1555 - <reg32 offset="0x8880" name="RB_STENCIL_CONTROL" usage="rp_blit"> 3734 3734 + <reg32 offset="0x8880" name="RB_STENCIL_CNTL" usage="rp_blit"> 1556 3735 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1557 3736 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> 1558 3737 <!-- ··· 1574 3753 <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit"> 1575 3754 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1576 3755 </reg32> 1577 1577 - <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A6XX" usage="rp_blit"> 3756 3756 + <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 1578 3757 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 1579 3758 <bitfield name="UNK1" pos="1" type="boolean"/> 1580 3759 </reg32> 1581 1581 - <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit"> 3760 3760 + <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1582 3761 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 1583 3762 <bitfield name="UNK1" pos="1" type="boolean"/> 1584 3763 <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/> ··· 1586 3765 <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/> 1587 3766 <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/> 1588 3767 <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1589 1589 - <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> 1590 1590 - <reg32 offset="0x8887" name="RB_STENCILREF" usage="rp_blit"> 3768 3768 + <reg32 offset="0x8886" name="RB_STENCIL_GMEM_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 3769 3769 + <reg32 offset="0x8887" name="RB_STENCIL_REF_CNTL" usage="rp_blit"> 1591 3770 <bitfield name="REF" low="0" high="7"/> 1592 3771 <bitfield name="BFREF" low="8" high="15"/> 1593 3772 </reg32> 1594 1594 - <reg32 offset="0x8888" name="RB_STENCILMASK" usage="rp_blit"> 3773 3773 + <reg32 offset="0x8888" name="RB_STENCIL_MASK" usage="rp_blit"> 1595 3774 <bitfield name="MASK" low="0" high="7"/> 1596 3775 <bitfield name="BFMASK" low="8" high="15"/> 1597 3776 </reg32> 1598 1598 - <reg32 offset="0x8889" name="RB_STENCILWRMASK" usage="rp_blit"> 3777 3777 + <reg32 offset="0x8889" name="RB_STENCIL_WRITE_MASK" usage="rp_blit"> 1599 3778 <bitfield name="WRMASK" low="0" high="7"/> 1600 3779 <bitfield name="BFWRMASK" low="8" high="15"/> 1601 3780 </reg32> 1602 3781 <!-- 0x888a-0x888f invalid --> 1603 3782 <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 1604 1604 - <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL" usage="cmd"> 3783 3783 + <reg32 offset="0x8891" name="RB_SAMPLE_COUNTER_CNTL" usage="cmd"> 1605 3784 <bitfield name="DISABLE" pos="0" type="boolean"/> 1606 3785 <bitfield name="COPY" pos="1" type="boolean"/> 1607 3786 </reg32> ··· 1612 3791 <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/> 1613 3792 <!-- 0x8899-0x88bf invalid --> 1614 3793 <!-- clamps depth value for depth test/write --> 1615 1615 - <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float" usage="rp_blit"/> 1616 1616 - <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float" usage="rp_blit"/> 3794 3794 + <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit"/> 3795 3795 + <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit"/> 1617 3796 <!-- 0x88c2-0x88cf invalid--> 1618 1618 - <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0" usage="rp_blit"> 3797 3797 + <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="rp_blit"> 1619 3798 <bitfield name="UNK0" low="0" high="12"/> 1620 3799 <bitfield name="UNK16" low="16" high="26"/> 1621 3800 </reg32> 1622 1622 - <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1623 1623 - <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 3801 3801 + <reg32 offset="0x88d1" name="RB_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> 3802 3802 + <reg32 offset="0x88d2" name="RB_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> 1624 3803 <!-- weird to duplicate other regs from same block?? --> 1625 1625 - <reg32 offset="0x88d3" name="RB_BIN_CONTROL2" usage="rp_blit"> 3804 3804 + <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" usage="rp_blit"> 1626 3805 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1627 3806 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1628 3807 </reg32> 1629 1629 - <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy" usage="rp_blit"/> 1630 1630 - <reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL" usage="rp_blit"> 3808 3808 + <reg32 offset="0x88d4" name="RB_RESOLVE_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 3809 3809 + <reg32 offset="0x88d5" name="RB_RESOLVE_GMEM_BUFFER_INFO" usage="rp_blit"> 1631 3810 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 1632 3811 </reg32> 1633 1633 - <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> 3812 3812 + <reg32 offset="0x88d6" name="RB_RESOLVE_GMEM_BUFFER_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 1634 3813 <!-- s/DST_FORMAT/DST_INFO/ probably: --> 1635 1635 - <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO" usage="rp_blit"> 3814 3814 + <reg32 offset="0x88d7" name="RB_RESOLVE_SYSTEM_BUFFER_INFO" usage="rp_blit"> 1636 3815 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 1637 3816 <bitfield name="FLAGS" pos="2" type="boolean"/> 1638 3817 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> ··· 1641 3820 <bitfield name="UNK15" pos="15" type="boolean"/> 1642 3821 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/> 1643 3822 </reg32> 1644 1644 - <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64" usage="rp_blit"/> 1645 1645 - <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 3823 3823 + <reg64 offset="0x88d8" name="RB_RESOLVE_SYSTEM_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 3824 3824 + <reg32 offset="0x88da" name="RB_RESOLVE_SYSTEM_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 1646 3825 <!-- array-pitch is size of layer --> 1647 1647 - <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> 1648 1648 - <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64" usage="rp_blit"/> 1649 1649 - <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH" usage="rp_blit"> 3826 3826 + <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> 3827 3827 + <reg64 offset="0x88dc" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 3828 3828 + <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" usage="rp_blit"> 1650 3829 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1651 3830 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 1652 3831 </reg32> 1653 3832 1654 1654 - <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0" usage="rp_blit"/> 1655 1655 - <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1" usage="rp_blit"/> 1656 1656 - <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/> 1657 1657 - <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/> 3833 3833 + <reg32 offset="0x88df" name="RB_RESOLVE_CLEAR_COLOR_DW0" usage="rp_blit"/> 3834 3834 + <reg32 offset="0x88e0" name="RB_RESOLVE_CLEAR_COLOR_DW1" usage="rp_blit"/> 3835 3835 + <reg32 offset="0x88e1" name="RB_RESOLVE_CLEAR_COLOR_DW2" usage="rp_blit"/> 3836 3836 + <reg32 offset="0x88e2" name="RB_RESOLVE_CLEAR_COLOR_DW3" usage="rp_blit"/> 3837 3837 + 3838 3838 + <enum name="a6xx_blit_event_type"> 3839 3839 + <value value="0x0" name="BLIT_EVENT_STORE"/> 3840 3840 + <value value="0x1" name="BLIT_EVENT_STORE_AND_CLEAR"/> 3841 3841 + <value value="0x2" name="BLIT_EVENT_CLEAR"/> 3842 3842 + <value value="0x3" name="BLIT_EVENT_LOAD"/> 3843 3843 + </enum> 1658 3844 1659 3845 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: --> 1660 1660 - <reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit"> 1661 1661 - <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? --> 1662 1662 - <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? --> 3846 3846 + <reg32 offset="0x88e3" name="RB_RESOLVE_OPERATION" usage="rp_blit"> 3847 3847 + <bitfield name="TYPE" low="0" high="1" type="a6xx_blit_event_type"/> 1663 3848 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging --> 1664 3849 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> 1665 3850 <doc> ··· 1680 3853 <!-- set when this is the last resolve on a650+ --> 1681 3854 <bitfield name="LAST" low="8" high="9"/> 1682 3855 <!-- 1683 1683 - a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil. 1684 1684 - a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise. 1685 1685 - 1686 1686 - We believe this is related to concurrent resolves 3856 3856 + a618 GLES: color render target number being resolved for CCU_RESOLVE, 0x8 for depth, 0x9 for separate stencil. 3857 3857 + a618 VK: 0x8 for depth CCU_RESOLVE, 0x9 for separate stencil, 0 otherwise. 3858 3858 + a7xx VK: 0x8 for depth, 0x9 for separate stencil, 0x0 to 0x7 used for concurrent resolves of color render 3859 3859 + targets inside a given resolve group. 1687 3860 --> 1688 3861 <bitfield name="BUFFER_ID" low="12" high="15"/> 1689 3862 </reg32> 1690 1690 - <reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit"> 1691 1691 - <!-- Value conditioned based on predicate, changed before blits --> 1692 1692 - <bitfield name="UNK0" pos="0" type="boolean"/> 3863 3863 + 3864 3864 + <enum name="a7xx_blit_clear_mode"> 3865 3865 + <value value="0x0" name="CLEAR_MODE_SYSMEM"/> 3866 3866 + <value value="0x1" name="CLEAR_MODE_GMEM"/> 3867 3867 + </enum> 3868 3868 + <reg32 offset="0x88e4" name="RB_CLEAR_TARGET" variants="A7XX-" usage="rp_blit"> 3869 3869 + <bitfield name="CLEAR_MODE" pos="0" type="a7xx_blit_clear_mode"/> 1693 3870 </reg32> 1694 3871 1695 3872 <enum name="a6xx_ccu_cache_size"> ··· 1702 3871 <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/> 1703 3872 <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/> 1704 3873 </enum> 1705 1705 - <reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd"> 3874 3874 + <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX-" usage="cmd"> 1706 3875 <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/> 1707 3876 <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/> 1708 3877 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> ··· 1726 3895 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1727 3896 <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/> 1728 3897 </reg32> 1729 1729 - <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/> 3898 3898 + 3899 3899 + <reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="rp_blit"> 3900 3900 + <bitfield name="UNK2" pos="2" type="boolean"/> 3901 3901 + <bitfield name="PIPELINE_FSR_ENABLE" pos="4" type="boolean"/> 3902 3902 + <bitfield name="ATTACHMENT_FSR_ENABLE" pos="5" type="boolean"/> 3903 3903 + <bitfield name="PRIMITIVE_FSR_ENABLE" pos="18" type="boolean"/> 3904 3904 + </reg32> 1730 3905 <!-- Connected to VK_EXT_fragment_density_map? --> 1731 3906 <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/> 1732 3907 <!-- 0x88f6-0x88ff invalid --> ··· 1743 3906 <bitfield name="UNK8" low="8" high="10"/> 1744 3907 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 1745 3908 </reg32> 1746 1746 - <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> 3909 3909 + <array offset="0x8903" name="RB_COLOR_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> 1747 3910 <reg64 offset="0" name="ADDR" type="waddress" align="64"/> 1748 3911 <reg32 offset="2" name="PITCH"> 1749 3912 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> ··· 1752 3915 </array> 1753 3916 <!-- 0x891b-0x8926 invalid --> 1754 3917 <doc> 1755 1755 - RB_SAMPLE_COUNT_ADDR register is used up to (and including) a730. After that 3918 3918 + RB_SAMPLE_COUNTER_BASE register is used up to (and including) a730. After that 1756 3919 the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. 1757 3920 </doc> 1758 1758 - <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16" usage="cmd"/> 3921 3921 + <reg64 offset="0x8927" name="RB_SAMPLE_COUNTER_BASE" type="waddress" align="16" usage="cmd"/> 1759 3922 <!-- 0x8929-0x89ff invalid --> 1760 3923 1761 3924 <!-- TODO: there are some registers in the 0x8a00-0x8bff range --> ··· 1769 3932 <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/> 1770 3933 <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/> 1771 3934 1772 1772 - <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/> 1773 1773 - <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/> 3935 3935 + <reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> 3936 3936 + <reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="rp_blit"/> 1774 3937 1775 1775 - <bitset name="a6xx_2d_src_surf_info" inline="yes"> 3938 3938 + <bitset name="a6xx_a2d_src_texture_info" inline="yes"> 1776 3939 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1777 3940 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 1778 3941 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> ··· 1791 3954 <bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/> 1792 3955 </bitset> 1793 3956 1794 1794 - <bitset name="a6xx_2d_dst_surf_info" inline="yes"> 3957 3957 + <bitset name="a6xx_a2d_dest_buffer_info" inline="yes"> 1795 3958 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1796 3959 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 1797 3960 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> ··· 1802 3965 </bitset> 1803 3966 1804 3967 <!-- 0x8c02-0x8c16 invalid --> 1805 1805 - <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_dst_surf_info" usage="rp_blit"/> 1806 1806 - <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64" usage="rp_blit"/> 1807 1807 - <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 3968 3968 + <reg32 offset="0x8c17" name="RB_A2D_DEST_BUFFER_INFO" type="a6xx_a2d_dest_buffer_info" usage="rp_blit"/> 3969 3969 + <reg64 offset="0x8c18" name="RB_A2D_DEST_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 3970 3970 + <reg32 offset="0x8c1a" name="RB_A2D_DEST_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 1808 3971 <!-- this is a guess but seems likely (for NV12/IYUV): --> 1809 1809 - <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64" usage="rp_blit"/> 1810 1810 - <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 1811 1811 - <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64" usage="rp_blit"/> 3972 3972 + <reg64 offset="0x8c1b" name="RB_A2D_DEST_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> 3973 3973 + <reg32 offset="0x8c1d" name="RB_A2D_DEST_BUFFER_PITCH_1" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 3974 3974 + <reg64 offset="0x8c1e" name="RB_A2D_DEST_BUFFER_BASE_2" type="waddress" align="64" usage="rp_blit"/> 1812 3975 1813 1813 - <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64" usage="rp_blit"/> 1814 1814 - <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 3976 3976 + <reg64 offset="0x8c20" name="RB_A2D_DEST_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 3977 3977 + <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 1815 3978 <!-- this is a guess but seems likely (for NV12 with UBWC): --> 1816 1816 - <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64" usage="rp_blit"/> 1817 1817 - <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 3979 3979 + <reg64 offset="0x8c23" name="RB_A2D_DEST_FLAG_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> 3980 3980 + <reg32 offset="0x8c25" name="RB_A2D_DEST_FLAG_BUFFER_PITCH_1" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 1818 3981 1819 3982 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers --> 1820 3983 <!-- unlike a5xx, these are per channel values rather than packed --> 1821 1821 - <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0" usage="rp_blit"/> 1822 1822 - <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/> 1823 1823 - <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/> 1824 1824 - <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/> 3984 3984 + <reg32 offset="0x8c2c" name="RB_A2D_CLEAR_COLOR_DW0" usage="rp_blit"/> 3985 3985 + <reg32 offset="0x8c2d" name="RB_A2D_CLEAR_COLOR_DW1" usage="rp_blit"/> 3986 3986 + <reg32 offset="0x8c2e" name="RB_A2D_CLEAR_COLOR_DW2" usage="rp_blit"/> 3987 3987 + <reg32 offset="0x8c2f" name="RB_A2D_CLEAR_COLOR_DW3" usage="rp_blit"/> 1825 3988 1826 3989 <reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/> 1827 3990 ··· 1833 3996 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff --> 1834 3997 <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 1835 3998 <!-- 0x02080000 in GMEM, zero otherwise? --> 1836 1836 - <reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/> 3999 3999 + <reg32 offset="0x8e06" name="RB_CCU_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 1837 4000 1838 4001 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX"> 1839 4002 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> ··· 1854 4017 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 1855 4018 <!--TODO: valid mask 0xfffffc1f --> 1856 4019 </reg32> 4020 4020 + <enum name="a7xx_concurrent_resolve_mode"> 4021 4021 + <value value="0x0" name="CONCURRENT_RESOLVE_MODE_DISABLED"/> 4022 4022 + <value value="0x1" name="CONCURRENT_RESOLVE_MODE_1"/> 4023 4023 + <value value="0x2" name="CONCURRENT_RESOLVE_MODE_2"/> 4024 4024 + </enum> 4025 4025 + <enum name="a7xx_concurrent_unresolve_mode"> 4026 4026 + <value value="0x0" name="CONCURRENT_UNRESOLVE_MODE_DISABLED"/> 4027 4027 + <value value="0x1" name="CONCURRENT_UNRESOLVE_MODE_PARTIAL"/> 4028 4028 + <value value="0x3" name="CONCURRENT_UNRESOLVE_MODE_FULL"/> 4029 4029 + </enum> 1857 4030 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-"> 1858 4031 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 1859 1859 - <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/> 1860 1860 - <!-- rest of the bits were moved to RB_CCU_CNTL2 --> 4032 4032 + <bitfield name="CONCURRENT_RESOLVE_MODE" low="2" high="3" type="a7xx_concurrent_resolve_mode"/> 4033 4033 + <bitfield name="CONCURRENT_UNRESOLVE_MODE" low="5" high="6" type="a7xx_concurrent_unresolve_mode"/> 4034 4034 + <!-- rest of the bits were moved to RB_CCU_CACHE_CNTL --> 1861 4035 </reg32> 1862 4036 <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"> 1863 4037 <bitfield name="MODE" pos="0" type="boolean"/> ··· 1894 4046 <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/> 1895 4047 <!-- 0x8e3e-0x8e4f invalid --> 1896 4048 <!-- GMEM save/restore for preemption: --> 1897 1897 - <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/> 4049 4049 + <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE" pos="0" type="boolean"/> 1898 4050 <!-- address for GMEM save/restore? --> 1899 1899 - <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/> 4051 4051 + <reg32 offset="0x8e51" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR" type="waddress" align="1"/> 1900 4052 <!-- 0x8e53-0x8e7f invalid --> 1901 4053 <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/> 1902 4054 <!-- 0x8e80-0x8e83 are valid --> ··· 1917 4069 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> 1918 4070 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> 1919 4071 </bitset> 1920 1920 - <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1921 1921 - <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1922 1922 - <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 4072 4072 + <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 4073 4073 + <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 4074 4074 + <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1923 4075 1924 1924 - <reg32 offset="0x9311" name="VPC_VS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1925 1925 - <reg32 offset="0x9312" name="VPC_GS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1926 1926 - <reg32 offset="0x9313" name="VPC_DS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 4076 4076 + <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 4077 4077 + <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 4078 4078 + <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1927 4079 1928 1928 - <bitset name="a6xx_vpc_xs_layer_cntl" inline="yes"> 4080 4080 + <bitset name="a6xx_vpc_xs_siv_cntl" inline="yes"> 1929 4081 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> 1930 4082 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/> 1931 4083 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/> 1932 4084 </bitset> 1933 4085 1934 1934 - <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 1935 1935 - <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 1936 1936 - <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 4086 4086 + <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 4087 4087 + <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 4088 4088 + <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1937 4089 1938 1938 - <reg32 offset="0x9314" name="VPC_VS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 1939 1939 - <reg32 offset="0x9315" name="VPC_GS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 1940 1940 - <reg32 offset="0x9316" name="VPC_DS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 4090 4090 + <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 4091 4091 + <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 4092 4092 + <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1941 4093 1942 4094 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit"> 1943 1943 - <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused --> 4095 4095 + <!-- this mirrors VPC_RAST_STREAM_CNTL::DISCARD, although it seems it's unused --> 1944 4096 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> 1945 4097 <bitfield name="UNK2" pos="2" type="boolean"/> 1946 4098 </reg32> 1947 1947 - <reg32 offset="0x9108" name="VPC_POLYGON_MODE" usage="rp_blit"> 4099 4099 + <reg32 offset="0x9108" name="VPC_RAST_CNTL" usage="rp_blit"> 1948 4100 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 1949 4101 </reg32> 1950 4102 1951 1951 - <bitset name="a6xx_primitive_cntl_0" inline="yes"> 4103 4103 + <bitset name="a6xx_pc_cntl" inline="yes"> 1952 4104 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 1953 4105 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> 1954 4106 <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean"> ··· 1961 4113 <bitfield name="UNK3" pos="3" type="boolean"/> 1962 4114 </bitset> 1963 4115 1964 1964 - <bitset name="a6xx_primitive_cntl_5" inline="yes"> 4116 4116 + <bitset name="a6xx_gs_param_0" inline="yes"> 1965 4117 <doc> 1966 4118 geometry shader 1967 4119 </doc> ··· 1973 4125 <bitfield name="UNK18" pos="18"/> 1974 4126 </bitset> 1975 4127 1976 1976 - <bitset name="a6xx_multiview_cntl" inline="yes"> 4128 4128 + <bitset name="a6xx_stereo_rendering_cntl" inline="yes"> 1977 4129 <bitfield name="ENABLE" pos="0" type="boolean"/> 1978 4130 <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean"> 1979 4131 <doc> ··· 1987 4139 <bitfield name="VIEWS" low="2" high="6" type="uint"/> 1988 4140 </bitset> 1989 4141 1990 1990 - <reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" usage="rp_blit"/> 1991 1991 - <reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" usage="rp_blit"/> 1992 1992 - <reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> 1993 1993 - <reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/> 4142 4142 + <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX-" usage="rp_blit"/> 4143 4143 + <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX-" usage="rp_blit"/> 4144 4144 + <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> 4145 4145 + <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX-" usage="rp_blit"/> 1994 4146 1995 4147 <enum name="a6xx_varying_interp_mode"> 1996 4148 <value value="0" name="INTERP_SMOOTH"/> ··· 2007 4159 </enum> 2008 4160 2009 4161 <!-- 0x9109-0x91ff invalid --> 2010 2010 - <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit"> 4162 4162 + <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" usage="rp_blit"> 2011 4163 <doc>Packed array of a6xx_varying_interp_mode</doc> 2012 4164 <reg32 offset="0x0" name="MODE"/> 2013 4165 </array> 2014 2014 - <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit"> 4166 4166 + <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE_0" stride="1" length="8" usage="rp_blit"> 2015 4167 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 2016 4168 <reg32 offset="0x0" name="MODE"/> 2017 4169 </array> ··· 2020 4172 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> 2021 4173 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> 2022 4174 2023 2023 - <array offset="0x9212" name="VPC_VAR" stride="1" length="4" usage="rp_blit"> 4175 4175 + <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL_0" stride="1" length="4" usage="rp_blit"> 2024 4176 <!-- one bit per varying component: --> 2025 4177 <reg32 offset="0" name="DISABLE"/> 2026 4178 </array> 2027 4179 2028 2028 - <reg32 offset="0x9216" name="VPC_SO_CNTL" usage="rp_blit"> 4180 4180 + <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" usage="rp_blit"> 2029 4181 <!-- 2030 4182 Choose which DWORD to write to. There is an array of 2031 4183 (4 * 64) DWORD's, dumped in the devcoredump at ··· 2046 4198 When EmitStreamVertex(N) happens, the HW goes to DWORD 2047 4199 64 * N and then "executes" the next 64 DWORD's. 2048 4200 2049 2049 - This field is auto-incremented when VPC_SO_PROG is 4201 4201 + This field is auto-incremented when VPC_SO_MAPPING_PORT is 2050 4202 written to. 2051 4203 --> 2052 4204 <bitfield name="ADDR" low="0" high="7" type="hex"/> ··· 2054 4206 <bitfield name="RESET" pos="16" type="boolean"/> 2055 4207 </reg32> 2056 4208 <!-- special register, write multiple times to load SO program (not readable) --> 2057 2057 - <reg32 offset="0x9217" name="VPC_SO_PROG" usage="rp_blit"> 4209 4209 + <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" usage="rp_blit"> 2058 4210 <bitfield name="A_BUF" low="0" high="1" type="uint"/> 2059 4211 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> 2060 4212 <bitfield name="A_EN" pos="11" type="boolean"/> ··· 2063 4215 <bitfield name="B_EN" pos="23" type="boolean"/> 2064 4216 </reg32> 2065 4217 2066 2066 - <reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32" usage="cmd"/> 4218 4218 + <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" usage="cmd"/> 2067 4219 2068 4220 <array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd"> 2069 4221 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> ··· 2073 4225 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 2074 4226 </array> 2075 4227 2076 2076 - <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT" usage="cmd"> 4228 4228 + <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" usage="cmd"> 2077 4229 <bitfield name="INVERT" pos="0" type="boolean"/> 2078 4230 </reg32> 2079 4231 <!-- 0x9237-0x92ff invalid --> 2080 4232 <!-- always 0x0 ? --> 2081 4233 <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/> 2082 4234 2083 2083 - <bitset name="a6xx_vpc_xs_pack" inline="yes"> 4235 4235 + <bitset name="a6xx_vpc_xs_cntl" inline="yes"> 2084 4236 <doc> 2085 4237 num of varyings plus four for gl_Position (plus one if gl_PointSize) 2086 4238 plus # of transform-feedback (streamout) varyings if using the ··· 2097 4249 </doc> 2098 4250 </bitfield> 2099 4251 </bitset> 2100 2100 - <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> 2101 2101 - <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> 2102 2102 - <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> 4252 4252 + <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 4253 4253 + <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 4254 4254 + <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2103 4255 2104 2104 - <reg32 offset="0x9304" name="VPC_CNTL_0" usage="rp_blit"> 4256 4256 + <reg32 offset="0x9304" name="VPC_PS_CNTL" usage="rp_blit"> 2105 4257 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 2106 4258 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> 2107 4259 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> ··· 2120 4272 </bitfield> 2121 4273 </reg32> 2122 4274 2123 2123 - <reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL" usage="rp_blit"> 4275 4275 + <reg32 offset="0x9305" name="VPC_SO_CNTL" usage="rp_blit"> 2124 4276 <!-- 2125 4277 It's offset by 1, and 0 means "disabled" 2126 4278 --> ··· 2130 4282 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> 2131 4283 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2132 4284 </reg32> 2133 2133 - <reg32 offset="0x9306" name="VPC_SO_DISABLE" usage="rp_blit"> 4285 4285 + <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" usage="rp_blit"> 2134 4286 <bitfield name="DISABLE" pos="0" type="boolean"/> 2135 4287 </reg32> 2136 2136 - <reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit"> 4288 4288 + <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" variants="A6XX-" usage="rp_blit"> <!-- A702 + A7xx --> 2137 4289 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2138 4290 </reg32> 2139 2139 - <reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit"> 4291 4291 + <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> 2140 4292 <bitfield name="SIZE_GMEM" low="0" high="31"/> 2141 4293 </reg32> 2142 2142 - <reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit"> 4294 4294 + <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX-" usage="rp_blit"> 2143 4295 <bitfield name="BASE_GMEM" low="0" high="31"/> 2144 4296 </reg32> 2145 2145 - <reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit"> 4297 4297 + <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> 2146 4298 <bitfield name="SIZE_GMEM" low="0" high="31"/> 2147 4299 </reg32> 2148 4300 ··· 2159 4311 <!-- TODO: regs from 0x9624-0x963a --> 2160 4312 <!-- 0x963b-0x97ff invalid --> 2161 4313 2162 2162 - <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/> 4314 4314 + <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" usage="rp_blit"/> 2163 4315 2164 4316 <!-- always 0x0 ? --> 2165 2165 - <reg32 offset="0x9801" name="PC_HS_INPUT_SIZE" usage="rp_blit"> 4317 4317 + <reg32 offset="0x9801" name="PC_HS_PARAM_1" usage="rp_blit"> 2166 4318 <bitfield name="SIZE" low="0" high="10" type="uint"/> 2167 4319 <bitfield name="UNK13" pos="13"/> 2168 4320 </reg32> 2169 4321 2170 2170 - <reg32 offset="0x9802" name="PC_TESS_CNTL" usage="rp_blit"> 4322 4322 + <reg32 offset="0x9802" name="PC_DS_PARAM" usage="rp_blit"> 2171 4323 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> 2172 4324 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> 2173 4325 </reg32> ··· 2182 4334 </reg32> 2183 4335 2184 4336 <!-- New in a6xx gen3+ --> 2185 2185 - <reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit"> 4337 4337 + <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" usage="rp_blit"> 2186 4338 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2187 4339 </reg32> 2188 4340 ··· 2192 4344 <!-- 0x980b-0x983f invalid --> 2193 4345 2194 4346 <!-- 0x9840 - 0x9842 are not readable --> 2195 2195 - <reg32 offset="0x9840" name="PC_DRAW_CMD"> 4347 4347 + <reg32 offset="0x9840" name="PC_DRAW_INITIATOR"> 2196 4348 <bitfield name="STATE_ID" low="0" high="7"/> 2197 4349 </reg32> 2198 4350 2199 2199 - <reg32 offset="0x9841" name="PC_DISPATCH_CMD"> 4351 4351 + <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR"> 2200 4352 <bitfield name="STATE_ID" low="0" high="7"/> 2201 4353 </reg32> 2202 4354 2203 2203 - <reg32 offset="0x9842" name="PC_EVENT_CMD"> 4355 4355 + <reg32 offset="0x9842" name="PC_EVENT_INITIATOR"> 2204 4356 <!-- I think only the low bit is actually used? --> 2205 4357 <bitfield name="STATE_ID" low="16" high="23"/> 2206 4358 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> ··· 2215 4367 2216 4368 <!-- 0x9843-0x997f invalid --> 2217 4369 2218 2218 - <reg32 offset="0x9981" name="PC_POLYGON_MODE" variants="A6XX" usage="rp_blit"> 4370 4370 + <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" variants="A6XX" usage="rp_blit"> 2219 4371 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2220 4372 </reg32> 2221 2221 - <reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit"> 4373 4373 + <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" variants="A7XX-" usage="rp_blit"> 2222 4374 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2223 4375 </reg32> 2224 4376 2225 2225 - <reg32 offset="0x9980" name="PC_RASTER_CNTL" variants="A6XX" usage="rp_blit"> 4377 4377 + <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" variants="A6XX" usage="rp_blit"> 2226 4378 <!-- which stream to send to GRAS --> 2227 4379 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2228 4380 <!-- discard primitives before rasterization --> 2229 4381 <bitfield name="DISCARD" pos="2" type="boolean"/> 2230 4382 </reg32> 2231 2231 - <!-- VPC_RASTER_CNTL --> 2232 2232 - <reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit"> 4383 4383 + <!-- VPC_RAST_STREAM_CNTL --> 4384 4384 + <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" variants="A7XX-" usage="rp_blit"> 2233 4385 <!-- which stream to send to GRAS --> 2234 4386 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2235 4387 <!-- discard primitives before rasterization --> 2236 4388 <bitfield name="DISCARD" pos="2" type="boolean"/> 2237 4389 </reg32> 2238 2238 - <reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit"> 4390 4390 + <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" variants="A7XX-" usage="rp_blit"> 2239 4391 <!-- which stream to send to GRAS --> 2240 4392 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2241 4393 <!-- discard primitives before rasterization --> ··· 2245 4397 <!-- Both are a750+. 2246 4398 Probably needed to correctly overlap execution of several draws. 2247 4399 --> 2248 2248 - <reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/> 4400 4400 + <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> 2249 4401 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of 2250 4402 this additional space is not known. 2251 4403 --> 2252 2252 - <reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/> 4404 4404 + <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> 2253 4405 2254 4406 <!-- 0x9982-0x9aff invalid --> 2255 4407 2256 2256 - <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/> 4408 4408 + <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" usage="rp_blit"/> 2257 4409 2258 2258 - <bitset name="a6xx_xs_out_cntl" inline="yes"> 4410 4410 + <bitset name="a6xx_pc_xs_cntl" inline="yes"> 2259 4411 <doc> 2260 4412 num of varyings plus four for gl_Position (plus one if gl_PointSize) 2261 4413 plus # of transform-feedback (streamout) varyings if using the ··· 2265 4417 <bitfield name="PSIZE" pos="8" type="boolean"/> 2266 4418 <bitfield name="LAYER" pos="9" type="boolean"/> 2267 4419 <bitfield name="VIEW" pos="10" type="boolean"/> 2268 2268 - <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit --> 4420 4420 + <!-- note: PC_VS_CNTL doesn't have the PRIMITIVE_ID bit --> 2269 4421 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> 2270 4422 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> 2271 4423 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/> 2272 4424 </bitset> 2273 4425 2274 2274 - <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> 2275 2275 - <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> 4426 4426 + <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 4427 4427 + <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2276 4428 <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 2277 2277 - <reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> 2278 2278 - <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> 4429 4429 + <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 4430 4430 + <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2279 4431 2280 2280 - <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" usage="rp_blit"/> 4432 4432 + <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" usage="rp_blit"/> 2281 4433 2282 4434 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit"> 2283 4435 <doc> ··· 2286 4438 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> 2287 4439 </reg32> 2288 4440 2289 2289 - <reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/> 4441 4441 + <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> 2290 4442 <!-- mask of enabled views, doesn't exist on A630 --> 2291 2291 - <reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/> 4443 4443 + <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" usage="rp_blit"/> 2292 4444 <!-- 0x9b09-0x9bff invalid --> 2293 4445 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 2294 4446 <!-- special register (but note first 8 bits can be written/read) --> ··· 2299 4451 <!-- TODO: 0x9e00-0xa000 range incomplete --> 2300 4452 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/> 2301 4453 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2302 2302 - <reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/> 2303 2303 - <reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/> 2304 2304 - <reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/> 2305 2305 - <reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" variants="A6XX" type="waddress" align="32" usage="cmd"/> 2306 2306 - <reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage="cmd"/> 4454 4454 + <reg64 offset="0x9e04" name="PC_DMA_BASE"/> 4455 4455 + <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint"/> 4456 4456 + <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint"/> 4457 4457 + <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 4458 4458 + <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX-" type="waddress" align="32" usage="cmd"/> 2307 4459 2308 2308 - <reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx"> 4460 4460 + <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx"> 2309 4461 <doc> 2310 4462 Possibly not really "initiating" the draw but the layout is similar 2311 4463 to VGT_DRAW_INITIATOR on older gens 2312 4464 </doc> 2313 4465 </reg32> 2314 2314 - <reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/> 2315 2315 - <reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/> 4466 4466 + <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint"/> 4467 4467 + <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint"/> 2316 4468 2317 4469 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 2318 2318 - <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL"> 4470 4470 + <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL"> 2319 4471 <bitfield name="UNK0" low="0" high="15"/> 2320 4472 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 2321 4473 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 2322 4474 </reg32> 2323 2323 - <reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/> 2324 2324 - <reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/> 4475 4475 + <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32"/> 4476 4476 + <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32"/> 2325 4477 2326 2326 - <reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE"> 4478 4478 + <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE"> 2327 4479 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 2328 4480 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 2329 4481 </reg32> ··· 2336 4488 <!-- always 0x0 --> 2337 4489 <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/> 2338 4490 2339 2339 - <reg32 offset="0xa000" name="VFD_CONTROL_0" usage="rp_blit"> 4491 4491 + <reg32 offset="0xa000" name="VFD_CNTL_0" usage="rp_blit"> 2340 4492 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/> 2341 4493 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/> 2342 4494 </reg32> 2343 2343 - <reg32 offset="0xa001" name="VFD_CONTROL_1" usage="rp_blit"> 4495 4495 + <reg32 offset="0xa001" name="VFD_CNTL_1" usage="rp_blit"> 2344 4496 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> 2345 4497 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> 2346 4498 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> 2347 4499 <!-- only used for VS in non-multi-position-output case --> 2348 4500 <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/> 2349 4501 </reg32> 2350 2350 - <reg32 offset="0xa002" name="VFD_CONTROL_2" usage="rp_blit"> 4502 4502 + <reg32 offset="0xa002" name="VFD_CNTL_2" usage="rp_blit"> 2351 4503 <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid"> 2352 4504 <doc> 2353 4505 This is the ID of the current patch within the ··· 2360 4512 </bitfield> 2361 4513 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/> 2362 4514 </reg32> 2363 2363 - <reg32 offset="0xa003" name="VFD_CONTROL_3" usage="rp_blit"> 4515 4515 + <reg32 offset="0xa003" name="VFD_CNTL_3" usage="rp_blit"> 2364 4516 <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/> 2365 4517 <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/> 2366 4518 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> 2367 4519 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> 2368 4520 </reg32> 2369 2369 - <reg32 offset="0xa004" name="VFD_CONTROL_4" usage="rp_blit"> 4521 4521 + <reg32 offset="0xa004" name="VFD_CNTL_4" usage="rp_blit"> 2370 4522 <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/> 2371 4523 </reg32> 2372 2372 - <reg32 offset="0xa005" name="VFD_CONTROL_5" usage="rp_blit"> 4524 4524 + <reg32 offset="0xa005" name="VFD_CNTL_5" usage="rp_blit"> 2373 4525 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/> 2374 4526 <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/> 2375 4527 </reg32> 2376 2376 - <reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit"> 4528 4528 + <reg32 offset="0xa006" name="VFD_CNTL_6" usage="rp_blit"> 2377 4529 <!-- 2378 4530 True if gl_PrimitiveID is read via the FS 2379 4531 --> 2380 4532 <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/> 2381 4533 </reg32> 2382 4534 2383 2383 - <reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd"> 4535 4535 + <reg32 offset="0xa007" name="VFD_RENDER_MODE" usage="cmd"> 2384 4536 <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/> 2385 4537 </reg32> 2386 4538 2387 2387 - <reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/> 2388 2388 - <reg32 offset="0xa009" name="VFD_ADD_OFFSET" usage="cmd"> 4539 4539 + <reg32 offset="0xa008" name="VFD_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> 4540 4540 + <reg32 offset="0xa009" name="VFD_MODE_CNTL" usage="cmd"> 2389 4541 <!-- add VFD_INDEX_OFFSET to REGID4VTX --> 2390 4542 <bitfield name="VERTEX" pos="0" type="boolean"/> 2391 4543 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST --> ··· 2394 4546 2395 4547 <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/> 2396 4548 <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/> 2397 2397 - <array offset="0xa010" name="VFD_FETCH" stride="4" length="32" usage="rp_blit"> 4549 4549 + <array offset="0xa010" name="VFD_VERTEX_BUFFER" stride="4" length="32" usage="rp_blit"> 2398 4550 <reg64 offset="0x0" name="BASE" type="address" align="1"/> 2399 4551 <reg32 offset="0x2" name="SIZE" type="uint"/> 2400 4552 <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/> 2401 4553 </array> 2402 2402 - <array offset="0xa090" name="VFD_DECODE" stride="2" length="32" usage="rp_blit"> 4554 4554 + <array offset="0xa090" name="VFD_FETCH_INSTR" stride="2" length="32" usage="rp_blit"> 2403 4555 <reg32 offset="0x0" name="INSTR"> 2404 2404 - <!-- IDX and byte OFFSET into VFD_FETCH --> 4556 4556 + <!-- IDX and byte OFFSET into VFD_VERTEX_BUFFER --> 2405 4557 <bitfield name="IDX" low="0" high="4" type="uint"/> 2406 4558 <bitfield name="OFFSET" low="5" high="16"/> 2407 4559 <bitfield name="INSTANCED" pos="17" type="boolean"/> ··· 2421 4573 2422 4574 <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 2423 4575 2424 2424 - <reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/> 4576 4576 + <reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 2425 4577 2426 4578 <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2427 4579 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/> ··· 2436 4588 <value value="1" name="THREAD128"/> 2437 4589 </enum> 2438 4590 2439 2439 - <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes"> 4591 4591 + <bitset name="a6xx_sp_xs_cntl_0" inline="yes"> 2440 4592 <!-- if set to SINGLE, only use 1 concurrent wave on each SP --> 2441 4593 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> 2442 4594 <!-- ··· 2468 4620 --> 2469 4621 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/> 2470 4622 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/> 2471 2471 - <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/> 4623 4623 + <bitfield name="BINDLESS_UAV" pos="2" type="boolean"/> 2472 4624 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/> 2473 4625 2474 4626 <bitfield name="ENABLED" pos="8" type="boolean"/> ··· 2478 4630 --> 2479 4631 <bitfield name="NTEX" low="9" high="16" type="uint"/> 2480 4632 <bitfield name="NSAMP" low="17" high="21" type="uint"/> 2481 2481 - <bitfield name="NIBO" low="22" high="28" type="uint"/> 4633 4633 + <bitfield name="NUAV" low="22" high="28" type="uint"/> 2482 4634 </bitset> 2483 4635 2484 2484 - <bitset name="a6xx_sp_xs_prim_cntl" inline="yes"> 4636 4636 + <bitset name="a6xx_sp_xs_output_cntl" inline="yes"> 2485 4637 <!-- # of VS outputs including pos/psize --> 2486 4638 <bitfield name="OUT" low="0" high="5" type="uint"/> 2487 4639 <!-- FLAGS_REGID only for GS --> 2488 4640 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> 2489 4641 </bitset> 2490 4642 2491 2491 - <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 4643 4643 + <reg32 offset="0xa800" name="SP_VS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2492 4644 <!-- 2493 4645 This field actually controls all geometry stages. TCS, TES, and 2494 4646 GS must have the same mergedregs setting as VS. ··· 2513 4665 </reg32> 2514 4666 <!-- bitmask of true/false conditions for VS brac.N instructions, 2515 4667 bit N corresponds to brac.N --> 2516 2516 - <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/> 4668 4668 + <reg32 offset="0xa801" name="SP_VS_BOOLEAN_CF_MASK" type="hex"/> 2517 4669 <!-- # of VS outputs including pos/psize --> 2518 2518 - <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> 2519 2519 - <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16" usage="rp_blit"> 4670 4670 + <reg32 offset="0xa802" name="SP_VS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 4671 4671 + <array offset="0xa803" name="SP_VS_OUTPUT" stride="1" length="16" usage="rp_blit"> 2520 4672 <reg32 offset="0x0" name="REG"> 2521 4673 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 2522 4674 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> ··· 2526 4678 </array> 2527 4679 <!-- 2528 4680 Starting with a5xx, position/psize outputs from shader end up in the 2529 2529 - SP_VS_OUT map, with highest OUTLOCn position. (Generally they are 4681 4681 + SP_VS_OUTPUT map, with highest OUTLOCn position. (Generally they are 2530 4682 the last entries too, except when gl_PointCoord is used, blob inserts 2531 4683 an extra varying after, but with a lower OUTLOC position. If present, 2532 4684 psize is last, preceded by position. 2533 4685 --> 2534 2534 - <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8" usage="rp_blit"> 4686 4686 + <array offset="0xa813" name="SP_VS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 2535 4687 <reg32 offset="0x0" name="REG"> 2536 4688 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 2537 4689 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> ··· 2600 4752 </bitfield> 2601 4753 </bitset> 2602 4754 2603 2603 - <bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes"> 4755 4755 + <bitset name="a6xx_sp_xs_pvt_mem_stack_offset" inline="yes"> 2604 4756 <doc> 2605 4757 This seems to be be the equivalent of HWSTACKOFFSET in 2606 4758 a3xx. The ldp/stp offset formula above isn't affected by ··· 2611 4763 <bitfield name="OFFSET" low="0" high="18" shr="11"/> 2612 4764 </bitset> 2613 4765 2614 2614 - <reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 2615 2615 - <reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32" usage="rp_blit"/> 4766 4766 + <reg32 offset="0xa81b" name="SP_VS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 4767 4767 + <reg64 offset="0xa81c" name="SP_VS_BASE" type="address" align="32" usage="rp_blit"/> 2616 4768 <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2617 2617 - <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 4769 4769 + <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2618 4770 <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2619 2619 - <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 4771 4771 + <reg32 offset="0xa822" name="SP_VS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2620 4772 <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 2621 2621 - <reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 2622 2622 - <reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 2623 2623 - <reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 4773 4773 + <reg32 offset="0xa824" name="SP_VS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 4774 4774 + <reg32 offset="0xa825" name="SP_VS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 4775 4775 + <reg32 offset="0xa82d" name="SP_VS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2624 4776 2625 2625 - <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 4777 4777 + <reg32 offset="0xa830" name="SP_HS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2626 4778 <!-- There is no mergedregs bit, that comes from the VS. --> 2627 4779 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 2628 4780 </reg32> ··· 2630 4782 Total size of local storage in dwords divided by the wave size. 2631 4783 The maximum value is 64. With the wave size being always 64 for HS, 2632 4784 the maximum size of local storage should be: 2633 2633 - 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k 4785 4785 + 64 (wavesize) * 64 (SP_HS_CNTL_1) * 4 = 16k 2634 4786 --> 2635 2635 - <reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2636 2636 - <reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex" usage="rp_blit"/> 4787 4787 + <reg32 offset="0xa831" name="SP_HS_CNTL_1" low="0" high="7" type="uint" usage="rp_blit"/> 4788 4788 + <reg32 offset="0xa832" name="SP_HS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> 2637 4789 2638 4790 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 2639 2639 - <reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 2640 2640 - <reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32" usage="rp_blit"/> 4791 4791 + <reg32 offset="0xa833" name="SP_HS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 4792 4792 + <reg64 offset="0xa834" name="SP_HS_BASE" type="address" align="32" usage="rp_blit"/> 2641 4793 <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2642 2642 - <reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 4794 4794 + <reg64 offset="0xa837" name="SP_HS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2643 4795 <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2644 2644 - <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 4796 4796 + <reg32 offset="0xa83a" name="SP_HS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2645 4797 <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 2646 2646 - <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 2647 2647 - <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 2648 2648 - <reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 4798 4798 + <reg32 offset="0xa83c" name="SP_HS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 4799 4799 + <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 4800 4800 + <reg32 offset="0xa82f" name="SP_HS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2649 4801 2650 2650 - <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 4802 4802 + <reg32 offset="0xa840" name="SP_DS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2651 4803 <!-- There is no mergedregs bit, that comes from the VS. --> 2652 4804 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 2653 4805 </reg32> 2654 2654 - <reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/> 4806 4806 + <reg32 offset="0xa841" name="SP_DS_BOOLEAN_CF_MASK" type="hex"/> 2655 4807 2656 4808 <!-- TODO: exact same layout as 0xa802-0xa81a --> 2657 2657 - <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> 2658 2658 - <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16" usage="rp_blit"> 4809 4809 + <reg32 offset="0xa842" name="SP_DS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 4810 4810 + <array offset="0xa843" name="SP_DS_OUTPUT" stride="1" length="16" usage="rp_blit"> 2659 4811 <reg32 offset="0x0" name="REG"> 2660 4812 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 2661 4813 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> ··· 2663 4815 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 2664 4816 </reg32> 2665 4817 </array> 2666 2666 - <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8" usage="rp_blit"> 4818 4818 + <array offset="0xa853" name="SP_DS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 2667 4819 <reg32 offset="0x0" name="REG"> 2668 4820 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 2669 4821 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> ··· 2673 4825 </array> 2674 4826 2675 4827 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 2676 2676 - <reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 2677 2677 - <reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32" usage="rp_blit"/> 4828 4828 + <reg32 offset="0xa85b" name="SP_DS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 4829 4829 + <reg64 offset="0xa85c" name="SP_DS_BASE" type="address" align="32" usage="rp_blit"/> 2678 4830 <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2679 2679 - <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 4831 4831 + <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2680 4832 <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2681 2681 - <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 4833 4833 + <reg32 offset="0xa862" name="SP_DS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2682 4834 <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 2683 2683 - <reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 2684 2684 - <reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 2685 2685 - <reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 4835 4835 + <reg32 offset="0xa864" name="SP_DS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 4836 4836 + <reg32 offset="0xa865" name="SP_DS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 4837 4837 + <reg32 offset="0xa868" name="SP_DS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2686 4838 2687 2687 - <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 4839 4839 + <reg32 offset="0xa870" name="SP_GS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2688 4840 <!-- There is no mergedregs bit, that comes from the VS. --> 2689 4841 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 2690 4842 </reg32> 2691 2691 - <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit"> 4843 4843 + <reg32 offset="0xa871" name="SP_GS_CNTL_1" low="0" high="7" type="uint" usage="rp_blit"> 2692 4844 <doc> 2693 4845 Normally the size of the output of the last stage in 2694 4846 dwords. It should be programmed as follows: ··· 2702 4854 doesn't matter in practice. 2703 4855 </doc> 2704 4856 </reg32> 2705 2705 - <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex" usage="rp_blit"/> 4857 4857 + <reg32 offset="0xa872" name="SP_GS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> 2706 4858 2707 4859 <!-- TODO: exact same layout as 0xa802-0xa81a --> 2708 2708 - <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> 2709 2709 - <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16" usage="rp_blit"> 4860 4860 + <reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 4861 4861 + <array offset="0xa874" name="SP_GS_OUTPUT" stride="1" length="16" usage="rp_blit"> 2710 4862 <reg32 offset="0x0" name="REG"> 2711 4863 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 2712 4864 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> ··· 2715 4867 </reg32> 2716 4868 </array> 2717 4869 2718 2718 - <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8" usage="rp_blit"> 4870 4870 + <array offset="0xa884" name="SP_GS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 2719 4871 <reg32 offset="0x0" name="REG"> 2720 4872 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 2721 4873 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> ··· 2725 4877 </array> 2726 4878 2727 4879 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 2728 2728 - <reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 2729 2729 - <reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32" usage="rp_blit"/> 4880 4880 + <reg32 offset="0xa88c" name="SP_GS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 4881 4881 + <reg64 offset="0xa88d" name="SP_GS_BASE" type="address" align="32" usage="rp_blit"/> 2730 4882 <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2731 2731 - <reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 4883 4883 + <reg64 offset="0xa890" name="SP_GS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2732 4884 <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2733 2733 - <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 4885 4885 + <reg32 offset="0xa893" name="SP_GS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2734 4886 <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 2735 2735 - <reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 2736 2736 - <reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 2737 2737 - <reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 4887 4887 + <reg32 offset="0xa895" name="SP_GS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 4888 4888 + <reg32 offset="0xa896" name="SP_GS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 4889 4889 + <reg32 offset="0xa899" name="SP_GS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2738 4890 2739 2739 - <reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16" usage="cmd"/> 2740 2740 - <reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16" usage="cmd"/> 2741 2741 - <reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16" usage="cmd"/> 2742 2742 - <reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16" usage="cmd"/> 2743 2743 - <reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64" usage="cmd"/> 2744 2744 - <reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64" usage="cmd"/> 2745 2745 - <reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64" usage="cmd"/> 2746 2746 - <reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64" usage="cmd"/> 4891 4891 + <reg64 offset="0xa8a0" name="SP_VS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 4892 4892 + <reg64 offset="0xa8a2" name="SP_HS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 4893 4893 + <reg64 offset="0xa8a4" name="SP_DS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 4894 4894 + <reg64 offset="0xa8a6" name="SP_GS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 4895 4895 + <reg64 offset="0xa8a8" name="SP_VS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 4896 4896 + <reg64 offset="0xa8aa" name="SP_HS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 4897 4897 + <reg64 offset="0xa8ac" name="SP_DS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 4898 4898 + <reg64 offset="0xa8ae" name="SP_GS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 2747 4899 2748 4900 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 --> 2749 4901 2750 2750 - <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 4902 4902 + <reg32 offset="0xa980" name="SP_PS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2751 4903 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 2752 4904 <bitfield name="UNK21" pos="21" type="boolean"/> 2753 4905 <bitfield name="VARYING" pos="22" type="boolean"/> ··· 2757 4909 fine derivatives and quad subgroup ops. 2758 4910 </doc> 2759 4911 </bitfield> 2760 2760 - <!-- note: vk blob uses bit24 --> 2761 2761 - <bitfield name="UNK24" pos="24" type="boolean"/> 4912 4912 + <bitfield name="INOUTREGOVERLAP" pos="24" type="boolean"/> 2762 4913 <bitfield name="UNK25" pos="25" type="boolean"/> 2763 4914 <bitfield name="PIXLODENABLE" pos="26" type="boolean"> 2764 4915 <doc> ··· 2770 4923 <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/> 2771 4924 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 2772 4925 </reg32> 2773 2773 - <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/> 2774 2774 - <reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 2775 2775 - <reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32" usage="rp_blit"/> 2776 2776 - <reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2777 2777 - <reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 2778 2778 - <reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 4926 4926 + <reg32 offset="0xa981" name="SP_PS_BOOLEAN_CF_MASK" type="hex"/> 4927 4927 + <reg32 offset="0xa982" name="SP_PS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 4928 4928 + <reg64 offset="0xa983" name="SP_PS_BASE" type="address" align="32" usage="rp_blit"/> 4929 4929 + <reg32 offset="0xa985" name="SP_PS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 4930 4930 + <reg64 offset="0xa986" name="SP_PS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 4931 4931 + <reg32 offset="0xa988" name="SP_PS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2779 4932 2780 4933 <reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit"> 2781 4934 <!-- per-mrt enable bit --> ··· 2795 4948 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 2796 4949 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 2797 4950 </reg32> 2798 2798 - <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS" usage="rp_blit"> 4951 4951 + <reg32 offset="0xa98b" name="SP_PS_OUTPUT_MASK" usage="rp_blit"> 2799 4952 <bitfield name="RT0" low="0" high="3"/> 2800 4953 <bitfield name="RT1" low="4" high="7"/> 2801 4954 <bitfield name="RT2" low="8" high="11"/> ··· 2805 4958 <bitfield name="RT6" low="24" high="27"/> 2806 4959 <bitfield name="RT7" low="28" high="31"/> 2807 4960 </reg32> 2808 2808 - <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0" usage="rp_blit"> 4961 4961 + <reg32 offset="0xa98c" name="SP_PS_OUTPUT_CNTL" usage="rp_blit"> 2809 4962 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 2810 4963 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> 2811 4964 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> 2812 4965 <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/> 2813 4966 </reg32> 2814 2814 - <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1" usage="rp_blit"> 4967 4967 + <reg32 offset="0xa98d" name="SP_PS_MRT_CNTL" usage="rp_blit"> 2815 4968 <bitfield name="MRT" low="0" high="3" type="uint"/> 2816 4969 </reg32> 2817 4970 2818 2818 - <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8" usage="rp_blit"> 4971 4971 + <array offset="0xa98e" name="SP_PS_OUTPUT" stride="1" length="8" usage="rp_blit"> 2819 4972 <doc>per MRT</doc> 2820 4973 <reg32 offset="0x0" name="REG"> 2821 4974 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> ··· 2823 4976 </reg32> 2824 4977 </array> 2825 4978 2826 2826 - <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8" usage="rp_blit"> 4979 4979 + <array offset="0xa996" name="SP_PS_MRT" stride="1" length="8" usage="rp_blit"> 2827 4980 <reg32 offset="0" name="REG"> 2828 4981 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2829 4982 <bitfield name="COLOR_SINT" pos="8" type="boolean"/> ··· 2832 4985 </reg32> 2833 4986 </array> 2834 4987 2835 2835 - <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL" usage="rp_blit"> 4988 4988 + <reg32 offset="0xa99e" name="SP_PS_INITIAL_TEX_LOAD_CNTL" usage="rp_blit"> 2836 4989 <bitfield name="COUNT" low="0" high="2" type="uint"/> 2837 4990 <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/> 2838 4991 <doc> ··· 2849 5002 <!-- Blob never uses it --> 2850 5003 <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/> 2851 5004 </reg32> 2852 2852 - <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit"> 5005 5005 + <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A6XX" usage="rp_blit"> 2853 5006 <reg32 offset="0" name="CMD" variants="A6XX"> 2854 5007 <bitfield name="SRC" low="0" high="6" type="uint"/> 2855 5008 <bitfield name="SAMP_ID" low="7" high="10" type="uint"/> ··· 2863 5016 <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/> 2864 5017 </reg32> 2865 5018 </array> 2866 2866 - <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit"> 5019 5019 + <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A7XX-" usage="rp_blit"> 2867 5020 <reg32 offset="0" name="CMD" variants="A7XX-"> 2868 5021 <bitfield name="SRC" low="0" high="6" type="uint"/> 2869 5022 <bitfield name="SAMP_ID" low="7" high="9" type="uint"/> ··· 2875 5028 <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/> 2876 5029 </reg32> 2877 5030 </array> 2878 2878 - <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4" usage="rp_blit"> 5031 5031 + <array offset="0xa9a3" name="SP_PS_INITIAL_TEX_INDEX" stride="1" length="4" usage="rp_blit"> 2879 5032 <reg32 offset="0" name="CMD"> 2880 5033 <bitfield name="SAMP_ID" low="0" high="15" type="uint"/> 2881 5034 <bitfield name="TEX_ID" low="16" high="31" type="uint"/> 2882 5035 </reg32> 2883 5036 </array> 2884 2884 - <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 5037 5037 + <reg32 offset="0xa9a7" name="SP_PS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2885 5038 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? --> 2886 2886 - <reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 5039 5039 + <reg32 offset="0xa9a9" name="SP_PS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 5040 5040 + <reg32 offset="0xa9ab" name="SP_PS_UNKNOWN_A9AB" variants="A7XX-" usage="cmd"/> 2887 5041 2888 5042 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS --> 2889 5043 2890 5044 2891 5045 2892 5046 2893 2893 - <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="cmd"> 5047 5047 + <reg32 offset="0xa9b0" name="SP_CS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="cmd"> 2894 5048 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 2895 5049 <!-- seems to make SP use less concurrent threads when possible? --> 2896 5050 <bitfield name="UNK21" pos="21" type="boolean"/> ··· 2901 5053 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 2902 5054 </reg32> 2903 5055 5056 5056 + <enum name="a6xx_const_ram_mode"> 5057 5057 + <value value="0x0" name="CONSTLEN_128"/> 5058 5058 + <value value="0x1" name="CONSTLEN_192"/> 5059 5059 + <value value="0x2" name="CONSTLEN_256"/> 5060 5060 + <value value="0x3" name="CONSTLEN_512"/> <!-- a7xx only --> 5061 5061 + </enum> 5062 5062 + 2904 5063 <!-- set for compute shaders --> 2905 2905 - <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" usage="cmd"> 5064 5064 + <reg32 offset="0xa9b1" name="SP_CS_CNTL_1" usage="cmd"> 2906 5065 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"> 2907 5066 <doc> 2908 5067 If 0 - all 32k of shared storage is enabled, otherwise ··· 2920 5065 always return 0) 2921 5066 </doc> 2922 5067 </bitfield> 2923 2923 - <bitfield name="UNK5" pos="5" type="boolean"/> 2924 2924 - <!-- always 1 ? --> 2925 2925 - <bitfield name="UNK6" pos="6" type="boolean"/> 5068 5068 + <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"> 5069 5069 + <doc> 5070 5070 + This defines the split between consts and local 5071 5071 + memory in the Local Buffer. The programmed value 5072 5072 + must be at least the actual CONSTLEN. 5073 5073 + </doc> 5074 5074 + </bitfield> 2926 5075 </reg32> 2927 2927 - <reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex" usage="cmd"/> 2928 2928 - <reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="cmd"/> 2929 2929 - <reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32" usage="cmd"/> 5076 5076 + <reg32 offset="0xa9b2" name="SP_CS_BOOLEAN_CF_MASK" type="hex" usage="cmd"/> 5077 5077 + <reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="cmd"/> 5078 5078 + <reg64 offset="0xa9b4" name="SP_CS_BASE" type="address" align="32" usage="cmd"/> 2930 5079 <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/> 2931 2931 - <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32" usage="cmd"/> 5080 5080 + <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" align="32" usage="cmd"/> 2932 5081 <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/> 2933 2933 - <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/> 5082 5082 + <reg32 offset="0xa9ba" name="SP_CS_TSIZE" low="0" high="7" type="uint" usage="cmd"/> 2934 5083 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/> 2935 2935 - <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/> 2936 2936 - <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="cmd"/> 5084 5084 + <reg32 offset="0xa9bc" name="SP_CS_INSTR_SIZE" low="0" high="27" type="uint" usage="cmd"/> 5085 5085 + <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="cmd"/> 2937 5086 <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/> 2938 2938 - <reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 5087 5087 + <reg32 offset="0xa9c5" name="SP_CS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2939 5088 2940 2940 - <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 --> 2941 2941 - <reg32 offset="0xa9c2" name="SP_CS_CNTL_0" usage="cmd"> 5089 5089 + <!-- new in a6xx gen4, matches SP_CS_CONST_CONFIG_0 --> 5090 5090 + <reg32 offset="0xa9c2" name="SP_CS_WIE_CNTL_0" usage="cmd"> 2942 5091 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 2943 5092 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 2944 5093 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 2945 5094 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 2946 5095 </reg32> 2947 2947 - <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 --> 2948 2948 - <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A6XX" usage="cmd"> 5096 5096 + <!-- new in a6xx gen4, matches SP_CS_WGE_CNTL --> 5097 5097 + <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A6XX" usage="cmd"> 2949 5098 <!-- gl_LocalInvocationIndex --> 2950 5099 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 2951 5100 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only ··· 2961 5102 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 2962 5103 </reg32> 2963 5104 2964 2964 - <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd"> 5105 5105 + <enum name="a7xx_workitem_rast_order"> 5106 5106 + <value value="0x0" name="WORKITEMRASTORDER_LINEAR"/> 5107 5107 + <doc> 5108 5108 + This is a fixed tiling, with 4x4 invocation outer tiles 5109 5109 + containing 2x2 invocation inner tiles. The intent is to 5110 5110 + improve cache locality with textures and images accessed 5111 5111 + using gl_LocalInvocationID. 5112 5112 + </doc> 5113 5113 + <value value="0x1" name="WORKITEMRASTORDER_TILED"/> 5114 5114 + </enum> 5115 5115 + 5116 5116 + <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A7XX-" usage="cmd"> 2965 5117 <!-- gl_LocalInvocationIndex --> 2966 5118 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 2967 5119 <!-- Must match SP_CS_CTRL --> ··· 2980 5110 <!-- 1 thread per wave (would hang if THREAD128 is also set) --> 2981 5111 <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/> 2982 5112 2983 2983 - <!-- Affects getone. If enabled, getone sometimes executed 1? less times 2984 2984 - than there are subgroups. 2985 2985 - --> 2986 2986 - <bitfield name="UNK15" pos="15" type="boolean"/> 5113 5113 + <doc>How invocations/fibers within a workgroup are tiled.</doc> 5114 5114 + <bitfield name="WORKITEMRASTORDER" pos="15" type="a7xx_workitem_rast_order"/> 2987 5115 </reg32> 2988 5116 2989 5117 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 --> 2990 5118 2991 2991 - <reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16" usage="rp_blit"/> 2992 2992 - <reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16" usage="cmd"/> 2993 2993 - <reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64" usage="rp_blit"/> 2994 2994 - <reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64" usage="cmd"/> 5119 5119 + <reg64 offset="0xa9e0" name="SP_PS_SAMPLER_BASE" type="address" align="16" usage="rp_blit"/> 5120 5120 + <reg64 offset="0xa9e2" name="SP_CS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 5121 5121 + <reg64 offset="0xa9e4" name="SP_PS_TEXMEMOBJ_BASE" type="address" align="64" usage="rp_blit"/> 5122 5122 + <reg64 offset="0xa9e6" name="SP_CS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 2995 5123 2996 5124 <enum name="a6xx_bindless_descriptor_size"> 2997 5125 <doc> ··· 3014 5146 </array> 3015 5147 3016 5148 <!-- 3017 3017 - IBO state for compute shader: 5149 5149 + UAV state for compute shader: 3018 5150 --> 3019 3019 - <reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/> 3020 3020 - <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/> 5151 5151 + <reg64 offset="0xa9f2" name="SP_CS_UAV_BASE" type="address" align="16" variants="A6XX"/> 5152 5152 + <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX"/> 5153 5153 + <reg32 offset="0xaa00" name="SP_CS_USIZE" low="0" high="6" type="uint"/> 3021 5154 3022 5155 <!-- Correlated with avgs/uvgs usage in FS --> 3023 3023 - <reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/> 5156 5156 + <reg32 offset="0xaa01" name="SP_PS_VGS_CNTL" type="uint" variants="A7XX-" usage="cmd"/> 3024 5157 3025 3025 - <reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd"> 5158 5158 + <reg32 offset="0xaa02" name="SP_PS_OUTPUT_CONST_CNTL" variants="A7XX-" usage="cmd"> 3026 5159 <bitfield name="ENABLED" pos="0" type="boolean"/> 3027 5160 </reg32> 3028 3028 - <reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd"> 5161 5161 + <reg32 offset="0xaa03" name="SP_PS_OUTPUT_CONST_MASK" variants="A7XX-" usage="cmd"> 3029 5162 <doc> 3030 5163 Specify for which components the output color should be read 3031 5164 from alias, e.g. for: ··· 3036 5167 alias.1.b32.0 r1.x, c4.x 3037 5168 alias.1.b32.0 r0.x, c0.x 3038 5169 3039 3039 - the SP_PS_ALIASED_COMPONENTS would be 0x00001111 5170 5170 + the SP_PS_OUTPUT_CONST_MASK would be 0x00001111 3040 5171 </doc> 3041 5172 3042 5173 <bitfield name="RT0" low="0" high="3"/> ··· 3062 5193 <value value="0x2" name="ISAMMODE_GL"/> 3063 5194 </enum> 3064 5195 3065 3065 - <reg32 offset="0xab00" name="SP_MODE_CONTROL" usage="rp_blit"> 5196 5196 + <reg32 offset="0xab00" name="SP_MODE_CNTL" usage="rp_blit"> 3066 5197 <!-- 3067 5198 When set, half register loads from the constant file will 3068 5199 load a 32-bit value (so hc0.y loads the same value as c0.y) ··· 3079 5210 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/> 3080 5211 <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/> 3081 5212 3082 3082 - <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3083 3083 - <reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 5213 5213 + <reg32 offset="0xab04" name="SP_PS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 5214 5214 + <reg32 offset="0xab05" name="SP_PS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3084 5215 3085 3085 - <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 5216 5216 + <array offset="0xab10" name="SP_GFX_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 3086 5217 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 3087 5218 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 3088 5219 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 3089 5220 </reg64> 3090 5221 </array> 3091 3091 - <array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit"> 5222 5222 + <array offset="0xab0a" name="SP_GFX_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit"> 3092 5223 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 3093 5224 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 3094 5225 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> ··· 3096 5227 </array> 3097 5228 3098 5229 <!-- 3099 3099 - Combined IBO state for 3d pipe, used for Image and SSBO write/atomic 3100 3100 - instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders. 5230 5230 + Combined UAV state for 3d pipe, used for Image and SSBO write/atomic 5231 5231 + instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. 3101 5232 --> 3102 3102 - <reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/> 3103 3103 - <reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/> 5233 5233 + <reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/> 5234 5234 + <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" usage="cmd"/> 3104 5235 3105 5236 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/> 3106 5237 3107 3107 - <bitset name="a6xx_sp_2d_dst_format" inline="yes"> 5238 5238 + <bitset name="a6xx_sp_a2d_output_info" inline="yes"> 3108 5239 <bitfield name="NORM" pos="0" type="boolean"/> 3109 5240 <bitfield name="SINT" pos="1" type="boolean"/> 3110 5241 <bitfield name="UINT" pos="2" type="boolean"/> ··· 3117 5248 <bitfield name="MASK" low="12" high="15"/> 3118 5249 </bitset> 3119 5250 3120 3120 - <reg32 offset="0xacc0" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A6XX" usage="rp_blit"/> 3121 3121 - <reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage="rp_blit"/> 5251 5251 + <reg32 offset="0xacc0" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A6XX" usage="rp_blit"/> 5252 5252 + <reg32 offset="0xa9bf" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A7XX-" usage="rp_blit"/> 3122 5253 3123 5254 <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/> 3124 5255 <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> ··· 3126 5257 <!-- TODO: valid bits 0x3c3f, see kernel --> 3127 5258 </reg32> 3128 5259 <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/> 3129 3129 - <reg32 offset="0xae04" name="SP_FLOAT_CNTL" usage="cmd"> 5260 5260 + <reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="cmd"> 3130 5261 <bitfield name="F16_NO_INF" pos="3" type="boolean"/> 3131 5262 </reg32> 3132 5263 3133 5264 <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/> 3134 3134 - <reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/> 3135 3135 - <reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/> 3136 3136 - <reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/> 5265 5265 + <reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="cmd"/> 5266 5266 + <reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="cmd"/> 5267 5267 + <reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="cmd"/> 3137 5268 3138 3138 - <reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE" usage="cmd"> 5269 5269 + <reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="cmd"> 3139 5270 <!-- some perfcntrs are affected by a per-stage enable bit 3140 5271 (PERF_SP_ALU_WORKING_CYCLES for example) 3141 5272 TODO: verify position of HS/DS/GS bits --> ··· 3150 5281 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/> 3151 5282 <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/> 3152 5283 <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/> 3153 3153 - <reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/> 5284 5284 + <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 3154 5285 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> 3155 5286 <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/> 3156 5287 <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/> ··· 3170 5301 "a6xx_sp_ps_tp_cluster" but this actually specifies the border 3171 5302 color base for compute shaders. 3172 5303 --> 3173 3173 - <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/> 5304 5304 + <reg64 offset="0xb180" name="TPL1_CS_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 3174 5305 <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/> 3175 5306 <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/> 3176 5307 3177 5308 <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/> 3178 5309 <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/> 3179 5310 3180 3180 - <!-- could be all the stuff below here is actually TPL1?? --> 3181 3181 - 3182 3182 - <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL" usage="rp_blit"> 5311 5311 + <reg32 offset="0xb300" name="TPL1_RAS_MSAA_CNTL" usage="rp_blit"> 3183 5312 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 3184 5313 <bitfield name="UNK2" low="2" high="3"/> 3185 5314 </reg32> 3186 3186 - <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL" usage="rp_blit"> 5315 5315 + <reg32 offset="0xb301" name="TPL1_DEST_MSAA_CNTL" usage="rp_blit"> 3187 5316 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 3188 5317 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 3189 5318 </reg32> 3190 5319 3191 5320 <!-- looks to work in the same way as a5xx: --> 3192 3192 - <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/> 3193 3193 - <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> 3194 3194 - <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> 3195 3195 - <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> 3196 3196 - <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 3197 3197 - <reg32 offset="0xb309" name="SP_TP_MODE_CNTL" usage="cmd"> 5321 5321 + <reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 5322 5322 + <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 5323 5323 + <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 5324 5324 + <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 5325 5325 + <reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 5326 5326 + 5327 5327 + <enum name="a6xx_coord_round"> 5328 5328 + <value value="0" name="COORD_TRUNCATE"/> 5329 5329 + <value value="1" name="COORD_ROUND_NEAREST_EVEN"/> 5330 5330 + </enum> 5331 5331 + 5332 5332 + <enum name="a6xx_nearest_mode"> 5333 5333 + <value value="0" name="ROUND_CLAMP_TRUNCATE"/> 5334 5334 + <value value="1" name="CLAMP_ROUND_TRUNCATE"/> 5335 5335 + </enum> 5336 5336 + 5337 5337 + <reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd"> 3198 5338 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/> 3199 3199 - <bitfield name="UNK3" low="2" high="7"/> 5339 5339 + <bitfield name="TEXCOORDROUNDMODE" pos="2" type="a6xx_coord_round"/> 5340 5340 + <bitfield name="NEARESTMIPSNAP" pos="5" type="a6xx_nearest_mode"/> 5341 5341 + <bitfield name="DESTDATATYPEOVERRIDE" pos="7" type="boolean"/> 3200 5342 </reg32> 3201 5343 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/> 3202 5344 ··· 3216 5336 badly named or the functionality moved in a6xx. But downstream kernel 3217 5337 calls this "a6xx_sp_ps_tp_2d_cluster" 3218 5338 --> 3219 3219 - <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A6XX" usage="rp_blit"/> 3220 3220 - <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE" variants="A6XX" usage="rp_blit"> 5339 5339 + <reg32 offset="0xb4c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A6XX" usage="rp_blit"/> 5340 5340 + <reg32 offset="0xb4c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A6XX" usage="rp_blit"> 3221 5341 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3222 5342 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3223 5343 </reg32> 3224 3224 - <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A6XX" usage="rp_blit"/> 3225 3225 - <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH" variants="A6XX" usage="rp_blit"> 5344 5344 + <reg64 offset="0xb4c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A6XX" usage="rp_blit"/> 5345 5345 + <reg32 offset="0xb4c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A6XX" usage="rp_blit"> 3226 5346 <bitfield name="UNK0" low="0" high="8"/> 3227 5347 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> 3228 5348 </reg32> 3229 5349 3230 3230 - <reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A7XX-" usage="rp_blit"/> 3231 3231 - <reg32 offset="0xb2c1" name="SP_PS_2D_SRC_SIZE" variants="A7XX"> 5350 5350 + <reg32 offset="0xb2c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A7XX-" usage="rp_blit"/> 5351 5351 + <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX"> 3232 5352 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3233 5353 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3234 5354 </reg32> 3235 3235 - <reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 3236 3236 - <reg32 offset="0xb2c4" name="SP_PS_2D_SRC_PITCH" variants="A7XX"> 3237 3237 - <bitfield name="UNK0" low="0" high="8"/> 3238 3238 - <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> 5355 5355 + <reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 5356 5356 + <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX"> 5357 5357 + <!-- 5358 5358 + Bits from 3..9 must be zero unless 'TPL1_A2D_BLT_CNTL::TYPE' 5359 5359 + is A6XX_TEX_IMG_BUFFER, which allows for lower alignment. 5360 5360 + --> 5361 5361 + <bitfield name="PITCH" low="3" high="23" type="uint"/> 3239 5362 </reg32> 3240 5363 3241 5364 <!-- planes for NV12, etc. (TODO: not tested) --> 3242 3242 - <reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A6XX"/> 3243 3243 - <reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A6XX"/> 3244 3244 - <reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A6XX"/> 5365 5365 + <reg64 offset="0xb4c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A6XX"/> 5366 5366 + <reg32 offset="0xb4c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A6XX"/> 5367 5367 + <reg64 offset="0xb4c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A6XX"/> 3245 5368 3246 3246 - <reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/> 3247 3247 - <reg32 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/> 3248 3248 - <reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/> 5369 5369 + <reg64 offset="0xb2c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A7XX-"/> 5370 5370 + <reg32 offset="0xb2c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A7XX-"/> 5371 5371 + <reg64 offset="0xb2c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A7XX-"/> 3249 5372 3250 3250 - <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A6XX" usage="rp_blit"/> 3251 3251 - <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/> 5373 5373 + <reg64 offset="0xb4ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A6XX" usage="rp_blit"/> 5374 5374 + <reg32 offset="0xb4cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/> 3252 5375 3253 3253 - <reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 3254 3254 - <reg32 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/> 5376 5376 + <reg64 offset="0xb2ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 5377 5377 + <reg32 offset="0xb2cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/> 3255 5378 3256 5379 <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/> 3257 5380 <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/> ··· 3266 5383 <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/> 3267 5384 <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/> 3268 5385 <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/> 3269 3269 - <reg32 offset="0xb2d1" name="SP_PS_2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/> 3270 3270 - <reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/> 5386 5386 + <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/> 5387 5387 + <reg32 offset="0xb2d2" name="TPL1_A2D_BLT_CNTL" variants="A7XX-" usage="rp_blit"> 5388 5388 + <bitfield name="RAW_COPY" pos="0" type="boolean"/> 5389 5389 + <bitfield name="START_OFFSET_TEXELS" low="16" high="21"/> 5390 5390 + <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 5391 5391 + </reg32> 3271 5392 <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/> 3272 5393 3273 5394 <!-- always 0x100000 or 0x1000000? --> ··· 3309 5422 3310 5423 <!-- TODO: 4 more perfcntr sel at 0xb620 ? --> 3311 5424 3312 3312 - <bitset name="a6xx_hlsq_xs_cntl" inline="yes"> 5425 5425 + <bitset name="a6xx_xs_const_config" inline="yes"> 3313 5426 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/> 3314 5427 <bitfield name="ENABLED" pos="8" type="boolean"/> 3315 5428 <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/> 3316 5429 </bitset> 3317 5430 3318 3318 - <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 3319 3319 - <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 3320 3320 - <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 3321 3321 - <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 5431 5431 + <reg32 offset="0xb800" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 5432 5432 + <reg32 offset="0xb801" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 5433 5433 + <reg32 offset="0xb802" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 5434 5434 + <reg32 offset="0xb803" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 3322 5435 3323 3323 - <reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 3324 3324 - <reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 3325 3325 - <reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 3326 3326 - <reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 5436 5436 + <reg32 offset="0xa827" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 5437 5437 + <reg32 offset="0xa83f" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 5438 5438 + <reg32 offset="0xa867" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 5439 5439 + <reg32 offset="0xa898" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3327 5440 3328 3328 - <reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit"> 3329 3329 - <!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG --> 3330 3330 - <bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/> 5441 5441 + <reg32 offset="0xa9aa" name="SP_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 5442 5442 + <bitfield name="FS_DISABLE" pos="0" type="boolean"/> 3331 5443 </reg32> 3332 5444 3333 3333 - <!-- Always 0 --> 3334 3334 - <reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/> 5445 5445 + <reg32 offset="0xa9ac" name="SP_DITHER_CNTL" variants="A7XX-" usage="cmd"> 5446 5446 + <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 5447 5447 + <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 5448 5448 + <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 5449 5449 + <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 5450 5450 + <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 5451 5451 + <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 5452 5452 + <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> 5453 5453 + <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 5454 5454 + </reg32> 3335 5455 3336 3336 - <!-- Used in VK_KHR_fragment_shading_rate --> 3337 3337 - <reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/> 5456 5456 + <reg32 offset="0xa9ad" name="SP_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> 5457 5457 + <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 5458 5458 + <bitfield name="ATTACHMENT_FSR_ENABLE" pos="1" type="boolean"/> 5459 5459 + <bitfield name="PRIMITIVE_FSR_ENABLE" pos="3" type="boolean"/> 5460 5460 + </reg32> 3338 5461 3339 3339 - <reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit"> 5462 5462 + <reg32 offset="0xa9ae" name="SP_PS_CNTL_1" variants="A7XX-" usage="rp_blit"> 3340 5463 <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/> 3341 5464 <!-- UNK8 is set on a730/a740 --> 3342 5465 <bitfield name="UNK8" pos="8" type="boolean"/> ··· 3359 5462 <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/> 3360 5463 3361 5464 3362 3362 - <bitset name="a6xx_hlsq_fs_cntl_0" inline="yes"> 5465 5465 + <bitset name="a6xx_sp_ps_wave_cntl" inline="yes"> 3363 5466 <!-- must match SP_FS_CTRL --> 3364 5467 <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/> 3365 5468 <bitfield name="VARYINGS" pos="1" type="boolean"/> 3366 5469 <bitfield name="UNK2" low="2" high="11"/> 3367 5470 </bitset> 3368 3368 - <bitset name="a6xx_hlsq_control_3_reg" inline="yes"> 5471 5471 + <bitset name="a6xx_sp_reg_prog_id_1" inline="yes"> 3369 5472 <!-- register loaded with position (bary.f) --> 3370 5473 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/> 3371 5474 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/> 3372 5475 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/> 3373 5476 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/> 3374 5477 </bitset> 3375 3375 - <bitset name="a6xx_hlsq_control_4_reg" inline="yes"> 5478 5478 + <bitset name="a6xx_sp_reg_prog_id_2" inline="yes"> 3376 5479 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/> 3377 5480 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/> 3378 5481 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> 3379 5482 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> 3380 5483 </bitset> 3381 3381 - <bitset name="a6xx_hlsq_control_5_reg" inline="yes"> 5484 5484 + <bitset name="a6xx_sp_reg_prog_id_3" inline="yes"> 3382 5485 <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/> 3383 5486 <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/> 3384 5487 </bitset> 3385 5488 3386 3386 - <reg32 offset="0xb980" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A6XX" usage="rp_blit"/> 5489 5489 + <reg32 offset="0xb980" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A6XX" usage="rp_blit"/> 3387 5490 <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob --> 3388 3388 - <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit"> 5491 5491 + <reg32 offset="0xb982" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A6XX" usage="rp_blit"> 3389 5492 <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the 3390 5493 A3xx field, except that it's not necessary to set it to anything but the maximum, since 3391 5494 the hardware will simply emit smaller waves when it runs out of space. --> 3392 5495 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 3393 5496 </reg32> 3394 3394 - <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX" usage="rp_blit"> 5497 5497 + <reg32 offset="0xb983" name="SP_REG_PROG_ID_0" variants="A6XX" usage="rp_blit"> 3395 5498 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 3396 5499 <!-- SAMPLEID is loaded into a half-precision register: --> 3397 5500 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 3398 5501 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 3399 5502 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 3400 5503 </reg32> 3401 3401 - <reg32 offset="0xb984" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A6XX" usage="rp_blit"/> 3402 3402 - <reg32 offset="0xb985" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A6XX" usage="rp_blit"/> 3403 3403 - <reg32 offset="0xb986" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A6XX" usage="rp_blit"/> 3404 3404 - <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="cmd"/> 3405 3405 - <reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp_blit"/> 3406 3406 - <reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit"> 5504 5504 + <reg32 offset="0xb984" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A6XX" usage="rp_blit"/> 5505 5505 + <reg32 offset="0xb985" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A6XX" usage="rp_blit"/> 5506 5506 + <reg32 offset="0xb986" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A6XX" usage="rp_blit"/> 5507 5507 + <reg32 offset="0xb987" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="cmd"/> 5508 5508 + <reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX-" usage="rp_blit"/> 5509 5509 + <reg32 offset="0xa9c7" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A7XX-" usage="rp_blit"> 3407 5510 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 3408 5511 </reg32> 3409 3409 - <reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit"> 5512 5512 + <reg32 offset="0xa9c8" name="SP_REG_PROG_ID_0" variants="A7XX-" usage="rp_blit"> 3410 5513 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 3411 5514 <!-- SAMPLEID is loaded into a half-precision register: --> 3412 5515 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 3413 5516 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 3414 5517 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 3415 5518 </reg32> 3416 3416 - <reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" usage="rp_blit"/> 3417 3417 - <reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" usage="rp_blit"/> 3418 3418 - <reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" usage="rp_blit"/> 3419 3419 - <reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/> 5519 5519 + <reg32 offset="0xa9c9" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A7XX-" usage="rp_blit"/> 5520 5520 + <reg32 offset="0xa9ca" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A7XX-" usage="rp_blit"/> 5521 5521 + <reg32 offset="0xa9cb" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A7XX-" usage="rp_blit"/> 5522 5522 + <reg32 offset="0xa9cd" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="cmd"/> 3420 5523 3421 5524 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 3422 3422 - <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0" variants="A6XX" usage="rp_blit"> 5525 5525 + <reg32 offset="0xb990" name="SP_CS_NDRANGE_0" variants="A6XX" usage="rp_blit"> 3423 5526 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 3424 5527 <!-- localsize is value minus one: --> 3425 5528 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 3426 5529 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 3427 5530 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 3428 5531 </reg32> 3429 3429 - <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1" variants="A6XX" usage="rp_blit"> 5532 5532 + <reg32 offset="0xb991" name="SP_CS_NDRANGE_1" variants="A6XX" usage="rp_blit"> 3430 5533 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 3431 5534 </reg32> 3432 3432 - <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2" variants="A6XX" usage="rp_blit"> 5535 5535 + <reg32 offset="0xb992" name="SP_CS_NDRANGE_2" variants="A6XX" usage="rp_blit"> 3433 5536 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 3434 5537 </reg32> 3435 3435 - <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3" variants="A6XX" usage="rp_blit"> 5538 5538 + <reg32 offset="0xb993" name="SP_CS_NDRANGE_3" variants="A6XX" usage="rp_blit"> 3436 5539 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 3437 5540 </reg32> 3438 3438 - <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4" variants="A6XX" usage="rp_blit"> 5541 5541 + <reg32 offset="0xb994" name="SP_CS_NDRANGE_4" variants="A6XX" usage="rp_blit"> 3439 5542 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 3440 5543 </reg32> 3441 3441 - <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5" variants="A6XX" usage="rp_blit"> 5544 5544 + <reg32 offset="0xb995" name="SP_CS_NDRANGE_5" variants="A6XX" usage="rp_blit"> 3442 5545 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 3443 5546 </reg32> 3444 3444 - <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6" variants="A6XX" usage="rp_blit"> 5547 5547 + <reg32 offset="0xb996" name="SP_CS_NDRANGE_6" variants="A6XX" usage="rp_blit"> 3445 5548 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 3446 5549 </reg32> 3447 3447 - <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0" variants="A6XX" usage="rp_blit"> 5550 5550 + <reg32 offset="0xb997" name="SP_CS_CONST_CONFIG_0" variants="A6XX" usage="rp_blit"> 3448 5551 <!-- these are all vec3. first 3 need to be high regs 3449 3449 - WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0) 5552 5552 + WGSIZECONSTID is the local size (from SP_CS_NDRANGE_0) 3450 5553 WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID 3451 5554 --> 3452 5555 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> ··· 3454 5557 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 3455 5558 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 3456 5559 </reg32> 3457 3457 - <reg32 offset="0xb998" name="HLSQ_CS_CNTL_1" variants="A6XX" usage="rp_blit"> 5560 5560 + <reg32 offset="0xb998" name="SP_CS_WGE_CNTL" variants="A6XX" usage="rp_blit"> 3458 5561 <!-- gl_LocalInvocationIndex --> 3459 5562 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 3460 5563 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only ··· 3466 5569 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 3467 5570 </reg32> 3468 5571 <!--note: vulkan blob doesn't use these --> 3469 3469 - <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/> 3470 3470 - <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/> 3471 3471 - <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/> 5572 5572 + <reg32 offset="0xb999" name="SP_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/> 5573 5573 + <reg32 offset="0xb99a" name="SP_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/> 5574 5574 + <reg32 offset="0xb99b" name="SP_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/> 3472 5575 3473 5576 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 3474 3474 - <reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit"> 5577 5577 + <reg32 offset="0xa9d4" name="SP_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit"> 3475 5578 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 3476 5579 <!-- localsize is value minus one: --> 3477 5580 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 3478 5581 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 3479 5582 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 3480 5583 </reg32> 3481 3481 - <reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit"> 5584 5584 + <reg32 offset="0xa9d5" name="SP_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit"> 3482 5585 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 3483 5586 </reg32> 3484 3484 - <reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit"> 5587 5587 + <reg32 offset="0xa9d6" name="SP_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit"> 3485 5588 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 3486 5589 </reg32> 3487 3487 - <reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit"> 5590 5590 + <reg32 offset="0xa9d7" name="SP_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit"> 3488 5591 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 3489 5592 </reg32> 3490 3490 - <reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit"> 5593 5593 + <reg32 offset="0xa9d8" name="SP_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit"> 3491 5594 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 3492 5595 </reg32> 3493 3493 - <reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit"> 5596 5596 + <reg32 offset="0xa9d9" name="SP_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit"> 3494 5597 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 3495 5598 </reg32> 3496 3496 - <reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit"> 5599 5599 + <reg32 offset="0xa9da" name="SP_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit"> 3497 5600 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 3498 5601 </reg32> 3499 5602 <!--note: vulkan blob doesn't use these --> 3500 3500 - <reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/> 3501 3501 - <reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/> 3502 3502 - <reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/> 5603 5603 + <reg32 offset="0xa9dc" name="SP_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/> 5604 5604 + <reg32 offset="0xa9dd" name="SP_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/> 5605 5605 + <reg32 offset="0xa9de" name="SP_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/> 3503 5606 3504 5607 <enum name="a7xx_cs_yalign"> 3505 5608 <value name="CS_YALIGN_1" value="8"/> ··· 3508 5611 <value name="CS_YALIGN_8" value="1"/> 3509 5612 </enum> 3510 5613 3511 3511 - <reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit"> 5614 5614 + <reg32 offset="0xa9db" name="SP_CS_WGE_CNTL" variants="A7XX-" usage="rp_blit"> 3512 5615 <!-- gl_LocalInvocationIndex --> 3513 5616 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 3514 5617 <!-- Must match SP_CS_CTRL --> 3515 5618 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 3516 3516 - <bitfield name="UNK11" pos="11" type="boolean"/> 3517 3517 - <bitfield name="UNK22" pos="22" type="boolean"/> 3518 3518 - <bitfield name="UNK26" pos="26" type="boolean"/> 3519 3519 - <bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/> 5619 5619 + <doc> 5620 5620 + When this bit is enabled, the dispatch order interleaves 5621 5621 + the z coordinate instead of launching all workgroups 5622 5622 + with z=0, then all with z=1 and so on. 5623 5623 + </doc> 5624 5624 + <bitfield name="WORKGROUPRASTORDERZFIRSTEN" pos="11" type="boolean"/> 5625 5625 + <doc> 5626 5626 + When both fields are non-0 then the dispatcher uses 5627 5627 + these tile sizes to launch workgroups in a tiled manner 5628 5628 + when the x and y workgroup counts are 5629 5629 + both more than 1. 5630 5630 + </doc> 5631 5631 + <bitfield name="WGTILEWIDTH" low="20" high="25"/> 5632 5632 + <bitfield name="WGTILEHEIGHT" low="26" high="31"/> 3520 5633 </reg32> 3521 5634 3522 3522 - <reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd"> 3523 3523 - <!-- localsize is value minus one: --> 5635 5635 + <reg32 offset="0xa9df" name="SP_CS_NDRANGE_7" variants="A7XX-" usage="cmd"> 5636 5636 + <!-- The size of the last workgroup. localsize is value minus one: --> 3524 5637 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 3525 5638 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 3526 5639 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> ··· 3548 5641 </reg64> 3549 5642 </array> 3550 5643 3551 3551 - <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? --> 3552 3552 - <reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0" variants="A6XX" usage="cmd"> 5644 5644 + <!-- new in a6xx gen4, mirror of SP_CS_CNTL_1? --> 5645 5645 + <reg32 offset="0xb9d0" name="HLSQ_CS_CTRL_REG1" variants="A6XX" usage="cmd"> 3553 5646 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/> 3554 3554 - <bitfield name="UNK5" pos="5" type="boolean"/> 3555 3555 - <!-- always 1 ? --> 3556 3556 - <bitfield name="UNK6" pos="6" type="boolean"/> 5647 5647 + <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"/> 3557 5648 </reg32> 3558 5649 3559 3559 - <reg32 offset="0xbb00" name="HLSQ_DRAW_CMD" variants="A6XX"> 5650 5650 + <reg32 offset="0xbb00" name="SP_DRAW_INITIATOR" variants="A6XX"> 3560 5651 <bitfield name="STATE_ID" low="0" high="7"/> 3561 5652 </reg32> 3562 5653 3563 3563 - <reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD" variants="A6XX"> 5654 5654 + <reg32 offset="0xbb01" name="SP_KERNEL_INITIATOR" variants="A6XX"> 3564 5655 <bitfield name="STATE_ID" low="0" high="7"/> 3565 5656 </reg32> 3566 5657 3567 3567 - <reg32 offset="0xbb02" name="HLSQ_EVENT_CMD" variants="A6XX"> 5658 5658 + <reg32 offset="0xbb02" name="SP_EVENT_INITIATOR" variants="A6XX"> 3568 5659 <!-- I think only the low bit is actually used? --> 3569 5660 <bitfield name="STATE_ID" low="16" high="23"/> 3570 5661 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3571 5662 </reg32> 3572 5663 3573 3573 - <reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD" variants="A6XX" usage="cmd"> 5664 5664 + <reg32 offset="0xbb08" name="SP_UPDATE_CNTL" variants="A6XX" usage="cmd"> 3574 5665 <doc> 3575 5666 This register clears pending loads queued up by 3576 5667 CP_LOAD_STATE6. Each bit resets a particular kind(s) of ··· 3583 5678 <bitfield name="FS_STATE" pos="4" type="boolean"/> 3584 5679 <bitfield name="CS_STATE" pos="5" type="boolean"/> 3585 5680 3586 3586 - <bitfield name="CS_IBO" pos="6" type="boolean"/> 3587 3587 - <bitfield name="GFX_IBO" pos="7" type="boolean"/> 5681 5681 + <bitfield name="CS_UAV" pos="6" type="boolean"/> 5682 5682 + <bitfield name="GFX_UAV" pos="7" type="boolean"/> 3588 5683 3589 5684 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 --> 3590 5685 <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/> ··· 3595 5690 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/> 3596 5691 </reg32> 3597 5692 3598 3598 - <reg32 offset="0xab1c" name="HLSQ_DRAW_CMD" variants="A7XX-"> 5693 5693 + <reg32 offset="0xab1c" name="SP_DRAW_INITIATOR" variants="A7XX-"> 3599 5694 <bitfield name="STATE_ID" low="0" high="7"/> 3600 5695 </reg32> 3601 5696 3602 3602 - <reg32 offset="0xab1d" name="HLSQ_DISPATCH_CMD" variants="A7XX-"> 5697 5697 + <reg32 offset="0xab1d" name="SP_KERNEL_INITIATOR" variants="A7XX-"> 3603 5698 <bitfield name="STATE_ID" low="0" high="7"/> 3604 5699 </reg32> 3605 5700 3606 3606 - <reg32 offset="0xab1e" name="HLSQ_EVENT_CMD" variants="A7XX-"> 5701 5701 + <reg32 offset="0xab1e" name="SP_EVENT_INITIATOR" variants="A7XX-"> 3607 5702 <bitfield name="STATE_ID" low="16" high="23"/> 3608 5703 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3609 5704 </reg32> 3610 5705 3611 3611 - <reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd"> 5706 5706 + <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX-" usage="cmd"> 3612 5707 <doc> 3613 5708 This register clears pending loads queued up by 3614 5709 CP_LOAD_STATE6. Each bit resets a particular kind(s) of ··· 3623 5718 <bitfield name="FS_STATE" pos="4" type="boolean"/> 3624 5719 <bitfield name="CS_STATE" pos="5" type="boolean"/> 3625 5720 3626 3626 - <bitfield name="CS_IBO" pos="6" type="boolean"/> 3627 3627 - <bitfield name="GFX_IBO" pos="7" type="boolean"/> 5721 5721 + <bitfield name="CS_UAV" pos="6" type="boolean"/> 5722 5722 + <bitfield name="GFX_UAV" pos="7" type="boolean"/> 3628 5723 3629 5724 <!-- SS6_BINDLESS: one bit per bindless base --> 3630 5725 <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/> 3631 5726 <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/> 3632 5727 </reg32> 3633 5728 3634 3634 - <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 3635 3635 - <reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 5729 5729 + <reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 5730 5730 + <reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3636 5731 3637 3637 - <array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/> 5732 5732 + <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX_0" stride="1" length="64" variants="A7XX-"/> 3638 5733 3639 5734 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd"> 3640 5735 <doc> ··· 3643 5738 const pool and 16 in the geometry const pool although 3644 5739 only 8 are actually used (why?) and they are mapped to 3645 5740 c504-c511 in each stage. Both VS and FS shared consts 3646 3646 - are written using ST6_CONSTANTS/SB6_IBO, so that both 5741 5741 + are written using ST6_CONSTANTS/SB6_UAV, so that both 3647 5742 the geometry and FS shared consts can be written at once 3648 5743 by using CP_LOAD_STATE6 rather than 3649 5744 CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition ··· 3652 5747 3653 5748 There is also a separate shared constant pool for CS, 3654 5749 which is loaded through CP_LOAD_STATE6_FRAG with 3655 3655 - ST6_UBO/ST6_IBO. However the only real difference for CS 5750 5750 + ST6_UBO/ST6_UAV. However the only real difference for CS 3656 5751 is the dword units. 3657 5752 </doc> 3658 5753 <bitfield name="ENABLE" pos="0" type="boolean"/> 3659 5754 </reg32> 3660 5755 3661 3661 - <!-- mirror of SP_BINDLESS_BASE --> 5756 5756 + <!-- mirror of SP_GFX_BINDLESS_BASE --> 3662 5757 <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> 3663 5758 <reg64 offset="0" name="DESCRIPTOR"> 3664 5759 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> ··· 3693 5788 sequence. The sequence used internally for an event looks like: 3694 5789 - write EVENT_CMD pipe register 3695 5790 - write CP_EVENT_START 3696 3696 - - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD 3697 3697 - - write PC_EVENT_CMD with event or PC_DRAW_CMD 3698 3698 - - write HLSQ_EVENT_CMD(CONTEXT_DONE) 3699 3699 - - write PC_EVENT_CMD(CONTEXT_DONE) 5791 5791 + - write SP_EVENT_INITIATOR with event or SP_DRAW_INITIATOR 5792 5792 + - write PC_EVENT_INITIATOR with event or PC_DRAW_INITIATOR 5793 5793 + - write SP_EVENT_INITIATOR(CONTEXT_DONE) 5794 5794 + - write PC_EVENT_INITIATOR(CONTEXT_DONE) 3700 5795 - write CP_EVENT_END 3701 5796 Writing to CP_EVENT_END seems to actually trigger the context roll 3702 5797 --> ··· 3711 5806 </reg32> 3712 5807 <reg32 offset="0xd701" name="CP_2D_EVENT_END"> 3713 5808 <bitfield name="STATE_ID" low="0" high="7"/> 3714 3714 - </reg32> 3715 3715 - </domain> 3716 3716 - 3717 3717 - <!-- Seems basically the same as a5xx, maybe move to common.xml.. --> 3718 3718 - <domain name="A6XX_TEX_SAMP" width="32"> 3719 3719 - <doc>Texture sampler dwords</doc> 3720 3720 - <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> 3721 3721 - <value name="A6XX_TEX_NEAREST" value="0"/> 3722 3722 - <value name="A6XX_TEX_LINEAR" value="1"/> 3723 3723 - <value name="A6XX_TEX_ANISO" value="2"/> 3724 3724 - <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> 3725 3725 - </enum> 3726 3726 - <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> 3727 3727 - <value name="A6XX_TEX_REPEAT" value="0"/> 3728 3728 - <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> 3729 3729 - <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> 3730 3730 - <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> 3731 3731 - <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> 3732 3732 - </enum> 3733 3733 - <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> 3734 3734 - <value name="A6XX_TEX_ANISO_1" value="0"/> 3735 3735 - <value name="A6XX_TEX_ANISO_2" value="1"/> 3736 3736 - <value name="A6XX_TEX_ANISO_4" value="2"/> 3737 3737 - <value name="A6XX_TEX_ANISO_8" value="3"/> 3738 3738 - <value name="A6XX_TEX_ANISO_16" value="4"/> 3739 3739 - </enum> 3740 3740 - <enum name="a6xx_reduction_mode"> 3741 3741 - <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> 3742 3742 - <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> 3743 3743 - <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> 3744 3744 - </enum> 3745 3745 - 3746 3746 - <reg32 offset="0" name="0"> 3747 3747 - <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> 3748 3748 - <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/> 3749 3749 - <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/> 3750 3750 - <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/> 3751 3751 - <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/> 3752 3752 - <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/> 3753 3753 - <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/> 3754 3754 - <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> 3755 3755 - </reg32> 3756 3756 - <reg32 offset="1" name="1"> 3757 3757 - <bitfield name="CLAMPENABLE" pos="0" type="boolean"> 3758 3758 - <doc> 3759 3759 - clamp result to [0, 1] if the format is unorm or 3760 3760 - [-1, 1] if the format is snorm, *after* 3761 3761 - filtering. Has no effect for other formats. 3762 3762 - </doc> 3763 3763 - </bitfield> 3764 3764 - <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> 3765 3765 - <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> 3766 3766 - <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> 3767 3767 - <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> 3768 3768 - <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> 3769 3769 - <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> 3770 3770 - </reg32> 3771 3771 - <reg32 offset="2" name="2"> 3772 3772 - <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/> 3773 3773 - <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/> 3774 3774 - <bitfield name="BCOLOR" low="7" high="31"/> 3775 3775 - </reg32> 3776 3776 - <reg32 offset="3" name="3"/> 3777 3777 - </domain> 3778 3778 - 3779 3779 - <domain name="A6XX_TEX_CONST" width="32" varset="chip"> 3780 3780 - <doc>Texture constant dwords</doc> 3781 3781 - <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> 3782 3782 - <value name="A6XX_TEX_X" value="0"/> 3783 3783 - <value name="A6XX_TEX_Y" value="1"/> 3784 3784 - <value name="A6XX_TEX_Z" value="2"/> 3785 3785 - <value name="A6XX_TEX_W" value="3"/> 3786 3786 - <value name="A6XX_TEX_ZERO" value="4"/> 3787 3787 - <value name="A6XX_TEX_ONE" value="5"/> 3788 3788 - </enum> 3789 3789 - <enum name="a6xx_tex_type"> <!-- same as a4xx? --> 3790 3790 - <value name="A6XX_TEX_1D" value="0"/> 3791 3791 - <value name="A6XX_TEX_2D" value="1"/> 3792 3792 - <value name="A6XX_TEX_CUBE" value="2"/> 3793 3793 - <value name="A6XX_TEX_3D" value="3"/> 3794 3794 - <value name="A6XX_TEX_BUFFER" value="4"/> 3795 3795 - </enum> 3796 3796 - <reg32 offset="0" name="0"> 3797 3797 - <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 3798 3798 - <bitfield name="SRGB" pos="2" type="boolean"/> 3799 3799 - <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/> 3800 3800 - <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/> 3801 3801 - <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/> 3802 3802 - <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/> 3803 3803 - <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> 3804 3804 - <!-- overlaps with MIPLVLS --> 3805 3805 - <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/> 3806 3806 - <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/> 3807 3807 - <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/> 3808 3808 - <bitfield name="FMT" low="22" high="29" type="a6xx_format"/> 3809 3809 - <!-- 3810 3810 - Why is the swap needed in addition to SWIZ_*? The swap 3811 3811 - is performed before border color replacement, while the 3812 3812 - swizzle is applied after after it. 3813 3813 - --> 3814 3814 - <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> 3815 3815 - </reg32> 3816 3816 - <reg32 offset="1" name="1"> 3817 3817 - <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3818 3818 - <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3819 3819 - <bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/> 3820 3820 - </reg32> 3821 3821 - <reg32 offset="2" name="2"> 3822 3822 - <!-- 3823 3823 - These fields overlap PITCH, and are used instead of 3824 3824 - PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER. 3825 3825 - --> 3826 3826 - <doc> probably for D3D structured UAVs, normally set to 1 </doc> 3827 3827 - <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/> 3828 3828 - <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/> 3829 3829 - 3830 3830 - <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) --> 3831 3831 - <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/> 3832 3832 - <doc>Pitch in bytes (so actually stride)</doc> 3833 3833 - <bitfield name="PITCH" low="7" high="28" type="uint"/> 3834 3834 - <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 3835 3835 - </reg32> 3836 3836 - <reg32 offset="3" name="3"> 3837 3837 - <!-- 3838 3838 - ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and 3839 3839 - for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the 3840 3840 - layer size at the point that it stops being reduced moving to 3841 3841 - higher (smaller) mipmap levels 3842 3842 - --> 3843 3843 - <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/> 3844 3844 - <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> 3845 3845 - <!-- 3846 3846 - by default levels with w < 16 are linear 3847 3847 - TILE_ALL makes all levels have tiling 3848 3848 - seems required when using UBWC, since all levels have UBWC (can possibly be disabled?) 3849 3849 - --> 3850 3850 - <bitfield name="TILE_ALL" pos="27" type="boolean"/> 3851 3851 - <bitfield name="FLAG" pos="28" type="boolean"/> 3852 3852 - </reg32> 3853 3853 - <!-- for 2-3 plane format, BASE is flag buffer address (if enabled) 3854 3854 - the address of the non-flag base buffer is determined automatically, 3855 3855 - and must follow the flag buffer 3856 3856 - --> 3857 3857 - <reg32 offset="4" name="4"> 3858 3858 - <bitfield name="BASE_LO" low="5" high="31" shr="5"/> 3859 3859 - </reg32> 3860 3860 - <reg32 offset="5" name="5"> 3861 3861 - <bitfield name="BASE_HI" low="0" high="16"/> 3862 3862 - <bitfield name="DEPTH" low="17" high="29" type="uint"/> 3863 3863 - </reg32> 3864 3864 - <reg32 offset="6" name="6"> 3865 3865 - <!-- overlaps with PLANE_PITCH --> 3866 3866 - <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/> 3867 3867 - <!-- pitch for plane 2 / plane 3 --> 3868 3868 - <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/> 3869 3869 - </reg32> 3870 3870 - <!-- 7/8 is plane 2 address for planar formats --> 3871 3871 - <reg32 offset="7" name="7"> 3872 3872 - <bitfield name="FLAG_LO" low="5" high="31" shr="5"/> 3873 3873 - </reg32> 3874 3874 - <reg32 offset="8" name="8"> 3875 3875 - <bitfield name="FLAG_HI" low="0" high="16"/> 3876 3876 - </reg32> 3877 3877 - <!-- 9/10 is plane 3 address for planar formats --> 3878 3878 - <reg32 offset="9" name="9"> 3879 3879 - <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> 3880 3880 - </reg32> 3881 3881 - <reg32 offset="10" name="10"> 3882 3882 - <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> 3883 3883 - <!-- log2 size of the first level, required for mipmapping --> 3884 3884 - <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/> 3885 3885 - <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/> 3886 3886 - </reg32> 3887 3887 - <reg32 offset="11" name="11"/> 3888 3888 - <reg32 offset="12" name="12"/> 3889 3889 - <reg32 offset="13" name="13"/> 3890 3890 - <reg32 offset="14" name="14"/> 3891 3891 - <reg32 offset="15" name="15"/> 3892 3892 - </domain> 3893 3893 - 3894 3894 - <domain name="A6XX_UBO" width="32"> 3895 3895 - <reg32 offset="0" name="0"> 3896 3896 - <bitfield name="BASE_LO" low="0" high="31"/> 3897 3897 - </reg32> 3898 3898 - <reg32 offset="1" name="1"> 3899 3899 - <bitfield name="BASE_HI" low="0" high="16"/> 3900 3900 - <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units --> 3901 5809 </reg32> 3902 5810 </domain> 3903 5811

+198

drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml

reviewed

··· 1 1 + <?xml version="1.0" encoding="UTF-8"?> 2 2 + <database xmlns="http://nouveau.freedesktop.org/" 3 3 + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 4 + xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5 5 + <import file="freedreno_copyright.xml"/> 6 6 + <import file="adreno/adreno_common.xml"/> 7 7 + <import file="adreno/adreno_pm4.xml"/> 8 8 + <import file="adreno/a6xx_enums.xml"/> 9 9 + 10 10 + <domain name="A6XX_TEX_SAMP" width="32"> 11 11 + <doc>Texture sampler dwords</doc> 12 12 + <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> 13 13 + <value name="A6XX_TEX_NEAREST" value="0"/> 14 14 + <value name="A6XX_TEX_LINEAR" value="1"/> 15 15 + <value name="A6XX_TEX_ANISO" value="2"/> 16 16 + <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> 17 17 + </enum> 18 18 + <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> 19 19 + <value name="A6XX_TEX_REPEAT" value="0"/> 20 20 + <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> 21 21 + <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> 22 22 + <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> 23 23 + <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> 24 24 + </enum> 25 25 + <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> 26 26 + <value name="A6XX_TEX_ANISO_1" value="0"/> 27 27 + <value name="A6XX_TEX_ANISO_2" value="1"/> 28 28 + <value name="A6XX_TEX_ANISO_4" value="2"/> 29 29 + <value name="A6XX_TEX_ANISO_8" value="3"/> 30 30 + <value name="A6XX_TEX_ANISO_16" value="4"/> 31 31 + </enum> 32 32 + <enum name="a6xx_reduction_mode"> 33 33 + <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> 34 34 + <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> 35 35 + <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> 36 36 + </enum> 37 37 + <enum name="a6xx_fast_border_color"> 38 38 + <!-- R B G A --> 39 39 + <value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/> 40 40 + <value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/> 41 41 + <value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/> 42 42 + <value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/> 43 43 + </enum> 44 44 + 45 45 + <reg32 offset="0" name="0"> 46 46 + <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> 47 47 + <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/> 48 48 + <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/> 49 49 + <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/> 50 50 + <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/> 51 51 + <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/> 52 52 + <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/> 53 53 + <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> 54 54 + </reg32> 55 55 + <reg32 offset="1" name="1"> 56 56 + <bitfield name="CLAMPENABLE" pos="0" type="boolean"> 57 57 + <doc> 58 58 + clamp result to [0, 1] if the format is unorm or 59 59 + [-1, 1] if the format is snorm, *after* 60 60 + filtering. Has no effect for other formats. 61 61 + </doc> 62 62 + </bitfield> 63 63 + <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> 64 64 + <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> 65 65 + <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> 66 66 + <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> 67 67 + <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> 68 68 + <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> 69 69 + </reg32> 70 70 + <reg32 offset="2" name="2"> 71 71 + <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/> 72 72 + <bitfield name="FASTBORDERCOLOR" low="2" high="3" type="a6xx_fast_border_color"/> 73 73 + <bitfield name="FASTBORDERCOLOREN" pos="4" type="boolean"/> 74 74 + <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/> 75 75 + <bitfield name="BCOLOR" low="7" high="31"/> 76 76 + </reg32> 77 77 + <reg32 offset="3" name="3"/> 78 78 + </domain> 79 79 + 80 80 + <domain name="A6XX_TEX_CONST" width="32" varset="chip"> 81 81 + <doc>Texture constant dwords</doc> 82 82 + <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> 83 83 + <value name="A6XX_TEX_X" value="0"/> 84 84 + <value name="A6XX_TEX_Y" value="1"/> 85 85 + <value name="A6XX_TEX_Z" value="2"/> 86 86 + <value name="A6XX_TEX_W" value="3"/> 87 87 + <value name="A6XX_TEX_ZERO" value="4"/> 88 88 + <value name="A6XX_TEX_ONE" value="5"/> 89 89 + </enum> 90 90 + <reg32 offset="0" name="0"> 91 91 + <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 92 92 + <bitfield name="SRGB" pos="2" type="boolean"/> 93 93 + <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/> 94 94 + <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/> 95 95 + <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/> 96 96 + <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/> 97 97 + <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> 98 98 + <!-- overlaps with MIPLVLS --> 99 99 + <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/> 100 100 + <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/> 101 101 + <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/> 102 102 + <bitfield name="FMT" low="22" high="29" type="a6xx_format"/> 103 103 + <!-- 104 104 + Why is the swap needed in addition to SWIZ_*? The swap 105 105 + is performed before border color replacement, while the 106 106 + swizzle is applied after after it. 107 107 + --> 108 108 + <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> 109 109 + </reg32> 110 110 + <reg32 offset="1" name="1"> 111 111 + <bitfield name="WIDTH" low="0" high="14" type="uint"/> 112 112 + <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 113 113 + <bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/> 114 114 + </reg32> 115 115 + <reg32 offset="2" name="2"> 116 116 + <!-- 117 117 + These fields overlap PITCH, and are used instead of 118 118 + PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER. 119 119 + --> 120 120 + <doc> probably for D3D structured UAVs, normally set to 1 </doc> 121 121 + <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/> 122 122 + <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/> 123 123 + 124 124 + <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) --> 125 125 + <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/> 126 126 + <doc>Pitch in bytes (so actually stride)</doc> 127 127 + <bitfield name="PITCH" low="7" high="28" type="uint"/> 128 128 + <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 129 129 + </reg32> 130 130 + <reg32 offset="3" name="3"> 131 131 + <!-- 132 132 + ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and 133 133 + for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the 134 134 + layer size at the point that it stops being reduced moving to 135 135 + higher (smaller) mipmap levels 136 136 + --> 137 137 + <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/> 138 138 + <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> 139 139 + <!-- 140 140 + by default levels with w < 16 are linear 141 141 + TILE_ALL makes all levels have tiling 142 142 + seems required when using UBWC, since all levels have UBWC (can possibly be disabled?) 143 143 + --> 144 144 + <bitfield name="TILE_ALL" pos="27" type="boolean"/> 145 145 + <bitfield name="FLAG" pos="28" type="boolean"/> 146 146 + </reg32> 147 147 + <!-- for 2-3 plane format, BASE is flag buffer address (if enabled) 148 148 + the address of the non-flag base buffer is determined automatically, 149 149 + and must follow the flag buffer 150 150 + --> 151 151 + <reg32 offset="4" name="4"> 152 152 + <bitfield name="BASE_LO" low="5" high="31" shr="5"/> 153 153 + </reg32> 154 154 + <reg32 offset="5" name="5"> 155 155 + <bitfield name="BASE_HI" low="0" high="16"/> 156 156 + <bitfield name="DEPTH" low="17" high="29" type="uint"/> 157 157 + </reg32> 158 158 + <reg32 offset="6" name="6"> 159 159 + <!-- overlaps with PLANE_PITCH --> 160 160 + <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/> 161 161 + <!-- pitch for plane 2 / plane 3 --> 162 162 + <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/> 163 163 + </reg32> 164 164 + <!-- 7/8 is plane 2 address for planar formats --> 165 165 + <reg32 offset="7" name="7"> 166 166 + <bitfield name="FLAG_LO" low="5" high="31" shr="5"/> 167 167 + </reg32> 168 168 + <reg32 offset="8" name="8"> 169 169 + <bitfield name="FLAG_HI" low="0" high="16"/> 170 170 + </reg32> 171 171 + <!-- 9/10 is plane 3 address for planar formats --> 172 172 + <reg32 offset="9" name="9"> 173 173 + <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> 174 174 + </reg32> 175 175 + <reg32 offset="10" name="10"> 176 176 + <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> 177 177 + <!-- log2 size of the first level, required for mipmapping --> 178 178 + <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/> 179 179 + <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/> 180 180 + </reg32> 181 181 + <reg32 offset="11" name="11"/> 182 182 + <reg32 offset="12" name="12"/> 183 183 + <reg32 offset="13" name="13"/> 184 184 + <reg32 offset="14" name="14"/> 185 185 + <reg32 offset="15" name="15"/> 186 186 + </domain> 187 187 + 188 188 + <domain name="A6XX_UBO" width="32"> 189 189 + <reg32 offset="0" name="0"> 190 190 + <bitfield name="BASE_LO" low="0" high="31"/> 191 191 + </reg32> 192 192 + <reg32 offset="1" name="1"> 193 193 + <bitfield name="BASE_HI" low="0" high="16"/> 194 194 + <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units --> 195 195 + </reg32> 196 196 + </domain> 197 197 + 198 198 + </database>

+383

drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml

reviewed

··· 1 1 + <?xml version="1.0" encoding="UTF-8"?> 2 2 + <database xmlns="http://nouveau.freedesktop.org/" 3 3 + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 4 + xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5 5 + <import file="freedreno_copyright.xml"/> 6 6 + <import file="adreno/adreno_common.xml"/> 7 7 + <import file="adreno/adreno_pm4.xml"/> 8 8 + 9 9 + <enum name="a6xx_tile_mode"> 10 10 + <value name="TILE6_LINEAR" value="0"/> 11 11 + <value name="TILE6_2" value="2"/> 12 12 + <value name="TILE6_3" value="3"/> 13 13 + </enum> 14 14 + 15 15 + <enum name="a6xx_format"> 16 16 + <value value="0x02" name="FMT6_A8_UNORM"/> 17 17 + <value value="0x03" name="FMT6_8_UNORM"/> 18 18 + <value value="0x04" name="FMT6_8_SNORM"/> 19 19 + <value value="0x05" name="FMT6_8_UINT"/> 20 20 + <value value="0x06" name="FMT6_8_SINT"/> 21 21 + 22 22 + <value value="0x08" name="FMT6_4_4_4_4_UNORM"/> 23 23 + <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/> 24 24 + <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only --> 25 25 + <value value="0x0e" name="FMT6_5_6_5_UNORM"/> 26 26 + 27 27 + <value value="0x0f" name="FMT6_8_8_UNORM"/> 28 28 + <value value="0x10" name="FMT6_8_8_SNORM"/> 29 29 + <value value="0x11" name="FMT6_8_8_UINT"/> 30 30 + <value value="0x12" name="FMT6_8_8_SINT"/> 31 31 + <value value="0x13" name="FMT6_L8_A8_UNORM"/> 32 32 + 33 33 + <value value="0x15" name="FMT6_16_UNORM"/> 34 34 + <value value="0x16" name="FMT6_16_SNORM"/> 35 35 + <value value="0x17" name="FMT6_16_FLOAT"/> 36 36 + <value value="0x18" name="FMT6_16_UINT"/> 37 37 + <value value="0x19" name="FMT6_16_SINT"/> 38 38 + 39 39 + <value value="0x21" name="FMT6_8_8_8_UNORM"/> 40 40 + <value value="0x22" name="FMT6_8_8_8_SNORM"/> 41 41 + <value value="0x23" name="FMT6_8_8_8_UINT"/> 42 42 + <value value="0x24" name="FMT6_8_8_8_SINT"/> 43 43 + 44 44 + <value value="0x30" name="FMT6_8_8_8_8_UNORM"/> 45 45 + <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha --> 46 46 + <value value="0x32" name="FMT6_8_8_8_8_SNORM"/> 47 47 + <value value="0x33" name="FMT6_8_8_8_8_UINT"/> 48 48 + <value value="0x34" name="FMT6_8_8_8_8_SINT"/> 49 49 + 50 50 + <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/> 51 51 + 52 52 + <value value="0x36" name="FMT6_10_10_10_2_UNORM"/> 53 53 + <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/> 54 54 + <value value="0x39" name="FMT6_10_10_10_2_SNORM"/> 55 55 + <value value="0x3a" name="FMT6_10_10_10_2_UINT"/> 56 56 + <value value="0x3b" name="FMT6_10_10_10_2_SINT"/> 57 57 + 58 58 + <value value="0x42" name="FMT6_11_11_10_FLOAT"/> 59 59 + 60 60 + <value value="0x43" name="FMT6_16_16_UNORM"/> 61 61 + <value value="0x44" name="FMT6_16_16_SNORM"/> 62 62 + <value value="0x45" name="FMT6_16_16_FLOAT"/> 63 63 + <value value="0x46" name="FMT6_16_16_UINT"/> 64 64 + <value value="0x47" name="FMT6_16_16_SINT"/> 65 65 + 66 66 + <value value="0x48" name="FMT6_32_UNORM"/> 67 67 + <value value="0x49" name="FMT6_32_SNORM"/> 68 68 + <value value="0x4a" name="FMT6_32_FLOAT"/> 69 69 + <value value="0x4b" name="FMT6_32_UINT"/> 70 70 + <value value="0x4c" name="FMT6_32_SINT"/> 71 71 + <value value="0x4d" name="FMT6_32_FIXED"/> 72 72 + 73 73 + <value value="0x58" name="FMT6_16_16_16_UNORM"/> 74 74 + <value value="0x59" name="FMT6_16_16_16_SNORM"/> 75 75 + <value value="0x5a" name="FMT6_16_16_16_FLOAT"/> 76 76 + <value value="0x5b" name="FMT6_16_16_16_UINT"/> 77 77 + <value value="0x5c" name="FMT6_16_16_16_SINT"/> 78 78 + 79 79 + <value value="0x60" name="FMT6_16_16_16_16_UNORM"/> 80 80 + <value value="0x61" name="FMT6_16_16_16_16_SNORM"/> 81 81 + <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/> 82 82 + <value value="0x63" name="FMT6_16_16_16_16_UINT"/> 83 83 + <value value="0x64" name="FMT6_16_16_16_16_SINT"/> 84 84 + 85 85 + <value value="0x65" name="FMT6_32_32_UNORM"/> 86 86 + <value value="0x66" name="FMT6_32_32_SNORM"/> 87 87 + <value value="0x67" name="FMT6_32_32_FLOAT"/> 88 88 + <value value="0x68" name="FMT6_32_32_UINT"/> 89 89 + <value value="0x69" name="FMT6_32_32_SINT"/> 90 90 + <value value="0x6a" name="FMT6_32_32_FIXED"/> 91 91 + 92 92 + <value value="0x70" name="FMT6_32_32_32_UNORM"/> 93 93 + <value value="0x71" name="FMT6_32_32_32_SNORM"/> 94 94 + <value value="0x72" name="FMT6_32_32_32_UINT"/> 95 95 + <value value="0x73" name="FMT6_32_32_32_SINT"/> 96 96 + <value value="0x74" name="FMT6_32_32_32_FLOAT"/> 97 97 + <value value="0x75" name="FMT6_32_32_32_FIXED"/> 98 98 + 99 99 + <value value="0x80" name="FMT6_32_32_32_32_UNORM"/> 100 100 + <value value="0x81" name="FMT6_32_32_32_32_SNORM"/> 101 101 + <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/> 102 102 + <value value="0x83" name="FMT6_32_32_32_32_UINT"/> 103 103 + <value value="0x84" name="FMT6_32_32_32_32_SINT"/> 104 104 + <value value="0x85" name="FMT6_32_32_32_32_FIXED"/> 105 105 + 106 106 + <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY --> 107 107 + <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV --> 108 108 + <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 --> 109 109 + <value value="0x8f" name="FMT6_NV21"/> 110 110 + <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 --> 111 111 + 112 112 + <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/> 113 113 + 114 114 + <!-- Note: tiling/UBWC for these may be different from equivalent formats 115 115 + For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM 116 116 + --> 117 117 + <value value="0x94" name="FMT6_NV12_Y"/> 118 118 + <value value="0x95" name="FMT6_NV12_UV"/> 119 119 + <value value="0x96" name="FMT6_NV12_VU"/> 120 120 + <value value="0x97" name="FMT6_NV12_4R"/> 121 121 + <value value="0x98" name="FMT6_NV12_4R_Y"/> 122 122 + <value value="0x99" name="FMT6_NV12_4R_UV"/> 123 123 + <value value="0x9a" name="FMT6_P010"/> 124 124 + <value value="0x9b" name="FMT6_P010_Y"/> 125 125 + <value value="0x9c" name="FMT6_P010_UV"/> 126 126 + <value value="0x9d" name="FMT6_TP10"/> 127 127 + <value value="0x9e" name="FMT6_TP10_Y"/> 128 128 + <value value="0x9f" name="FMT6_TP10_UV"/> 129 129 + 130 130 + <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/> 131 131 + 132 132 + <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/> 133 133 + <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/> 134 134 + <value value="0xad" name="FMT6_ETC2_R11_UNORM"/> 135 135 + <value value="0xae" name="FMT6_ETC2_R11_SNORM"/> 136 136 + <value value="0xaf" name="FMT6_ETC1"/> 137 137 + <value value="0xb0" name="FMT6_ETC2_RGB8"/> 138 138 + <value value="0xb1" name="FMT6_ETC2_RGBA8"/> 139 139 + <value value="0xb2" name="FMT6_ETC2_RGB8A1"/> 140 140 + <value value="0xb3" name="FMT6_DXT1"/> 141 141 + <value value="0xb4" name="FMT6_DXT3"/> 142 142 + <value value="0xb5" name="FMT6_DXT5"/> 143 143 + <value value="0xb6" name="FMT6_RGTC1_UNORM"/> 144 144 + <value value="0xb7" name="FMT6_RGTC1_UNORM_FAST"/> 145 145 + <value value="0xb8" name="FMT6_RGTC1_SNORM"/> 146 146 + <value value="0xb9" name="FMT6_RGTC1_SNORM_FAST"/> 147 147 + <value value="0xba" name="FMT6_RGTC2_UNORM"/> 148 148 + <value value="0xbb" name="FMT6_RGTC2_UNORM_FAST"/> 149 149 + <value value="0xbc" name="FMT6_RGTC2_SNORM"/> 150 150 + <value value="0xbd" name="FMT6_RGTC2_SNORM_FAST"/> 151 151 + <value value="0xbe" name="FMT6_BPTC_UFLOAT"/> 152 152 + <value value="0xbf" name="FMT6_BPTC_FLOAT"/> 153 153 + <value value="0xc0" name="FMT6_BPTC"/> 154 154 + <value value="0xc1" name="FMT6_ASTC_4x4"/> 155 155 + <value value="0xc2" name="FMT6_ASTC_5x4"/> 156 156 + <value value="0xc3" name="FMT6_ASTC_5x5"/> 157 157 + <value value="0xc4" name="FMT6_ASTC_6x5"/> 158 158 + <value value="0xc5" name="FMT6_ASTC_6x6"/> 159 159 + <value value="0xc6" name="FMT6_ASTC_8x5"/> 160 160 + <value value="0xc7" name="FMT6_ASTC_8x6"/> 161 161 + <value value="0xc8" name="FMT6_ASTC_8x8"/> 162 162 + <value value="0xc9" name="FMT6_ASTC_10x5"/> 163 163 + <value value="0xca" name="FMT6_ASTC_10x6"/> 164 164 + <value value="0xcb" name="FMT6_ASTC_10x8"/> 165 165 + <value value="0xcc" name="FMT6_ASTC_10x10"/> 166 166 + <value value="0xcd" name="FMT6_ASTC_12x10"/> 167 167 + <value value="0xce" name="FMT6_ASTC_12x12"/> 168 168 + 169 169 + <!-- for sampling stencil (integer, 2nd channel), not available on a630 --> 170 170 + <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/> 171 171 + 172 172 + <!-- Not a hw enum, used internally in driver --> 173 173 + <value value="0xff" name="FMT6_NONE"/> 174 174 + 175 175 + </enum> 176 176 + 177 177 + <!-- probably same as a5xx --> 178 178 + <enum name="a6xx_polygon_mode"> 179 179 + <value name="POLYMODE6_POINTS" value="1"/> 180 180 + <value name="POLYMODE6_LINES" value="2"/> 181 181 + <value name="POLYMODE6_TRIANGLES" value="3"/> 182 182 + </enum> 183 183 + 184 184 + <enum name="a6xx_depth_format"> 185 185 + <value name="DEPTH6_NONE" value="0"/> 186 186 + <value name="DEPTH6_16" value="1"/> 187 187 + <value name="DEPTH6_24_8" value="2"/> 188 188 + <value name="DEPTH6_32" value="4"/> 189 189 + </enum> 190 190 + 191 191 + <bitset name="a6x_cp_protect" inline="yes"> 192 192 + <bitfield name="BASE_ADDR" low="0" high="17"/> 193 193 + <bitfield name="MASK_LEN" low="18" high="30"/> 194 194 + <bitfield name="READ" pos="31" type="boolean"/> 195 195 + </bitset> 196 196 + 197 197 + <enum name="a6xx_shader_id"> 198 198 + <value value="0x9" name="A6XX_TP0_TMO_DATA"/> 199 199 + <value value="0xa" name="A6XX_TP0_SMO_DATA"/> 200 200 + <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/> 201 201 + <value value="0x19" name="A6XX_TP1_TMO_DATA"/> 202 202 + <value value="0x1a" name="A6XX_TP1_SMO_DATA"/> 203 203 + <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/> 204 204 + <value value="0x29" name="A6XX_SP_INST_DATA"/> 205 205 + <value value="0x2a" name="A6XX_SP_LB_0_DATA"/> 206 206 + <value value="0x2b" name="A6XX_SP_LB_1_DATA"/> 207 207 + <value value="0x2c" name="A6XX_SP_LB_2_DATA"/> 208 208 + <value value="0x2d" name="A6XX_SP_LB_3_DATA"/> 209 209 + <value value="0x2e" name="A6XX_SP_LB_4_DATA"/> 210 210 + <value value="0x2f" name="A6XX_SP_LB_5_DATA"/> 211 211 + <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/> 212 212 + <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/> 213 213 + <value value="0x32" name="A6XX_SP_GFX_UAV_BASE_DATA"/> 214 214 + <value value="0x33" name="A6XX_SP_INST_TAG"/> 215 215 + <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/> 216 216 + <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/> 217 217 + <value value="0x36" name="A6XX_SP_SMO_TAG"/> 218 218 + <value value="0x37" name="A6XX_SP_STATE_DATA"/> 219 219 + <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/> 220 220 + <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/> 221 221 + <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/> 222 222 + <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/> 223 223 + <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> 224 224 + <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> 225 225 + <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/> 226 226 + <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/> 227 227 + <value value="0x52" name="A6XX_HLSQ_INST_RAM"/> 228 228 + <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/> 229 229 + <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/> 230 230 + <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/> 231 231 + <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/> 232 232 + <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/> 233 233 + <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> 234 234 + <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> 235 235 + <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/> 236 236 + <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/> 237 237 + <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/> 238 238 + <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/> 239 239 + <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/> 240 240 + <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/> 241 241 + <value value="0x70" name="A6XX_SP_LB_6_DATA"/> 242 242 + <value value="0x71" name="A6XX_SP_LB_7_DATA"/> 243 243 + <value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/> 244 244 + </enum> 245 245 + 246 246 + <enum name="a6xx_debugbus_id"> 247 247 + <value value="0x1" name="A6XX_DBGBUS_CP"/> 248 248 + <value value="0x2" name="A6XX_DBGBUS_RBBM"/> 249 249 + <value value="0x3" name="A6XX_DBGBUS_VBIF"/> 250 250 + <value value="0x4" name="A6XX_DBGBUS_HLSQ"/> 251 251 + <value value="0x5" name="A6XX_DBGBUS_UCHE"/> 252 252 + <value value="0x6" name="A6XX_DBGBUS_DPM"/> 253 253 + <value value="0x7" name="A6XX_DBGBUS_TESS"/> 254 254 + <value value="0x8" name="A6XX_DBGBUS_PC"/> 255 255 + <value value="0x9" name="A6XX_DBGBUS_VFDP"/> 256 256 + <value value="0xa" name="A6XX_DBGBUS_VPC"/> 257 257 + <value value="0xb" name="A6XX_DBGBUS_TSE"/> 258 258 + <value value="0xc" name="A6XX_DBGBUS_RAS"/> 259 259 + <value value="0xd" name="A6XX_DBGBUS_VSC"/> 260 260 + <value value="0xe" name="A6XX_DBGBUS_COM"/> 261 261 + <value value="0x10" name="A6XX_DBGBUS_LRZ"/> 262 262 + <value value="0x11" name="A6XX_DBGBUS_A2D"/> 263 263 + <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/> 264 264 + <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/> 265 265 + <value value="0x14" name="A6XX_DBGBUS_RBP"/> 266 266 + <value value="0x15" name="A6XX_DBGBUS_DCS"/> 267 267 + <value value="0x16" name="A6XX_DBGBUS_DBGC"/> 268 268 + <value value="0x17" name="A6XX_DBGBUS_CX"/> 269 269 + <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/> 270 270 + <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/> 271 271 + <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/> 272 272 + <value value="0x1d" name="A6XX_DBGBUS_GPC"/> 273 273 + <value value="0x1e" name="A6XX_DBGBUS_LARC"/> 274 274 + <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/> 275 275 + <value value="0x20" name="A6XX_DBGBUS_RB_0"/> 276 276 + <value value="0x21" name="A6XX_DBGBUS_RB_1"/> 277 277 + <value value="0x22" name="A6XX_DBGBUS_RB_2"/> 278 278 + <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/> 279 279 + <value value="0x28" name="A6XX_DBGBUS_CCU_0"/> 280 280 + <value value="0x29" name="A6XX_DBGBUS_CCU_1"/> 281 281 + <value value="0x2a" name="A6XX_DBGBUS_CCU_2"/> 282 282 + <value value="0x38" name="A6XX_DBGBUS_VFD_0"/> 283 283 + <value value="0x39" name="A6XX_DBGBUS_VFD_1"/> 284 284 + <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/> 285 285 + <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/> 286 286 + <value value="0x3c" name="A6XX_DBGBUS_VFD_4"/> 287 287 + <value value="0x3d" name="A6XX_DBGBUS_VFD_5"/> 288 288 + <value value="0x40" name="A6XX_DBGBUS_SP_0"/> 289 289 + <value value="0x41" name="A6XX_DBGBUS_SP_1"/> 290 290 + <value value="0x42" name="A6XX_DBGBUS_SP_2"/> 291 291 + <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/> 292 292 + <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/> 293 293 + <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/> 294 294 + <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/> 295 295 + <value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/> 296 296 + <value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/> 297 297 + <value value="0x58" name="A6XX_DBGBUS_SPTP_0"/> 298 298 + <value value="0x59" name="A6XX_DBGBUS_SPTP_1"/> 299 299 + <value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/> 300 300 + <value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/> 301 301 + <value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/> 302 302 + <value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/> 303 303 + </enum> 304 304 + 305 305 + <!-- 306 306 + Used in a6xx_a2d_bit_cntl.. the value mostly seems to correlate to the 307 307 + component type/size, so I think it relates to internal format used for 308 308 + blending? The one exception is that 16b unorm and 32b float use the 309 309 + same value... maybe 16b unorm is uncommon enough that it was just easier 310 310 + to upconvert to 32b float internally? 311 311 + 312 312 + 8b unorm: 10 (sometimes 0, is the high bit part of something else?) 313 313 + 16b unorm: 4 314 314 + 315 315 + 32b int: 7 316 316 + 16b int: 6 317 317 + 8b int: 5 318 318 + 319 319 + 32b float: 4 320 320 + 16b float: 3 321 321 + --> 322 322 + <enum name="a6xx_2d_ifmt"> 323 323 + <value value="0x10" name="R2D_UNORM8"/> 324 324 + <value value="0x7" name="R2D_INT32"/> 325 325 + <value value="0x6" name="R2D_INT16"/> 326 326 + <value value="0x5" name="R2D_INT8"/> 327 327 + <value value="0x4" name="R2D_FLOAT32"/> 328 328 + <value value="0x3" name="R2D_FLOAT16"/> 329 329 + <value value="0x1" name="R2D_UNORM8_SRGB"/> 330 330 + <value value="0x0" name="R2D_RAW"/> 331 331 + </enum> 332 332 + 333 333 + <enum name="a6xx_tex_type"> 334 334 + <value name="A6XX_TEX_1D" value="0"/> 335 335 + <value name="A6XX_TEX_2D" value="1"/> 336 336 + <value name="A6XX_TEX_CUBE" value="2"/> 337 337 + <value name="A6XX_TEX_3D" value="3"/> 338 338 + <value name="A6XX_TEX_BUFFER" value="4"/> 339 339 + <doc> 340 340 + A special buffer type for usage as the source for buffer 341 341 + to image copies with lower alignment requirements than 342 342 + A6XX_TEX_2D, available since A7XX. 343 343 + </doc> 344 344 + <value name="A6XX_TEX_IMG_BUFFER" value="5"/> 345 345 + </enum> 346 346 + 347 347 + <enum name="a6xx_ztest_mode"> 348 348 + <doc>Allow early z-test and early-lrz (if applicable)</doc> 349 349 + <value value="0x0" name="A6XX_EARLY_Z"/> 350 350 + <doc>Disable early z-test and early-lrz test (if applicable)</doc> 351 351 + <value value="0x1" name="A6XX_LATE_Z"/> 352 352 + <doc> 353 353 + A special mode that allows early-lrz (if applicable) or early-z 354 354 + tests, but also does late-z tests at which point it writes depth. 355 355 + 356 356 + This mode is used when fragment can be killed (via discard or 357 357 + sample mask) after early-z tests and it writes depth. In such case 358 358 + depth can be written only at late-z stage, but it's ok to use 359 359 + early-z to discard fragments. 360 360 + 361 361 + However this mode is not compatible with: 362 362 + - Lack of D/S attachment 363 363 + - Stencil writes on stencil or depth test failures 364 364 + - Per-sample shading 365 365 + </doc> 366 366 + <value value="0x2" name="A6XX_EARLY_Z_LATE_Z"/> 367 367 + <doc>Not a real hw value, used internally by mesa</doc> 368 368 + <value value="0x3" name="A6XX_INVALID_ZTEST"/> 369 369 + </enum> 370 370 + 371 371 + <enum name="a6xx_tess_spacing"> 372 372 + <value value="0x0" name="TESS_EQUAL"/> 373 373 + <value value="0x2" name="TESS_FRACTIONAL_ODD"/> 374 374 + <value value="0x3" name="TESS_FRACTIONAL_EVEN"/> 375 375 + </enum> 376 376 + <enum name="a6xx_tess_output"> 377 377 + <value value="0x0" name="TESS_POINTS"/> 378 378 + <value value="0x1" name="TESS_LINES"/> 379 379 + <value value="0x2" name="TESS_CW_TRIS"/> 380 380 + <value value="0x3" name="TESS_CCW_TRIS"/> 381 381 + </enum> 382 382 + 383 383 + </database>

+600

drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.xml

reviewed

··· 1 1 + <?xml version="1.0" encoding="UTF-8"?> 2 2 + <database xmlns="http://nouveau.freedesktop.org/" 3 3 + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 4 + xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5 5 + <import file="freedreno_copyright.xml"/> 6 6 + <import file="adreno/adreno_common.xml"/> 7 7 + <import file="adreno/adreno_pm4.xml"/> 8 8 + 9 9 + <enum name="a6xx_cp_perfcounter_select"> 10 10 + <value value="0" name="PERF_CP_ALWAYS_COUNT"/> 11 11 + <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> 12 12 + <value value="2" name="PERF_CP_BUSY_CYCLES"/> 13 13 + <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> 14 14 + <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> 15 15 + <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 16 16 + <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 17 17 + <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 18 18 + <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> 19 19 + <value value="9" name="PERF_CP_MODE_SWITCH"/> 20 20 + <value value="10" name="PERF_CP_ZPASS_DONE"/> 21 21 + <value value="11" name="PERF_CP_CONTEXT_DONE"/> 22 22 + <value value="12" name="PERF_CP_CACHE_FLUSH"/> 23 23 + <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/> 24 24 + <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/> 25 25 + <value value="15" name="PERF_CP_SQE_IDLE"/> 26 26 + <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/> 27 27 + <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/> 28 28 + <value value="18" name="PERF_CP_SQE_MRB_STARVE"/> 29 29 + <value value="19" name="PERF_CP_SQE_RRB_STARVE"/> 30 30 + <value value="20" name="PERF_CP_SQE_VSD_STARVE"/> 31 31 + <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/> 32 32 + <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/> 33 33 + <value value="23" name="PERF_CP_SQE_SYNC_STALL"/> 34 34 + <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/> 35 35 + <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/> 36 36 + <value value="26" name="PERF_CP_SQE_T4_EXEC"/> 37 37 + <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/> 38 38 + <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/> 39 39 + <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/> 40 40 + <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> 41 41 + <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/> 42 42 + <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/> 43 43 + <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/> 44 44 + <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> 45 45 + <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> 46 46 + <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/> 47 47 + <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/> 48 48 + <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/> 49 49 + <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/> 50 50 + <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/> 51 51 + <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/> 52 52 + <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/> 53 53 + <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/> 54 54 + <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/> 55 55 + <value value="45" name="PERF_CP_PM4_DATA"/> 56 56 + <value value="46" name="PERF_CP_PM4_HEADERS"/> 57 57 + <value value="47" name="PERF_CP_VBIF_READ_BEATS"/> 58 58 + <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/> 59 59 + <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/> 60 60 + </enum> 61 61 + 62 62 + <enum name="a6xx_rbbm_perfcounter_select"> 63 63 + <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> 64 64 + <value value="1" name="PERF_RBBM_ALWAYS_ON"/> 65 65 + <value value="2" name="PERF_RBBM_TSE_BUSY"/> 66 66 + <value value="3" name="PERF_RBBM_RAS_BUSY"/> 67 67 + <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> 68 68 + <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> 69 69 + <value value="6" name="PERF_RBBM_STATUS_MASKED"/> 70 70 + <value value="7" name="PERF_RBBM_COM_BUSY"/> 71 71 + <value value="8" name="PERF_RBBM_DCOM_BUSY"/> 72 72 + <value value="9" name="PERF_RBBM_VBIF_BUSY"/> 73 73 + <value value="10" name="PERF_RBBM_VSC_BUSY"/> 74 74 + <value value="11" name="PERF_RBBM_TESS_BUSY"/> 75 75 + <value value="12" name="PERF_RBBM_UCHE_BUSY"/> 76 76 + <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> 77 77 + </enum> 78 78 + 79 79 + <enum name="a6xx_pc_perfcounter_select"> 80 80 + <value value="0" name="PERF_PC_BUSY_CYCLES"/> 81 81 + <value value="1" name="PERF_PC_WORKING_CYCLES"/> 82 82 + <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> 83 83 + <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> 84 84 + <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> 85 85 + <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> 86 86 + <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> 87 87 + <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> 88 88 + <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> 89 89 + <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> 90 90 + <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> 91 91 + <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> 92 92 + <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> 93 93 + <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> 94 94 + <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> 95 95 + <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> 96 96 + <value value="16" name="PERF_PC_INSTANCES"/> 97 97 + <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> 98 98 + <value value="18" name="PERF_PC_DEAD_PRIM"/> 99 99 + <value value="19" name="PERF_PC_LIVE_PRIM"/> 100 100 + <value value="20" name="PERF_PC_VERTEX_HITS"/> 101 101 + <value value="21" name="PERF_PC_IA_VERTICES"/> 102 102 + <value value="22" name="PERF_PC_IA_PRIMITIVES"/> 103 103 + <value value="23" name="PERF_PC_GS_PRIMITIVES"/> 104 104 + <value value="24" name="PERF_PC_HS_INVOCATIONS"/> 105 105 + <value value="25" name="PERF_PC_DS_INVOCATIONS"/> 106 106 + <value value="26" name="PERF_PC_VS_INVOCATIONS"/> 107 107 + <value value="27" name="PERF_PC_GS_INVOCATIONS"/> 108 108 + <value value="28" name="PERF_PC_DS_PRIMITIVES"/> 109 109 + <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> 110 110 + <value value="30" name="PERF_PC_3D_DRAWCALLS"/> 111 111 + <value value="31" name="PERF_PC_2D_DRAWCALLS"/> 112 112 + <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> 113 113 + <value value="33" name="PERF_TESS_BUSY_CYCLES"/> 114 114 + <value value="34" name="PERF_TESS_WORKING_CYCLES"/> 115 115 + <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> 116 116 + <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> 117 117 + <value value="37" name="PERF_PC_TSE_TRANSACTION"/> 118 118 + <value value="38" name="PERF_PC_TSE_VERTEX"/> 119 119 + <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/> 120 120 + <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/> 121 121 + <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/> 122 122 + </enum> 123 123 + 124 124 + <enum name="a6xx_vfd_perfcounter_select"> 125 125 + <value value="0" name="PERF_VFD_BUSY_CYCLES"/> 126 126 + <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> 127 127 + <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> 128 128 + <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> 129 129 + <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> 130 130 + <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/> 131 131 + <value value="6" name="PERF_VFD_RBUFFER_FULL"/> 132 132 + <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> 133 133 + <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> 134 134 + <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/> 135 135 + <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/> 136 136 + <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/> 137 137 + <value value="12" name="PERF_VFD_MODE_0_FIBERS"/> 138 138 + <value value="13" name="PERF_VFD_MODE_1_FIBERS"/> 139 139 + <value value="14" name="PERF_VFD_MODE_2_FIBERS"/> 140 140 + <value value="15" name="PERF_VFD_MODE_3_FIBERS"/> 141 141 + <value value="16" name="PERF_VFD_MODE_4_FIBERS"/> 142 142 + <value value="17" name="PERF_VFD_TOTAL_VERTICES"/> 143 143 + <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/> 144 144 + <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> 145 145 + <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> 146 146 + <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/> 147 147 + <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/> 148 148 + </enum> 149 149 + 150 150 + <enum name="a6xx_hlsq_perfcounter_select"> 151 151 + <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> 152 152 + <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> 153 153 + <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> 154 154 + <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> 155 155 + <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> 156 156 + <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> 157 157 + <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/> 158 158 + <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/> 159 159 + <value value="8" name="PERF_HLSQ_QUADS"/> 160 160 + <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/> 161 161 + <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> 162 162 + <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> 163 163 + <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> 164 164 + <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> 165 165 + <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> 166 166 + <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> 167 167 + <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> 168 168 + <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> 169 169 + <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/> 170 170 + <value value="19" name="PERF_HLSQ_PIXELS"/> 171 171 + <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> 172 172 + </enum> 173 173 + 174 174 + <enum name="a6xx_vpc_perfcounter_select"> 175 175 + <value value="0" name="PERF_VPC_BUSY_CYCLES"/> 176 176 + <value value="1" name="PERF_VPC_WORKING_CYCLES"/> 177 177 + <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> 178 178 + <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> 179 179 + <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> 180 180 + <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> 181 181 + <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> 182 182 + <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/> 183 183 + <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/> 184 184 + <value value="9" name="PERF_VPC_PC_PRIMITIVES"/> 185 185 + <value value="10" name="PERF_VPC_SP_COMPONENTS"/> 186 186 + <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> 187 187 + <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> 188 188 + <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/> 189 189 + <value value="14" name="PERF_VPC_LM_TRANSACTION"/> 190 190 + <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/> 191 191 + <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/> 192 192 + <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/> 193 193 + <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/> 194 194 + <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/> 195 195 + <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/> 196 196 + <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/> 197 197 + <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/> 198 198 + <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/> 199 199 + <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> 200 200 + <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/> 201 201 + <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/> 202 202 + <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/> 203 203 + </enum> 204 204 + 205 205 + <enum name="a6xx_tse_perfcounter_select"> 206 206 + <value value="0" name="PERF_TSE_BUSY_CYCLES"/> 207 207 + <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> 208 208 + <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> 209 209 + <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> 210 210 + <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> 211 211 + <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> 212 212 + <value value="6" name="PERF_TSE_INPUT_PRIM"/> 213 213 + <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> 214 214 + <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> 215 215 + <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> 216 216 + <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> 217 217 + <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> 218 218 + <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> 219 219 + <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> 220 220 + <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> 221 221 + <value value="15" name="PERF_TSE_CINVOCATION"/> 222 222 + <value value="16" name="PERF_TSE_CPRIMITIVES"/> 223 223 + <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> 224 224 + <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/> 225 225 + <value value="19" name="PERF_TSE_CLIP_PLANES"/> 226 226 + </enum> 227 227 + 228 228 + <enum name="a6xx_ras_perfcounter_select"> 229 229 + <value value="0" name="PERF_RAS_BUSY_CYCLES"/> 230 230 + <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> 231 231 + <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> 232 232 + <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> 233 233 + <value value="4" name="PERF_RAS_SUPER_TILES"/> 234 234 + <value value="5" name="PERF_RAS_8X4_TILES"/> 235 235 + <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> 236 236 + <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> 237 237 + <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> 238 238 + <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> 239 239 + <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> 240 240 + <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> 241 241 + <value value="12" name="PERF_RAS_BLOCKS"/> 242 242 + </enum> 243 243 + 244 244 + <enum name="a6xx_uche_perfcounter_select"> 245 245 + <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> 246 246 + <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/> 247 247 + <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> 248 248 + <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> 249 249 + <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> 250 250 + <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> 251 251 + <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> 252 252 + <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> 253 253 + <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> 254 254 + <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> 255 255 + <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> 256 256 + <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> 257 257 + <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> 258 258 + <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> 259 259 + <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> 260 260 + <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> 261 261 + <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> 262 262 + <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> 263 263 + <value value="18" name="PERF_UCHE_EVICTS"/> 264 264 + <value value="19" name="PERF_UCHE_BANK_REQ0"/> 265 265 + <value value="20" name="PERF_UCHE_BANK_REQ1"/> 266 266 + <value value="21" name="PERF_UCHE_BANK_REQ2"/> 267 267 + <value value="22" name="PERF_UCHE_BANK_REQ3"/> 268 268 + <value value="23" name="PERF_UCHE_BANK_REQ4"/> 269 269 + <value value="24" name="PERF_UCHE_BANK_REQ5"/> 270 270 + <value value="25" name="PERF_UCHE_BANK_REQ6"/> 271 271 + <value value="26" name="PERF_UCHE_BANK_REQ7"/> 272 272 + <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> 273 273 + <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> 274 274 + <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> 275 275 + <value value="30" name="PERF_UCHE_TPH_REF_FULL"/> 276 276 + <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/> 277 277 + <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/> 278 278 + <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/> 279 279 + <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/> 280 280 + <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/> 281 281 + <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/> 282 282 + <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/> 283 283 + <value value="38" name="PERF_UCHE_RAM_READ_REQ"/> 284 284 + <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/> 285 285 + </enum> 286 286 + 287 287 + <enum name="a6xx_tp_perfcounter_select"> 288 288 + <value value="0" name="PERF_TP_BUSY_CYCLES"/> 289 289 + <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> 290 290 + <value value="2" name="PERF_TP_LATENCY_CYCLES"/> 291 291 + <value value="3" name="PERF_TP_LATENCY_TRANS"/> 292 292 + <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> 293 293 + <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> 294 294 + <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> 295 295 + <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> 296 296 + <value value="8" name="PERF_TP_SP_TP_TRANS"/> 297 297 + <value value="9" name="PERF_TP_TP_SP_TRANS"/> 298 298 + <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> 299 299 + <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> 300 300 + <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> 301 301 + <value value="13" name="PERF_TP_QUADS_RECEIVED"/> 302 302 + <value value="14" name="PERF_TP_QUADS_OFFSET"/> 303 303 + <value value="15" name="PERF_TP_QUADS_SHADOW"/> 304 304 + <value value="16" name="PERF_TP_QUADS_ARRAY"/> 305 305 + <value value="17" name="PERF_TP_QUADS_GRADIENT"/> 306 306 + <value value="18" name="PERF_TP_QUADS_1D"/> 307 307 + <value value="19" name="PERF_TP_QUADS_2D"/> 308 308 + <value value="20" name="PERF_TP_QUADS_BUFFER"/> 309 309 + <value value="21" name="PERF_TP_QUADS_3D"/> 310 310 + <value value="22" name="PERF_TP_QUADS_CUBE"/> 311 311 + <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> 312 312 + <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> 313 313 + <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/> 314 314 + <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> 315 315 + <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/> 316 316 + <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> 317 317 + <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> 318 318 + <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/> 319 319 + <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/> 320 320 + <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/> 321 321 + <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/> 322 322 + <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> 323 323 + <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> 324 324 + <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> 325 325 + <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> 326 326 + <value value="38" name="PERF_TP_TPA2TPC_TRANS"/> 327 327 + <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/> 328 328 + <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/> 329 329 + <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/> 330 330 + <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/> 331 331 + <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/> 332 332 + <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/> 333 333 + <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> 334 334 + <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/> 335 335 + <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> 336 336 + <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/> 337 337 + <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/> 338 338 + <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> 339 339 + <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> 340 340 + <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/> 341 341 + <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/> 342 342 + <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> 343 343 + <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/> 344 344 + <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/> 345 345 + </enum> 346 346 + 347 347 + <enum name="a6xx_sp_perfcounter_select"> 348 348 + <value value="0" name="PERF_SP_BUSY_CYCLES"/> 349 349 + <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> 350 350 + <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> 351 351 + <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> 352 352 + <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> 353 353 + <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> 354 354 + <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> 355 355 + <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/> 356 356 + <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> 357 357 + <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> 358 358 + <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> 359 359 + <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> 360 360 + <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> 361 361 + <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> 362 362 + <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> 363 363 + <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> 364 364 + <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> 365 365 + <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> 366 366 + <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> 367 367 + <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> 368 368 + <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> 369 369 + <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> 370 370 + <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> 371 371 + <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> 372 372 + <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> 373 373 + <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> 374 374 + <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> 375 375 + <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> 376 376 + <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> 377 377 + <value value="29" name="PERF_SP_LM_ATOMICS"/> 378 378 + <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> 379 379 + <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> 380 380 + <value value="32" name="PERF_SP_GM_ATOMICS"/> 381 381 + <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> 382 382 + <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> 383 383 + <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> 384 384 + <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> 385 385 + <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> 386 386 + <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> 387 387 + <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> 388 388 + <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> 389 389 + <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> 390 390 + <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> 391 391 + <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/> 392 392 + <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/> 393 393 + <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/> 394 394 + <value value="46" name="PERF_SP_UCHE_READ_TRANS"/> 395 395 + <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/> 396 396 + <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/> 397 397 + <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/> 398 398 + <value value="50" name="PERF_SP_PIXELS_KILLED"/> 399 399 + <value value="51" name="PERF_SP_ICL1_REQUESTS"/> 400 400 + <value value="52" name="PERF_SP_ICL1_MISSES"/> 401 401 + <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/> 402 402 + <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/> 403 403 + <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/> 404 404 + <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/> 405 405 + <value value="57" name="PERF_SP_GPR_READ"/> 406 406 + <value value="58" name="PERF_SP_GPR_WRITE"/> 407 407 + <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> 408 408 + <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> 409 409 + <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/> 410 410 + <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> 411 411 + <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> 412 412 + <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> 413 413 + <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/> 414 414 + <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/> 415 415 + <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/> 416 416 + <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> 417 417 + <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/> 418 418 + <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/> 419 419 + <value value="71" name="PERF_SP_WORKING_EU"/> 420 420 + <value value="72" name="PERF_SP_ANY_EU_WORKING"/> 421 421 + <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/> 422 422 + <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/> 423 423 + <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/> 424 424 + <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/> 425 425 + <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/> 426 426 + <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/> 427 427 + <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/> 428 428 + <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/> 429 429 + <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/> 430 430 + <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/> 431 431 + <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> 432 432 + <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/> 433 433 + </enum> 434 434 + 435 435 + <enum name="a6xx_rb_perfcounter_select"> 436 436 + <value value="0" name="PERF_RB_BUSY_CYCLES"/> 437 437 + <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/> 438 438 + <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> 439 439 + <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> 440 440 + <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> 441 441 + <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/> 442 442 + <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> 443 443 + <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/> 444 444 + <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> 445 445 + <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> 446 446 + <value value="10" name="PERF_RB_Z_WORKLOAD"/> 447 447 + <value value="11" name="PERF_RB_HLSQ_ACTIVE"/> 448 448 + <value value="12" name="PERF_RB_Z_READ"/> 449 449 + <value value="13" name="PERF_RB_Z_WRITE"/> 450 450 + <value value="14" name="PERF_RB_C_READ"/> 451 451 + <value value="15" name="PERF_RB_C_WRITE"/> 452 452 + <value value="16" name="PERF_RB_TOTAL_PASS"/> 453 453 + <value value="17" name="PERF_RB_Z_PASS"/> 454 454 + <value value="18" name="PERF_RB_Z_FAIL"/> 455 455 + <value value="19" name="PERF_RB_S_FAIL"/> 456 456 + <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> 457 457 + <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> 458 458 + <value value="22" name="PERF_RB_PS_INVOCATIONS"/> 459 459 + <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/> 460 460 + <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/> 461 461 + <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> 462 462 + <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/> 463 463 + <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/> 464 464 + <value value="28" name="PERF_RB_2D_VALID_PIXELS"/> 465 465 + <value value="29" name="PERF_RB_3D_PIXELS"/> 466 466 + <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/> 467 467 + <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/> 468 468 + <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/> 469 469 + <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/> 470 470 + <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> 471 471 + <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> 472 472 + <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> 473 473 + <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> 474 474 + <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/> 475 475 + <value value="39" name="PERF_RB_2D_INPUT_TRANS"/> 476 476 + <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> 477 477 + <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> 478 478 + <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/> 479 479 + <value value="43" name="PERF_RB_COLOR_PIX_TILES"/> 480 480 + <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/> 481 481 + <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/> 482 482 + <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/> 483 483 + <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/> 484 484 + </enum> 485 485 + 486 486 + <enum name="a6xx_vsc_perfcounter_select"> 487 487 + <value value="0" name="PERF_VSC_BUSY_CYCLES"/> 488 488 + <value value="1" name="PERF_VSC_WORKING_CYCLES"/> 489 489 + <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> 490 490 + <value value="3" name="PERF_VSC_EOT_NUM"/> 491 491 + <value value="4" name="PERF_VSC_INPUT_TILES"/> 492 492 + </enum> 493 493 + 494 494 + <enum name="a6xx_ccu_perfcounter_select"> 495 495 + <value value="0" name="PERF_CCU_BUSY_CYCLES"/> 496 496 + <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> 497 497 + <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> 498 498 + <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> 499 499 + <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> 500 500 + <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> 501 501 + <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> 502 502 + <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> 503 503 + <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> 504 504 + <value value="9" name="PERF_CCU_GMEM_READ"/> 505 505 + <value value="10" name="PERF_CCU_GMEM_WRITE"/> 506 506 + <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> 507 507 + <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> 508 508 + <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> 509 509 + <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> 510 510 + <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> 511 511 + <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/> 512 512 + <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/> 513 513 + <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/> 514 514 + <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> 515 515 + <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> 516 516 + <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> 517 517 + <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> 518 518 + <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> 519 519 + <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/> 520 520 + <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/> 521 521 + <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/> 522 522 + <value value="27" name="PERF_CCU_2D_RD_REQ"/> 523 523 + <value value="28" name="PERF_CCU_2D_WR_REQ"/> 524 524 + </enum> 525 525 + 526 526 + <enum name="a6xx_lrz_perfcounter_select"> 527 527 + <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> 528 528 + <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> 529 529 + <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> 530 530 + <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> 531 531 + <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> 532 532 + <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> 533 533 + <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> 534 534 + <value value="7" name="PERF_LRZ_LRZ_READ"/> 535 535 + <value value="8" name="PERF_LRZ_LRZ_WRITE"/> 536 536 + <value value="9" name="PERF_LRZ_READ_LATENCY"/> 537 537 + <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> 538 538 + <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> 539 539 + <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> 540 540 + <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> 541 541 + <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> 542 542 + <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> 543 543 + <value value="16" name="PERF_LRZ_TILE_KILLED"/> 544 544 + <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> 545 545 + <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> 546 546 + <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/> 547 547 + <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/> 548 548 + <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/> 549 549 + <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/> 550 550 + <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/> 551 551 + <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> 552 552 + <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> 553 553 + <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/> 554 554 + <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/> 555 555 + </enum> 556 556 + 557 557 + <enum name="a6xx_cmp_perfcounter_select"> 558 558 + <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/> 559 559 + <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> 560 560 + <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> 561 561 + <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> 562 562 + <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> 563 563 + <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> 564 564 + <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> 565 565 + <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> 566 566 + <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> 567 567 + <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> 568 568 + <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> 569 569 + <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> 570 570 + <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> 571 571 + <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> 572 572 + <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> 573 573 + <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> 574 574 + <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> 575 575 + <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> 576 576 + <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> 577 577 + <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> 578 578 + <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> 579 579 + <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> 580 580 + <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> 581 581 + <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> 582 582 + <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> 583 583 + <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> 584 584 + <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> 585 585 + <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> 586 586 + <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/> 587 587 + <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/> 588 588 + <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> 589 589 + <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> 590 590 + <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/> 591 591 + <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> 592 592 + <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> 593 593 + <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> 594 594 + <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> 595 595 + <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/> 596 596 + <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/> 597 597 + <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/> 598 598 + </enum> 599 599 + 600 600 + </database>

+223

drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml

reviewed

··· 1 1 + <?xml version="1.0" encoding="UTF-8"?> 2 2 + <database xmlns="http://nouveau.freedesktop.org/" 3 3 + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 4 + xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5 5 + <import file="freedreno_copyright.xml"/> 6 6 + <import file="adreno/adreno_common.xml"/> 7 7 + <import file="adreno/adreno_pm4.xml"/> 8 8 + 9 9 + <enum name="a7xx_statetype_id"> 10 10 + <value value="0" name="A7XX_TP0_NCTX_REG"/> 11 11 + <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/> 12 12 + <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/> 13 13 + <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/> 14 14 + <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/> 15 15 + <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/> 16 16 + <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/> 17 17 + <value value="9" name="A7XX_TP0_TMO_DATA"/> 18 18 + <value value="10" name="A7XX_TP0_SMO_DATA"/> 19 19 + <value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/> 20 20 + <value value="32" name="A7XX_SP_NCTX_REG"/> 21 21 + <value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/> 22 22 + <value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/> 23 23 + <value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/> 24 24 + <value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/> 25 25 + <value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/> 26 26 + <value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/> 27 27 + <value value="39" name="A7XX_SP_INST_DATA"/> 28 28 + <value value="40" name="A7XX_SP_INST_DATA_1"/> 29 29 + <value value="41" name="A7XX_SP_LB_0_DATA"/> 30 30 + <value value="42" name="A7XX_SP_LB_1_DATA"/> 31 31 + <value value="43" name="A7XX_SP_LB_2_DATA"/> 32 32 + <value value="44" name="A7XX_SP_LB_3_DATA"/> 33 33 + <value value="45" name="A7XX_SP_LB_4_DATA"/> 34 34 + <value value="46" name="A7XX_SP_LB_5_DATA"/> 35 35 + <value value="47" name="A7XX_SP_LB_6_DATA"/> 36 36 + <value value="48" name="A7XX_SP_LB_7_DATA"/> 37 37 + <value value="49" name="A7XX_SP_CB_RAM"/> 38 38 + <value value="50" name="A7XX_SP_LB_13_DATA"/> 39 39 + <value value="51" name="A7XX_SP_LB_14_DATA"/> 40 40 + <value value="52" name="A7XX_SP_INST_TAG"/> 41 41 + <value value="53" name="A7XX_SP_INST_DATA_2"/> 42 42 + <value value="54" name="A7XX_SP_TMO_TAG"/> 43 43 + <value value="55" name="A7XX_SP_SMO_TAG"/> 44 44 + <value value="56" name="A7XX_SP_STATE_DATA"/> 45 45 + <value value="57" name="A7XX_SP_HWAVE_RAM"/> 46 46 + <value value="58" name="A7XX_SP_L0_INST_BUF"/> 47 47 + <value value="59" name="A7XX_SP_LB_8_DATA"/> 48 48 + <value value="60" name="A7XX_SP_LB_9_DATA"/> 49 49 + <value value="61" name="A7XX_SP_LB_10_DATA"/> 50 50 + <value value="62" name="A7XX_SP_LB_11_DATA"/> 51 51 + <value value="63" name="A7XX_SP_LB_12_DATA"/> 52 52 + <value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/> 53 53 + <value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/> 54 54 + <value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/> 55 55 + <value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/> 56 56 + <value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/> 57 57 + <value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/> 58 58 + <value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/> 59 59 + <value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/> 60 60 + <value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/> 61 61 + <value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/> 62 62 + <value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/> 63 63 + <value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> 64 64 + <value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> 65 65 + <value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/> 66 66 + <value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/> 67 67 + <value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/> 68 68 + <value value="82" name="A7XX_HLSQ_INST_RAM"/> 69 69 + <value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/> 70 70 + <value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/> 71 71 + <value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/> 72 72 + <value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/> 73 73 + <value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/> 74 74 + <value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> 75 75 + <value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> 76 76 + <value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/> 77 77 + <value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/> 78 78 + <value value="92" name="A7XX_HLSQ_INST_RAM_1"/> 79 79 + <value value="93" name="A7XX_HLSQ_STPROC_META"/> 80 80 + <value value="94" name="A7XX_HLSQ_BV_BE_META"/> 81 81 + <value value="95" name="A7XX_HLSQ_INST_RAM_2"/> 82 82 + <value value="96" name="A7XX_HLSQ_DATAPATH_META"/> 83 83 + <value value="97" name="A7XX_HLSQ_FRONTEND_META"/> 84 84 + <value value="98" name="A7XX_HLSQ_INDIRECT_META"/> 85 85 + <value value="99" name="A7XX_HLSQ_BACKEND_META"/> 86 86 + </enum> 87 87 + 88 88 + <enum name="a7xx_state_location"> 89 89 + <value value="0" name="A7XX_HLSQ_STATE"/> 90 90 + <value value="1" name="A7XX_HLSQ_DP"/> 91 91 + <value value="2" name="A7XX_SP_TOP"/> 92 92 + <value value="3" name="A7XX_USPTP"/> 93 93 + <value value="4" name="A7XX_HLSQ_DP_STR"/> 94 94 + </enum> 95 95 + 96 96 + <enum name="a7xx_pipe"> 97 97 + <value value="0" name="A7XX_PIPE_NONE"/> 98 98 + <value value="1" name="A7XX_PIPE_BR"/> 99 99 + <value value="2" name="A7XX_PIPE_BV"/> 100 100 + <value value="3" name="A7XX_PIPE_LPAC"/> 101 101 + </enum> 102 102 + 103 103 + <enum name="a7xx_cluster"> 104 104 + <value value="0" name="A7XX_CLUSTER_NONE"/> 105 105 + <value value="1" name="A7XX_CLUSTER_FE"/> 106 106 + <value value="2" name="A7XX_CLUSTER_SP_VS"/> 107 107 + <value value="3" name="A7XX_CLUSTER_PC_VS"/> 108 108 + <value value="4" name="A7XX_CLUSTER_GRAS"/> 109 109 + <value value="5" name="A7XX_CLUSTER_SP_PS"/> 110 110 + <value value="6" name="A7XX_CLUSTER_VPC_PS"/> 111 111 + <value value="7" name="A7XX_CLUSTER_PS"/> 112 112 + </enum> 113 113 + 114 114 + <enum name="a7xx_debugbus_id"> 115 115 + <value value="1" name="A7XX_DBGBUS_CP_0_0"/> 116 116 + <value value="2" name="A7XX_DBGBUS_CP_0_1"/> 117 117 + <value value="3" name="A7XX_DBGBUS_RBBM"/> 118 118 + <value value="5" name="A7XX_DBGBUS_GBIF_GX"/> 119 119 + <value value="6" name="A7XX_DBGBUS_GBIF_CX"/> 120 120 + <value value="7" name="A7XX_DBGBUS_HLSQ"/> 121 121 + <value value="9" name="A7XX_DBGBUS_UCHE_0"/> 122 122 + <value value="10" name="A7XX_DBGBUS_UCHE_1"/> 123 123 + <value value="13" name="A7XX_DBGBUS_TESS_BR"/> 124 124 + <value value="14" name="A7XX_DBGBUS_TESS_BV"/> 125 125 + <value value="17" name="A7XX_DBGBUS_PC_BR"/> 126 126 + <value value="18" name="A7XX_DBGBUS_PC_BV"/> 127 127 + <value value="21" name="A7XX_DBGBUS_VFDP_BR"/> 128 128 + <value value="22" name="A7XX_DBGBUS_VFDP_BV"/> 129 129 + <value value="25" name="A7XX_DBGBUS_VPC_BR"/> 130 130 + <value value="26" name="A7XX_DBGBUS_VPC_BV"/> 131 131 + <value value="29" name="A7XX_DBGBUS_TSE_BR"/> 132 132 + <value value="30" name="A7XX_DBGBUS_TSE_BV"/> 133 133 + <value value="33" name="A7XX_DBGBUS_RAS_BR"/> 134 134 + <value value="34" name="A7XX_DBGBUS_RAS_BV"/> 135 135 + <value value="37" name="A7XX_DBGBUS_VSC"/> 136 136 + <value value="39" name="A7XX_DBGBUS_COM_0"/> 137 137 + <value value="43" name="A7XX_DBGBUS_LRZ_BR"/> 138 138 + <value value="44" name="A7XX_DBGBUS_LRZ_BV"/> 139 139 + <value value="47" name="A7XX_DBGBUS_UFC_0"/> 140 140 + <value value="48" name="A7XX_DBGBUS_UFC_1"/> 141 141 + <value value="55" name="A7XX_DBGBUS_GMU_GX"/> 142 142 + <value value="59" name="A7XX_DBGBUS_DBGC"/> 143 143 + <value value="60" name="A7XX_DBGBUS_CX"/> 144 144 + <value value="61" name="A7XX_DBGBUS_GMU_CX"/> 145 145 + <value value="62" name="A7XX_DBGBUS_GPC_BR"/> 146 146 + <value value="63" name="A7XX_DBGBUS_GPC_BV"/> 147 147 + <value value="66" name="A7XX_DBGBUS_LARC"/> 148 148 + <value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/> 149 149 + <value value="70" name="A7XX_DBGBUS_RB_0"/> 150 150 + <value value="71" name="A7XX_DBGBUS_RB_1"/> 151 151 + <value value="72" name="A7XX_DBGBUS_RB_2"/> 152 152 + <value value="73" name="A7XX_DBGBUS_RB_3"/> 153 153 + <value value="74" name="A7XX_DBGBUS_RB_4"/> 154 154 + <value value="75" name="A7XX_DBGBUS_RB_5"/> 155 155 + <value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/> 156 156 + <value value="106" name="A7XX_DBGBUS_CCU_0"/> 157 157 + <value value="107" name="A7XX_DBGBUS_CCU_1"/> 158 158 + <value value="108" name="A7XX_DBGBUS_CCU_2"/> 159 159 + <value value="109" name="A7XX_DBGBUS_CCU_3"/> 160 160 + <value value="110" name="A7XX_DBGBUS_CCU_4"/> 161 161 + <value value="111" name="A7XX_DBGBUS_CCU_5"/> 162 162 + <value value="138" name="A7XX_DBGBUS_VFD_BR_0"/> 163 163 + <value value="139" name="A7XX_DBGBUS_VFD_BR_1"/> 164 164 + <value value="140" name="A7XX_DBGBUS_VFD_BR_2"/> 165 165 + <value value="141" name="A7XX_DBGBUS_VFD_BR_3"/> 166 166 + <value value="142" name="A7XX_DBGBUS_VFD_BR_4"/> 167 167 + <value value="143" name="A7XX_DBGBUS_VFD_BR_5"/> 168 168 + <value value="144" name="A7XX_DBGBUS_VFD_BR_6"/> 169 169 + <value value="145" name="A7XX_DBGBUS_VFD_BR_7"/> 170 170 + <value value="202" name="A7XX_DBGBUS_VFD_BV_0"/> 171 171 + <value value="203" name="A7XX_DBGBUS_VFD_BV_1"/> 172 172 + <value value="204" name="A7XX_DBGBUS_VFD_BV_2"/> 173 173 + <value value="205" name="A7XX_DBGBUS_VFD_BV_3"/> 174 174 + <value value="234" name="A7XX_DBGBUS_USP_0"/> 175 175 + <value value="235" name="A7XX_DBGBUS_USP_1"/> 176 176 + <value value="236" name="A7XX_DBGBUS_USP_2"/> 177 177 + <value value="237" name="A7XX_DBGBUS_USP_3"/> 178 178 + <value value="238" name="A7XX_DBGBUS_USP_4"/> 179 179 + <value value="239" name="A7XX_DBGBUS_USP_5"/> 180 180 + <value value="266" name="A7XX_DBGBUS_TP_0"/> 181 181 + <value value="267" name="A7XX_DBGBUS_TP_1"/> 182 182 + <value value="268" name="A7XX_DBGBUS_TP_2"/> 183 183 + <value value="269" name="A7XX_DBGBUS_TP_3"/> 184 184 + <value value="270" name="A7XX_DBGBUS_TP_4"/> 185 185 + <value value="271" name="A7XX_DBGBUS_TP_5"/> 186 186 + <value value="272" name="A7XX_DBGBUS_TP_6"/> 187 187 + <value value="273" name="A7XX_DBGBUS_TP_7"/> 188 188 + <value value="274" name="A7XX_DBGBUS_TP_8"/> 189 189 + <value value="275" name="A7XX_DBGBUS_TP_9"/> 190 190 + <value value="276" name="A7XX_DBGBUS_TP_10"/> 191 191 + <value value="277" name="A7XX_DBGBUS_TP_11"/> 192 192 + <value value="330" name="A7XX_DBGBUS_USPTP_0"/> 193 193 + <value value="331" name="A7XX_DBGBUS_USPTP_1"/> 194 194 + <value value="332" name="A7XX_DBGBUS_USPTP_2"/> 195 195 + <value value="333" name="A7XX_DBGBUS_USPTP_3"/> 196 196 + <value value="334" name="A7XX_DBGBUS_USPTP_4"/> 197 197 + <value value="335" name="A7XX_DBGBUS_USPTP_5"/> 198 198 + <value value="336" name="A7XX_DBGBUS_USPTP_6"/> 199 199 + <value value="337" name="A7XX_DBGBUS_USPTP_7"/> 200 200 + <value value="338" name="A7XX_DBGBUS_USPTP_8"/> 201 201 + <value value="339" name="A7XX_DBGBUS_USPTP_9"/> 202 202 + <value value="340" name="A7XX_DBGBUS_USPTP_10"/> 203 203 + <value value="341" name="A7XX_DBGBUS_USPTP_11"/> 204 204 + <value value="396" name="A7XX_DBGBUS_CCHE_0"/> 205 205 + <value value="397" name="A7XX_DBGBUS_CCHE_1"/> 206 206 + <value value="398" name="A7XX_DBGBUS_CCHE_2"/> 207 207 + <value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/> 208 208 + <value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/> 209 209 + <value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/> 210 210 + <value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/> 211 211 + <value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/> 212 212 + <value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/> 213 213 + <value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/> 214 214 + <value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/> 215 215 + <value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/> 216 216 + <value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/> 217 217 + <value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/> 218 218 + <value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/> 219 219 + <value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/> 220 220 + <value value="447" name="A7XX_DBGBUS_CGC_CORE"/> 221 221 + </enum> 222 222 + 223 223 + </database>

+1030

drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.xml

reviewed

··· 1 1 + <?xml version="1.0" encoding="UTF-8"?> 2 2 + <database xmlns="http://nouveau.freedesktop.org/" 3 3 + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 4 + xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5 5 + <import file="freedreno_copyright.xml"/> 6 6 + <import file="adreno/adreno_common.xml"/> 7 7 + <import file="adreno/adreno_pm4.xml"/> 8 8 + 9 9 + <enum name="a7xx_cp_perfcounter_select"> 10 10 + <value value="0" name="A7XX_PERF_CP_ALWAYS_COUNT"/> 11 11 + <value value="1" name="A7XX_PERF_CP_BUSY_GFX_CORE_IDLE"/> 12 12 + <value value="2" name="A7XX_PERF_CP_BUSY_CYCLES"/> 13 13 + <value value="3" name="A7XX_PERF_CP_NUM_PREEMPTIONS"/> 14 14 + <value value="4" name="A7XX_PERF_CP_PREEMPTION_REACTION_DELAY"/> 15 15 + <value value="5" name="A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 16 16 + <value value="6" name="A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 17 17 + <value value="7" name="A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 18 18 + <value value="8" name="A7XX_PERF_CP_PREDICATED_DRAWS_KILLED"/> 19 19 + <value value="9" name="A7XX_PERF_CP_MODE_SWITCH"/> 20 20 + <value value="10" name="A7XX_PERF_CP_ZPASS_DONE"/> 21 21 + <value value="11" name="A7XX_PERF_CP_CONTEXT_DONE"/> 22 22 + <value value="12" name="A7XX_PERF_CP_CACHE_FLUSH"/> 23 23 + <value value="13" name="A7XX_PERF_CP_LONG_PREEMPTIONS"/> 24 24 + <value value="14" name="A7XX_PERF_CP_SQE_I_CACHE_STARVE"/> 25 25 + <value value="15" name="A7XX_PERF_CP_SQE_IDLE"/> 26 26 + <value value="16" name="A7XX_PERF_CP_SQE_PM4_STARVE_RB_IB"/> 27 27 + <value value="17" name="A7XX_PERF_CP_SQE_PM4_STARVE_SDS"/> 28 28 + <value value="18" name="A7XX_PERF_CP_SQE_MRB_STARVE"/> 29 29 + <value value="19" name="A7XX_PERF_CP_SQE_RRB_STARVE"/> 30 30 + <value value="20" name="A7XX_PERF_CP_SQE_VSD_STARVE"/> 31 31 + <value value="21" name="A7XX_PERF_CP_VSD_DECODE_STARVE"/> 32 32 + <value value="22" name="A7XX_PERF_CP_SQE_PIPE_OUT_STALL"/> 33 33 + <value value="23" name="A7XX_PERF_CP_SQE_SYNC_STALL"/> 34 34 + <value value="24" name="A7XX_PERF_CP_SQE_PM4_WFI_STALL"/> 35 35 + <value value="25" name="A7XX_PERF_CP_SQE_SYS_WFI_STALL"/> 36 36 + <value value="26" name="A7XX_PERF_CP_SQE_T4_EXEC"/> 37 37 + <value value="27" name="A7XX_PERF_CP_SQE_LOAD_STATE_EXEC"/> 38 38 + <value value="28" name="A7XX_PERF_CP_SQE_SAVE_SDS_STATE"/> 39 39 + <value value="29" name="A7XX_PERF_CP_SQE_DRAW_EXEC"/> 40 40 + <value value="30" name="A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> 41 41 + <value value="31" name="A7XX_PERF_CP_SQE_EXEC_PROFILED"/> 42 42 + <value value="32" name="A7XX_PERF_CP_MEMORY_POOL_EMPTY"/> 43 43 + <value value="33" name="A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL"/> 44 44 + <value value="34" name="A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> 45 45 + <value value="35" name="A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> 46 46 + <value value="36" name="A7XX_PERF_CP_AHB_STALL_SQE_GMU"/> 47 47 + <value value="37" name="A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER"/> 48 48 + <value value="38" name="A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER"/> 49 49 + <value value="39" name="A7XX_PERF_CP_CLUSTER0_EMPTY"/> 50 50 + <value value="40" name="A7XX_PERF_CP_CLUSTER1_EMPTY"/> 51 51 + <value value="41" name="A7XX_PERF_CP_CLUSTER2_EMPTY"/> 52 52 + <value value="42" name="A7XX_PERF_CP_CLUSTER3_EMPTY"/> 53 53 + <value value="43" name="A7XX_PERF_CP_CLUSTER4_EMPTY"/> 54 54 + <value value="44" name="A7XX_PERF_CP_CLUSTER5_EMPTY"/> 55 55 + <value value="45" name="A7XX_PERF_CP_PM4_DATA"/> 56 56 + <value value="46" name="A7XX_PERF_CP_PM4_HEADERS"/> 57 57 + <value value="47" name="A7XX_PERF_CP_VBIF_READ_BEATS"/> 58 58 + <value value="48" name="A7XX_PERF_CP_VBIF_WRITE_BEATS"/> 59 59 + <value value="49" name="A7XX_PERF_CP_SQE_INSTR_COUNTER"/> 60 60 + <value value="50" name="A7XX_PERF_CP_RESERVED_50"/> 61 61 + <value value="51" name="A7XX_PERF_CP_RESERVED_51"/> 62 62 + <value value="52" name="A7XX_PERF_CP_RESERVED_52"/> 63 63 + <value value="53" name="A7XX_PERF_CP_RESERVED_53"/> 64 64 + <value value="54" name="A7XX_PERF_CP_RESERVED_54"/> 65 65 + <value value="55" name="A7XX_PERF_CP_RESERVED_55"/> 66 66 + <value value="56" name="A7XX_PERF_CP_RESERVED_56"/> 67 67 + <value value="57" name="A7XX_PERF_CP_RESERVED_57"/> 68 68 + <value value="58" name="A7XX_PERF_CP_RESERVED_58"/> 69 69 + <value value="59" name="A7XX_PERF_CP_RESERVED_59"/> 70 70 + <value value="60" name="A7XX_PERF_CP_CLUSTER0_FULL"/> 71 71 + <value value="61" name="A7XX_PERF_CP_CLUSTER1_FULL"/> 72 72 + <value value="62" name="A7XX_PERF_CP_CLUSTER2_FULL"/> 73 73 + <value value="63" name="A7XX_PERF_CP_CLUSTER3_FULL"/> 74 74 + <value value="64" name="A7XX_PERF_CP_CLUSTER4_FULL"/> 75 75 + <value value="65" name="A7XX_PERF_CP_CLUSTER5_FULL"/> 76 76 + <value value="66" name="A7XX_PERF_CP_CLUSTER6_FULL"/> 77 77 + <value value="67" name="A7XX_PERF_CP_CLUSTER6_EMPTY"/> 78 78 + <value value="68" name="A7XX_PERF_CP_ICACHE_MISSES"/> 79 79 + <value value="69" name="A7XX_PERF_CP_ICACHE_HITS"/> 80 80 + <value value="70" name="A7XX_PERF_CP_ICACHE_STALL"/> 81 81 + <value value="71" name="A7XX_PERF_CP_DCACHE_MISSES"/> 82 82 + <value value="72" name="A7XX_PERF_CP_DCACHE_HITS"/> 83 83 + <value value="73" name="A7XX_PERF_CP_DCACHE_STALLS"/> 84 84 + <value value="74" name="A7XX_PERF_CP_AQE_SQE_STALL"/> 85 85 + <value value="75" name="A7XX_PERF_CP_SQE_AQE_STARVE"/> 86 86 + <value value="76" name="A7XX_PERF_CP_PREEMPT_LATENCY"/> 87 87 + <value value="77" name="A7XX_PERF_CP_SQE_MD8_STALL_CYCLES"/> 88 88 + <value value="78" name="A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES"/> 89 89 + <value value="79" name="A7XX_PERF_CP_AQE_NUM_AS_CHUNKS"/> 90 90 + <value value="80" name="A7XX_PERF_CP_AQE_NUM_MS_CHUNKS"/> 91 91 + </enum> 92 92 + 93 93 + <enum name="a7xx_rbbm_perfcounter_select"> 94 94 + <value value="0" name="A7XX_PERF_RBBM_ALWAYS_COUNT"/> 95 95 + <value value="1" name="A7XX_PERF_RBBM_ALWAYS_ON"/> 96 96 + <value value="2" name="A7XX_PERF_RBBM_TSE_BUSY"/> 97 97 + <value value="3" name="A7XX_PERF_RBBM_RAS_BUSY"/> 98 98 + <value value="4" name="A7XX_PERF_RBBM_PC_DCALL_BUSY"/> 99 99 + <value value="5" name="A7XX_PERF_RBBM_PC_VSD_BUSY"/> 100 100 + <value value="6" name="A7XX_PERF_RBBM_STATUS_MASKED"/> 101 101 + <value value="7" name="A7XX_PERF_RBBM_COM_BUSY"/> 102 102 + <value value="8" name="A7XX_PERF_RBBM_DCOM_BUSY"/> 103 103 + <value value="9" name="A7XX_PERF_RBBM_VBIF_BUSY"/> 104 104 + <value value="10" name="A7XX_PERF_RBBM_VSC_BUSY"/> 105 105 + <value value="11" name="A7XX_PERF_RBBM_TESS_BUSY"/> 106 106 + <value value="12" name="A7XX_PERF_RBBM_UCHE_BUSY"/> 107 107 + <value value="13" name="A7XX_PERF_RBBM_HLSQ_BUSY"/> 108 108 + </enum> 109 109 + 110 110 + <enum name="a7xx_pc_perfcounter_select"> 111 111 + <value value="0" name="A7XX_PERF_PC_BUSY_CYCLES"/> 112 112 + <value value="1" name="A7XX_PERF_PC_WORKING_CYCLES"/> 113 113 + <value value="2" name="A7XX_PERF_PC_STALL_CYCLES_VFD"/> 114 114 + <value value="3" name="A7XX_PERF_PC_RESERVED"/> 115 115 + <value value="4" name="A7XX_PERF_PC_STALL_CYCLES_VPC"/> 116 116 + <value value="5" name="A7XX_PERF_PC_STALL_CYCLES_UCHE"/> 117 117 + <value value="6" name="A7XX_PERF_PC_STALL_CYCLES_TESS"/> 118 118 + <value value="7" name="A7XX_PERF_PC_STALL_CYCLES_VFD_ONLY"/> 119 119 + <value value="8" name="A7XX_PERF_PC_STALL_CYCLES_VPC_ONLY"/> 120 120 + <value value="9" name="A7XX_PERF_PC_PASS1_TF_STALL_CYCLES"/> 121 121 + <value value="10" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_INDEX"/> 122 122 + <value value="11" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> 123 123 + <value value="12" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> 124 124 + <value value="13" name="A7XX_PERF_PC_STARVE_CYCLES_DI"/> 125 125 + <value value="14" name="A7XX_PERF_PC_VIS_STREAMS_LOADED"/> 126 126 + <value value="15" name="A7XX_PERF_PC_INSTANCES"/> 127 127 + <value value="16" name="A7XX_PERF_PC_VPC_PRIMITIVES"/> 128 128 + <value value="17" name="A7XX_PERF_PC_DEAD_PRIM"/> 129 129 + <value value="18" name="A7XX_PERF_PC_LIVE_PRIM"/> 130 130 + <value value="19" name="A7XX_PERF_PC_VERTEX_HITS"/> 131 131 + <value value="20" name="A7XX_PERF_PC_IA_VERTICES"/> 132 132 + <value value="21" name="A7XX_PERF_PC_IA_PRIMITIVES"/> 133 133 + <value value="22" name="A7XX_PERF_PC_RESERVED_22"/> 134 134 + <value value="23" name="A7XX_PERF_PC_HS_INVOCATIONS"/> 135 135 + <value value="24" name="A7XX_PERF_PC_DS_INVOCATIONS"/> 136 136 + <value value="25" name="A7XX_PERF_PC_VS_INVOCATIONS"/> 137 137 + <value value="26" name="A7XX_PERF_PC_GS_INVOCATIONS"/> 138 138 + <value value="27" name="A7XX_PERF_PC_DS_PRIMITIVES"/> 139 139 + <value value="28" name="A7XX_PERF_PC_3D_DRAWCALLS"/> 140 140 + <value value="29" name="A7XX_PERF_PC_2D_DRAWCALLS"/> 141 141 + <value value="30" name="A7XX_PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> 142 142 + <value value="31" name="A7XX_PERF_PC_TESS_BUSY_CYCLES"/> 143 143 + <value value="32" name="A7XX_PERF_PC_TESS_WORKING_CYCLES"/> 144 144 + <value value="33" name="A7XX_PERF_PC_TESS_STALL_CYCLES_PC"/> 145 145 + <value value="34" name="A7XX_PERF_PC_TESS_STARVE_CYCLES_PC"/> 146 146 + <value value="35" name="A7XX_PERF_PC_TESS_SINGLE_PRIM_CYCLES"/> 147 147 + <value value="36" name="A7XX_PERF_PC_TESS_PC_UV_TRANS"/> 148 148 + <value value="37" name="A7XX_PERF_PC_TESS_PC_UV_PATCHES"/> 149 149 + <value value="38" name="A7XX_PERF_PC_TESS_FACTOR_TRANS"/> 150 150 + <value value="39" name="A7XX_PERF_PC_TAG_CHECKED_VERTICES"/> 151 151 + <value value="40" name="A7XX_PERF_PC_MESH_VS_WAVES"/> 152 152 + <value value="41" name="A7XX_PERF_PC_MESH_DRAWS"/> 153 153 + <value value="42" name="A7XX_PERF_PC_MESH_DEAD_DRAWS"/> 154 154 + <value value="43" name="A7XX_PERF_PC_MESH_MVIS_EN_DRAWS"/> 155 155 + <value value="44" name="A7XX_PERF_PC_MESH_DEAD_PRIM"/> 156 156 + <value value="45" name="A7XX_PERF_PC_MESH_LIVE_PRIM"/> 157 157 + <value value="46" name="A7XX_PERF_PC_MESH_PA_EN_PRIM"/> 158 158 + <value value="47" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_MVIS_STREAM"/> 159 159 + <value value="48" name="A7XX_PERF_PC_STARVE_CYCLES_PREDRAW"/> 160 160 + <value value="49" name="A7XX_PERF_PC_STALL_CYCLES_COMPUTE_GFX"/> 161 161 + <value value="50" name="A7XX_PERF_PC_STALL_CYCLES_GFX_COMPUTE"/> 162 162 + <value value="51" name="A7XX_PERF_PC_TESS_PC_MULTI_PATCH_TRANS"/> 163 163 + </enum> 164 164 + 165 165 + <enum name="a7xx_vfd_perfcounter_select"> 166 166 + <value value="0" name="A7XX_PERF_VFD_BUSY_CYCLES"/> 167 167 + <value value="1" name="A7XX_PERF_VFD_STALL_CYCLES_UCHE"/> 168 168 + <value value="2" name="A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> 169 169 + <value value="3" name="A7XX_PERF_VFD_STALL_CYCLES_SP_INFO"/> 170 170 + <value value="4" name="A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR"/> 171 171 + <value value="5" name="A7XX_PERF_VFD_STARVE_CYCLES_UCHE"/> 172 172 + <value value="6" name="A7XX_PERF_VFD_RBUFFER_FULL"/> 173 173 + <value value="7" name="A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL"/> 174 174 + <value value="8" name="A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> 175 175 + <value value="9" name="A7XX_PERF_VFD_NUM_ATTRIBUTES"/> 176 176 + <value value="10" name="A7XX_PERF_VFD_UPPER_SHADER_FIBERS"/> 177 177 + <value value="11" name="A7XX_PERF_VFD_LOWER_SHADER_FIBERS"/> 178 178 + <value value="12" name="A7XX_PERF_VFD_MODE_0_FIBERS"/> 179 179 + <value value="13" name="A7XX_PERF_VFD_MODE_1_FIBERS"/> 180 180 + <value value="14" name="A7XX_PERF_VFD_MODE_2_FIBERS"/> 181 181 + <value value="15" name="A7XX_PERF_VFD_MODE_3_FIBERS"/> 182 182 + <value value="16" name="A7XX_PERF_VFD_MODE_4_FIBERS"/> 183 183 + <value value="17" name="A7XX_PERF_VFD_TOTAL_VERTICES"/> 184 184 + <value value="18" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD"/> 185 185 + <value value="19" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> 186 186 + <value value="20" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG"/> 187 187 + <value value="21" name="A7XX_PERF_VFDP_STARVE_CYCLES_PC"/> 188 188 + <value value="22" name="A7XX_PERF_VFDP_VS_STAGE_WAVES"/> 189 189 + <value value="23" name="A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE"/> 190 190 + <value value="24" name="A7XX_PERF_VFD_STALL_CYCLES_CBSYNC"/> 191 191 + </enum> 192 192 + 193 193 + <enum name="a7xx_hlsq_perfcounter_select"> 194 194 + <value value="0" name="A7XX_PERF_HLSQ_BUSY_CYCLES"/> 195 195 + <value value="1" name="A7XX_PERF_HLSQ_STALL_CYCLES_UCHE"/> 196 196 + <value value="2" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE"/> 197 197 + <value value="3" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> 198 198 + <value value="4" name="A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES"/> 199 199 + <value value="5" name="A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT"/> 200 200 + <value value="6" name="A7XX_PERF_HLSQ_RESERVED_6"/> 201 201 + <value value="7" name="A7XX_PERF_HLSQ_RESERVED_7"/> 202 202 + <value value="8" name="A7XX_PERF_HLSQ_RESERVED_8"/> 203 203 + <value value="9" name="A7XX_PERF_HLSQ_RESERVED_9"/> 204 204 + <value value="10" name="A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS"/> 205 205 + <value value="11" name="A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> 206 206 + <value value="12" name="A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> 207 207 + <value value="13" name="A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> 208 208 + <value value="14" name="A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> 209 209 + <value value="15" name="A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> 210 210 + <value value="16" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> 211 211 + <value value="17" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> 212 212 + <value value="18" name="A7XX_PERF_HLSQ_STALL_CYCLES_VPC"/> 213 213 + <value value="19" name="A7XX_PERF_HLSQ_RESERVED_19"/> 214 214 + <value value="20" name="A7XX_PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> 215 215 + <value value="21" name="A7XX_PERF_HLSQ_VSBR_STALL_CYCLES"/> 216 216 + <value value="22" name="A7XX_PERF_HLSQ_FS_STALL_CYCLES"/> 217 217 + <value value="23" name="A7XX_PERF_HLSQ_LPAC_STALL_CYCLES"/> 218 218 + <value value="24" name="A7XX_PERF_HLSQ_BV_STALL_CYCLES"/> 219 219 + <value value="25" name="A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES"/> 220 220 + <value value="26" name="A7XX_PERF_HLSQ_FS_DEREF_CYCLES"/> 221 221 + <value value="27" name="A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES"/> 222 222 + <value value="28" name="A7XX_PERF_HLSQ_BV_DEREF_CYCLES"/> 223 223 + <value value="29" name="A7XX_PERF_HLSQ_VSBR_S2W_CYCLES"/> 224 224 + <value value="30" name="A7XX_PERF_HLSQ_FS_S2W_CYCLES"/> 225 225 + <value value="31" name="A7XX_PERF_HLSQ_LPAC_S2W_CYCLES"/> 226 226 + <value value="32" name="A7XX_PERF_HLSQ_BV_S2W_CYCLES"/> 227 227 + <value value="33" name="A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W"/> 228 228 + <value value="34" name="A7XX_PERF_HLSQ_FS_WAIT_VS_S2W"/> 229 229 + <value value="35" name="A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W"/> 230 230 + <value value="36" name="A7XX_PERF_HLSQ_BV_WAIT_FS_S2W"/> 231 231 + <value value="37" name="A7XX_PERF_HLSQ_VS_WAIT_CONST_RESOURCE"/> 232 232 + <value value="38" name="A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W"/> 233 233 + <value value="39" name="A7XX_PERF_HLSQ_FS_STARVING_SP"/> 234 234 + <value value="40" name="A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING"/> 235 235 + <value value="41" name="A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING"/> 236 236 + <value value="42" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS"/> 237 237 + <value value="43" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS"/> 238 238 + <value value="44" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS"/> 239 239 + <value value="45" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS"/> 240 240 + <value value="46" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV"/> 241 241 + <value value="47" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV"/> 242 242 + <value value="48" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC"/> 243 243 + <value value="49" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC"/> 244 244 + <value value="50" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS"/> 245 245 + <value value="51" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS"/> 246 246 + <value value="52" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV"/> 247 247 + <value value="53" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC"/> 248 248 + <value value="54" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS"/> 249 249 + <value value="55" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS"/> 250 250 + <value value="56" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV"/> 251 251 + <value value="57" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC"/> 252 252 + </enum> 253 253 + 254 254 + <enum name="a7xx_vpc_perfcounter_select"> 255 255 + <value value="0" name="A7XX_PERF_VPC_BUSY_CYCLES"/> 256 256 + <value value="1" name="A7XX_PERF_VPC_WORKING_CYCLES"/> 257 257 + <value value="2" name="A7XX_PERF_VPC_STALL_CYCLES_UCHE"/> 258 258 + <value value="3" name="A7XX_PERF_VPC_STALL_CYCLES_VFD_WACK"/> 259 259 + <value value="4" name="A7XX_PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> 260 260 + <value value="5" name="A7XX_PERF_VPC_RESERVED_5"/> 261 261 + <value value="6" name="A7XX_PERF_VPC_STALL_CYCLES_SP_LM"/> 262 262 + <value value="7" name="A7XX_PERF_VPC_STARVE_CYCLES_SP"/> 263 263 + <value value="8" name="A7XX_PERF_VPC_STARVE_CYCLES_LRZ"/> 264 264 + <value value="9" name="A7XX_PERF_VPC_PC_PRIMITIVES"/> 265 265 + <value value="10" name="A7XX_PERF_VPC_SP_COMPONENTS"/> 266 266 + <value value="11" name="A7XX_PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> 267 267 + <value value="12" name="A7XX_PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> 268 268 + <value value="13" name="A7XX_PERF_VPC_RB_VISIBLE_PRIMITIVES"/> 269 269 + <value value="14" name="A7XX_PERF_VPC_LM_TRANSACTION"/> 270 270 + <value value="15" name="A7XX_PERF_VPC_STREAMOUT_TRANSACTION"/> 271 271 + <value value="16" name="A7XX_PERF_VPC_VS_BUSY_CYCLES"/> 272 272 + <value value="17" name="A7XX_PERF_VPC_PS_BUSY_CYCLES"/> 273 273 + <value value="18" name="A7XX_PERF_VPC_VS_WORKING_CYCLES"/> 274 274 + <value value="19" name="A7XX_PERF_VPC_PS_WORKING_CYCLES"/> 275 275 + <value value="20" name="A7XX_PERF_VPC_STARVE_CYCLES_RB"/> 276 276 + <value value="21" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_POS"/> 277 277 + <value value="22" name="A7XX_PERF_VPC_WIT_FULL_CYCLES"/> 278 278 + <value value="23" name="A7XX_PERF_VPC_VPCRAM_FULL_CYCLES"/> 279 279 + <value value="24" name="A7XX_PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> 280 280 + <value value="25" name="A7XX_PERF_VPC_NUM_VPCRAM_WRITE"/> 281 281 + <value value="26" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_SO"/> 282 282 + <value value="27" name="A7XX_PERF_VPC_NUM_ATTR_REQ_LM"/> 283 283 + <value value="28" name="A7XX_PERF_VPC_STALL_CYCLE_TSE"/> 284 284 + <value value="29" name="A7XX_PERF_VPC_TSE_PRIMITIVES"/> 285 285 + <value value="30" name="A7XX_PERF_VPC_GS_PRIMITIVES"/> 286 286 + <value value="31" name="A7XX_PERF_VPC_TSE_TRANSACTIONS"/> 287 287 + <value value="32" name="A7XX_PERF_VPC_STALL_CYCLES_CCU"/> 288 288 + <value value="33" name="A7XX_PERF_VPC_NUM_WM_HIT"/> 289 289 + <value value="34" name="A7XX_PERF_VPC_STALL_DQ_WACK"/> 290 290 + <value value="35" name="A7XX_PERF_VPC_STALL_CYCLES_CCHE"/> 291 291 + <value value="36" name="A7XX_PERF_VPC_STARVE_CYCLES_CCHE"/> 292 292 + <value value="37" name="A7XX_PERF_VPC_NUM_PA_REQ"/> 293 293 + <value value="38" name="A7XX_PERF_VPC_NUM_LM_REQ_HIT"/> 294 294 + <value value="39" name="A7XX_PERF_VPC_CCHE_REQBUF_FULL"/> 295 295 + <value value="40" name="A7XX_PERF_VPC_STALL_CYCLES_LM_ACK"/> 296 296 + <value value="41" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_FE"/> 297 297 + <value value="42" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_PCVS"/> 298 298 + <value value="43" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_VPCPS"/> 299 299 + </enum> 300 300 + 301 301 + <enum name="a7xx_tse_perfcounter_select"> 302 302 + <value value="0" name="A7XX_PERF_TSE_BUSY_CYCLES"/> 303 303 + <value value="1" name="A7XX_PERF_TSE_CLIPPING_CYCLES"/> 304 304 + <value value="2" name="A7XX_PERF_TSE_STALL_CYCLES_RAS"/> 305 305 + <value value="3" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> 306 306 + <value value="4" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> 307 307 + <value value="5" name="A7XX_PERF_TSE_STARVE_CYCLES_PC"/> 308 308 + <value value="6" name="A7XX_PERF_TSE_INPUT_PRIM"/> 309 309 + <value value="7" name="A7XX_PERF_TSE_INPUT_NULL_PRIM"/> 310 310 + <value value="8" name="A7XX_PERF_TSE_TRIVAL_REJ_PRIM"/> 311 311 + <value value="9" name="A7XX_PERF_TSE_CLIPPED_PRIM"/> 312 312 + <value value="10" name="A7XX_PERF_TSE_ZERO_AREA_PRIM"/> 313 313 + <value value="11" name="A7XX_PERF_TSE_FACENESS_CULLED_PRIM"/> 314 314 + <value value="12" name="A7XX_PERF_TSE_ZERO_PIXEL_PRIM"/> 315 315 + <value value="13" name="A7XX_PERF_TSE_OUTPUT_NULL_PRIM"/> 316 316 + <value value="14" name="A7XX_PERF_TSE_OUTPUT_VISIBLE_PRIM"/> 317 317 + <value value="15" name="A7XX_PERF_TSE_CINVOCATION"/> 318 318 + <value value="16" name="A7XX_PERF_TSE_CPRIMITIVES"/> 319 319 + <value value="17" name="A7XX_PERF_TSE_2D_INPUT_PRIM"/> 320 320 + <value value="18" name="A7XX_PERF_TSE_2D_ALIVE_CYCLES"/> 321 321 + <value value="19" name="A7XX_PERF_TSE_CLIP_PLANES"/> 322 322 + </enum> 323 323 + 324 324 + <enum name="a7xx_ras_perfcounter_select"> 325 325 + <value value="0" name="A7XX_PERF_RAS_BUSY_CYCLES"/> 326 326 + <value value="1" name="A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> 327 327 + <value value="2" name="A7XX_PERF_RAS_STALL_CYCLES_LRZ"/> 328 328 + <value value="3" name="A7XX_PERF_RAS_STARVE_CYCLES_TSE"/> 329 329 + <value value="4" name="A7XX_PERF_RAS_SUPER_TILES"/> 330 330 + <value value="5" name="A7XX_PERF_RAS_8X4_TILES"/> 331 331 + <value value="6" name="A7XX_PERF_RAS_MASKGEN_ACTIVE"/> 332 332 + <value value="7" name="A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES"/> 333 333 + <value value="8" name="A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES"/> 334 334 + <value value="9" name="A7XX_PERF_RAS_PRIM_KILLED_INVISILBE"/> 335 335 + <value value="10" name="A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> 336 336 + <value value="11" name="A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> 337 337 + <value value="12" name="A7XX_PERF_RAS_BLOCKS"/> 338 338 + <value value="13" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_l2"/> 339 339 + <value value="14" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_l2"/> 340 340 + <value value="15" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_l2"/> 341 341 + <value value="16" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_l2"/> 342 342 + <value value="17" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_l2"/> 343 343 + <value value="18" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_l2"/> 344 344 + <value value="19" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_l2"/> 345 345 + <value value="20" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_l2"/> 346 346 + <value value="21" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_l2"/> 347 347 + <value value="22" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_l2"/> 348 348 + <value value="23" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_l2"/> 349 349 + <value value="24" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_l2"/> 350 350 + <value value="25" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_l2"/> 351 351 + <value value="26" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_l2"/> 352 352 + <value value="27" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_l2"/> 353 353 + <value value="28" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_l2"/> 354 354 + <value value="29" name="A7XX_PERF_RAS_FALSE_PARTIAL_STILE"/> 355 355 + 356 356 + </enum> 357 357 + 358 358 + <enum name="a7xx_uche_perfcounter_select"> 359 359 + <value value="0" name="A7XX_PERF_UCHE_BUSY_CYCLES"/> 360 360 + <value value="1" name="A7XX_PERF_UCHE_STALL_CYCLES_ARBITER"/> 361 361 + <value value="2" name="A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES"/> 362 362 + <value value="3" name="A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES"/> 363 363 + <value value="4" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_TP"/> 364 364 + <value value="5" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD"/> 365 365 + <value value="6" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> 366 366 + <value value="7" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ"/> 367 367 + <value value="8" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_SP"/> 368 368 + <value value="9" name="A7XX_PERF_UCHE_READ_REQUESTS_TP"/> 369 369 + <value value="10" name="A7XX_PERF_UCHE_READ_REQUESTS_VFD"/> 370 370 + <value value="11" name="A7XX_PERF_UCHE_READ_REQUESTS_HLSQ"/> 371 371 + <value value="12" name="A7XX_PERF_UCHE_READ_REQUESTS_LRZ"/> 372 372 + <value value="13" name="A7XX_PERF_UCHE_READ_REQUESTS_SP"/> 373 373 + <value value="14" name="A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ"/> 374 374 + <value value="15" name="A7XX_PERF_UCHE_WRITE_REQUESTS_SP"/> 375 375 + <value value="16" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VPC"/> 376 376 + <value value="17" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VSC"/> 377 377 + <value value="18" name="A7XX_PERF_UCHE_EVICTS"/> 378 378 + <value value="19" name="A7XX_PERF_UCHE_BANK_REQ0"/> 379 379 + <value value="20" name="A7XX_PERF_UCHE_BANK_REQ1"/> 380 380 + <value value="21" name="A7XX_PERF_UCHE_BANK_REQ2"/> 381 381 + <value value="22" name="A7XX_PERF_UCHE_BANK_REQ3"/> 382 382 + <value value="23" name="A7XX_PERF_UCHE_BANK_REQ4"/> 383 383 + <value value="24" name="A7XX_PERF_UCHE_BANK_REQ5"/> 384 384 + <value value="25" name="A7XX_PERF_UCHE_BANK_REQ6"/> 385 385 + <value value="26" name="A7XX_PERF_UCHE_BANK_REQ7"/> 386 386 + <value value="27" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0"/> 387 387 + <value value="28" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1"/> 388 388 + <value value="29" name="A7XX_PERF_UCHE_GMEM_READ_BEATS"/> 389 389 + <value value="30" name="A7XX_PERF_UCHE_TPH_REF_FULL"/> 390 390 + <value value="31" name="A7XX_PERF_UCHE_TPH_VICTIM_FULL"/> 391 391 + <value value="32" name="A7XX_PERF_UCHE_TPH_EXT_FULL"/> 392 392 + <value value="33" name="A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA"/> 393 393 + <value value="34" name="A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES"/> 394 394 + <value value="35" name="A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES"/> 395 395 + <value value="36" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_PC"/> 396 396 + <value value="37" name="A7XX_PERF_UCHE_READ_REQUESTS_PC"/> 397 397 + <value value="38" name="A7XX_PERF_UCHE_RAM_READ_REQ"/> 398 398 + <value value="39" name="A7XX_PERF_UCHE_RAM_WRITE_REQ"/> 399 399 + <value value="40" name="A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP"/> 400 400 + <value value="41" name="A7XX_PERF_UCHE_STALL_CYCLES_DECMP"/> 401 401 + <value value="42" name="A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF"/> 402 402 + <value value="43" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC"/> 403 403 + <value value="44" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_NONUBWC"/> 404 404 + <value value="45" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM"/> 405 405 + <value value="46" name="A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS_KAILUA"/> 406 406 + <value value="47" name="A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS_KAILUA"/> 407 407 + <value value="48" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE"/> 408 408 + <value value="49" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER_KAILUA"/> 409 409 + <value value="50" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE"/> 410 410 + <value value="51" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS"/> 411 411 + <value value="52" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0"/> 412 412 + <value value="53" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1"/> 413 413 + <value value="54" name="A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL"/> 414 414 + <value value="55" name="A7XX_PERF_UCHE_CCHE_DPH_QUEUE_FULL"/> 415 415 + <value value="56" name="A7XX_PERF_UCHE_GMEM_WRITE_BEATS"/> 416 416 + <value value="57" name="A7XX_PERF_UCHE_UBWC_READ_BEATS"/> 417 417 + <value value="58" name="A7XX_PERF_UCHE_UBWC_WRITE_BEATS"/> 418 418 + </enum> 419 419 + 420 420 + <enum name="a7xx_tp_perfcounter_select"> 421 421 + <value value="0" name="A7XX_PERF_TP_BUSY_CYCLES"/> 422 422 + <value value="1" name="A7XX_PERF_TP_STALL_CYCLES_UCHE"/> 423 423 + <value value="2" name="A7XX_PERF_TP_LATENCY_CYCLES"/> 424 424 + <value value="3" name="A7XX_PERF_TP_LATENCY_TRANS"/> 425 425 + <value value="4" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES"/> 426 426 + <value value="5" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES"/> 427 427 + <value value="6" name="A7XX_PERF_TP_L1_CACHELINE_REQUESTS"/> 428 428 + <value value="7" name="A7XX_PERF_TP_L1_CACHELINE_MISSES"/> 429 429 + <value value="8" name="A7XX_PERF_TP_SP_TP_TRANS"/> 430 430 + <value value="9" name="A7XX_PERF_TP_TP_SP_TRANS"/> 431 431 + <value value="10" name="A7XX_PERF_TP_OUTPUT_PIXELS"/> 432 432 + <value value="11" name="A7XX_PERF_TP_FILTER_WORKLOAD_16BIT"/> 433 433 + <value value="12" name="A7XX_PERF_TP_FILTER_WORKLOAD_32BIT"/> 434 434 + <value value="13" name="A7XX_PERF_TP_QUADS_RECEIVED"/> 435 435 + <value value="14" name="A7XX_PERF_TP_QUADS_OFFSET"/> 436 436 + <value value="15" name="A7XX_PERF_TP_QUADS_SHADOW"/> 437 437 + <value value="16" name="A7XX_PERF_TP_QUADS_ARRAY"/> 438 438 + <value value="17" name="A7XX_PERF_TP_QUADS_GRADIENT"/> 439 439 + <value value="18" name="A7XX_PERF_TP_QUADS_1D"/> 440 440 + <value value="19" name="A7XX_PERF_TP_QUADS_2D"/> 441 441 + <value value="20" name="A7XX_PERF_TP_QUADS_BUFFER"/> 442 442 + <value value="21" name="A7XX_PERF_TP_QUADS_3D"/> 443 443 + <value value="22" name="A7XX_PERF_TP_QUADS_CUBE"/> 444 444 + <value value="23" name="A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED"/> 445 445 + <value value="24" name="A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS"/> 446 446 + <value value="25" name="A7XX_PERF_TP_OUTPUT_PIXELS_POINT"/> 447 447 + <value value="26" name="A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR"/> 448 448 + <value value="27" name="A7XX_PERF_TP_OUTPUT_PIXELS_MIP"/> 449 449 + <value value="28" name="A7XX_PERF_TP_OUTPUT_PIXELS_ANISO"/> 450 450 + <value value="29" name="A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> 451 451 + <value value="30" name="A7XX_PERF_TP_FLAG_CACHE_REQUESTS"/> 452 452 + <value value="31" name="A7XX_PERF_TP_FLAG_CACHE_MISSES"/> 453 453 + <value value="32" name="A7XX_PERF_TP_L1_5_L2_REQUESTS"/> 454 454 + <value value="33" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS"/> 455 455 + <value value="34" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT"/> 456 456 + <value value="35" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> 457 457 + <value value="36" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> 458 458 + <value value="37" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> 459 459 + <value value="38" name="A7XX_PERF_TP_TPA2TPC_TRANS"/> 460 460 + <value value="39" name="A7XX_PERF_TP_L1_MISSES_ASTC_1TILE"/> 461 461 + <value value="40" name="A7XX_PERF_TP_L1_MISSES_ASTC_2TILE"/> 462 462 + <value value="41" name="A7XX_PERF_TP_L1_MISSES_ASTC_4TILE"/> 463 463 + <value value="42" name="A7XX_PERF_TP_L1_5_COMPRESS_REQS"/> 464 464 + <value value="43" name="A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS"/> 465 465 + <value value="44" name="A7XX_PERF_TP_L1_BANK_CONFLICT"/> 466 466 + <value value="45" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> 467 467 + <value value="46" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS"/> 468 468 + <value value="47" name="A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> 469 469 + <value value="48" name="A7XX_PERF_TP_FRONTEND_WORKING_CYCLES"/> 470 470 + <value value="49" name="A7XX_PERF_TP_L1_TAG_WORKING_CYCLES"/> 471 471 + <value value="50" name="A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> 472 472 + <value value="51" name="A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> 473 473 + <value value="52" name="A7XX_PERF_TP_BACKEND_WORKING_CYCLES"/> 474 474 + <value value="53" name="A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> 475 475 + <value value="54" name="A7XX_PERF_TP_STARVE_CYCLES_SP"/> 476 476 + <value value="55" name="A7XX_PERF_TP_STARVE_CYCLES_UCHE"/> 477 477 + <value value="56" name="A7XX_PERF_TP_STALL_CYCLES_UFC"/> 478 478 + <value value="57" name="A7XX_PERF_TP_FORMAT_DECOMP"/> 479 479 + <value value="58" name="A7XX_PERF_TP_FILTER_POINT_FP16"/> 480 480 + <value value="59" name="A7XX_PERF_TP_FILTER_POINT_FP32"/> 481 481 + <value value="60" name="A7XX_PERF_TP_LATENCY_FIFO_FULL"/> 482 482 + <value value="61" name="A7XX_PERF_TP_RESERVED_61"/> 483 483 + <value value="62" name="A7XX_PERF_TP_RESERVED_62"/> 484 484 + <value value="63" name="A7XX_PERF_TP_RESERVED_63"/> 485 485 + <value value="64" name="A7XX_PERF_TP_RESERVED_64"/> 486 486 + <value value="65" name="A7XX_PERF_TP_RESERVED_65"/> 487 487 + <value value="66" name="A7XX_PERF_TP_RESERVED_66"/> 488 488 + <value value="67" name="A7XX_PERF_TP_RESERVED_67"/> 489 489 + <value value="68" name="A7XX_PERF_TP_RESERVED_68"/> 490 490 + <value value="69" name="A7XX_PERF_TP_RESERVED_69"/> 491 491 + <value value="70" name="A7XX_PERF_TP_RESERVED_70"/> 492 492 + <value value="71" name="A7XX_PERF_TP_RESERVED_71"/> 493 493 + <value value="72" name="A7XX_PERF_TP_RESERVED_72"/> 494 494 + <value value="73" name="A7XX_PERF_TP_RESERVED_73"/> 495 495 + <value value="74" name="A7XX_PERF_TP_RESERVED_74"/> 496 496 + <value value="75" name="A7XX_PERF_TP_RESERVED_75"/> 497 497 + <value value="76" name="A7XX_PERF_TP_RESERVED_76"/> 498 498 + <value value="77" name="A7XX_PERF_TP_RESERVED_77"/> 499 499 + <value value="78" name="A7XX_PERF_TP_RESERVED_78"/> 500 500 + <value value="79" name="A7XX_PERF_TP_RESERVED_79"/> 501 501 + <value value="80" name="A7XX_PERF_TP_RESERVED_80"/> 502 502 + <value value="81" name="A7XX_PERF_TP_RESERVED_81"/> 503 503 + <value value="82" name="A7XX_PERF_TP_RESERVED_82"/> 504 504 + <value value="83" name="A7XX_PERF_TP_RESERVED_83"/> 505 505 + <value value="84" name="A7XX_PERF_TP_RESERVED_84"/> 506 506 + <value value="85" name="A7XX_PERF_TP_RESERVED_85"/> 507 507 + <value value="86" name="A7XX_PERF_TP_RESERVED_86"/> 508 508 + <value value="87" name="A7XX_PERF_TP_RESERVED_87"/> 509 509 + <value value="88" name="A7XX_PERF_TP_RESERVED_88"/> 510 510 + <value value="89" name="A7XX_PERF_TP_RESERVED_89"/> 511 511 + <value value="90" name="A7XX_PERF_TP_RESERVED_90"/> 512 512 + <value value="91" name="A7XX_PERF_TP_RESERVED_91"/> 513 513 + <value value="92" name="A7XX_PERF_TP_RESERVED_92"/> 514 514 + <value value="93" name="A7XX_PERF_TP_RESERVED_93"/> 515 515 + <value value="94" name="A7XX_PERF_TP_RESERVED_94"/> 516 516 + <value value="95" name="A7XX_PERF_TP_RESERVED_95"/> 517 517 + <value value="96" name="A7XX_PERF_TP_RESERVED_96"/> 518 518 + <value value="97" name="A7XX_PERF_TP_RESERVED_97"/> 519 519 + <value value="98" name="A7XX_PERF_TP_RESERVED_98"/> 520 520 + <value value="99" name="A7XX_PERF_TP_RESERVED_99"/> 521 521 + <value value="100" name="A7XX_PERF_TP_RESERVED_100"/> 522 522 + <value value="101" name="A7XX_PERF_TP_RESERVED_101"/> 523 523 + <value value="102" name="A7XX_PERF_TP_RESERVED_102"/> 524 524 + <value value="103" name="A7XX_PERF_TP_RESERVED_103"/> 525 525 + <value value="104" name="A7XX_PERF_TP_RESERVED_104"/> 526 526 + <value value="105" name="A7XX_PERF_TP_RESERVED_105"/> 527 527 + <value value="106" name="A7XX_PERF_TP_RESERVED_106"/> 528 528 + <value value="107" name="A7XX_PERF_TP_RESERVED_107"/> 529 529 + <value value="108" name="A7XX_PERF_TP_RESERVED_108"/> 530 530 + <value value="109" name="A7XX_PERF_TP_RESERVED_109"/> 531 531 + <value value="110" name="A7XX_PERF_TP_RESERVED_110"/> 532 532 + <value value="111" name="A7XX_PERF_TP_RESERVED_111"/> 533 533 + <value value="112" name="A7XX_PERF_TP_RESERVED_112"/> 534 534 + <value value="113" name="A7XX_PERF_TP_RESERVED_113"/> 535 535 + <value value="114" name="A7XX_PERF_TP_RESERVED_114"/> 536 536 + <value value="115" name="A7XX_PERF_TP_RESERVED_115"/> 537 537 + <value value="116" name="A7XX_PERF_TP_RESERVED_116"/> 538 538 + <value value="117" name="A7XX_PERF_TP_RESERVED_117"/> 539 539 + <value value="118" name="A7XX_PERF_TP_RESERVED_118"/> 540 540 + <value value="119" name="A7XX_PERF_TP_RESERVED_119"/> 541 541 + <value value="120" name="A7XX_PERF_TP_RESERVED_120"/> 542 542 + <value value="121" name="A7XX_PERF_TP_RESERVED_121"/> 543 543 + <value value="122" name="A7XX_PERF_TP_RESERVED_122"/> 544 544 + <value value="123" name="A7XX_PERF_TP_RESERVED_123"/> 545 545 + <value value="124" name="A7XX_PERF_TP_RESERVED_124"/> 546 546 + <value value="125" name="A7XX_PERF_TP_RESERVED_125"/> 547 547 + <value value="126" name="A7XX_PERF_TP_RESERVED_126"/> 548 548 + <value value="127" name="A7XX_PERF_TP_RESERVED_127"/> 549 549 + <value value="128" name="A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR"/> 550 550 + <value value="129" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16"/> 551 551 + <value value="130" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16"/> 552 552 + <value value="131" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32"/> 553 553 + <value value="132" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32"/> 554 554 + </enum> 555 555 + 556 556 + <enum name="a7xx_sp_perfcounter_select"> 557 557 + <value value="0" name="A7XX_PERF_SP_BUSY_CYCLES"/> 558 558 + <value value="1" name="A7XX_PERF_SP_ALU_WORKING_CYCLES"/> 559 559 + <value value="2" name="A7XX_PERF_SP_EFU_WORKING_CYCLES"/> 560 560 + <value value="3" name="A7XX_PERF_SP_STALL_CYCLES_VPC"/> 561 561 + <value value="4" name="A7XX_PERF_SP_STALL_CYCLES_TP"/> 562 562 + <value value="5" name="A7XX_PERF_SP_STALL_CYCLES_UCHE"/> 563 563 + <value value="6" name="A7XX_PERF_SP_STALL_CYCLES_RB"/> 564 564 + <value value="7" name="A7XX_PERF_SP_NON_EXECUTION_CYCLES"/> 565 565 + <value value="8" name="A7XX_PERF_SP_WAVE_CONTEXTS"/> 566 566 + <value value="9" name="A7XX_PERF_SP_WAVE_CONTEXT_CYCLES"/> 567 567 + <value value="10" name="A7XX_PERF_SP_STAGE_WAVE_CYCLES"/> 568 568 + <value value="11" name="A7XX_PERF_SP_STAGE_WAVE_SAMPLES"/> 569 569 + <value value="12" name="A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES"/> 570 570 + <value value="13" name="A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES"/> 571 571 + <value value="14" name="A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES"/> 572 572 + <value value="15" name="A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES"/> 573 573 + <value value="16" name="A7XX_PERF_SP_WAVE_CTRL_CYCLES"/> 574 574 + <value value="17" name="A7XX_PERF_SP_WAVE_LOAD_CYCLES"/> 575 575 + <value value="18" name="A7XX_PERF_SP_WAVE_EMIT_CYCLES"/> 576 576 + <value value="19" name="A7XX_PERF_SP_WAVE_NOP_CYCLES"/> 577 577 + <value value="20" name="A7XX_PERF_SP_WAVE_WAIT_CYCLES"/> 578 578 + <value value="21" name="A7XX_PERF_SP_WAVE_FETCH_CYCLES"/> 579 579 + <value value="22" name="A7XX_PERF_SP_WAVE_IDLE_CYCLES"/> 580 580 + <value value="23" name="A7XX_PERF_SP_WAVE_END_CYCLES"/> 581 581 + <value value="24" name="A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES"/> 582 582 + <value value="25" name="A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> 583 583 + <value value="26" name="A7XX_PERF_SP_WAVE_JOIN_CYCLES"/> 584 584 + <value value="27" name="A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS"/> 585 585 + <value value="28" name="A7XX_PERF_SP_LM_STORE_INSTRUCTIONS"/> 586 586 + <value value="29" name="A7XX_PERF_SP_LM_ATOMICS"/> 587 587 + <value value="30" name="A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS"/> 588 588 + <value value="31" name="A7XX_PERF_SP_GM_STORE_INSTRUCTIONS"/> 589 589 + <value value="32" name="A7XX_PERF_SP_GM_ATOMICS"/> 590 590 + <value value="33" name="A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> 591 591 + <value value="34" name="A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> 592 592 + <value value="35" name="A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> 593 593 + <value value="36" name="A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> 594 594 + <value value="37" name="A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> 595 595 + <value value="38" name="A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> 596 596 + <value value="39" name="A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> 597 597 + <value value="40" name="A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> 598 598 + <value value="41" name="A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> 599 599 + <value value="42" name="A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> 600 600 + <value value="43" name="A7XX_PERF_SP_VS_INSTRUCTIONS"/> 601 601 + <value value="44" name="A7XX_PERF_SP_FS_INSTRUCTIONS"/> 602 602 + <value value="45" name="A7XX_PERF_SP_ADDR_LOCK_COUNT"/> 603 603 + <value value="46" name="A7XX_PERF_SP_UCHE_READ_TRANS"/> 604 604 + <value value="47" name="A7XX_PERF_SP_UCHE_WRITE_TRANS"/> 605 605 + <value value="48" name="A7XX_PERF_SP_EXPORT_VPC_TRANS"/> 606 606 + <value value="49" name="A7XX_PERF_SP_EXPORT_RB_TRANS"/> 607 607 + <value value="50" name="A7XX_PERF_SP_PIXELS_KILLED"/> 608 608 + <value value="51" name="A7XX_PERF_SP_ICL1_REQUESTS"/> 609 609 + <value value="52" name="A7XX_PERF_SP_ICL1_MISSES"/> 610 610 + <value value="53" name="A7XX_PERF_SP_HS_INSTRUCTIONS"/> 611 611 + <value value="54" name="A7XX_PERF_SP_DS_INSTRUCTIONS"/> 612 612 + <value value="55" name="A7XX_PERF_SP_GS_INSTRUCTIONS"/> 613 613 + <value value="56" name="A7XX_PERF_SP_CS_INSTRUCTIONS"/> 614 614 + <value value="57" name="A7XX_PERF_SP_GPR_READ"/> 615 615 + <value value="58" name="A7XX_PERF_SP_GPR_WRITE"/> 616 616 + <value value="59" name="A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> 617 617 + <value value="60" name="A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> 618 618 + <value value="61" name="A7XX_PERF_SP_LM_BANK_CONFLICTS"/> 619 619 + <value value="62" name="A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> 620 620 + <value value="63" name="A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> 621 621 + <value value="64" name="A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> 622 622 + <value value="65" name="A7XX_PERF_SP_LM_WORKING_CYCLES"/> 623 623 + <value value="66" name="A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES"/> 624 624 + <value value="67" name="A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES"/> 625 625 + <value value="68" name="A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> 626 626 + <value value="69" name="A7XX_PERF_SP_STARVE_CYCLES_HLSQ"/> 627 627 + <value value="70" name="A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES"/> 628 628 + <value value="71" name="A7XX_PERF_SP_WORKING_EU"/> 629 629 + <value value="72" name="A7XX_PERF_SP_ANY_EU_WORKING"/> 630 630 + <value value="73" name="A7XX_PERF_SP_WORKING_EU_FS_STAGE"/> 631 631 + <value value="74" name="A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE"/> 632 632 + <value value="75" name="A7XX_PERF_SP_WORKING_EU_VS_STAGE"/> 633 633 + <value value="76" name="A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE"/> 634 634 + <value value="77" name="A7XX_PERF_SP_WORKING_EU_CS_STAGE"/> 635 635 + <value value="78" name="A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE"/> 636 636 + <value value="79" name="A7XX_PERF_SP_GPR_READ_PREFETCH"/> 637 637 + <value value="80" name="A7XX_PERF_SP_GPR_READ_CONFLICT"/> 638 638 + <value value="81" name="A7XX_PERF_SP_GPR_WRITE_CONFLICT"/> 639 639 + <value value="82" name="A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES"/> 640 640 + <value value="83" name="A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> 641 641 + <value value="84" name="A7XX_PERF_SP_EXECUTABLE_WAVES"/> 642 642 + <value value="85" name="A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES"/> 643 643 + <value value="86" name="A7XX_PERF_SP_WORKING_EU_LPAC"/> 644 644 + <value value="87" name="A7XX_PERF_SP_BYPASS_BUSY_CYCLES"/> 645 645 + <value value="88" name="A7XX_PERF_SP_ANY_EU_WORKING_LPAC"/> 646 646 + <value value="89" name="A7XX_PERF_SP_WAVE_ALU_CYCLES"/> 647 647 + <value value="90" name="A7XX_PERF_SP_WAVE_EFU_CYCLES"/> 648 648 + <value value="91" name="A7XX_PERF_SP_WAVE_INT_CYCLES"/> 649 649 + <value value="92" name="A7XX_PERF_SP_WAVE_CSP_CYCLES"/> 650 650 + <value value="93" name="A7XX_PERF_SP_EWAVE_CONTEXTS"/> 651 651 + <value value="94" name="A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES"/> 652 652 + <value value="95" name="A7XX_PERF_SP_LPAC_BUSY_CYCLES"/> 653 653 + <value value="96" name="A7XX_PERF_SP_LPAC_INSTRUCTIONS"/> 654 654 + <value value="97" name="A7XX_PERF_SP_FS_STAGE_1X_WAVES"/> 655 655 + <value value="98" name="A7XX_PERF_SP_FS_STAGE_2X_WAVES"/> 656 656 + <value value="99" name="A7XX_PERF_SP_QUADS"/> 657 657 + <value value="100" name="A7XX_PERF_SP_CS_INVOCATIONS"/> 658 658 + <value value="101" name="A7XX_PERF_SP_PIXELS"/> 659 659 + <value value="102" name="A7XX_PERF_SP_LPAC_DRAWCALLS"/> 660 660 + <value value="103" name="A7XX_PERF_SP_PI_WORKING_CYCLES"/> 661 661 + <value value="104" name="A7XX_PERF_SP_WAVE_INPUT_CYCLES"/> 662 662 + <value value="105" name="A7XX_PERF_SP_WAVE_OUTPUT_CYCLES"/> 663 663 + <value value="106" name="A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES"/> 664 664 + <value value="107" name="A7XX_PERF_SP_WAVE_HWAVE_SYNC"/> 665 665 + <value value="108" name="A7XX_PERF_SP_OUTPUT_3D_PIXELS"/> 666 666 + <value value="109" name="A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS"/> 667 667 + <value value="110" name="A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS"/> 668 668 + <value value="111" name="A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS"/> 669 669 + <value value="112" name="A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS"/> 670 670 + <value value="113" name="A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS"/> 671 671 + <value value="114" name="A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS"/> 672 672 + <value value="115" name="A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS"/> 673 673 + <value value="116" name="A7XX_PERF_SP_ALU_GPR_READ_CYCLES"/> 674 674 + <value value="117" name="A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES"/> 675 675 + <value value="118" name="A7XX_PERF_SP_LM_FULL_CYCLES"/> 676 676 + <value value="119" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES"/> 677 677 + <value value="120" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES"/> 678 678 + <value value="121" name="A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION"/> 679 679 + <value value="122" name="A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS"/> 680 680 + <value value="123" name="A7XX_PERF_SP_RBRT_KICKOFF_FIBERS"/> 681 681 + <value value="124" name="A7XX_PERF_SP_RBRT_KICKOFF_DQUADS"/> 682 682 + <value value="125" name="A7XX_PERF_SP_RTU_BUSY_CYCLES"/> 683 683 + <value value="126" name="A7XX_PERF_SP_RTU_L0_HITS"/> 684 684 + <value value="127" name="A7XX_PERF_SP_RTU_L0_MISSES"/> 685 685 + <value value="128" name="A7XX_PERF_SP_RTU_L0_HIT_ON_MISS"/> 686 686 + <value value="129" name="A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE"/> 687 687 + <value value="130" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE"/> 688 688 + <value value="131" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE"/> 689 689 + <value value="132" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE"/> 690 690 + <value value="133" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA"/> 691 691 + <value value="134" name="A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT"/> 692 692 + <value value="135" name="A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT"/> 693 693 + <value value="136" name="A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE"/> 694 694 + <value value="137" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0"/> 695 695 + <value value="138" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO"/> 696 696 + <value value="139" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES"/> 697 697 + <value value="140" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES"/> 698 698 + <value value="141" name="A7XX_PERF_SP_STCHE_MISS_INC_VS"/> 699 699 + <value value="142" name="A7XX_PERF_SP_STCHE_MISS_INC_FS"/> 700 700 + <value value="143" name="A7XX_PERF_SP_STCHE_MISS_INC_BV"/> 701 701 + <value value="144" name="A7XX_PERF_SP_STCHE_MISS_INC_LPAC"/> 702 702 + <value value="145" name="A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS"/> 703 703 + <value value="146" name="A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS"/> 704 704 + <value value="147" name="A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS"/> 705 705 + <value value="148" name="A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS"/> 706 706 + <value value="149" name="A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS"/> 707 707 + <value value="150" name="A7XX_PERF_SP_SCH_STALL_CYCLES_RTU"/> 708 708 + </enum> 709 709 + 710 710 + <enum name="a7xx_rb_perfcounter_select"> 711 711 + <value value="0" name="A7XX_PERF_RB_BUSY_CYCLES"/> 712 712 + <value value="1" name="A7XX_PERF_RB_STALL_CYCLES_HLSQ"/> 713 713 + <value value="2" name="A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL"/> 714 714 + <value value="3" name="A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL"/> 715 715 + <value value="4" name="A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL"/> 716 716 + <value value="5" name="A7XX_PERF_RB_STARVE_CYCLES_SP"/> 717 717 + <value value="6" name="A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE"/> 718 718 + <value value="7" name="A7XX_PERF_RB_STARVE_CYCLES_CCU"/> 719 719 + <value value="8" name="A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE"/> 720 720 + <value value="9" name="A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE"/> 721 721 + <value value="10" name="A7XX_PERF_RB_Z_WORKLOAD"/> 722 722 + <value value="11" name="A7XX_PERF_RB_HLSQ_ACTIVE"/> 723 723 + <value value="12" name="A7XX_PERF_RB_Z_READ"/> 724 724 + <value value="13" name="A7XX_PERF_RB_Z_WRITE"/> 725 725 + <value value="14" name="A7XX_PERF_RB_C_READ"/> 726 726 + <value value="15" name="A7XX_PERF_RB_C_WRITE"/> 727 727 + <value value="16" name="A7XX_PERF_RB_TOTAL_PASS"/> 728 728 + <value value="17" name="A7XX_PERF_RB_Z_PASS"/> 729 729 + <value value="18" name="A7XX_PERF_RB_Z_FAIL"/> 730 730 + <value value="19" name="A7XX_PERF_RB_S_FAIL"/> 731 731 + <value value="20" name="A7XX_PERF_RB_BLENDED_FXP_COMPONENTS"/> 732 732 + <value value="21" name="A7XX_PERF_RB_BLENDED_FP16_COMPONENTS"/> 733 733 + <value value="22" name="A7XX_PERF_RB_PS_INVOCATIONS"/> 734 734 + <value value="23" name="A7XX_PERF_RB_2D_ALIVE_CYCLES"/> 735 735 + <value value="24" name="A7XX_PERF_RB_2D_STALL_CYCLES_A2D"/> 736 736 + <value value="25" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SRC"/> 737 737 + <value value="26" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SP"/> 738 738 + <value value="27" name="A7XX_PERF_RB_2D_STARVE_CYCLES_DST"/> 739 739 + <value value="28" name="A7XX_PERF_RB_2D_VALID_PIXELS"/> 740 740 + <value value="29" name="A7XX_PERF_RB_3D_PIXELS"/> 741 741 + <value value="30" name="A7XX_PERF_RB_BLENDER_WORKING_CYCLES"/> 742 742 + <value value="31" name="A7XX_PERF_RB_ZPROC_WORKING_CYCLES"/> 743 743 + <value value="32" name="A7XX_PERF_RB_CPROC_WORKING_CYCLES"/> 744 744 + <value value="33" name="A7XX_PERF_RB_SAMPLER_WORKING_CYCLES"/> 745 745 + <value value="34" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> 746 746 + <value value="35" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> 747 747 + <value value="36" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> 748 748 + <value value="37" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> 749 749 + <value value="38" name="A7XX_PERF_RB_STALL_CYCLES_VPC"/> 750 750 + <value value="39" name="A7XX_PERF_RB_2D_INPUT_TRANS"/> 751 751 + <value value="40" name="A7XX_PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> 752 752 + <value value="41" name="A7XX_PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> 753 753 + <value value="42" name="A7XX_PERF_RB_BLENDED_FP32_COMPONENTS"/> 754 754 + <value value="43" name="A7XX_PERF_RB_COLOR_PIX_TILES"/> 755 755 + <value value="44" name="A7XX_PERF_RB_STALL_CYCLES_CCU"/> 756 756 + <value value="45" name="A7XX_PERF_RB_EARLY_Z_ARB3_GRANT"/> 757 757 + <value value="46" name="A7XX_PERF_RB_LATE_Z_ARB3_GRANT"/> 758 758 + <value value="47" name="A7XX_PERF_RB_EARLY_Z_SKIP_GRANT"/> 759 759 + <value value="48" name="A7XX_PERF_RB_VRS_1x1_QUADS"/> 760 760 + <value value="49" name="A7XX_PERF_RB_VRS_2x1_QUADS"/> 761 761 + <value value="50" name="A7XX_PERF_RB_VRS_1x2_QUADS"/> 762 762 + <value value="51" name="A7XX_PERF_RB_VRS_2x2_QUADS"/> 763 763 + <value value="52" name="A7XX_PERF_RB_VRS_4x2_QUADS"/> 764 764 + <value value="53" name="A7XX_PERF_RB_VRS_4x4_QUADS"/> 765 765 + </enum> 766 766 + 767 767 + <enum name="a7xx_vsc_perfcounter_select"> 768 768 + <value value="0" name="A7XX_PERF_VSC_BUSY_CYCLES"/> 769 769 + <value value="1" name="A7XX_PERF_VSC_WORKING_CYCLES"/> 770 770 + <value value="2" name="A7XX_PERF_VSC_STALL_CYCLES_UCHE"/> 771 771 + <value value="3" name="A7XX_PERF_VSC_EOT_NUM"/> 772 772 + <value value="4" name="A7XX_PERF_VSC_INPUT_TILES"/> 773 773 + </enum> 774 774 + 775 775 + <enum name="a7xx_ccu_perfcounter_select"> 776 776 + <value value="0" name="A7XX_PERF_CCU_BUSY_CYCLES"/> 777 777 + <value value="1" name="A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> 778 778 + <value value="2" name="A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> 779 779 + <value value="3" name="A7XX_PERF_CCU_DEPTH_BLOCKS"/> 780 780 + <value value="4" name="A7XX_PERF_CCU_COLOR_BLOCKS"/> 781 781 + <value value="5" name="A7XX_PERF_CCU_DEPTH_BLOCK_HIT"/> 782 782 + <value value="6" name="A7XX_PERF_CCU_COLOR_BLOCK_HIT"/> 783 783 + <value value="7" name="A7XX_PERF_CCU_PARTIAL_BLOCK_READ"/> 784 784 + <value value="8" name="A7XX_PERF_CCU_GMEM_READ"/> 785 785 + <value value="9" name="A7XX_PERF_CCU_GMEM_WRITE"/> 786 786 + <value value="10" name="A7XX_PERF_CCU_2D_RD_REQ"/> 787 787 + <value value="11" name="A7XX_PERF_CCU_2D_WR_REQ"/> 788 788 + <value value="12" name="A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT"/> 789 789 + <value value="13" name="A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT"/> 790 790 + <value value="14" name="A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED"/> 791 791 + <value value="15" name="A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED"/> 792 792 + <value value="16" name="A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT"/> 793 793 + <value value="17" name="A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT"/> 794 794 + <value value="18" name="A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER"/> 795 795 + <value value="19" name="A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER"/> 796 796 + <value value="20" name="A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ"/> 797 797 + <value value="21" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA"/> 798 798 + <value value="22" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL"/> 799 799 + </enum> 800 800 + 801 801 + <enum name="a7xx_lrz_perfcounter_select"> 802 802 + <value value="0" name="A7XX_PERF_LRZ_BUSY_CYCLES"/> 803 803 + <value value="1" name="A7XX_PERF_LRZ_STARVE_CYCLES_RAS"/> 804 804 + <value value="2" name="A7XX_PERF_LRZ_STALL_CYCLES_RB"/> 805 805 + <value value="3" name="A7XX_PERF_LRZ_STALL_CYCLES_VSC"/> 806 806 + <value value="4" name="A7XX_PERF_LRZ_STALL_CYCLES_VPC"/> 807 807 + <value value="5" name="A7XX_PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> 808 808 + <value value="6" name="A7XX_PERF_LRZ_STALL_CYCLES_UCHE"/> 809 809 + <value value="7" name="A7XX_PERF_LRZ_LRZ_READ"/> 810 810 + <value value="8" name="A7XX_PERF_LRZ_LRZ_WRITE"/> 811 811 + <value value="9" name="A7XX_PERF_LRZ_READ_LATENCY"/> 812 812 + <value value="10" name="A7XX_PERF_LRZ_MERGE_CACHE_UPDATING"/> 813 813 + <value value="11" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> 814 814 + <value value="12" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ"/> 815 815 + <value value="13" name="A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> 816 816 + <value value="14" name="A7XX_PERF_LRZ_FULL_8X8_TILES"/> 817 817 + <value value="15" name="A7XX_PERF_LRZ_PARTIAL_8X8_TILES"/> 818 818 + <value value="16" name="A7XX_PERF_LRZ_TILE_KILLED"/> 819 819 + <value value="17" name="A7XX_PERF_LRZ_TOTAL_PIXEL"/> 820 820 + <value value="18" name="A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> 821 821 + <value value="19" name="A7XX_PERF_LRZ_FEEDBACK_ACCEPT"/> 822 822 + <value value="20" name="A7XX_PERF_LRZ_FEEDBACK_DISCARD"/> 823 823 + <value value="21" name="A7XX_PERF_LRZ_FEEDBACK_STALL"/> 824 824 + <value value="22" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> 825 825 + <value value="23" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> 826 826 + <value value="24" name="A7XX_PERF_LRZ_RAS_MASK_TRANS"/> 827 827 + <value value="25" name="A7XX_PERF_LRZ_STALL_CYCLES_MVC"/> 828 828 + <value value="26" name="A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS"/> 829 829 + <value value="27" name="A7XX_PERF_LRZ_TILE_KILLED_BY_Z"/> 830 830 + </enum> 831 831 + 832 832 + <enum name="a7xx_cmp_perfcounter_select"> 833 833 + <value value="0" name="A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB"/> 834 834 + <value value="1" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> 835 835 + <value value="2" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> 836 836 + <value value="3" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> 837 837 + <value value="4" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> 838 838 + <value value="5" name="A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST"/> 839 839 + <value value="6" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> 840 840 + <value value="7" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA"/> 841 841 + <value value="8" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA"/> 842 842 + <value value="9" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> 843 843 + <value value="10" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> 844 844 + <value value="11" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> 845 845 + <value value="12" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> 846 846 + <value value="13" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> 847 847 + <value value="14" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> 848 848 + <value value="15" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> 849 849 + <value value="16" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> 850 850 + <value value="17" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> 851 851 + <value value="18" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> 852 852 + <value value="19" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> 853 853 + <value value="20" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> 854 854 + <value value="21" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> 855 855 + <value value="22" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> 856 856 + <value value="23" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> 857 857 + <value value="24" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> 858 858 + <value value="25" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> 859 859 + <value value="26" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> 860 860 + <value value="27" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> 861 861 + <value value="28" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> 862 862 + <value value="29" name="A7XX_PERF_CMPDECMP_RESOLVE_EVENTS"/> 863 863 + <value value="30" name="A7XX_PERF_CMPDECMP_CONCURRENT_RESOLVE_EVENTS"/> 864 864 + <value value="31" name="A7XX_PERF_CMPDECMP_DROPPED_CLEAR_EVENTS"/> 865 865 + <value value="32" name="A7XX_PERF_CMPDECMP_ST_BLOCKS_CONCURRENT"/> 866 866 + <value value="33" name="A7XX_PERF_CMPDECMP_LRZ_ST_BLOCKS_CONCURRENT"/> 867 867 + <value value="34" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT"/> 868 868 + <value value="35" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT"/> 869 869 + <value value="36" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT"/> 870 870 + <value value="37" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT"/> 871 871 + <value value="38" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT"/> 872 872 + <value value="39" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT"/> 873 873 + <value value="40" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT"/> 874 874 + <value value="41" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT"/> 875 875 + <value value="42" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT"/> 876 876 + <value value="43" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT"/> 877 877 + <value value="44" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT"/> 878 878 + <value value="45" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT"/> 879 879 + <value value="46" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT"/> 880 880 + <value value="47" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT"/> 881 881 + <value value="48" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT"/> 882 882 + <value value="49" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT"/> 883 883 + </enum> 884 884 + 885 885 + <enum name="a7xx_gbif_perfcounter_select"> 886 886 + <value value="0" name="A7XX_PERF_GBIF_RESERVED_0"/> 887 887 + <value value="1" name="A7XX_PERF_GBIF_RESERVED_1"/> 888 888 + <value value="2" name="A7XX_PERF_GBIF_RESERVED_2"/> 889 889 + <value value="3" name="A7XX_PERF_GBIF_RESERVED_3"/> 890 890 + <value value="4" name="A7XX_PERF_GBIF_RESERVED_4"/> 891 891 + <value value="5" name="A7XX_PERF_GBIF_RESERVED_5"/> 892 892 + <value value="6" name="A7XX_PERF_GBIF_RESERVED_6"/> 893 893 + <value value="7" name="A7XX_PERF_GBIF_RESERVED_7"/> 894 894 + <value value="8" name="A7XX_PERF_GBIF_RESERVED_8"/> 895 895 + <value value="9" name="A7XX_PERF_GBIF_RESERVED_9"/> 896 896 + <value value="10" name="A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL"/> 897 897 + <value value="11" name="A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL"/> 898 898 + <value value="12" name="A7XX_PERF_GBIF_RESERVED_12"/> 899 899 + <value value="13" name="A7XX_PERF_GBIF_RESERVED_13"/> 900 900 + <value value="14" name="A7XX_PERF_GBIF_RESERVED_14"/> 901 901 + <value value="15" name="A7XX_PERF_GBIF_RESERVED_15"/> 902 902 + <value value="16" name="A7XX_PERF_GBIF_RESERVED_16"/> 903 903 + <value value="17" name="A7XX_PERF_GBIF_RESERVED_17"/> 904 904 + <value value="18" name="A7XX_PERF_GBIF_RESERVED_18"/> 905 905 + <value value="19" name="A7XX_PERF_GBIF_RESERVED_19"/> 906 906 + <value value="20" name="A7XX_PERF_GBIF_RESERVED_20"/> 907 907 + <value value="21" name="A7XX_PERF_GBIF_RESERVED_21"/> 908 908 + <value value="22" name="A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL"/> 909 909 + <value value="23" name="A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL"/> 910 910 + <value value="24" name="A7XX_PERF_GBIF_RESERVED_24"/> 911 911 + <value value="25" name="A7XX_PERF_GBIF_RESERVED_25"/> 912 912 + <value value="26" name="A7XX_PERF_GBIF_RESERVED_26"/> 913 913 + <value value="27" name="A7XX_PERF_GBIF_RESERVED_27"/> 914 914 + <value value="28" name="A7XX_PERF_GBIF_RESERVED_28"/> 915 915 + <value value="29" name="A7XX_PERF_GBIF_RESERVED_29"/> 916 916 + <value value="30" name="A7XX_PERF_GBIF_RESERVED_30"/> 917 917 + <value value="31" name="A7XX_PERF_GBIF_RESERVED_31"/> 918 918 + <value value="32" name="A7XX_PERF_GBIF_RESERVED_32"/> 919 919 + <value value="33" name="A7XX_PERF_GBIF_RESERVED_33"/> 920 920 + <value value="34" name="A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL"/> 921 921 + <value value="35" name="A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL"/> 922 922 + <value value="36" name="A7XX_PERF_GBIF_RESERVED_36"/> 923 923 + <value value="37" name="A7XX_PERF_GBIF_RESERVED_37"/> 924 924 + <value value="38" name="A7XX_PERF_GBIF_RESERVED_38"/> 925 925 + <value value="39" name="A7XX_PERF_GBIF_RESERVED_39"/> 926 926 + <value value="40" name="A7XX_PERF_GBIF_RESERVED_40"/> 927 927 + <value value="41" name="A7XX_PERF_GBIF_RESERVED_41"/> 928 928 + <value value="42" name="A7XX_PERF_GBIF_RESERVED_42"/> 929 929 + <value value="43" name="A7XX_PERF_GBIF_RESERVED_43"/> 930 930 + <value value="44" name="A7XX_PERF_GBIF_RESERVED_44"/> 931 931 + <value value="45" name="A7XX_PERF_GBIF_RESERVED_45"/> 932 932 + <value value="46" name="A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL"/> 933 933 + <value value="47" name="A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL"/> 934 934 + <value value="48" name="A7XX_PERF_GBIF_RESERVED_48"/> 935 935 + <value value="49" name="A7XX_PERF_GBIF_RESERVED_49"/> 936 936 + <value value="50" name="A7XX_PERF_GBIF_RESERVED_50"/> 937 937 + <value value="51" name="A7XX_PERF_GBIF_RESERVED_51"/> 938 938 + <value value="52" name="A7XX_PERF_GBIF_RESERVED_52"/> 939 939 + <value value="53" name="A7XX_PERF_GBIF_RESERVED_53"/> 940 940 + <value value="54" name="A7XX_PERF_GBIF_RESERVED_54"/> 941 941 + <value value="55" name="A7XX_PERF_GBIF_RESERVED_55"/> 942 942 + <value value="56" name="A7XX_PERF_GBIF_RESERVED_56"/> 943 943 + <value value="57" name="A7XX_PERF_GBIF_RESERVED_57"/> 944 944 + <value value="58" name="A7XX_PERF_GBIF_RESERVED_58"/> 945 945 + <value value="59" name="A7XX_PERF_GBIF_RESERVED_59"/> 946 946 + <value value="60" name="A7XX_PERF_GBIF_RESERVED_60"/> 947 947 + <value value="61" name="A7XX_PERF_GBIF_RESERVED_61"/> 948 948 + <value value="62" name="A7XX_PERF_GBIF_RESERVED_62"/> 949 949 + <value value="63" name="A7XX_PERF_GBIF_RESERVED_63"/> 950 950 + <value value="64" name="A7XX_PERF_GBIF_RESERVED_64"/> 951 951 + <value value="65" name="A7XX_PERF_GBIF_RESERVED_65"/> 952 952 + <value value="66" name="A7XX_PERF_GBIF_RESERVED_66"/> 953 953 + <value value="67" name="A7XX_PERF_GBIF_RESERVED_67"/> 954 954 + <value value="68" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL"/> 955 955 + <value value="69" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL"/> 956 956 + <value value="70" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL"/> 957 957 + <value value="71" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL"/> 958 958 + <value value="72" name="A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF"/> 959 959 + <value value="73" name="A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF"/> 960 960 + <value value="74" name="A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF"/> 961 961 + <value value="75" name="A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF"/> 962 962 + <value value="76" name="A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF"/> 963 963 + <value value="77" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF"/> 964 964 + <value value="78" name="A7XX_PERF_GBIF_AXI_ALL_READ_BEATS"/> 965 965 + <value value="79" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_BEATS"/> 966 966 + <value value="80" name="A7XX_PERF_GBIF_AXI_ALL_BEATS"/> 967 967 + </enum> 968 968 + 969 969 + <enum name="a7xx_ufc_perfcounter_select"> 970 970 + <value value="0" name="A7XX_PERF_UFC_BUSY_CYCLES"/> 971 971 + <value value="1" name="A7XX_PERF_UFC_READ_DATA_VBIF"/> 972 972 + <value value="2" name="A7XX_PERF_UFC_WRITE_DATA_VBIF"/> 973 973 + <value value="3" name="A7XX_PERF_UFC_READ_REQUEST_VBIF"/> 974 974 + <value value="4" name="A7XX_PERF_UFC_WRITE_REQUEST_VBIF"/> 975 975 + <value value="5" name="A7XX_PERF_UFC_LRZ_FILTER_HIT"/> 976 976 + <value value="6" name="A7XX_PERF_UFC_LRZ_FILTER_MISS"/> 977 977 + <value value="7" name="A7XX_PERF_UFC_CRE_FILTER_HIT"/> 978 978 + <value value="8" name="A7XX_PERF_UFC_CRE_FILTER_MISS"/> 979 979 + <value value="9" name="A7XX_PERF_UFC_SP_FILTER_HIT"/> 980 980 + <value value="10" name="A7XX_PERF_UFC_SP_FILTER_MISS"/> 981 981 + <value value="11" name="A7XX_PERF_UFC_SP_REQUESTS"/> 982 982 + <value value="12" name="A7XX_PERF_UFC_TP_FILTER_HIT"/> 983 983 + <value value="13" name="A7XX_PERF_UFC_TP_FILTER_MISS"/> 984 984 + <value value="14" name="A7XX_PERF_UFC_TP_REQUESTS"/> 985 985 + <value value="15" name="A7XX_PERF_UFC_MAIN_HIT_LRZ_PREFETCH"/> 986 986 + <value value="16" name="A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH"/> 987 987 + <value value="17" name="A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH"/> 988 988 + <value value="18" name="A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH"/> 989 989 + <value value="19" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_READ"/> 990 990 + <value value="20" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE"/> 991 991 + <value value="21" name="A7XX_PERF_UFC_MAIN_MISS_LRZ_PREFETCH"/> 992 992 + <value value="22" name="A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH"/> 993 993 + <value value="23" name="A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH"/> 994 994 + <value value="24" name="A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH"/> 995 995 + <value value="25" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_READ"/> 996 996 + <value value="26" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE"/> 997 997 + <value value="27" name="A7XX_PERF_UFC_UBWC_READ_UFC_TRANS"/> 998 998 + <value value="28" name="A7XX_PERF_UFC_UBWC_WRITE_UFC_TRANS"/> 999 999 + <value value="29" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD"/> 1000 1000 + <value value="30" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA"/> 1001 1001 + <value value="31" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA"/> 1002 1002 + <value value="32" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG"/> 1003 1003 + <value value="33" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN"/> 1004 1004 + <value value="34" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT"/> 1005 1005 + <value value="35" name="A7XX_PERF_UFC_LRZ_PREFETCH_STALLED_CYCLES"/> 1006 1006 + <value value="36" name="A7XX_PERF_UFC_CRE_PREFETCH_STALLED_CYCLES"/> 1007 1007 + <value value="37" name="A7XX_PERF_UFC_SPTP_PREFETCH_STALLED_CYCLES"/> 1008 1008 + <value value="38" name="A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES"/> 1009 1009 + <value value="39" name="A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES"/> 1010 1010 + <value value="40" name="A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES"/> 1011 1011 + <value value="41" name="A7XX_PERF_UFC_EVICTION_STALLED_CYCLES"/> 1012 1012 + <value value="42" name="A7XX_PERF_UFC_LOCK_STALLED_CYCLES"/> 1013 1013 + <value value="43" name="A7XX_PERF_UFC_MISS_LATENCY_CYCLES"/> 1014 1014 + <value value="44" name="A7XX_PERF_UFC_MISS_LATENCY_SAMPLES"/> 1015 1015 + <value value="45" name="A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES"/> 1016 1016 + <value value="46" name="A7XX_PERF_UFC_TP_HINT_TAG_MISS"/> 1017 1017 + <value value="47" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_RDY"/> 1018 1018 + <value value="48" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_NRDY"/> 1019 1019 + <value value="49" name="A7XX_PERF_UFC_TP_HINT_IS_FCLEAR"/> 1020 1020 + <value value="50" name="A7XX_PERF_UFC_TP_HINT_IS_ALPHA0"/> 1021 1021 + <value value="51" name="A7XX_PERF_UFC_SP_L1_FILTER_HIT"/> 1022 1022 + <value value="52" name="A7XX_PERF_UFC_SP_L1_FILTER_MISS"/> 1023 1023 + <value value="53" name="A7XX_PERF_UFC_SP_L1_FILTER_REQUESTS"/> 1024 1024 + <value value="54" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_RDY"/> 1025 1025 + <value value="55" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_NRDY"/> 1026 1026 + <value value="56" name="A7XX_PERF_UFC_TP_L1_TAG_MISS"/> 1027 1027 + <value value="57" name="A7XX_PERF_UFC_TP_L1_FILTER_REQUESTS"/> 1028 1028 + </enum> 1029 1029 + 1030 1030 + </database>

+213 -89

drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml

reviewed

··· 21 21 <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/> 22 22 <value name="VIZQUERY_END" value="8" variants="A2XX"/> 23 23 <value name="SC_WAIT_WC" value="9" variants="A2XX"/> 24 24 - <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/> 25 25 - <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/> 26 26 - <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/> 24 24 + <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/> 25 25 + <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/> 26 26 + <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/> 27 27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ --> 28 28 <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/> 29 29 <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/> ··· 31 31 <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/> 32 32 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/> 33 33 <doc> 34 34 - If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed 35 35 - sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main 34 34 + If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed 35 35 + sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main 36 36 memory, skipping UCHE. 37 37 </doc> 38 38 <value name="ZPASS_DONE" value="21"/> ··· 98 98 <value name="BLIT" value="30" variants="A5XX-"/> 99 99 100 100 <doc> 101 101 + Flip between the primary and secondary LRZ buffers. This is used 102 102 + for concurrent binning, so that BV can write to one buffer while 103 103 + BR reads from the other. 104 104 + </doc> 105 105 + <value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX"/> 106 106 + 107 107 + <doc> 101 108 Clears based on GRAS_LRZ_CNTL configuration, could clear 102 109 fast-clear buffer or LRZ direction. 103 110 LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which ··· 121 114 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/> 122 115 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/> 123 116 <value name="UNK_40" value="40" variants="A7XX"/> 117 117 + <value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/> 124 118 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/> 125 119 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/> 126 120 <value name="UNK_2C" value="44" variants="A5XX-"/> ··· 380 372 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/> 381 373 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/> 382 374 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc> 383 383 - <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/> 375 375 + <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a" variants="A3XX-A5XX"/> 384 376 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc> 385 377 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/> 386 378 <doc>Load a buffer with pre-fetch enabled</doc> ··· 546 538 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/> 547 539 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/> 548 540 <!-- 549 549 - Note: For IBO state (Image/SSBOs) which have shared state across 541 541 + Note: For UAV state (Image/SSBOs) which have shared state across 550 542 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for 551 543 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are 552 544 interchangable. ··· 575 567 <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/> 576 568 577 569 <!-- TODO do these exist on A5xx? --> 578 578 - <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/> 570 570 + <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX-"/> 579 571 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/> 580 572 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/> 581 573 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/> ··· 658 650 659 651 <doc>Reset various on-chip state used for synchronization</doc> 660 652 <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/> 653 653 + 654 654 + <doc>Invalidates the "CCHE" introduced on a740</doc> 655 655 + <value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/> 656 656 + 657 657 + <value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/> 661 658 </enum> 662 659 663 660 ··· 805 792 <value name="SB6_GS_SHADER" value="0xb"/> 806 793 <value name="SB6_FS_SHADER" value="0xc"/> 807 794 <value name="SB6_CS_SHADER" value="0xd"/> 808 808 - <value name="SB6_IBO" value="0xe"/> 809 809 - <value name="SB6_CS_IBO" value="0xf"/> 795 795 + <value name="SB6_UAV" value="0xe"/> 796 796 + <value name="SB6_CS_UAV" value="0xf"/> 810 797 </enum> 811 798 <enum name="a6xx_state_type"> 812 799 <value name="ST6_SHADER" value="0"/> 813 800 <value name="ST6_CONSTANTS" value="1"/> 814 801 <value name="ST6_UBO" value="2"/> 815 815 - <value name="ST6_IBO" value="3"/> 802 802 + <value name="ST6_UAV" value="3"/> 816 803 </enum> 817 804 <enum name="a6xx_state_src"> 818 805 <value name="SS6_DIRECT" value="0"/> ··· 1134 1121 </reg32> 1135 1122 </domain> 1136 1123 1124 1124 + <enum name="a7xx_abs_mask_mode"> 1125 1125 + <value name="ABS_MASK" value="0x1"/> 1126 1126 + <value name="NO_ABS_MASK" value="0x0"/> 1127 1127 + </enum> 1128 1128 + 1137 1129 <domain name="CP_SET_BIN_DATA5" width="32"> 1138 1130 <reg32 offset="0" name="0"> 1131 1131 + <bitfield name="VSC_MASK" low="0" high="15" type="hex"> 1132 1132 + <doc> 1133 1133 + A mask of bins, starting at VSC_N, whose 1134 1134 + visibility is OR'd together. A value of 0 is 1135 1135 + interpreted as 1 (i.e. just use VSC_N for 1136 1136 + visbility) for backwards compatibility. Only 1137 1137 + exists on a7xx. 1138 1138 + </doc> 1139 1139 + </bitfield> 1139 1140 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1140 1141 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1141 1142 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1142 1143 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1144 1144 + <bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"> 1145 1145 + <doc> 1146 1146 + If this field is 1, VSC_MASK and VSC_N are 1147 1147 + ignored and instead a new ordinal immediately 1148 1148 + after specifies the full 32-bit mask of bins 1149 1149 + to use. The mask is "absolute" instead of 1150 1150 + relative to VSC_N. 1151 1151 + </doc> 1152 1152 + </bitfield> 1143 1153 </reg32> 1144 1144 - <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1145 1145 - <reg32 offset="1" name="1"> 1146 1146 - <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1147 1147 - </reg32> 1148 1148 - <reg32 offset="2" name="2"> 1149 1149 - <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1150 1150 - </reg32> 1151 1151 - <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1152 1152 - <reg32 offset="3" name="3"> 1153 1153 - <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1154 1154 - </reg32> 1155 1155 - <reg32 offset="4" name="4"> 1156 1156 - <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1157 1157 - </reg32> 1158 1158 - <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1159 1159 - <reg32 offset="5" name="5"> 1160 1160 - <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1161 1161 - </reg32> 1162 1162 - <reg32 offset="6" name="6"> 1163 1163 - <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1164 1164 - </reg32> 1165 1165 - <!-- 1166 1166 - a7xx adds a few more addresses to the end of the pkt 1167 1167 - --> 1168 1168 - <reg64 offset="7" name="7"/> 1169 1169 - <reg64 offset="9" name="9"/> 1154 1154 + <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> 1155 1155 + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1156 1156 + <reg32 offset="1" name="1"> 1157 1157 + <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1158 1158 + </reg32> 1159 1159 + <reg32 offset="2" name="2"> 1160 1160 + <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1161 1161 + </reg32> 1162 1162 + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1163 1163 + <reg32 offset="3" name="3"> 1164 1164 + <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1165 1165 + </reg32> 1166 1166 + <reg32 offset="4" name="4"> 1167 1167 + <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1168 1168 + </reg32> 1169 1169 + <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1170 1170 + <reg32 offset="5" name="5"> 1171 1171 + <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1172 1172 + </reg32> 1173 1173 + <reg32 offset="6" name="6"> 1174 1174 + <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1175 1175 + </reg32> 1176 1176 + <!-- 1177 1177 + a7xx adds a few more addresses to the end of the pkt 1178 1178 + --> 1179 1179 + <reg64 offset="7" name="7"/> 1180 1180 + <reg64 offset="9" name="9"/> 1181 1181 + </stripe> 1182 1182 + <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> 1183 1183 + <reg32 offset="1" name="ABS_MASK"/> 1184 1184 + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1185 1185 + <reg32 offset="2" name="2"> 1186 1186 + <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1187 1187 + </reg32> 1188 1188 + <reg32 offset="3" name="3"> 1189 1189 + <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1190 1190 + </reg32> 1191 1191 + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1192 1192 + <reg32 offset="4" name="4"> 1193 1193 + <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1194 1194 + </reg32> 1195 1195 + <reg32 offset="5" name="5"> 1196 1196 + <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1197 1197 + </reg32> 1198 1198 + <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1199 1199 + <reg32 offset="6" name="6"> 1200 1200 + <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1201 1201 + </reg32> 1202 1202 + <reg32 offset="7" name="7"> 1203 1203 + <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1204 1204 + </reg32> 1205 1205 + <!-- 1206 1206 + a7xx adds a few more addresses to the end of the pkt 1207 1207 + --> 1208 1208 + <reg64 offset="8" name="8"/> 1209 1209 + <reg64 offset="10" name="10"/> 1210 1210 + </stripe> 1170 1211 </domain> 1171 1212 1172 1213 <domain name="CP_SET_BIN_DATA5_OFFSET" width="32"> ··· 1231 1164 stream is recorded. 1232 1165 </doc> 1233 1166 <reg32 offset="0" name="0"> 1167 1167 + <bitfield name="VSC_MASK" low="0" high="15" type="hex"/> 1234 1168 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1235 1169 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1236 1170 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1237 1171 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1172 1172 + <bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"/> 1238 1173 </reg32> 1239 1239 - <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1240 1240 - <reg32 offset="1" name="1"> 1241 1241 - <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1242 1242 - </reg32> 1243 1243 - <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1244 1244 - <reg32 offset="2" name="2"> 1245 1245 - <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1246 1246 - </reg32> 1247 1247 - <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1248 1248 - <reg32 offset="3" name="3"> 1249 1249 - <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1250 1250 - </reg32> 1174 1174 + <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> 1175 1175 + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1176 1176 + <reg32 offset="1" name="1"> 1177 1177 + <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1178 1178 + </reg32> 1179 1179 + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1180 1180 + <reg32 offset="2" name="2"> 1181 1181 + <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1182 1182 + </reg32> 1183 1183 + <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1184 1184 + <reg32 offset="3" name="3"> 1185 1185 + <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1186 1186 + </reg32> 1187 1187 + </stripe> 1188 1188 + <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> 1189 1189 + <reg32 offset="1" name="ABS_MASK"/> 1190 1190 + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1191 1191 + <reg32 offset="2" name="2"> 1192 1192 + <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1193 1193 + </reg32> 1194 1194 + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1195 1195 + <reg32 offset="3" name="3"> 1196 1196 + <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1197 1197 + </reg32> 1198 1198 + <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1199 1199 + <reg32 offset="4" name="4"> 1200 1200 + <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1201 1201 + </reg32> 1202 1202 + </stripe> 1251 1203 </domain> 1252 1204 1253 1205 <domain name="CP_REG_RMW" width="32"> ··· 1284 1198 </doc> 1285 1199 <reg32 offset="0" name="0"> 1286 1200 <bitfield name="DST_REG" low="0" high="17" type="hex"/> 1201 1201 + <bitfield name="DST_SCRATCH" pos="19" type="boolean" varset="chip" variants="A7XX-"/> 1202 1202 + <!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME --> 1203 1203 + <bitfield name="SKIP_WAIT_FOR_ME" pos="23" type="boolean" varset="chip" variants="A7XX-"/> 1287 1204 <bitfield name="ROTATE" low="24" high="28" type="uint"/> 1288 1205 <bitfield name="SRC1_ADD" pos="29" type="boolean"/> 1289 1206 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/> ··· 1437 1348 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1438 1349 <!-- number of registers/dwords copied is CNT + 1. --> 1439 1350 <bitfield name="CNT" low="24" high="26" type="uint"/> 1351 1351 + <!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME --> 1352 1352 + <bitfield name="SKIP_WAIT_FOR_ME" pos="27" type="boolean" varset="chip" variants="A7XX-"/> 1440 1353 </reg32> 1441 1354 </domain> 1442 1355 ··· 1746 1655 <bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/> 1747 1656 <!-- Write sample count at (iova + 16) --> 1748 1657 <bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/> 1749 1749 - <!-- *(iova + 8) = *(iova + 16) - *iova --> 1750 1750 - <bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/> 1658 1658 + <!-- *(iova + 8) += *(iova + 16) - *iova --> 1659 1659 + <bitfield name="WRITE_ACCUM_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/> 1751 1660 1752 1661 <!-- Next 4 flags are valid to set only when concurrent binning is enabled --> 1753 1662 <!-- Increment 16b BV counter. Valid only in BV pipe --> ··· 1761 1670 <bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/> 1762 1671 <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. --> 1763 1672 <bitfield name="WRITE_ENABLED" pos="27" type="boolean"/> 1673 1673 + <bitfield name="IRQ" pos="31" type="boolean"/> 1764 1674 </reg32> 1765 1675 1766 1676 <stripe varset="event_write_dst" variants="EV_DST_RAM"> 1767 1767 - <reg32 offset="1" name="1"> 1768 1768 - <bitfield name="ADDR_0_LO" low="0" high="31"/> 1769 1769 - </reg32> 1770 1770 - <reg32 offset="2" name="2"> 1771 1771 - <bitfield name="ADDR_0_HI" low="0" high="31"/> 1772 1772 - </reg32> 1677 1677 + <reg64 offset="1" name="1" type="waddress"/> 1773 1678 <reg32 offset="3" name="3"> 1774 1679 <bitfield name="PAYLOAD_0" low="0" high="31"/> 1775 1680 </reg32> ··· 1860 1773 1861 1774 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1862 1775 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc> 1776 1776 + <enum name="set_marker_mode"> 1777 1777 + <value value="0" name="SET_RENDER_MODE"/> 1778 1778 + <!-- IFPC - inter-frame power collapse --> 1779 1779 + <value value="1" name="SET_IFPC_MODE"/> 1780 1780 + </enum> 1781 1781 + <enum name="a6xx_ifpc_mode"> 1782 1782 + <value value="0" name="IFPC_ENABLE"/> 1783 1783 + <value value="1" name="IFPC_DISABLE"/> 1784 1784 + </enum> 1863 1785 <enum name="a6xx_marker"> 1864 1864 - <value value="1" name="RM6_BYPASS"/> 1865 1865 - <value value="2" name="RM6_BINNING"/> 1866 1866 - <value value="4" name="RM6_GMEM"/> 1867 1867 - <value value="5" name="RM6_ENDVIS"/> 1868 1868 - <value value="6" name="RM6_RESOLVE"/> 1869 1869 - <value value="7" name="RM6_YIELD"/> 1786 1786 + <value value="1" name="RM6_DIRECT_RENDER"/> 1787 1787 + <value value="2" name="RM6_BIN_VISIBILITY"/> 1788 1788 + <value value="3" name="RM6_BIN_DIRECT"/> 1789 1789 + <value value="4" name="RM6_BIN_RENDER_START"/> 1790 1790 + <value value="5" name="RM6_BIN_END_OF_DRAWS"/> 1791 1791 + <value value="6" name="RM6_BIN_RESOLVE"/> 1792 1792 + <value value="7" name="RM6_BIN_RENDER_END"/> 1870 1793 <value value="8" name="RM6_COMPUTE"/> 1871 1794 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> 1872 1795 ··· 1886 1789 --> 1887 1790 <value value="0xd" name="RM6_IB1LIST_START"/> 1888 1791 <value value="0xe" name="RM6_IB1LIST_END"/> 1889 1889 - <!-- IFPC - inter-frame power collapse --> 1890 1890 - <value value="0x100" name="RM6_IFPC_ENABLE"/> 1891 1891 - <value value="0x101" name="RM6_IFPC_DISABLE"/> 1892 1792 </enum> 1893 1793 <reg32 offset="0" name="0"> 1794 1794 + <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> 1795 1795 + <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> 1796 1796 + 1797 1797 + <bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1798 1798 + <!-- used by preemption to determine if GMEM needs to be saved or not --> 1799 1799 + <bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1800 1800 + 1801 1801 + <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> 1802 1802 + 1894 1803 <!-- 1895 1895 - NOTE: blob driver and some versions of freedreno/turnip set 1896 1896 - b4, which is unused (at least by current sqe fw), but interferes 1897 1897 - with parsing if we extend the size of the bitfield to include 1898 1898 - b8 (only sent by kernel mode driver). Really, the way the 1899 1899 - parsing works in the firmware, only b0-b3 are considered, but 1900 1900 - if b8 is set, the low bits are interpreted differently. To 1901 1901 - model this, without getting confused by spurious b4, this is 1902 1902 - described as two overlapping bitfields: 1903 1903 - --> 1904 1904 - <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/> 1905 1905 - <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/> 1804 1804 + CP_SET_MARKER is used with these bits to create a 1805 1805 + critical section around a workaround for ray tracing. 1806 1806 + The workaround happens after BVH building, and appears 1807 1807 + to invalidate the RTU's BVH node cache. It makes sure 1808 1808 + that only one of BR/BV/LPAC is executing the 1809 1809 + workaround at a time, and no draws using RT on BV/LPAC 1810 1810 + are executing while the workaround is executed on BR (or 1811 1811 + vice versa, that no draws on BV/BR using RT are executed 1812 1812 + while the workaround executes on LPAC), by 1813 1813 + hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS. 1814 1814 + The blob usage is: 1815 1815 + 1816 1816 + CP_SET_MARKER(RT_WA_START) 1817 1817 + ... workaround here ... 1818 1818 + CP_SET_MARKER(RT_WA_END) 1819 1819 + ... 1820 1820 + CP_SET_MARKER(SHADER_USES_RT) 1821 1821 + CP_DRAW_INDX(...) or CP_EXEC_CS(...) 1822 1822 + --> 1823 1823 + <bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/> 1824 1824 + <bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/> 1825 1825 + <bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/> 1906 1826 </reg32> 1907 1827 </domain> 1908 1828 ··· 1946 1832 If concurrent binning is disabled then BR also does binning so it will also 1947 1833 write the "real" registers in BR. 1948 1834 --> 1949 1949 - <value value="8" name="DRAW_STRM_ADDRESS"/> 1950 1950 - <value value="9" name="DRAW_STRM_SIZE_ADDRESS"/> 1951 1951 - <value value="10" name="PRIM_STRM_ADDRESS"/> 1835 1835 + <value value="8" name="VSC_PIPE_DATA_DRAW_BASE"/> 1836 1836 + <value value="9" name="VSC_SIZE_BASE"/> 1837 1837 + <value value="10" name="VSC_PIPE_DATA_PRIM_BASE"/> 1952 1838 <value value="11" name="UNK_STRM_ADDRESS"/> 1953 1839 <value value="12" name="UNK_STRM_SIZE_ADDRESS"/> 1954 1840 ··· 2049 1935 a bitmask of which modes pass the test. 2050 1936 --> 2051 1937 2052 2052 - <!-- RM6_BINNING --> 1938 1938 + <!-- RM6_BIN_VISIBILITY --> 2053 1939 <bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/> 2054 1940 <!-- all others --> 2055 1941 <bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/> 2056 2056 - <!-- RM6_BYPASS --> 1942 1942 + <!-- RM6_DIRECT_RENDER --> 2057 1943 <bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/> 2058 1944 2059 1945 <bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/> ··· 2128 2014 2129 2015 <domain name="CP_SET_AMBLE" width="32"> 2130 2016 <doc> 2131 2131 - Used by the userspace and kernel drivers to set various IB's 2132 2132 - which are executed during context save/restore for handling 2133 2133 - state that isn't restored by the context switch routine itself. 2134 2134 - </doc> 2017 2017 + Used by the userspace and kernel drivers to set various IB's 2018 2018 + which are executed during context save/restore for handling 2019 2019 + state that isn't restored by the context switch routine itself. 2020 2020 + </doc> 2135 2021 <enum name="amble_type"> 2136 2022 <value name="PREAMBLE_AMBLE_TYPE" value="0"> 2137 2023 <doc>Executed unconditionally when switching back to the context.</doc> ··· 2201 2087 <value name="UNK_EVENT_WRITE" value="0x4"/> 2202 2088 <doc> 2203 2089 Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and 2204 2204 - GRAS_LRZ_DEPTH_VIEW with previous values, and if one of 2090 2090 + GRAS_LRZ_VIEW_INFO with previous values, and if one of 2205 2091 the following is true: 2206 2092 - GRAS_LRZ_CNTL::GREATER has changed 2207 2093 - GRAS_LRZ_CNTL::DIR has changed, the old value is not 2208 2094 CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED 2209 2209 - - GRAS_LRZ_DEPTH_VIEW has changed 2095 2095 + - GRAS_LRZ_VIEW_INFO has changed 2210 2096 then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE 2211 2097 forced to 1. 2212 2098 Only exists in a650_sqe.fw. ··· 2321 2207 2322 2208 <domain name="CP_MEM_TO_SCRATCH_MEM" width="32"> 2323 2209 <doc> 2324 2324 - Best guess is that it is a faster way to fetch all the VSC_STATE registers 2210 2210 + Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers 2325 2211 and keep them in a local scratch memory instead of fetching every time 2326 2212 when skipping IBs. 2327 2213 </doc> ··· 2371 2257 <bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/> 2372 2258 <bitfield name="CLEAR_BV_BR_COUNTER" pos="2" type="boolean"/> 2373 2259 <bitfield name="RESET_GLOBAL_LOCAL_TS" pos="3" type="boolean"/> 2260 2260 + </reg32> 2261 2261 + </domain> 2262 2262 + 2263 2263 + <domain name="CP_SCOPE_CNTL" width="32"> 2264 2264 + <enum name="cp_scope"> 2265 2265 + <value value="0" name="INTERRUPTS"/> 2266 2266 + </enum> 2267 2267 + <reg32 offset="0" name="0"> 2268 2268 + <bitfield name="DISABLE_PREEMPTION" pos="0" type="boolean"/> 2269 2269 + <bitfield low="28" high="31" name="SCOPE" type="cp_scope"/> 2374 2270 </reg32> 2375 2271 </domain> 2376 2272