Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Pull SCSI updates from James Bottomley:
"Usual driver updates (ufs, mpi3mr, lpfc, pm80xx, mpt3sas) plus
assorted cleanups and fixes.
The only core update is to sd.c and is mostly cosmetic"
* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (105 commits)
scsi: MAINTAINERS: Update FC element owners
scsi: mpt3sas: Update driver version to 54.100.00.00
scsi: mpt3sas: Add support for 22.5 Gbps SAS link rate
scsi: mpt3sas: Suppress unnecessary IOCLogInfo on CONFIG_INVALID_PAGE
scsi: mpt3sas: Fix crash in transport port remove by using ioc_info()
scsi: ufs: ufs-qcom: Add support for limiting HS gear and rate
scsi: ufs: pltfrm: Add DT support to limit HS gear and gear rate
scsi: ufs: ufs-qcom: Remove redundant re-assignment to hs_rate
scsi: ufs: dt-bindings: Document gear and rate limit properties
scsi: ufs: core: Fix data race in CPU latency PM QoS request handling
scsi: libfc: Fix potential buffer overflow in fc_ct_ms_fill()
scsi: storvsc: Remove redundant ternary operators
scsi: ufs: core: Change MCQ interrupt enable flow
scsi: smartpqi: Replace kmalloc() + copy_from_user() with memdup_user()
scsi: hpsa: Replace kmalloc() + copy_from_user() with memdup_user()
scsi: hpsa: Fix potential memory leak in hpsa_big_passthru_ioctl()
scsi: lpfc: Copyright updates for 14.4.0.11 patches
scsi: lpfc: Update lpfc version to 14.4.0.11
scsi: lpfc: Convert debugfs directory counts from atomic to unsigned int
scsi: lpfc: Clean up extraneous phba dentries
...
+1624
-1133
+167
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
+167
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ufs/qcom,sc7180-ufshc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SC7180 and Other SoCs UFS Controllers
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
+
12
+
# Select only our matches, not all jedec,ufs-2.0
13
+
select:
14
+
properties:
15
+
compatible:
16
+
contains:
17
+
enum:
18
+
- qcom,msm8998-ufshc
19
+
- qcom,qcs8300-ufshc
20
+
- qcom,sa8775p-ufshc
21
+
- qcom,sc7180-ufshc
22
+
- qcom,sc7280-ufshc
23
+
- qcom,sc8180x-ufshc
24
+
- qcom,sc8280xp-ufshc
25
+
- qcom,sm8250-ufshc
26
+
- qcom,sm8350-ufshc
27
+
- qcom,sm8450-ufshc
28
+
- qcom,sm8550-ufshc
29
+
required:
30
+
- compatible
31
+
32
+
properties:
33
+
compatible:
34
+
items:
35
+
- enum:
36
+
- qcom,msm8998-ufshc
37
+
- qcom,qcs8300-ufshc
38
+
- qcom,sa8775p-ufshc
39
+
- qcom,sc7180-ufshc
40
+
- qcom,sc7280-ufshc
41
+
- qcom,sc8180x-ufshc
42
+
- qcom,sc8280xp-ufshc
43
+
- qcom,sm8250-ufshc
44
+
- qcom,sm8350-ufshc
45
+
- qcom,sm8450-ufshc
46
+
- qcom,sm8550-ufshc
47
+
- const: qcom,ufshc
48
+
- const: jedec,ufs-2.0
49
+
50
+
reg:
51
+
maxItems: 1
52
+
53
+
reg-names:
54
+
items:
55
+
- const: std
56
+
57
+
clocks:
58
+
minItems: 7
59
+
maxItems: 8
60
+
61
+
clock-names:
62
+
minItems: 7
63
+
items:
64
+
- const: core_clk
65
+
- const: bus_aggr_clk
66
+
- const: iface_clk
67
+
- const: core_clk_unipro
68
+
- const: ref_clk
69
+
- const: tx_lane0_sync_clk
70
+
- const: rx_lane0_sync_clk
71
+
- const: rx_lane1_sync_clk
72
+
73
+
qcom,ice:
74
+
$ref: /schemas/types.yaml#/definitions/phandle
75
+
description: phandle to the Inline Crypto Engine node
76
+
77
+
required:
78
+
- compatible
79
+
- reg
80
+
81
+
allOf:
82
+
- $ref: qcom,ufs-common.yaml
83
+
84
+
- if:
85
+
properties:
86
+
compatible:
87
+
contains:
88
+
enum:
89
+
- qcom,sc7180-ufshc
90
+
then:
91
+
properties:
92
+
clocks:
93
+
maxItems: 7
94
+
clock-names:
95
+
maxItems: 7
96
+
else:
97
+
properties:
98
+
clocks:
99
+
minItems: 8
100
+
clock-names:
101
+
minItems: 8
102
+
103
+
unevaluatedProperties: false
104
+
105
+
examples:
106
+
- |
107
+
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
108
+
#include <dt-bindings/clock/qcom,rpmh.h>
109
+
#include <dt-bindings/gpio/gpio.h>
110
+
#include <dt-bindings/interconnect/qcom,sm8450.h>
111
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
112
+
113
+
soc {
114
+
#address-cells = <2>;
115
+
#size-cells = <2>;
116
+
117
+
ufs@1d84000 {
118
+
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
119
+
"jedec,ufs-2.0";
120
+
reg = <0x0 0x01d84000 0x0 0x3000>;
121
+
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
122
+
phys = <&ufs_mem_phy_lanes>;
123
+
phy-names = "ufsphy";
124
+
lanes-per-direction = <2>;
125
+
#reset-cells = <1>;
126
+
resets = <&gcc GCC_UFS_PHY_BCR>;
127
+
reset-names = "rst";
128
+
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
129
+
130
+
vcc-supply = <&vreg_l7b_2p5>;
131
+
vcc-max-microamp = <1100000>;
132
+
vccq-supply = <&vreg_l9b_1p2>;
133
+
vccq-max-microamp = <1200000>;
134
+
135
+
power-domains = <&gcc UFS_PHY_GDSC>;
136
+
iommus = <&apps_smmu 0xe0 0x0>;
137
+
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
138
+
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
139
+
interconnect-names = "ufs-ddr", "cpu-ufs";
140
+
141
+
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
142
+
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
143
+
<&gcc GCC_UFS_PHY_AHB_CLK>,
144
+
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
145
+
<&rpmhcc RPMH_CXO_CLK>,
146
+
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
147
+
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
148
+
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
149
+
clock-names = "core_clk",
150
+
"bus_aggr_clk",
151
+
"iface_clk",
152
+
"core_clk_unipro",
153
+
"ref_clk",
154
+
"tx_lane0_sync_clk",
155
+
"rx_lane0_sync_clk",
156
+
"rx_lane1_sync_clk";
157
+
freq-table-hz = <75000000 300000000>,
158
+
<0 0>,
159
+
<0 0>,
160
+
<75000000 300000000>,
161
+
<75000000 300000000>,
162
+
<0 0>,
163
+
<0 0>,
164
+
<0 0>;
165
+
qcom,ice = <&ice>;
166
+
};
167
+
};
+178
Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
+178
Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ufs/qcom,sm8650-ufshc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM8650 and Other SoCs UFS Controllers
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
+
12
+
# Select only our matches, not all jedec,ufs-2.0
13
+
select:
14
+
properties:
15
+
compatible:
16
+
contains:
17
+
enum:
18
+
- qcom,sm8650-ufshc
19
+
- qcom,sm8750-ufshc
20
+
required:
21
+
- compatible
22
+
23
+
properties:
24
+
compatible:
25
+
items:
26
+
- enum:
27
+
- qcom,sm8650-ufshc
28
+
- qcom,sm8750-ufshc
29
+
- const: qcom,ufshc
30
+
- const: jedec,ufs-2.0
31
+
32
+
reg:
33
+
minItems: 1
34
+
maxItems: 2
35
+
36
+
reg-names:
37
+
minItems: 1
38
+
items:
39
+
- const: std
40
+
- const: mcq
41
+
42
+
clocks:
43
+
minItems: 8
44
+
maxItems: 8
45
+
46
+
clock-names:
47
+
items:
48
+
- const: core_clk
49
+
- const: bus_aggr_clk
50
+
- const: iface_clk
51
+
- const: core_clk_unipro
52
+
- const: ref_clk
53
+
- const: tx_lane0_sync_clk
54
+
- const: rx_lane0_sync_clk
55
+
- const: rx_lane1_sync_clk
56
+
57
+
qcom,ice:
58
+
$ref: /schemas/types.yaml#/definitions/phandle
59
+
description: phandle to the Inline Crypto Engine node
60
+
61
+
required:
62
+
- compatible
63
+
- reg
64
+
65
+
allOf:
66
+
- $ref: qcom,ufs-common.yaml
67
+
68
+
unevaluatedProperties: false
69
+
70
+
examples:
71
+
- |
72
+
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
73
+
#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
74
+
#include <dt-bindings/clock/qcom,rpmh.h>
75
+
#include <dt-bindings/gpio/gpio.h>
76
+
#include <dt-bindings/interconnect/qcom,icc.h>
77
+
#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
78
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
79
+
80
+
soc {
81
+
#address-cells = <2>;
82
+
#size-cells = <2>;
83
+
84
+
ufshc@1d84000 {
85
+
compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
86
+
reg = <0x0 0x01d84000 0x0 0x3000>;
87
+
88
+
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
89
+
90
+
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
91
+
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
92
+
<&gcc GCC_UFS_PHY_AHB_CLK>,
93
+
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
94
+
<&tcsr TCSR_UFS_PAD_CLKREF_EN>,
95
+
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
96
+
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
97
+
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
98
+
clock-names = "core_clk",
99
+
"bus_aggr_clk",
100
+
"iface_clk",
101
+
"core_clk_unipro",
102
+
"ref_clk",
103
+
"tx_lane0_sync_clk",
104
+
"rx_lane0_sync_clk",
105
+
"rx_lane1_sync_clk";
106
+
107
+
resets = <&gcc GCC_UFS_PHY_BCR>;
108
+
reset-names = "rst";
109
+
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
110
+
111
+
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
112
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
113
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
114
+
&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
115
+
interconnect-names = "ufs-ddr",
116
+
"cpu-ufs";
117
+
118
+
power-domains = <&gcc UFS_PHY_GDSC>;
119
+
required-opps = <&rpmhpd_opp_nom>;
120
+
121
+
operating-points-v2 = <&ufs_opp_table>;
122
+
123
+
iommus = <&apps_smmu 0x60 0>;
124
+
125
+
lanes-per-direction = <2>;
126
+
qcom,ice = <&ice>;
127
+
128
+
phys = <&ufs_mem_phy>;
129
+
phy-names = "ufsphy";
130
+
131
+
#reset-cells = <1>;
132
+
133
+
vcc-supply = <&vreg_l7b_2p5>;
134
+
vcc-max-microamp = <1100000>;
135
+
vccq-supply = <&vreg_l9b_1p2>;
136
+
vccq-max-microamp = <1200000>;
137
+
138
+
ufs_opp_table: opp-table {
139
+
compatible = "operating-points-v2";
140
+
141
+
opp-100000000 {
142
+
opp-hz = /bits/ 64 <100000000>,
143
+
/bits/ 64 <0>,
144
+
/bits/ 64 <0>,
145
+
/bits/ 64 <100000000>,
146
+
/bits/ 64 <0>,
147
+
/bits/ 64 <0>,
148
+
/bits/ 64 <0>,
149
+
/bits/ 64 <0>;
150
+
required-opps = <&rpmhpd_opp_low_svs>;
151
+
};
152
+
153
+
opp-201500000 {
154
+
opp-hz = /bits/ 64 <201500000>,
155
+
/bits/ 64 <0>,
156
+
/bits/ 64 <0>,
157
+
/bits/ 64 <201500000>,
158
+
/bits/ 64 <0>,
159
+
/bits/ 64 <0>,
160
+
/bits/ 64 <0>,
161
+
/bits/ 64 <0>;
162
+
required-opps = <&rpmhpd_opp_svs>;
163
+
};
164
+
165
+
opp-403000000 {
166
+
opp-hz = /bits/ 64 <403000000>,
167
+
/bits/ 64 <0>,
168
+
/bits/ 64 <0>,
169
+
/bits/ 64 <403000000>,
170
+
/bits/ 64 <0>,
171
+
/bits/ 64 <0>,
172
+
/bits/ 64 <0>,
173
+
/bits/ 64 <0>;
174
+
required-opps = <&rpmhpd_opp_nom>;
175
+
};
176
+
};
177
+
};
178
+
};
+67
Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml
+67
Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ufs/qcom,ufs-common.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Universal Flash Storage (UFS) Controller Common Properties
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
+
12
+
properties:
13
+
clocks:
14
+
minItems: 7
15
+
maxItems: 9
16
+
17
+
clock-names:
18
+
minItems: 7
19
+
maxItems: 9
20
+
21
+
dma-coherent: true
22
+
23
+
interconnects:
24
+
minItems: 2
25
+
maxItems: 2
26
+
27
+
interconnect-names:
28
+
items:
29
+
- const: ufs-ddr
30
+
- const: cpu-ufs
31
+
32
+
iommus:
33
+
minItems: 1
34
+
maxItems: 2
35
+
36
+
phys:
37
+
maxItems: 1
38
+
39
+
phy-names:
40
+
items:
41
+
- const: ufsphy
42
+
43
+
power-domains:
44
+
maxItems: 1
45
+
46
+
required-opps:
47
+
maxItems: 1
48
+
49
+
resets:
50
+
maxItems: 1
51
+
52
+
'#reset-cells':
53
+
const: 1
54
+
55
+
reset-names:
56
+
items:
57
+
- const: rst
58
+
59
+
reset-gpios:
60
+
maxItems: 1
61
+
description:
62
+
GPIO connected to the RESET pin of the UFS memory device.
63
+
64
+
allOf:
65
+
- $ref: ufs-common.yaml
66
+
67
+
additionalProperties: true
+34
-151
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+34
-151
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
···
15
15
properties:
16
16
compatible:
17
17
contains:
18
-
const: qcom,ufshc
18
+
enum:
19
+
- qcom,msm8994-ufshc
20
+
- qcom,msm8996-ufshc
21
+
- qcom,qcs615-ufshc
22
+
- qcom,sdm845-ufshc
23
+
- qcom,sm6115-ufshc
24
+
- qcom,sm6125-ufshc
25
+
- qcom,sm6350-ufshc
26
+
- qcom,sm8150-ufshc
19
27
required:
20
28
- compatible
21
29
···
33
25
- enum:
34
26
- qcom,msm8994-ufshc
35
27
- qcom,msm8996-ufshc
36
-
- qcom,msm8998-ufshc
37
28
- qcom,qcs615-ufshc
38
-
- qcom,qcs8300-ufshc
39
-
- qcom,sa8775p-ufshc
40
-
- qcom,sc7180-ufshc
41
-
- qcom,sc7280-ufshc
42
-
- qcom,sc8180x-ufshc
43
-
- qcom,sc8280xp-ufshc
44
29
- qcom,sdm845-ufshc
45
30
- qcom,sm6115-ufshc
46
31
- qcom,sm6125-ufshc
47
32
- qcom,sm6350-ufshc
48
33
- qcom,sm8150-ufshc
49
-
- qcom,sm8250-ufshc
50
-
- qcom,sm8350-ufshc
51
-
- qcom,sm8450-ufshc
52
-
- qcom,sm8550-ufshc
53
-
- qcom,sm8650-ufshc
54
-
- qcom,sm8750-ufshc
55
34
- const: qcom,ufshc
56
35
- const: jedec,ufs-2.0
57
-
58
-
clocks:
59
-
minItems: 7
60
-
maxItems: 9
61
-
62
-
clock-names:
63
-
minItems: 7
64
-
maxItems: 9
65
-
66
-
dma-coherent: true
67
-
68
-
interconnects:
69
-
minItems: 2
70
-
maxItems: 2
71
-
72
-
interconnect-names:
73
-
items:
74
-
- const: ufs-ddr
75
-
- const: cpu-ufs
76
-
77
-
iommus:
78
-
minItems: 1
79
-
maxItems: 2
80
-
81
-
phys:
82
-
maxItems: 1
83
-
84
-
phy-names:
85
-
items:
86
-
- const: ufsphy
87
-
88
-
power-domains:
89
-
maxItems: 1
90
36
91
37
qcom,ice:
92
38
$ref: /schemas/types.yaml#/definitions/phandle
···
55
93
- const: std
56
94
- const: ice
57
95
58
-
required-opps:
59
-
maxItems: 1
60
-
61
-
resets:
62
-
maxItems: 1
63
-
64
-
'#reset-cells':
65
-
const: 1
66
-
67
-
reset-names:
68
-
items:
69
-
- const: rst
70
-
71
-
reset-gpios:
72
-
maxItems: 1
73
-
description:
74
-
GPIO connected to the RESET pin of the UFS memory device.
75
-
76
96
required:
77
97
- compatible
78
98
- reg
79
99
80
100
allOf:
81
-
- $ref: ufs-common.yaml
82
-
83
-
- if:
84
-
properties:
85
-
compatible:
86
-
contains:
87
-
enum:
88
-
- qcom,sc7180-ufshc
89
-
then:
90
-
properties:
91
-
clocks:
92
-
minItems: 7
93
-
maxItems: 7
94
-
clock-names:
95
-
items:
96
-
- const: core_clk
97
-
- const: bus_aggr_clk
98
-
- const: iface_clk
99
-
- const: core_clk_unipro
100
-
- const: ref_clk
101
-
- const: tx_lane0_sync_clk
102
-
- const: rx_lane0_sync_clk
103
-
reg:
104
-
maxItems: 1
105
-
reg-names:
106
-
maxItems: 1
107
-
108
-
- if:
109
-
properties:
110
-
compatible:
111
-
contains:
112
-
enum:
113
-
- qcom,msm8998-ufshc
114
-
- qcom,qcs8300-ufshc
115
-
- qcom,sa8775p-ufshc
116
-
- qcom,sc7280-ufshc
117
-
- qcom,sc8180x-ufshc
118
-
- qcom,sc8280xp-ufshc
119
-
- qcom,sm8250-ufshc
120
-
- qcom,sm8350-ufshc
121
-
- qcom,sm8450-ufshc
122
-
- qcom,sm8550-ufshc
123
-
- qcom,sm8650-ufshc
124
-
- qcom,sm8750-ufshc
125
-
then:
126
-
properties:
127
-
clocks:
128
-
minItems: 8
129
-
maxItems: 8
130
-
clock-names:
131
-
items:
132
-
- const: core_clk
133
-
- const: bus_aggr_clk
134
-
- const: iface_clk
135
-
- const: core_clk_unipro
136
-
- const: ref_clk
137
-
- const: tx_lane0_sync_clk
138
-
- const: rx_lane0_sync_clk
139
-
- const: rx_lane1_sync_clk
140
-
reg:
141
-
minItems: 1
142
-
maxItems: 1
143
-
reg-names:
144
-
maxItems: 1
101
+
- $ref: qcom,ufs-common.yaml
145
102
146
103
- if:
147
104
properties:
···
178
297
179
298
examples:
180
299
- |
181
-
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
300
+
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
182
301
#include <dt-bindings/clock/qcom,rpmh.h>
183
302
#include <dt-bindings/gpio/gpio.h>
184
-
#include <dt-bindings/interconnect/qcom,sm8450.h>
303
+
#include <dt-bindings/interconnect/qcom,sm8150.h>
185
304
#include <dt-bindings/interrupt-controller/arm-gic.h>
186
305
187
306
soc {
···
189
308
#size-cells = <2>;
190
309
191
310
ufs@1d84000 {
192
-
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
311
+
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
193
312
"jedec,ufs-2.0";
194
-
reg = <0 0x01d84000 0 0x3000>;
313
+
reg = <0x0 0x01d84000 0x0 0x2500>,
314
+
<0x0 0x01d90000 0x0 0x8000>;
315
+
reg-names = "std", "ice";
316
+
195
317
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
196
318
phys = <&ufs_mem_phy_lanes>;
197
319
phy-names = "ufsphy";
···
210
326
vccq-max-microamp = <1200000>;
211
327
212
328
power-domains = <&gcc UFS_PHY_GDSC>;
213
-
iommus = <&apps_smmu 0xe0 0x0>;
214
-
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
215
-
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
216
-
interconnect-names = "ufs-ddr", "cpu-ufs";
329
+
iommus = <&apps_smmu 0x300 0>;
217
330
218
-
clock-names = "core_clk",
219
-
"bus_aggr_clk",
220
-
"iface_clk",
221
-
"core_clk_unipro",
222
-
"ref_clk",
223
-
"tx_lane0_sync_clk",
224
-
"rx_lane0_sync_clk",
225
-
"rx_lane1_sync_clk";
226
331
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
227
332
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
228
333
<&gcc GCC_UFS_PHY_AHB_CLK>,
···
219
346
<&rpmhcc RPMH_CXO_CLK>,
220
347
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
221
348
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
222
-
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
223
-
freq-table-hz = <75000000 300000000>,
349
+
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
350
+
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
351
+
clock-names = "core_clk",
352
+
"bus_aggr_clk",
353
+
"iface_clk",
354
+
"core_clk_unipro",
355
+
"ref_clk",
356
+
"tx_lane0_sync_clk",
357
+
"rx_lane0_sync_clk",
358
+
"rx_lane1_sync_clk",
359
+
"ice_core_clk";
360
+
freq-table-hz = <37500000 300000000>,
224
361
<0 0>,
225
362
<0 0>,
226
-
<75000000 300000000>,
227
-
<75000000 300000000>,
363
+
<37500000 300000000>,
228
364
<0 0>,
229
365
<0 0>,
230
-
<0 0>;
231
-
qcom,ice = <&ice>;
366
+
<0 0>,
367
+
<0 0>,
368
+
<0 300000000>;
232
369
};
233
370
};
+16
Documentation/devicetree/bindings/ufs/ufs-common.yaml
+16
Documentation/devicetree/bindings/ufs/ufs-common.yaml
···
89
89
90
90
msi-parent: true
91
91
92
+
limit-hs-gear:
93
+
$ref: /schemas/types.yaml#/definitions/uint32
94
+
minimum: 1
95
+
maximum: 6
96
+
default: 6
97
+
description:
98
+
Restricts the maximum HS gear used in both TX and RX directions.
99
+
100
+
limit-gear-rate:
101
+
$ref: /schemas/types.yaml#/definitions/string
102
+
enum: [rate-a, rate-b]
103
+
default: rate-b
104
+
description:
105
+
Restricts the UFS controller to rate-a or rate-b for both TX and
106
+
RX directions.
107
+
92
108
dependencies:
93
109
freq-table-hz: [ clocks ]
94
110
operating-points-v2: [ clocks, clock-names ]
+5
-4
MAINTAINERS
+5
-4
MAINTAINERS
···
9135
9135
F: include/uapi/rdma/ocrdma-abi.h
9136
9136
9137
9137
EMULEX/BROADCOM EFCT FC/FCOE SCSI TARGET DRIVER
9138
-
M: James Smart <james.smart@broadcom.com>
9139
9138
M: Ram Vegesna <ram.vegesna@broadcom.com>
9140
9139
L: linux-scsi@vger.kernel.org
9141
9140
L: target-devel@vger.kernel.org
···
9143
9144
F: drivers/scsi/elx/
9144
9145
9145
9146
EMULEX/BROADCOM LPFC FC/FCOE SCSI DRIVER
9146
-
M: James Smart <james.smart@broadcom.com>
9147
-
M: Dick Kennedy <dick.kennedy@broadcom.com>
9147
+
M: Justin Tee <justin.tee@broadcom.com>
9148
+
M: Paul Ely <paul.ely@broadcom.com>
9148
9149
L: linux-scsi@vger.kernel.org
9149
9150
S: Supported
9150
9151
W: http://www.broadcom.com
···
18404
18405
F: include/linux/nvme-auth.h
18405
18406
18406
18407
NVM EXPRESS FC TRANSPORT DRIVERS
18407
-
M: James Smart <james.smart@broadcom.com>
18408
+
M: Justin Tee <justin.tee@broadcom.com>
18409
+
M: Naresh Gottumukkala <nareshgottumukkala83@gmail.com>
18410
+
M: Paul Ely <paul.ely@broadcom.com>
18408
18411
L: linux-nvme@lists.infradead.org
18409
18412
S: Supported
18410
18413
F: drivers/nvme/host/fc.c
-1
drivers/scsi/aic94xx/aic94xx_task.c
-1
drivers/scsi/aic94xx/aic94xx_task.c
-1
drivers/scsi/bfa/bfa_core.c
-1
drivers/scsi/bfa/bfa_core.c
···
1282
1282
struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp;
1283
1283
struct bfa_iocfc_fwcfg_s *fwcfg = &cfgrsp->fwcfg;
1284
1284
1285
-
fwcfg->num_cqs = fwcfg->num_cqs;
1286
1285
fwcfg->num_ioim_reqs = be16_to_cpu(fwcfg->num_ioim_reqs);
1287
1286
fwcfg->num_fwtio_reqs = be16_to_cpu(fwcfg->num_fwtio_reqs);
1288
1287
fwcfg->num_tskim_reqs = be16_to_cpu(fwcfg->num_tskim_reqs);
+2
-2
drivers/scsi/csiostor/csio_wr.c
+2
-2
drivers/scsi/csiostor/csio_wr.c
···
960
960
memcpy((uint8_t *) wrp->addr1 + wr_off, data_buf, nbytes);
961
961
data_len -= nbytes;
962
962
963
-
/* Write the remaining data from the begining of circular buffer */
963
+
/* Write the remaining data from the beginning of circular buffer */
964
964
if (data_len) {
965
965
CSIO_DB_ASSERT(data_len <= wrp->size2);
966
966
CSIO_DB_ASSERT(wrp->addr2 != NULL);
···
1224
1224
1225
1225
/*
1226
1226
* We need to re-arm SGE interrupts in case we got a stray interrupt,
1227
-
* especially in msix mode. With INTx, this may be a common occurence.
1227
+
* especially in msix mode. With INTx, this may be a common occurrence.
1228
1228
*/
1229
1229
if (unlikely(!q->inc_idx)) {
1230
1230
CSIO_INC_STATS(q, n_stray_comp);
+1
-1
drivers/scsi/hisi_sas/hisi_sas_main.c
+1
-1
drivers/scsi/hisi_sas/hisi_sas_main.c
···
876
876
device->lldd_dev = sas_dev;
877
877
hisi_hba->hw->setup_itct(hisi_hba, sas_dev);
878
878
879
-
if (parent_dev && dev_is_expander(parent_dev->dev_type)) {
879
+
if (dev_parent_is_expander(device)) {
880
880
int phy_no;
881
881
882
882
phy_no = sas_find_attached_phy_id(&parent_dev->ex_dev, device);
+2
-4
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+2
-4
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
···
925
925
struct device *dev = hisi_hba->dev;
926
926
u64 qw0, device_id = sas_dev->device_id;
927
927
struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
928
-
struct domain_device *parent_dev = device->parent;
929
928
struct asd_sas_port *sas_port = device->port;
930
929
struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
931
930
u64 sas_addr;
···
941
942
break;
942
943
case SAS_SATA_DEV:
943
944
case SAS_SATA_PENDING:
944
-
if (parent_dev && dev_is_expander(parent_dev->dev_type))
945
+
if (dev_parent_is_expander(device))
945
946
qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
946
947
else
947
948
qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
···
2493
2494
{
2494
2495
struct sas_task *task = slot->task;
2495
2496
struct domain_device *device = task->dev;
2496
-
struct domain_device *parent_dev = device->parent;
2497
2497
struct hisi_sas_device *sas_dev = device->lldd_dev;
2498
2498
struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2499
2499
struct asd_sas_port *sas_port = device->port;
···
2507
2509
/* create header */
2508
2510
/* dw0 */
2509
2511
dw0 = port->id << CMD_HDR_PORT_OFF;
2510
-
if (parent_dev && dev_is_expander(parent_dev->dev_type)) {
2512
+
if (dev_parent_is_expander(device)) {
2511
2513
dw0 |= 3 << CMD_HDR_CMD_OFF;
2512
2514
} else {
2513
2515
phy_id = device->phy->identify.phy_identifier;
+2
-4
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+2
-4
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
···
874
874
struct device *dev = hisi_hba->dev;
875
875
u64 qw0, device_id = sas_dev->device_id;
876
876
struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
877
-
struct domain_device *parent_dev = device->parent;
878
877
struct asd_sas_port *sas_port = device->port;
879
878
struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
880
879
u64 sas_addr;
···
890
891
break;
891
892
case SAS_SATA_DEV:
892
893
case SAS_SATA_PENDING:
893
-
if (parent_dev && dev_is_expander(parent_dev->dev_type))
894
+
if (dev_parent_is_expander(device))
894
895
qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
895
896
else
896
897
qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
···
1475
1476
{
1476
1477
struct sas_task *task = slot->task;
1477
1478
struct domain_device *device = task->dev;
1478
-
struct domain_device *parent_dev = device->parent;
1479
1479
struct hisi_sas_device *sas_dev = device->lldd_dev;
1480
1480
struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1481
1481
struct asd_sas_port *sas_port = device->port;
···
1485
1487
u32 dw1 = 0, dw2 = 0;
1486
1488
1487
1489
hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1488
-
if (parent_dev && dev_is_expander(parent_dev->dev_type)) {
1490
+
if (dev_parent_is_expander(device)) {
1489
1491
hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1490
1492
} else {
1491
1493
phy_id = device->phy->identify.phy_identifier;
+23
-30
drivers/scsi/hpsa.c
+23
-30
drivers/scsi/hpsa.c
···
2662
2662
case CMD_TARGET_STATUS:
2663
2663
cmd->result |= ei->ScsiStatus;
2664
2664
/* copy the sense data */
2665
-
if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2666
-
sense_data_size = SCSI_SENSE_BUFFERSIZE;
2667
-
else
2668
-
sense_data_size = sizeof(ei->SenseInfo);
2665
+
sense_data_size = min_t(unsigned long, SCSI_SENSE_BUFFERSIZE,
2666
+
sizeof(ei->SenseInfo));
2669
2667
if (ei->SenseLen < sense_data_size)
2670
2668
sense_data_size = ei->SenseLen;
2671
2669
memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
···
3626
3628
if (rc != 0)
3627
3629
goto exit_unsupported;
3628
3630
pages = buf[3];
3629
-
if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3630
-
bufsize = pages + HPSA_VPD_HEADER_SZ;
3631
-
else
3632
-
bufsize = 255;
3631
+
bufsize = min(pages + HPSA_VPD_HEADER_SZ, 255);
3633
3632
3634
3633
/* Get the whole VPD page list */
3635
3634
rc = hpsa_scsi_do_inquiry(h, scsi3addr,
···
6402
6407
return -EINVAL;
6403
6408
}
6404
6409
if (iocommand->buf_size > 0) {
6405
-
buff = kmalloc(iocommand->buf_size, GFP_KERNEL);
6406
-
if (buff == NULL)
6407
-
return -ENOMEM;
6408
6410
if (iocommand->Request.Type.Direction & XFER_WRITE) {
6409
-
/* Copy the data into the buffer we created */
6410
-
if (copy_from_user(buff, iocommand->buf,
6411
-
iocommand->buf_size)) {
6412
-
rc = -EFAULT;
6413
-
goto out_kfree;
6414
-
}
6411
+
buff = memdup_user(iocommand->buf, iocommand->buf_size);
6412
+
if (IS_ERR(buff))
6413
+
return PTR_ERR(buff);
6415
6414
} else {
6416
-
memset(buff, 0, iocommand->buf_size);
6415
+
buff = kzalloc(iocommand->buf_size, GFP_KERNEL);
6416
+
if (!buff)
6417
+
return -ENOMEM;
6417
6418
}
6418
6419
}
6419
6420
c = cmd_alloc(h);
···
6469
6478
}
6470
6479
out:
6471
6480
cmd_free(h, c);
6472
-
out_kfree:
6473
6481
kfree(buff);
6474
6482
return rc;
6475
6483
}
···
6512
6522
while (left) {
6513
6523
sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6514
6524
buff_size[sg_used] = sz;
6515
-
buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6516
-
if (buff[sg_used] == NULL) {
6517
-
status = -ENOMEM;
6518
-
goto cleanup1;
6519
-
}
6525
+
6520
6526
if (ioc->Request.Type.Direction & XFER_WRITE) {
6521
-
if (copy_from_user(buff[sg_used], data_ptr, sz)) {
6522
-
status = -EFAULT;
6527
+
buff[sg_used] = memdup_user(data_ptr, sz);
6528
+
if (IS_ERR(buff[sg_used])) {
6529
+
status = PTR_ERR(buff[sg_used]);
6523
6530
goto cleanup1;
6524
6531
}
6525
-
} else
6526
-
memset(buff[sg_used], 0, sz);
6532
+
} else {
6533
+
buff[sg_used] = kzalloc(sz, GFP_KERNEL);
6534
+
if (!buff[sg_used]) {
6535
+
status = -ENOMEM;
6536
+
goto cleanup1;
6537
+
}
6538
+
}
6539
+
6527
6540
left -= sz;
6528
6541
data_ptr += sz;
6529
6542
sg_used++;
···
7625
7632
}
7626
7633
7627
7634
/* Find and map CISS config table and transfer table
7628
-
+ * several items must be unmapped (freed) later
7629
-
+ * */
7635
+
* several items must be unmapped (freed) later
7636
+
*/
7630
7637
static int hpsa_find_cfgtables(struct ctlr_info *h)
7631
7638
{
7632
7639
u64 cfg_offset;
+4
-4
drivers/scsi/ipr.c
+4
-4
drivers/scsi/ipr.c
···
4281
4281
}
4282
4282
4283
4283
if (ioa_cfg->sis64)
4284
-
ioa_data = vmalloc(array_size(IPR_FMT3_MAX_NUM_DUMP_PAGES,
4285
-
sizeof(__be32 *)));
4284
+
ioa_data = vmalloc_array(IPR_FMT3_MAX_NUM_DUMP_PAGES,
4285
+
sizeof(__be32 *));
4286
4286
else
4287
-
ioa_data = vmalloc(array_size(IPR_FMT2_MAX_NUM_DUMP_PAGES,
4288
-
sizeof(__be32 *)));
4287
+
ioa_data = vmalloc_array(IPR_FMT2_MAX_NUM_DUMP_PAGES,
4288
+
sizeof(__be32 *));
4289
4289
4290
4290
if (!ioa_data) {
4291
4291
ipr_err("Dump memory allocation failed\n");
+1
-1
drivers/scsi/isci/remote_device.c
+1
-1
drivers/scsi/isci/remote_device.c
···
1434
1434
struct domain_device *dev = idev->domain_dev;
1435
1435
enum sci_status status;
1436
1436
1437
-
if (dev->parent && dev_is_expander(dev->parent->dev_type))
1437
+
if (dev_parent_is_expander(dev))
1438
1438
status = sci_remote_device_ea_construct(iport, idev);
1439
1439
else
1440
1440
status = sci_remote_device_da_construct(iport, idev);
+1
-1
drivers/scsi/libfc/fc_encode.h
+1
-1
drivers/scsi/libfc/fc_encode.h
+1
-4
drivers/scsi/libsas/sas_expander.c
+1
-4
drivers/scsi/libsas/sas_expander.c
+2
-48
drivers/scsi/lpfc/lpfc.h
+2
-48
drivers/scsi/lpfc/lpfc.h
···
1
1
/*******************************************************************
2
2
* This file is part of the Emulex Linux Device Driver for *
3
3
* Fibre Channel Host Bus Adapters. *
4
-
* Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term *
4
+
* Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term *
5
5
* “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6
6
* Copyright (C) 2004-2016 Emulex. All rights reserved. *
7
7
* EMULEX and SLI are trademarks of Emulex. *
···
661
661
uint32_t num_disc_nodes; /* in addition to hba_state */
662
662
uint32_t gidft_inp; /* cnt of outstanding GID_FTs */
663
663
664
-
uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
665
664
uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
666
665
uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
667
666
struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
668
667
struct lpfc_name fc_nodename; /* fc nodename */
669
668
struct lpfc_name fc_portname; /* fc portname */
670
-
671
-
struct lpfc_work_evt disc_timeout_evt;
672
669
673
670
struct timer_list fc_disctmo; /* Discovery rescue timer */
674
671
uint8_t fc_ns_retry; /* retries for fabric nameserver */
···
741
744
struct lpfc_vmid_priority_info vmid_priority;
742
745
743
746
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
744
-
struct dentry *debug_disc_trc;
745
-
struct dentry *debug_nodelist;
746
-
struct dentry *debug_nvmestat;
747
-
struct dentry *debug_scsistat;
748
-
struct dentry *debug_ioktime;
749
-
struct dentry *debug_hdwqstat;
750
747
struct dentry *vport_debugfs_root;
751
748
struct lpfc_debugfs_trc *disc_trc;
752
749
atomic_t disc_trc_cnt;
···
758
767
/* There is a single nvme instance per vport. */
759
768
struct nvme_fc_local_port *localport;
760
769
uint8_t nvmei_support; /* driver supports NVME Initiator */
761
-
uint32_t last_fcp_wqidx;
762
770
uint32_t rcv_flogi_cnt; /* How many unsol FLOGIs ACK'd. */
763
771
};
764
772
···
1050
1060
1051
1061
struct lpfc_dmabuf hbqslimp;
1052
1062
1053
-
uint16_t pci_cfg_value;
1054
-
1055
1063
uint8_t fc_linkspeed; /* Link speed after last READ_LA */
1056
1064
1057
1065
uint32_t fc_eventTag; /* event tag for link attention */
···
1076
1088
1077
1089
struct lpfc_stats fc_stat;
1078
1090
1079
-
struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
1080
1091
uint32_t nport_event_cnt; /* timestamp for nlplist entry */
1081
1092
1082
1093
uint8_t wwnn[8];
···
1216
1229
uint32_t hbq_count; /* Count of configured HBQs */
1217
1230
struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
1218
1231
1219
-
atomic_t fcp_qidx; /* next FCP WQ (RR Policy) */
1220
-
atomic_t nvme_qidx; /* next NVME WQ (RR Policy) */
1221
-
1222
1232
phys_addr_t pci_bar0_map; /* Physical address for PCI BAR0 */
1223
1233
phys_addr_t pci_bar1_map; /* Physical address for PCI BAR1 */
1224
1234
phys_addr_t pci_bar2_map; /* Physical address for PCI BAR2 */
···
1332
1348
unsigned long last_ramp_down_time;
1333
1349
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
1334
1350
struct dentry *hba_debugfs_root;
1335
-
atomic_t debugfs_vport_count;
1336
-
struct dentry *debug_multixri_pools;
1337
-
struct dentry *debug_hbqinfo;
1338
-
struct dentry *debug_dumpHostSlim;
1339
-
struct dentry *debug_dumpHBASlim;
1340
-
struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
1341
-
struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
1342
-
struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
1343
-
struct dentry *debug_writeGuard; /* inject write guard_tag errors */
1344
-
struct dentry *debug_writeApp; /* inject write app_tag errors */
1345
-
struct dentry *debug_writeRef; /* inject write ref_tag errors */
1346
-
struct dentry *debug_readGuard; /* inject read guard_tag errors */
1347
-
struct dentry *debug_readApp; /* inject read app_tag errors */
1348
-
struct dentry *debug_readRef; /* inject read ref_tag errors */
1351
+
unsigned int debugfs_vport_count;
1349
1352
1350
-
struct dentry *debug_nvmeio_trc;
1351
1353
struct lpfc_debugfs_nvmeio_trc *nvmeio_trc;
1352
-
struct dentry *debug_hdwqinfo;
1353
-
#ifdef LPFC_HDWQ_LOCK_STAT
1354
-
struct dentry *debug_lockstat;
1355
-
#endif
1356
-
struct dentry *debug_cgn_buffer;
1357
-
struct dentry *debug_rx_monitor;
1358
-
struct dentry *debug_ras_log;
1359
1354
atomic_t nvmeio_trc_cnt;
1360
1355
uint32_t nvmeio_trc_size;
1361
1356
uint32_t nvmeio_trc_output_idx;
···
1351
1388
sector_t lpfc_injerr_lba;
1352
1389
#define LPFC_INJERR_LBA_OFF (sector_t)(-1)
1353
1390
1354
-
struct dentry *debug_slow_ring_trc;
1355
1391
struct lpfc_debugfs_trc *slow_ring_trc;
1356
1392
atomic_t slow_ring_trc_cnt;
1357
1393
/* iDiag debugfs sub-directory */
1358
1394
struct dentry *idiag_root;
1359
-
struct dentry *idiag_pci_cfg;
1360
-
struct dentry *idiag_bar_acc;
1361
-
struct dentry *idiag_que_info;
1362
-
struct dentry *idiag_que_acc;
1363
-
struct dentry *idiag_drb_acc;
1364
-
struct dentry *idiag_ctl_acc;
1365
-
struct dentry *idiag_mbx_acc;
1366
-
struct dentry *idiag_ext_acc;
1367
1395
uint8_t lpfc_idiag_last_eq;
1368
1396
#endif
1369
1397
uint16_t nvmeio_trc_on;
+204
-410
drivers/scsi/lpfc/lpfc_debugfs.c
+204
-410
drivers/scsi/lpfc/lpfc_debugfs.c
···
2373
2373
2374
2374
static ssize_t
2375
2375
lpfc_debugfs_dif_err_read(struct file *file, char __user *buf,
2376
-
size_t nbytes, loff_t *ppos)
2376
+
size_t nbytes, loff_t *ppos)
2377
2377
{
2378
2378
struct lpfc_hba *phba = file->private_data;
2379
2379
int kind = debugfs_get_aux_num(file);
2380
-
char cbuf[32];
2381
-
uint64_t tmp = 0;
2380
+
char cbuf[32] = {0};
2382
2381
int cnt = 0;
2383
2382
2384
-
if (kind == writeGuard)
2385
-
cnt = scnprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_wgrd_cnt);
2386
-
else if (kind == writeApp)
2387
-
cnt = scnprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_wapp_cnt);
2388
-
else if (kind == writeRef)
2389
-
cnt = scnprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_wref_cnt);
2390
-
else if (kind == readGuard)
2391
-
cnt = scnprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_rgrd_cnt);
2392
-
else if (kind == readApp)
2393
-
cnt = scnprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_rapp_cnt);
2394
-
else if (kind == readRef)
2395
-
cnt = scnprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_rref_cnt);
2396
-
else if (kind == InjErrNPortID)
2397
-
cnt = scnprintf(cbuf, 32, "0x%06x\n",
2383
+
switch (kind) {
2384
+
case writeGuard:
2385
+
cnt = scnprintf(cbuf, sizeof(cbuf), "%u\n",
2386
+
phba->lpfc_injerr_wgrd_cnt);
2387
+
break;
2388
+
case writeApp:
2389
+
cnt = scnprintf(cbuf, sizeof(cbuf), "%u\n",
2390
+
phba->lpfc_injerr_wapp_cnt);
2391
+
break;
2392
+
case writeRef:
2393
+
cnt = scnprintf(cbuf, sizeof(cbuf), "%u\n",
2394
+
phba->lpfc_injerr_wref_cnt);
2395
+
break;
2396
+
case readGuard:
2397
+
cnt = scnprintf(cbuf, sizeof(cbuf), "%u\n",
2398
+
phba->lpfc_injerr_rgrd_cnt);
2399
+
break;
2400
+
case readApp:
2401
+
cnt = scnprintf(cbuf, sizeof(cbuf), "%u\n",
2402
+
phba->lpfc_injerr_rapp_cnt);
2403
+
break;
2404
+
case readRef:
2405
+
cnt = scnprintf(cbuf, sizeof(cbuf), "%u\n",
2406
+
phba->lpfc_injerr_rref_cnt);
2407
+
break;
2408
+
case InjErrNPortID:
2409
+
cnt = scnprintf(cbuf, sizeof(cbuf), "0x%06x\n",
2398
2410
phba->lpfc_injerr_nportid);
2399
-
else if (kind == InjErrWWPN) {
2400
-
memcpy(&tmp, &phba->lpfc_injerr_wwpn, sizeof(struct lpfc_name));
2401
-
tmp = cpu_to_be64(tmp);
2402
-
cnt = scnprintf(cbuf, 32, "0x%016llx\n", tmp);
2403
-
} else if (kind == InjErrLBA) {
2404
-
if (phba->lpfc_injerr_lba == (sector_t)(-1))
2405
-
cnt = scnprintf(cbuf, 32, "off\n");
2411
+
break;
2412
+
case InjErrWWPN:
2413
+
cnt = scnprintf(cbuf, sizeof(cbuf), "0x%016llx\n",
2414
+
be64_to_cpu(phba->lpfc_injerr_wwpn.u.wwn_be));
2415
+
break;
2416
+
case InjErrLBA:
2417
+
if (phba->lpfc_injerr_lba == LPFC_INJERR_LBA_OFF)
2418
+
cnt = scnprintf(cbuf, sizeof(cbuf), "off\n");
2406
2419
else
2407
-
cnt = scnprintf(cbuf, 32, "0x%llx\n",
2408
-
(uint64_t) phba->lpfc_injerr_lba);
2409
-
} else
2410
-
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2411
-
"0547 Unknown debugfs error injection entry\n");
2420
+
cnt = scnprintf(cbuf, sizeof(cbuf), "0x%llx\n",
2421
+
(uint64_t)phba->lpfc_injerr_lba);
2422
+
break;
2423
+
default:
2424
+
lpfc_log_msg(phba, KERN_WARNING, LOG_INIT,
2425
+
"0547 Unknown debugfs error injection entry\n");
2426
+
break;
2427
+
}
2412
2428
2413
2429
return simple_read_from_buffer(buf, nbytes, ppos, &cbuf, cnt);
2414
2430
}
2415
2431
2416
2432
static ssize_t
2417
2433
lpfc_debugfs_dif_err_write(struct file *file, const char __user *buf,
2418
-
size_t nbytes, loff_t *ppos)
2434
+
size_t nbytes, loff_t *ppos)
2419
2435
{
2420
2436
struct lpfc_hba *phba = file->private_data;
2421
2437
int kind = debugfs_get_aux_num(file);
2422
-
char dstbuf[33];
2423
-
uint64_t tmp = 0;
2424
-
int size;
2438
+
char dstbuf[33] = {0};
2439
+
unsigned long long tmp;
2440
+
unsigned long size;
2425
2441
2426
-
memset(dstbuf, 0, 33);
2427
-
size = (nbytes < 32) ? nbytes : 32;
2442
+
size = (nbytes < (sizeof(dstbuf) - 1)) ? nbytes : (sizeof(dstbuf) - 1);
2428
2443
if (copy_from_user(dstbuf, buf, size))
2429
2444
return -EFAULT;
2430
2445
2431
-
if (kind == InjErrLBA) {
2432
-
if ((dstbuf[0] == 'o') && (dstbuf[1] == 'f') &&
2433
-
(dstbuf[2] == 'f'))
2434
-
tmp = (uint64_t)(-1);
2446
+
if (kstrtoull(dstbuf, 0, &tmp)) {
2447
+
if (kind != InjErrLBA || !strstr(dstbuf, "off"))
2448
+
return -EINVAL;
2435
2449
}
2436
2450
2437
-
if ((tmp == 0) && (kstrtoull(dstbuf, 0, &tmp)))
2438
-
return -EINVAL;
2439
-
2440
-
if (kind == writeGuard)
2451
+
switch (kind) {
2452
+
case writeGuard:
2441
2453
phba->lpfc_injerr_wgrd_cnt = (uint32_t)tmp;
2442
-
else if (kind == writeApp)
2454
+
break;
2455
+
case writeApp:
2443
2456
phba->lpfc_injerr_wapp_cnt = (uint32_t)tmp;
2444
-
else if (kind == writeRef)
2457
+
break;
2458
+
case writeRef:
2445
2459
phba->lpfc_injerr_wref_cnt = (uint32_t)tmp;
2446
-
else if (kind == readGuard)
2460
+
break;
2461
+
case readGuard:
2447
2462
phba->lpfc_injerr_rgrd_cnt = (uint32_t)tmp;
2448
-
else if (kind == readApp)
2463
+
break;
2464
+
case readApp:
2449
2465
phba->lpfc_injerr_rapp_cnt = (uint32_t)tmp;
2450
-
else if (kind == readRef)
2466
+
break;
2467
+
case readRef:
2451
2468
phba->lpfc_injerr_rref_cnt = (uint32_t)tmp;
2452
-
else if (kind == InjErrLBA)
2453
-
phba->lpfc_injerr_lba = (sector_t)tmp;
2454
-
else if (kind == InjErrNPortID)
2469
+
break;
2470
+
case InjErrLBA:
2471
+
if (strstr(dstbuf, "off"))
2472
+
phba->lpfc_injerr_lba = LPFC_INJERR_LBA_OFF;
2473
+
else
2474
+
phba->lpfc_injerr_lba = (sector_t)tmp;
2475
+
break;
2476
+
case InjErrNPortID:
2455
2477
phba->lpfc_injerr_nportid = (uint32_t)(tmp & Mask_DID);
2456
-
else if (kind == InjErrWWPN) {
2457
-
tmp = cpu_to_be64(tmp);
2458
-
memcpy(&phba->lpfc_injerr_wwpn, &tmp, sizeof(struct lpfc_name));
2459
-
} else
2460
-
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2461
-
"0548 Unknown debugfs error injection entry\n");
2462
-
2478
+
break;
2479
+
case InjErrWWPN:
2480
+
phba->lpfc_injerr_wwpn.u.wwn_be = cpu_to_be64(tmp);
2481
+
break;
2482
+
default:
2483
+
lpfc_log_msg(phba, KERN_WARNING, LOG_INIT,
2484
+
"0548 Unknown debugfs error injection entry\n");
2485
+
break;
2486
+
}
2463
2487
return nbytes;
2464
2488
}
2465
2489
···
5752
5728
};
5753
5729
5754
5730
static struct dentry *lpfc_debugfs_root = NULL;
5755
-
static atomic_t lpfc_debugfs_hba_count;
5731
+
static unsigned int lpfc_debugfs_hba_count;
5756
5732
5757
5733
/*
5758
5734
* File operations for the iDiag debugfs
···
6074
6050
/* Setup lpfc root directory */
6075
6051
if (!lpfc_debugfs_root) {
6076
6052
lpfc_debugfs_root = debugfs_create_dir("lpfc", NULL);
6077
-
atomic_set(&lpfc_debugfs_hba_count, 0);
6053
+
lpfc_debugfs_hba_count = 0;
6054
+
if (IS_ERR(lpfc_debugfs_root)) {
6055
+
lpfc_vlog_msg(vport, KERN_WARNING, LOG_INIT,
6056
+
"0527 Cannot create debugfs lpfc\n");
6057
+
return;
6058
+
}
6078
6059
}
6079
6060
if (!lpfc_debugfs_start_time)
6080
6061
lpfc_debugfs_start_time = jiffies;
···
6090
6061
pport_setup = true;
6091
6062
phba->hba_debugfs_root =
6092
6063
debugfs_create_dir(name, lpfc_debugfs_root);
6093
-
atomic_inc(&lpfc_debugfs_hba_count);
6094
-
atomic_set(&phba->debugfs_vport_count, 0);
6064
+
phba->debugfs_vport_count = 0;
6065
+
if (IS_ERR(phba->hba_debugfs_root)) {
6066
+
lpfc_vlog_msg(vport, KERN_WARNING, LOG_INIT,
6067
+
"0528 Cannot create debugfs %s\n", name);
6068
+
return;
6069
+
}
6070
+
lpfc_debugfs_hba_count++;
6095
6071
6096
6072
/* Multi-XRI pools */
6097
-
snprintf(name, sizeof(name), "multixripools");
6098
-
phba->debug_multixri_pools =
6099
-
debugfs_create_file(name, S_IFREG | 0644,
6100
-
phba->hba_debugfs_root,
6101
-
phba,
6102
-
&lpfc_debugfs_op_multixripools);
6103
-
if (IS_ERR(phba->debug_multixri_pools)) {
6104
-
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6105
-
"0527 Cannot create debugfs multixripools\n");
6106
-
goto debug_failed;
6107
-
}
6073
+
debugfs_create_file("multixripools", 0644,
6074
+
phba->hba_debugfs_root, phba,
6075
+
&lpfc_debugfs_op_multixripools);
6108
6076
6109
6077
/* Congestion Info Buffer */
6110
-
scnprintf(name, sizeof(name), "cgn_buffer");
6111
-
phba->debug_cgn_buffer =
6112
-
debugfs_create_file(name, S_IFREG | 0644,
6113
-
phba->hba_debugfs_root,
6114
-
phba, &lpfc_cgn_buffer_op);
6115
-
if (IS_ERR(phba->debug_cgn_buffer)) {
6116
-
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6117
-
"6527 Cannot create debugfs "
6118
-
"cgn_buffer\n");
6119
-
goto debug_failed;
6120
-
}
6078
+
debugfs_create_file("cgn_buffer", 0644, phba->hba_debugfs_root,
6079
+
phba, &lpfc_cgn_buffer_op);
6121
6080
6122
6081
/* RX Monitor */
6123
-
scnprintf(name, sizeof(name), "rx_monitor");
6124
-
phba->debug_rx_monitor =
6125
-
debugfs_create_file(name, S_IFREG | 0644,
6126
-
phba->hba_debugfs_root,
6127
-
phba, &lpfc_rx_monitor_op);
6128
-
if (IS_ERR(phba->debug_rx_monitor)) {
6129
-
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6130
-
"6528 Cannot create debugfs "
6131
-
"rx_monitor\n");
6132
-
goto debug_failed;
6133
-
}
6082
+
debugfs_create_file("rx_monitor", 0644, phba->hba_debugfs_root,
6083
+
phba, &lpfc_rx_monitor_op);
6134
6084
6135
6085
/* RAS log */
6136
-
snprintf(name, sizeof(name), "ras_log");
6137
-
phba->debug_ras_log =
6138
-
debugfs_create_file(name, 0644,
6139
-
phba->hba_debugfs_root,
6140
-
phba, &lpfc_debugfs_ras_log);
6141
-
if (IS_ERR(phba->debug_ras_log)) {
6142
-
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6143
-
"6148 Cannot create debugfs"
6144
-
" ras_log\n");
6145
-
goto debug_failed;
6146
-
}
6086
+
debugfs_create_file("ras_log", 0644, phba->hba_debugfs_root,
6087
+
phba, &lpfc_debugfs_ras_log);
6147
6088
6148
6089
/* Setup hbqinfo */
6149
-
snprintf(name, sizeof(name), "hbqinfo");
6150
-
phba->debug_hbqinfo =
6151
-
debugfs_create_file(name, S_IFREG | 0644,
6152
-
phba->hba_debugfs_root,
6153
-
phba, &lpfc_debugfs_op_hbqinfo);
6090
+
debugfs_create_file("hbqinfo", 0644, phba->hba_debugfs_root,
6091
+
phba, &lpfc_debugfs_op_hbqinfo);
6154
6092
6155
6093
#ifdef LPFC_HDWQ_LOCK_STAT
6156
6094
/* Setup lockstat */
6157
-
snprintf(name, sizeof(name), "lockstat");
6158
-
phba->debug_lockstat =
6159
-
debugfs_create_file(name, S_IFREG | 0644,
6160
-
phba->hba_debugfs_root,
6161
-
phba, &lpfc_debugfs_op_lockstat);
6162
-
if (IS_ERR(phba->debug_lockstat)) {
6163
-
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6164
-
"4610 Can't create debugfs lockstat\n");
6165
-
goto debug_failed;
6166
-
}
6095
+
debugfs_create_file("lockstat", 0644, phba->hba_debugfs_root,
6096
+
phba, &lpfc_debugfs_op_lockstat);
6167
6097
#endif
6168
-
6169
-
/* Setup dumpHBASlim */
6170
6098
if (phba->sli_rev < LPFC_SLI_REV4) {
6171
-
snprintf(name, sizeof(name), "dumpHBASlim");
6172
-
phba->debug_dumpHBASlim =
6173
-
debugfs_create_file(name,
6174
-
S_IFREG|S_IRUGO|S_IWUSR,
6175
-
phba->hba_debugfs_root,
6176
-
phba, &lpfc_debugfs_op_dumpHBASlim);
6177
-
} else
6178
-
phba->debug_dumpHBASlim = NULL;
6099
+
/* Setup dumpHBASlim */
6100
+
debugfs_create_file("dumpHBASlim", 0644,
6101
+
phba->hba_debugfs_root, phba,
6102
+
&lpfc_debugfs_op_dumpHBASlim);
6103
+
}
6179
6104
6180
-
/* Setup dumpHostSlim */
6181
6105
if (phba->sli_rev < LPFC_SLI_REV4) {
6182
-
snprintf(name, sizeof(name), "dumpHostSlim");
6183
-
phba->debug_dumpHostSlim =
6184
-
debugfs_create_file(name,
6185
-
S_IFREG|S_IRUGO|S_IWUSR,
6186
-
phba->hba_debugfs_root,
6187
-
phba, &lpfc_debugfs_op_dumpHostSlim);
6188
-
} else
6189
-
phba->debug_dumpHostSlim = NULL;
6106
+
/* Setup dumpHostSlim */
6107
+
debugfs_create_file("dumpHostSlim", 0644,
6108
+
phba->hba_debugfs_root, phba,
6109
+
&lpfc_debugfs_op_dumpHostSlim);
6110
+
}
6190
6111
6191
6112
/* Setup DIF Error Injections */
6192
-
phba->debug_InjErrLBA =
6193
-
debugfs_create_file_aux_num("InjErrLBA", 0644,
6194
-
phba->hba_debugfs_root,
6195
-
phba, InjErrLBA, &lpfc_debugfs_op_dif_err);
6113
+
debugfs_create_file_aux_num("InjErrLBA", 0644,
6114
+
phba->hba_debugfs_root, phba,
6115
+
InjErrLBA,
6116
+
&lpfc_debugfs_op_dif_err);
6196
6117
phba->lpfc_injerr_lba = LPFC_INJERR_LBA_OFF;
6197
6118
6198
-
phba->debug_InjErrNPortID =
6199
-
debugfs_create_file_aux_num("InjErrNPortID", 0644,
6200
-
phba->hba_debugfs_root,
6201
-
phba, InjErrNPortID, &lpfc_debugfs_op_dif_err);
6119
+
debugfs_create_file_aux_num("InjErrNPortID", 0644,
6120
+
phba->hba_debugfs_root, phba,
6121
+
InjErrNPortID,
6122
+
&lpfc_debugfs_op_dif_err);
6202
6123
6203
-
phba->debug_InjErrWWPN =
6204
-
debugfs_create_file_aux_num("InjErrWWPN", 0644,
6205
-
phba->hba_debugfs_root,
6206
-
phba, InjErrWWPN, &lpfc_debugfs_op_dif_err);
6124
+
debugfs_create_file_aux_num("InjErrWWPN", 0644,
6125
+
phba->hba_debugfs_root, phba,
6126
+
InjErrWWPN,
6127
+
&lpfc_debugfs_op_dif_err);
6207
6128
6208
-
phba->debug_writeGuard =
6209
-
debugfs_create_file_aux_num("writeGuardInjErr", 0644,
6210
-
phba->hba_debugfs_root,
6211
-
phba, writeGuard, &lpfc_debugfs_op_dif_err);
6129
+
debugfs_create_file_aux_num("writeGuardInjErr", 0644,
6130
+
phba->hba_debugfs_root, phba,
6131
+
writeGuard,
6132
+
&lpfc_debugfs_op_dif_err);
6212
6133
6213
-
phba->debug_writeApp =
6214
-
debugfs_create_file_aux_num("writeAppInjErr", 0644,
6215
-
phba->hba_debugfs_root,
6216
-
phba, writeApp, &lpfc_debugfs_op_dif_err);
6134
+
debugfs_create_file_aux_num("writeAppInjErr", 0644,
6135
+
phba->hba_debugfs_root, phba,
6136
+
writeApp, &lpfc_debugfs_op_dif_err);
6217
6137
6218
-
phba->debug_writeRef =
6219
-
debugfs_create_file_aux_num("writeRefInjErr", 0644,
6220
-
phba->hba_debugfs_root,
6221
-
phba, writeRef, &lpfc_debugfs_op_dif_err);
6138
+
debugfs_create_file_aux_num("writeRefInjErr", 0644,
6139
+
phba->hba_debugfs_root, phba,
6140
+
writeRef, &lpfc_debugfs_op_dif_err);
6222
6141
6223
-
phba->debug_readGuard =
6224
-
debugfs_create_file_aux_num("readGuardInjErr", 0644,
6225
-
phba->hba_debugfs_root,
6226
-
phba, readGuard, &lpfc_debugfs_op_dif_err);
6142
+
debugfs_create_file_aux_num("readGuardInjErr", 0644,
6143
+
phba->hba_debugfs_root, phba,
6144
+
readGuard,
6145
+
&lpfc_debugfs_op_dif_err);
6227
6146
6228
-
phba->debug_readApp =
6229
-
debugfs_create_file_aux_num("readAppInjErr", 0644,
6230
-
phba->hba_debugfs_root,
6231
-
phba, readApp, &lpfc_debugfs_op_dif_err);
6147
+
debugfs_create_file_aux_num("readAppInjErr", 0644,
6148
+
phba->hba_debugfs_root, phba,
6149
+
readApp, &lpfc_debugfs_op_dif_err);
6232
6150
6233
-
phba->debug_readRef =
6234
-
debugfs_create_file_aux_num("readRefInjErr", 0644,
6235
-
phba->hba_debugfs_root,
6236
-
phba, readRef, &lpfc_debugfs_op_dif_err);
6151
+
debugfs_create_file_aux_num("readRefInjErr", 0644,
6152
+
phba->hba_debugfs_root, phba,
6153
+
readRef, &lpfc_debugfs_op_dif_err);
6237
6154
6238
6155
/* Setup slow ring trace */
6239
6156
if (lpfc_debugfs_max_slow_ring_trc) {
···
6199
6224
}
6200
6225
}
6201
6226
6202
-
snprintf(name, sizeof(name), "slow_ring_trace");
6203
-
phba->debug_slow_ring_trc =
6204
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6205
-
phba->hba_debugfs_root,
6206
-
phba, &lpfc_debugfs_op_slow_ring_trc);
6227
+
debugfs_create_file("slow_ring_trace", 0644,
6228
+
phba->hba_debugfs_root, phba,
6229
+
&lpfc_debugfs_op_slow_ring_trc);
6207
6230
if (!phba->slow_ring_trc) {
6208
6231
phba->slow_ring_trc = kcalloc(
6209
6232
lpfc_debugfs_max_slow_ring_trc,
···
6211
6238
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6212
6239
"0416 Cannot create debugfs "
6213
6240
"slow_ring buffer\n");
6214
-
goto debug_failed;
6241
+
goto out;
6215
6242
}
6216
6243
atomic_set(&phba->slow_ring_trc_cnt, 0);
6217
6244
}
6218
6245
6219
-
snprintf(name, sizeof(name), "nvmeio_trc");
6220
-
phba->debug_nvmeio_trc =
6221
-
debugfs_create_file(name, 0644,
6222
-
phba->hba_debugfs_root,
6223
-
phba, &lpfc_debugfs_op_nvmeio_trc);
6246
+
debugfs_create_file("nvmeio_trc", 0644, phba->hba_debugfs_root,
6247
+
phba, &lpfc_debugfs_op_nvmeio_trc);
6224
6248
6225
6249
atomic_set(&phba->nvmeio_trc_cnt, 0);
6226
6250
if (lpfc_debugfs_max_nvmeio_trc) {
···
6263
6293
if (!vport->vport_debugfs_root) {
6264
6294
vport->vport_debugfs_root =
6265
6295
debugfs_create_dir(name, phba->hba_debugfs_root);
6266
-
atomic_inc(&phba->debugfs_vport_count);
6296
+
if (IS_ERR(vport->vport_debugfs_root)) {
6297
+
lpfc_vlog_msg(vport, KERN_WARNING, LOG_INIT,
6298
+
"0529 Cannot create debugfs %s\n", name);
6299
+
return;
6300
+
}
6301
+
phba->debugfs_vport_count++;
6267
6302
}
6268
6303
6269
6304
if (lpfc_debugfs_max_disc_trc) {
···
6295
6320
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6296
6321
"0418 Cannot create debugfs disc trace "
6297
6322
"buffer\n");
6298
-
goto debug_failed;
6323
+
goto out;
6299
6324
}
6300
6325
atomic_set(&vport->disc_trc_cnt, 0);
6301
6326
6302
-
snprintf(name, sizeof(name), "discovery_trace");
6303
-
vport->debug_disc_trc =
6304
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6305
-
vport->vport_debugfs_root,
6306
-
vport, &lpfc_debugfs_op_disc_trc);
6307
-
snprintf(name, sizeof(name), "nodelist");
6308
-
vport->debug_nodelist =
6309
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6310
-
vport->vport_debugfs_root,
6311
-
vport, &lpfc_debugfs_op_nodelist);
6327
+
debugfs_create_file("discovery_trace", 0644, vport->vport_debugfs_root,
6328
+
vport, &lpfc_debugfs_op_disc_trc);
6312
6329
6313
-
snprintf(name, sizeof(name), "nvmestat");
6314
-
vport->debug_nvmestat =
6315
-
debugfs_create_file(name, 0644,
6316
-
vport->vport_debugfs_root,
6317
-
vport, &lpfc_debugfs_op_nvmestat);
6330
+
debugfs_create_file("nodelist", 0644, vport->vport_debugfs_root, vport,
6331
+
&lpfc_debugfs_op_nodelist);
6318
6332
6319
-
snprintf(name, sizeof(name), "scsistat");
6320
-
vport->debug_scsistat =
6321
-
debugfs_create_file(name, 0644,
6322
-
vport->vport_debugfs_root,
6323
-
vport, &lpfc_debugfs_op_scsistat);
6324
-
if (IS_ERR(vport->debug_scsistat)) {
6325
-
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6326
-
"4611 Cannot create debugfs scsistat\n");
6327
-
goto debug_failed;
6328
-
}
6333
+
debugfs_create_file("nvmestat", 0644, vport->vport_debugfs_root, vport,
6334
+
&lpfc_debugfs_op_nvmestat);
6329
6335
6330
-
snprintf(name, sizeof(name), "ioktime");
6331
-
vport->debug_ioktime =
6332
-
debugfs_create_file(name, 0644,
6333
-
vport->vport_debugfs_root,
6334
-
vport, &lpfc_debugfs_op_ioktime);
6335
-
if (IS_ERR(vport->debug_ioktime)) {
6336
-
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
6337
-
"0815 Cannot create debugfs ioktime\n");
6338
-
goto debug_failed;
6339
-
}
6336
+
debugfs_create_file("scsistat", 0644, vport->vport_debugfs_root, vport,
6337
+
&lpfc_debugfs_op_scsistat);
6340
6338
6341
-
snprintf(name, sizeof(name), "hdwqstat");
6342
-
vport->debug_hdwqstat =
6343
-
debugfs_create_file(name, 0644,
6344
-
vport->vport_debugfs_root,
6345
-
vport, &lpfc_debugfs_op_hdwqstat);
6339
+
debugfs_create_file("ioktime", 0644, vport->vport_debugfs_root, vport,
6340
+
&lpfc_debugfs_op_ioktime);
6341
+
6342
+
debugfs_create_file("hdwqstat", 0644, vport->vport_debugfs_root, vport,
6343
+
&lpfc_debugfs_op_hdwqstat);
6346
6344
6347
6345
/*
6348
6346
* The following section is for additional directories/files for the
···
6323
6375
*/
6324
6376
6325
6377
if (!pport_setup)
6326
-
goto debug_failed;
6378
+
return;
6327
6379
6328
6380
/*
6329
6381
* iDiag debugfs root entry points for SLI4 device only
6330
6382
*/
6331
6383
if (phba->sli_rev < LPFC_SLI_REV4)
6332
-
goto debug_failed;
6384
+
return;
6333
6385
6334
-
snprintf(name, sizeof(name), "iDiag");
6335
6386
if (!phba->idiag_root) {
6336
6387
phba->idiag_root =
6337
-
debugfs_create_dir(name, phba->hba_debugfs_root);
6388
+
debugfs_create_dir("iDiag", phba->hba_debugfs_root);
6338
6389
/* Initialize iDiag data structure */
6339
6390
memset(&idiag, 0, sizeof(idiag));
6340
6391
}
6341
6392
6342
6393
/* iDiag read PCI config space */
6343
-
snprintf(name, sizeof(name), "pciCfg");
6344
-
if (!phba->idiag_pci_cfg) {
6345
-
phba->idiag_pci_cfg =
6346
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6347
-
phba->idiag_root, phba, &lpfc_idiag_op_pciCfg);
6348
-
idiag.offset.last_rd = 0;
6349
-
}
6394
+
debugfs_create_file("pciCfg", 0644, phba->idiag_root, phba,
6395
+
&lpfc_idiag_op_pciCfg);
6396
+
idiag.offset.last_rd = 0;
6350
6397
6351
6398
/* iDiag PCI BAR access */
6352
-
snprintf(name, sizeof(name), "barAcc");
6353
-
if (!phba->idiag_bar_acc) {
6354
-
phba->idiag_bar_acc =
6355
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6356
-
phba->idiag_root, phba, &lpfc_idiag_op_barAcc);
6357
-
idiag.offset.last_rd = 0;
6358
-
}
6399
+
debugfs_create_file("barAcc", 0644, phba->idiag_root, phba,
6400
+
&lpfc_idiag_op_barAcc);
6401
+
idiag.offset.last_rd = 0;
6359
6402
6360
6403
/* iDiag get PCI function queue information */
6361
-
snprintf(name, sizeof(name), "queInfo");
6362
-
if (!phba->idiag_que_info) {
6363
-
phba->idiag_que_info =
6364
-
debugfs_create_file(name, S_IFREG|S_IRUGO,
6365
-
phba->idiag_root, phba, &lpfc_idiag_op_queInfo);
6366
-
}
6404
+
debugfs_create_file("queInfo", 0444, phba->idiag_root, phba,
6405
+
&lpfc_idiag_op_queInfo);
6367
6406
6368
6407
/* iDiag access PCI function queue */
6369
-
snprintf(name, sizeof(name), "queAcc");
6370
-
if (!phba->idiag_que_acc) {
6371
-
phba->idiag_que_acc =
6372
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6373
-
phba->idiag_root, phba, &lpfc_idiag_op_queAcc);
6374
-
}
6408
+
debugfs_create_file("queAcc", 0644, phba->idiag_root, phba,
6409
+
&lpfc_idiag_op_queAcc);
6375
6410
6376
6411
/* iDiag access PCI function doorbell registers */
6377
-
snprintf(name, sizeof(name), "drbAcc");
6378
-
if (!phba->idiag_drb_acc) {
6379
-
phba->idiag_drb_acc =
6380
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6381
-
phba->idiag_root, phba, &lpfc_idiag_op_drbAcc);
6382
-
}
6412
+
debugfs_create_file("drbAcc", 0644, phba->idiag_root, phba,
6413
+
&lpfc_idiag_op_drbAcc);
6383
6414
6384
6415
/* iDiag access PCI function control registers */
6385
-
snprintf(name, sizeof(name), "ctlAcc");
6386
-
if (!phba->idiag_ctl_acc) {
6387
-
phba->idiag_ctl_acc =
6388
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6389
-
phba->idiag_root, phba, &lpfc_idiag_op_ctlAcc);
6390
-
}
6416
+
debugfs_create_file("ctlAcc", 0644, phba->idiag_root, phba,
6417
+
&lpfc_idiag_op_ctlAcc);
6391
6418
6392
6419
/* iDiag access mbox commands */
6393
-
snprintf(name, sizeof(name), "mbxAcc");
6394
-
if (!phba->idiag_mbx_acc) {
6395
-
phba->idiag_mbx_acc =
6396
-
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
6397
-
phba->idiag_root, phba, &lpfc_idiag_op_mbxAcc);
6398
-
}
6420
+
debugfs_create_file("mbxAcc", 0644, phba->idiag_root, phba,
6421
+
&lpfc_idiag_op_mbxAcc);
6399
6422
6400
6423
/* iDiag extents access commands */
6401
6424
if (phba->sli4_hba.extents_in_use) {
6402
-
snprintf(name, sizeof(name), "extAcc");
6403
-
if (!phba->idiag_ext_acc) {
6404
-
phba->idiag_ext_acc =
6405
-
debugfs_create_file(name,
6406
-
S_IFREG|S_IRUGO|S_IWUSR,
6407
-
phba->idiag_root, phba,
6408
-
&lpfc_idiag_op_extAcc);
6409
-
}
6425
+
debugfs_create_file("extAcc", 0644, phba->idiag_root, phba,
6426
+
&lpfc_idiag_op_extAcc);
6410
6427
}
6411
-
6412
-
debug_failed:
6428
+
out:
6429
+
/* alloc'ed items are kfree'd in lpfc_debugfs_terminate */
6413
6430
return;
6414
6431
#endif
6415
6432
}
···
6399
6486
kfree(vport->disc_trc);
6400
6487
vport->disc_trc = NULL;
6401
6488
6402
-
debugfs_remove(vport->debug_disc_trc); /* discovery_trace */
6403
-
vport->debug_disc_trc = NULL;
6404
-
6405
-
debugfs_remove(vport->debug_nodelist); /* nodelist */
6406
-
vport->debug_nodelist = NULL;
6407
-
6408
-
debugfs_remove(vport->debug_nvmestat); /* nvmestat */
6409
-
vport->debug_nvmestat = NULL;
6410
-
6411
-
debugfs_remove(vport->debug_scsistat); /* scsistat */
6412
-
vport->debug_scsistat = NULL;
6413
-
6414
-
debugfs_remove(vport->debug_ioktime); /* ioktime */
6415
-
vport->debug_ioktime = NULL;
6416
-
6417
-
debugfs_remove(vport->debug_hdwqstat); /* hdwqstat */
6418
-
vport->debug_hdwqstat = NULL;
6419
-
6420
6489
if (vport->vport_debugfs_root) {
6421
6490
debugfs_remove(vport->vport_debugfs_root); /* vportX */
6422
6491
vport->vport_debugfs_root = NULL;
6423
-
atomic_dec(&phba->debugfs_vport_count);
6492
+
phba->debugfs_vport_count--;
6424
6493
}
6425
6494
6426
-
if (atomic_read(&phba->debugfs_vport_count) == 0) {
6427
-
6428
-
debugfs_remove(phba->debug_multixri_pools); /* multixripools*/
6429
-
phba->debug_multixri_pools = NULL;
6430
-
6431
-
debugfs_remove(phba->debug_hbqinfo); /* hbqinfo */
6432
-
phba->debug_hbqinfo = NULL;
6433
-
6434
-
debugfs_remove(phba->debug_cgn_buffer);
6435
-
phba->debug_cgn_buffer = NULL;
6436
-
6437
-
debugfs_remove(phba->debug_rx_monitor);
6438
-
phba->debug_rx_monitor = NULL;
6439
-
6440
-
debugfs_remove(phba->debug_ras_log);
6441
-
phba->debug_ras_log = NULL;
6442
-
6443
-
#ifdef LPFC_HDWQ_LOCK_STAT
6444
-
debugfs_remove(phba->debug_lockstat); /* lockstat */
6445
-
phba->debug_lockstat = NULL;
6446
-
#endif
6447
-
debugfs_remove(phba->debug_dumpHBASlim); /* HBASlim */
6448
-
phba->debug_dumpHBASlim = NULL;
6449
-
6450
-
debugfs_remove(phba->debug_dumpHostSlim); /* HostSlim */
6451
-
phba->debug_dumpHostSlim = NULL;
6452
-
6453
-
debugfs_remove(phba->debug_InjErrLBA); /* InjErrLBA */
6454
-
phba->debug_InjErrLBA = NULL;
6455
-
6456
-
debugfs_remove(phba->debug_InjErrNPortID);
6457
-
phba->debug_InjErrNPortID = NULL;
6458
-
6459
-
debugfs_remove(phba->debug_InjErrWWPN); /* InjErrWWPN */
6460
-
phba->debug_InjErrWWPN = NULL;
6461
-
6462
-
debugfs_remove(phba->debug_writeGuard); /* writeGuard */
6463
-
phba->debug_writeGuard = NULL;
6464
-
6465
-
debugfs_remove(phba->debug_writeApp); /* writeApp */
6466
-
phba->debug_writeApp = NULL;
6467
-
6468
-
debugfs_remove(phba->debug_writeRef); /* writeRef */
6469
-
phba->debug_writeRef = NULL;
6470
-
6471
-
debugfs_remove(phba->debug_readGuard); /* readGuard */
6472
-
phba->debug_readGuard = NULL;
6473
-
6474
-
debugfs_remove(phba->debug_readApp); /* readApp */
6475
-
phba->debug_readApp = NULL;
6476
-
6477
-
debugfs_remove(phba->debug_readRef); /* readRef */
6478
-
phba->debug_readRef = NULL;
6479
-
6495
+
if (!phba->debugfs_vport_count) {
6480
6496
kfree(phba->slow_ring_trc);
6481
6497
phba->slow_ring_trc = NULL;
6482
-
6483
-
/* slow_ring_trace */
6484
-
debugfs_remove(phba->debug_slow_ring_trc);
6485
-
phba->debug_slow_ring_trc = NULL;
6486
-
6487
-
debugfs_remove(phba->debug_nvmeio_trc);
6488
-
phba->debug_nvmeio_trc = NULL;
6489
6498
6490
6499
kfree(phba->nvmeio_trc);
6491
6500
phba->nvmeio_trc = NULL;
6492
6501
6493
-
/*
6494
-
* iDiag release
6495
-
*/
6496
-
if (phba->sli_rev == LPFC_SLI_REV4) {
6497
-
/* iDiag extAcc */
6498
-
debugfs_remove(phba->idiag_ext_acc);
6499
-
phba->idiag_ext_acc = NULL;
6500
-
6501
-
/* iDiag mbxAcc */
6502
-
debugfs_remove(phba->idiag_mbx_acc);
6503
-
phba->idiag_mbx_acc = NULL;
6504
-
6505
-
/* iDiag ctlAcc */
6506
-
debugfs_remove(phba->idiag_ctl_acc);
6507
-
phba->idiag_ctl_acc = NULL;
6508
-
6509
-
/* iDiag drbAcc */
6510
-
debugfs_remove(phba->idiag_drb_acc);
6511
-
phba->idiag_drb_acc = NULL;
6512
-
6513
-
/* iDiag queAcc */
6514
-
debugfs_remove(phba->idiag_que_acc);
6515
-
phba->idiag_que_acc = NULL;
6516
-
6517
-
/* iDiag queInfo */
6518
-
debugfs_remove(phba->idiag_que_info);
6519
-
phba->idiag_que_info = NULL;
6520
-
6521
-
/* iDiag barAcc */
6522
-
debugfs_remove(phba->idiag_bar_acc);
6523
-
phba->idiag_bar_acc = NULL;
6524
-
6525
-
/* iDiag pciCfg */
6526
-
debugfs_remove(phba->idiag_pci_cfg);
6527
-
phba->idiag_pci_cfg = NULL;
6528
-
6529
-
/* Finally remove the iDiag debugfs root */
6530
-
debugfs_remove(phba->idiag_root);
6531
-
phba->idiag_root = NULL;
6532
-
}
6533
-
6534
6502
if (phba->hba_debugfs_root) {
6535
6503
debugfs_remove(phba->hba_debugfs_root); /* fnX */
6536
6504
phba->hba_debugfs_root = NULL;
6537
-
atomic_dec(&lpfc_debugfs_hba_count);
6505
+
lpfc_debugfs_hba_count--;
6538
6506
}
6539
6507
6540
-
if (atomic_read(&lpfc_debugfs_hba_count) == 0) {
6508
+
if (!lpfc_debugfs_hba_count) {
6541
6509
debugfs_remove(lpfc_debugfs_root); /* lpfc */
6542
6510
lpfc_debugfs_root = NULL;
6543
6511
}
+4
-1
drivers/scsi/lpfc/lpfc_debugfs.h
+4
-1
drivers/scsi/lpfc/lpfc_debugfs.h
···
1
1
/*******************************************************************
2
2
* This file is part of the Emulex Linux Device Driver for *
3
3
* Fibre Channel Host Bus Adapters. *
4
-
* Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term *
4
+
* Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term *
5
5
* “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6
6
* Copyright (C) 2007-2011 Emulex. All rights reserved. *
7
7
* EMULEX and SLI are trademarks of Emulex. *
···
43
43
44
44
/* hbqinfo output buffer size */
45
45
#define LPFC_HBQINFO_SIZE 8192
46
+
47
+
/* hdwqinfo output buffer size */
48
+
#define LPFC_HDWQINFO_SIZE 8192
46
49
47
50
/* nvmestat output buffer size */
48
51
#define LPFC_NVMESTAT_SIZE 8192
+18
-5
drivers/scsi/lpfc/lpfc_els.c
+18
-5
drivers/scsi/lpfc/lpfc_els.c
···
3762
3762
memset(prdf, 0, cmdsize);
3763
3763
prdf->rdf.fpin_cmd = ELS_RDF;
3764
3764
prdf->rdf.desc_len = cpu_to_be32(sizeof(struct lpfc_els_rdf_req) -
3765
-
sizeof(struct fc_els_rdf));
3765
+
sizeof(struct fc_els_rdf_hdr));
3766
3766
prdf->reg_d1.reg_desc.desc_tag = cpu_to_be32(ELS_DTAG_FPIN_REGISTER);
3767
3767
prdf->reg_d1.reg_desc.desc_len = cpu_to_be32(
3768
3768
FC_TLV_DESC_LENGTH_FROM_SZ(prdf->reg_d1));
···
5339
5339
ulp_status, ulp_word4, did);
5340
5340
/* ELS response tag <ulpIoTag> completes */
5341
5341
lpfc_printf_vlog(vport, KERN_INFO, LOG_ELS,
5342
-
"0110 ELS response tag x%x completes "
5342
+
"0110 ELS response tag x%x completes fc_flag x%lx"
5343
5343
"Data: x%x x%x x%x x%x x%lx x%x x%x x%x %p %p\n",
5344
-
iotag, ulp_status, ulp_word4, tmo,
5344
+
iotag, vport->fc_flag, ulp_status, ulp_word4, tmo,
5345
5345
ndlp->nlp_DID, ndlp->nlp_flag, ndlp->nlp_state,
5346
5346
ndlp->nlp_rpi, kref_read(&ndlp->kref), mbox, ndlp);
5347
-
if (mbox) {
5347
+
if (mbox && !test_bit(FC_PT2PT, &vport->fc_flag)) {
5348
5348
if (ulp_status == 0 &&
5349
5349
test_bit(NLP_ACC_REGLOGIN, &ndlp->nlp_flag)) {
5350
5350
if (!lpfc_unreg_rpi(vport, ndlp) &&
···
5403
5403
}
5404
5404
out_free_mbox:
5405
5405
lpfc_mbox_rsrc_cleanup(phba, mbox, MBOX_THD_UNLOCKED);
5406
+
} else if (mbox && test_bit(FC_PT2PT, &vport->fc_flag) &&
5407
+
test_bit(NLP_ACC_REGLOGIN, &ndlp->nlp_flag)) {
5408
+
lpfc_mbx_cmpl_reg_login(phba, mbox);
5409
+
clear_bit(NLP_ACC_REGLOGIN, &ndlp->nlp_flag);
5406
5410
}
5407
5411
out:
5408
5412
if (ndlp && shost) {
···
11263
11259
lpfc_vlog_msg(vport, KERN_WARNING, LOG_ELS,
11264
11260
"0126 FDISC cmpl status: x%x/x%x)\n",
11265
11261
ulp_status, ulp_word4);
11262
+
11263
+
/* drop initial reference */
11264
+
if (!test_and_set_bit(NLP_DROPPED, &ndlp->nlp_flag))
11265
+
lpfc_nlp_put(ndlp);
11266
+
11266
11267
goto fdisc_failed;
11267
11268
}
11268
11269
···
12017
12008
sglq_entry->state = SGL_FREED;
12018
12009
spin_unlock_irqrestore(&phba->sli4_hba.sgl_list_lock,
12019
12010
iflag);
12020
-
12011
+
lpfc_printf_log(phba, KERN_INFO, LOG_ELS | LOG_SLI |
12012
+
LOG_DISCOVERY | LOG_NODE,
12013
+
"0732 ELS XRI ABORT on Node: ndlp=x%px "
12014
+
"xri=x%x\n",
12015
+
ndlp, xri);
12021
12016
if (ndlp) {
12022
12017
lpfc_set_rrq_active(phba, ndlp,
12023
12018
sglq_entry->sli4_lxritag,
+2
-1
drivers/scsi/lpfc/lpfc_hw.h
+2
-1
drivers/scsi/lpfc/lpfc_hw.h
···
1
1
/*******************************************************************
2
2
* This file is part of the Emulex Linux Device Driver for *
3
3
* Fibre Channel Host Bus Adapters. *
4
-
* Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term *
4
+
* Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term *
5
5
* “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6
6
* Copyright (C) 2004-2016 Emulex. All rights reserved. *
7
7
* EMULEX and SLI are trademarks of Emulex. *
···
366
366
} s;
367
367
uint8_t wwn[8];
368
368
uint64_t name __packed __aligned(4);
369
+
__be64 wwn_be __packed __aligned(4);
369
370
} u;
370
371
};
371
372
+3
-3
drivers/scsi/lpfc/lpfc_hw4.h
+3
-3
drivers/scsi/lpfc/lpfc_hw4.h
···
4909
4909
4910
4910
#define ELS_RDF_REG_TAG_CNT 4
4911
4911
struct lpfc_els_rdf_reg_desc {
4912
-
struct fc_df_desc_fpin_reg reg_desc; /* descriptor header */
4912
+
struct fc_df_desc_fpin_reg_hdr reg_desc; /* descriptor header */
4913
4913
__be32 desc_tags[ELS_RDF_REG_TAG_CNT];
4914
4914
/* tags in reg_desc */
4915
4915
};
4916
4916
4917
4917
struct lpfc_els_rdf_req {
4918
-
struct fc_els_rdf rdf; /* hdr up to descriptors */
4918
+
struct fc_els_rdf_hdr rdf; /* hdr up to descriptors */
4919
4919
struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */
4920
4920
};
4921
4921
4922
4922
struct lpfc_els_rdf_rsp {
4923
-
struct fc_els_rdf_resp rdf_resp; /* hdr up to descriptors */
4923
+
struct fc_els_rdf_resp_hdr rdf_resp; /* hdr up to descriptors */
4924
4924
struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */
4925
4925
};
4926
4926
+1
-11
drivers/scsi/lpfc/lpfc_init.c
+1
-11
drivers/scsi/lpfc/lpfc_init.c
···
3057
3057
lpfc_vmid_vport_cleanup(vport);
3058
3058
3059
3059
list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
3060
-
if (vport->port_type != LPFC_PHYSICAL_PORT &&
3061
-
ndlp->nlp_DID == Fabric_DID) {
3062
-
/* Just free up ndlp with Fabric_DID for vports */
3063
-
lpfc_nlp_put(ndlp);
3064
-
continue;
3065
-
}
3066
-
3067
3060
if (ndlp->nlp_DID == Fabric_Cntl_DID &&
3068
3061
ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
3069
3062
lpfc_nlp_put(ndlp);
···
8293
8300
phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
8294
8301
phba->cfg_nvme_seg_cnt);
8295
8302
8296
-
if (phba->cfg_sg_dma_buf_size < SLI4_PAGE_SIZE)
8297
-
i = phba->cfg_sg_dma_buf_size;
8298
-
else
8299
-
i = SLI4_PAGE_SIZE;
8303
+
i = min(phba->cfg_sg_dma_buf_size, SLI4_PAGE_SIZE);
8300
8304
8301
8305
phba->lpfc_sg_dma_buf_pool =
8302
8306
dma_pool_create("lpfc_sg_dma_buf_pool",
+19
-6
drivers/scsi/lpfc/lpfc_nportdisc.c
+19
-6
drivers/scsi/lpfc/lpfc_nportdisc.c
···
1
1
/*******************************************************************
2
2
* This file is part of the Emulex Linux Device Driver for *
3
3
* Fibre Channel Host Bus Adapters. *
4
-
* Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term *
4
+
* Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term *
5
5
* “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6
6
* Copyright (C) 2004-2016 Emulex. All rights reserved. *
7
7
* EMULEX and SLI are trademarks of Emulex. *
···
326
326
/* Now that REG_RPI completed successfully,
327
327
* we can now proceed with sending the PLOGI ACC.
328
328
*/
329
-
rc = lpfc_els_rsp_acc(login_mbox->vport, ELS_CMD_PLOGI,
330
-
save_iocb, ndlp, NULL);
329
+
if (test_bit(FC_PT2PT, &ndlp->vport->fc_flag)) {
330
+
rc = lpfc_els_rsp_acc(login_mbox->vport, ELS_CMD_PLOGI,
331
+
save_iocb, ndlp, login_mbox);
332
+
} else {
333
+
rc = lpfc_els_rsp_acc(login_mbox->vport, ELS_CMD_PLOGI,
334
+
save_iocb, ndlp, NULL);
335
+
}
336
+
331
337
if (rc) {
332
338
lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
333
339
"4576 PLOGI ACC fails pt2pt discovery: "
···
341
335
}
342
336
}
343
337
344
-
/* Now process the REG_RPI cmpl */
345
-
lpfc_mbx_cmpl_reg_login(phba, login_mbox);
346
-
clear_bit(NLP_ACC_REGLOGIN, &ndlp->nlp_flag);
338
+
/* If this is a fabric topology, complete the reg_rpi and prli now.
339
+
* For Pt2Pt, the reg_rpi and PRLI are deferred until after the LS_ACC
340
+
* completes. This ensures, in Pt2Pt, that the PLOGI LS_ACC is sent
341
+
* before the PRLI.
342
+
*/
343
+
if (!test_bit(FC_PT2PT, &ndlp->vport->fc_flag)) {
344
+
/* Now process the REG_RPI cmpl */
345
+
lpfc_mbx_cmpl_reg_login(phba, login_mbox);
346
+
clear_bit(NLP_ACC_REGLOGIN, &ndlp->nlp_flag);
347
+
}
347
348
kfree(save_iocb);
348
349
}
349
350
+2
-6
drivers/scsi/lpfc/lpfc_nvme.c
+2
-6
drivers/scsi/lpfc/lpfc_nvme.c
···
1234
1234
if ((phba->cfg_nvme_enable_fb) &&
1235
1235
test_bit(NLP_FIRSTBURST, &pnode->nlp_flag)) {
1236
1236
req_len = lpfc_ncmd->nvmeCmd->payload_length;
1237
-
if (req_len < pnode->nvme_fb_size)
1238
-
wqe->fcp_iwrite.initial_xfer_len =
1239
-
req_len;
1240
-
else
1241
-
wqe->fcp_iwrite.initial_xfer_len =
1242
-
pnode->nvme_fb_size;
1237
+
wqe->fcp_iwrite.initial_xfer_len = min(req_len,
1238
+
pnode->nvme_fb_size);
1243
1239
} else {
1244
1240
wqe->fcp_iwrite.initial_xfer_len = 0;
1245
1241
}
+10
-4
drivers/scsi/lpfc/lpfc_scsi.c
+10
-4
drivers/scsi/lpfc/lpfc_scsi.c
···
5935
5935
/**
5936
5936
* lpfc_reset_flush_io_context -
5937
5937
* @vport: The virtual port (scsi_host) for the flush context
5938
-
* @tgt_id: If aborting by Target contect - specifies the target id
5938
+
* @tgt_id: If aborting by Target context - specifies the target id
5939
5939
* @lun_id: If aborting by Lun context - specifies the lun id
5940
5940
* @context: specifies the context level to flush at.
5941
5941
*
···
6109
6109
pnode->nlp_fcp_info &= ~NLP_FCP_2_DEVICE;
6110
6110
spin_unlock_irqrestore(&pnode->lock, flags);
6111
6111
}
6112
-
lpfc_reset_flush_io_context(vport, tgt_id, lun_id,
6113
-
LPFC_CTX_TGT);
6112
+
status = lpfc_reset_flush_io_context(vport, tgt_id, lun_id,
6113
+
LPFC_CTX_TGT);
6114
+
if (status != SUCCESS) {
6115
+
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
6116
+
"0726 Target Reset flush status x%x\n",
6117
+
status);
6118
+
return status;
6119
+
}
6114
6120
return FAST_IO_FAIL;
6115
6121
}
6116
6122
···
6208
6202
int rc, ret = SUCCESS;
6209
6203
6210
6204
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
6211
-
"3172 SCSI layer issued Host Reset Data:\n");
6205
+
"3172 SCSI layer issued Host Reset\n");
6212
6206
6213
6207
lpfc_offline_prep(phba, LPFC_MBX_WAIT);
6214
6208
lpfc_offline(phba);
+6
-15
drivers/scsi/lpfc/lpfc_sli.c
+6
-15
drivers/scsi/lpfc/lpfc_sli.c
···
8820
8820
if (unlikely(rc)) {
8821
8821
lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8822
8822
"0381 Error %d during queue setup.\n", rc);
8823
-
goto out_stop_timers;
8823
+
goto out_destroy_queue;
8824
8824
}
8825
8825
/* Initialize the driver internal SLI layer lists. */
8826
8826
lpfc_sli4_setup(phba);
···
9103
9103
lpfc_free_iocb_list(phba);
9104
9104
out_destroy_queue:
9105
9105
lpfc_sli4_queue_destroy(phba);
9106
-
out_stop_timers:
9107
9106
lpfc_stop_hba_timers(phba);
9108
9107
out_free_mbox:
9109
9108
mempool_free(mboxq, phba->mbox_mem_pool);
···
12438
12439
}
12439
12440
12440
12441
/*
12441
-
* If we're unloading, don't abort iocb on the ELS ring, but change
12442
-
* the callback so that nothing happens when it finishes.
12442
+
* Always abort the outstanding WQE and set the IA bit correctly
12443
+
* for the context. This is necessary for correctly removing
12444
+
* outstanding ndlp reference counts when the CQE completes with
12445
+
* the XB bit set.
12443
12446
*/
12444
-
if (test_bit(FC_UNLOADING, &vport->load_flag) &&
12445
-
pring->ringno == LPFC_ELS_RING) {
12446
-
if (cmdiocb->cmd_flag & LPFC_IO_FABRIC)
12447
-
cmdiocb->fabric_cmd_cmpl = lpfc_ignore_els_cmpl;
12448
-
else
12449
-
cmdiocb->cmd_cmpl = lpfc_ignore_els_cmpl;
12450
-
return retval;
12451
-
}
12452
-
12453
-
/* issue ABTS for this IOCB based on iotag */
12454
12447
abtsiocbp = __lpfc_sli_get_iocbq(phba);
12455
12448
if (abtsiocbp == NULL)
12456
12449
return IOCB_NORESOURCE;
···
21364
21373
struct lpfc_sglq *sglq;
21365
21374
struct lpfc_sli_ring *pring;
21366
21375
unsigned long iflags;
21367
-
uint32_t ret = 0;
21376
+
int ret = 0;
21368
21377
21369
21378
/* NVME_LS and NVME_LS ABTS requests. */
21370
21379
if (pwqe->cmd_flag & LPFC_IO_NVME_LS) {
+1
-1
drivers/scsi/lpfc/lpfc_version.h
+1
-1
drivers/scsi/lpfc/lpfc_version.h
+37
-1
drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
+37
-1
drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
···
322
322
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01)
323
323
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00)
324
324
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01)
325
+
#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_WARNING (0x00)
326
+
#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_CRITICAL (0x01)
327
+
#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_FATAL (0x02)
325
328
#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00)
326
329
#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01)
327
330
#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00)
···
1253
1250
__le32 current_key[];
1254
1251
};
1255
1252
#define MPI3_IOUNIT17_PAGEVERSION (0x00)
1253
+
struct mpi3_io_unit_page18 {
1254
+
struct mpi3_config_page_header header;
1255
+
u8 flags;
1256
+
u8 poll_interval;
1257
+
__le16 reserved0a;
1258
+
__le32 reserved0c;
1259
+
};
1260
+
1261
+
#define MPI3_IOUNIT18_PAGEVERSION (0x00)
1262
+
#define MPI3_IOUNIT18_FLAGS_DIRECTATTACHED_ENABLE (0x01)
1263
+
#define MPI3_IOUNIT18_POLLINTERVAL_DISABLE (0x00)
1264
+
#ifndef MPI3_IOUNIT19_DEVICE_MAX
1265
+
#define MPI3_IOUNIT19_DEVICE_MAX (1)
1266
+
#endif
1267
+
struct mpi3_iounit19_device {
1268
+
__le16 temperature;
1269
+
__le16 dev_handle;
1270
+
__le16 persistent_id;
1271
+
__le16 reserved06;
1272
+
};
1273
+
1274
+
#define MPI3_IOUNIT19_DEVICE_TEMPERATURE_UNAVAILABLE (0x8000)
1275
+
struct mpi3_io_unit_page19 {
1276
+
struct mpi3_config_page_header header;
1277
+
__le16 num_devices;
1278
+
__le16 reserved0a;
1279
+
__le32 reserved0c;
1280
+
struct mpi3_iounit19_device device[MPI3_IOUNIT19_DEVICE_MAX];
1281
+
};
1282
+
1283
+
#define MPI3_IOUNIT19_PAGEVERSION (0x00)
1256
1284
struct mpi3_ioc_page0 {
1257
1285
struct mpi3_config_page_header header;
1258
1286
__le32 reserved08;
···
2390
2356
__le16 io_throttle_group;
2391
2357
__le16 io_throttle_group_low;
2392
2358
__le16 io_throttle_group_high;
2393
-
__le32 reserved0c;
2359
+
u8 vd_abort_to;
2360
+
u8 vd_reset_to;
2361
+
__le16 reserved0e;
2394
2362
};
2395
2363
#define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00)
2396
2364
#define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01)
+2
drivers/scsi/mpi3mr/mpi/mpi30_pci.h
+2
drivers/scsi/mpi3mr/mpi/mpi30_pci.h
···
9
9
#define MPI3_NVME_ENCAP_CMD_MAX (1)
10
10
#endif
11
11
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002)
12
+
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_SHIFT (1)
12
13
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000)
13
14
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002)
14
15
#define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK (0x0001)
16
+
#define MPI3_NVME_FLAGS_SUBMISSIONQ_SHIFT (0)
15
17
#define MPI3_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
16
18
#define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0001)
17
19
+1
drivers/scsi/mpi3mr/mpi/mpi30_sas.h
+1
drivers/scsi/mpi3mr/mpi/mpi30_sas.h
···
11
11
#define MPI3_SAS_DEVICE_INFO_STP_INITIATOR (0x00000010)
12
12
#define MPI3_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000008)
13
13
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK (0x00000007)
14
+
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_SHIFT (0)
14
15
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_NO_DEVICE (0x00000000)
15
16
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE (0x00000001)
16
17
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_EXPANDER (0x00000002)
+1
-1
drivers/scsi/mpi3mr/mpi/mpi30_transport.h
+1
-1
drivers/scsi/mpi3mr/mpi/mpi30_transport.h
+6
-2
drivers/scsi/mpi3mr/mpi3mr.h
+6
-2
drivers/scsi/mpi3mr/mpi3mr.h
···
56
56
extern int prot_mask;
57
57
extern atomic64_t event_counter;
58
58
59
-
#define MPI3MR_DRIVER_VERSION "8.14.0.5.50"
60
-
#define MPI3MR_DRIVER_RELDATE "27-June-2025"
59
+
#define MPI3MR_DRIVER_VERSION "8.15.0.5.50"
60
+
#define MPI3MR_DRIVER_RELDATE "12-August-2025"
61
61
62
62
#define MPI3MR_DRIVER_NAME "mpi3mr"
63
63
#define MPI3MR_DRIVER_LICENSE "GPL"
···
697
697
u16 tg_id;
698
698
u32 tg_high;
699
699
u32 tg_low;
700
+
u8 abort_to;
701
+
u8 reset_to;
700
702
struct mpi3mr_throttle_group_info *tg;
701
703
};
702
704
···
740
738
* @wwid: World wide ID
741
739
* @enclosure_logical_id: Enclosure logical identifier
742
740
* @dev_spec: Device type specific information
741
+
* @abort_to: Timeout for abort TM
742
+
* @reset_to: Timeout for Target/LUN reset TM
743
743
* @ref_count: Reference count
744
744
* @state: device state
745
745
*/
+13
drivers/scsi/mpi3mr/mpi3mr_fw.c
+13
drivers/scsi/mpi3mr/mpi3mr_fw.c
···
2353
2353
{
2354
2354
int retval = 0;
2355
2355
u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2356
+
u32 ioc_status;
2357
+
enum mpi3mr_iocstate ioc_state;
2356
2358
2357
2359
num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2358
2360
mrioc->facts.max_op_req_q);
···
2407
2405
2408
2406
if (i == 0) {
2409
2407
/* Not even one queue is created successfully*/
2408
+
retval = -1;
2409
+
goto out_failed;
2410
+
}
2411
+
ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2412
+
ioc_state = mpi3mr_get_iocstate(mrioc);
2413
+
if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2414
+
ioc_state != MRIOC_STATE_READY) {
2415
+
mpi3mr_print_fault_info(mrioc);
2410
2416
retval = -1;
2411
2417
goto out_failed;
2412
2418
}
···
5430
5420
mpi3mr_reset_rc_name(reset_reason));
5431
5421
5432
5422
mrioc->device_refresh_on = 0;
5423
+
scsi_block_requests(mrioc->shost);
5433
5424
mrioc->reset_in_progress = 1;
5434
5425
mrioc->stop_bsgs = 1;
5435
5426
mrioc->prev_reset_result = -1;
···
5539
5528
if (!retval) {
5540
5529
mrioc->diagsave_timeout = 0;
5541
5530
mrioc->reset_in_progress = 0;
5531
+
scsi_unblock_requests(mrioc->shost);
5542
5532
mrioc->pel_abort_requested = 0;
5543
5533
if (mrioc->pel_enabled) {
5544
5534
mrioc->pel_cmds.retry_count = 0;
···
5564
5552
mrioc->device_refresh_on = 0;
5565
5553
mrioc->unrecoverable = 1;
5566
5554
mrioc->reset_in_progress = 0;
5555
+
scsi_unblock_requests(mrioc->shost);
5567
5556
mrioc->stop_bsgs = 0;
5568
5557
retval = -1;
5569
5558
mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
+19
-9
drivers/scsi/mpi3mr/mpi3mr_os.c
+19
-9
drivers/scsi/mpi3mr/mpi3mr_os.c
···
1308
1308
if (vdinf->vd_state == MPI3_DEVICE0_VD_STATE_OFFLINE)
1309
1309
tgtdev->is_hidden = 1;
1310
1310
tgtdev->non_stl = 1;
1311
+
tgtdev->dev_spec.vd_inf.reset_to =
1312
+
max_t(u8, vdinf->vd_reset_to,
1313
+
MPI3MR_INTADMCMD_TIMEOUT);
1314
+
tgtdev->dev_spec.vd_inf.abort_to =
1315
+
max_t(u8, vdinf->vd_abort_to,
1316
+
MPI3MR_INTADMCMD_TIMEOUT);
1311
1317
tgtdev->dev_spec.vd_inf.tg_id = vdinf_io_throttle_group;
1312
1318
tgtdev->dev_spec.vd_inf.tg_high =
1313
1319
le16_to_cpu(vdinf->io_throttle_group_high) * 2048;
···
2055
2049
if (!fwevt->process_evt)
2056
2050
goto evt_ack;
2057
2051
2058
-
dprint_event_bh(mrioc, "processing event(0x%02x) in the bottom half handler\n",
2059
-
fwevt->event_id);
2052
+
dprint_event_bh(mrioc, "processing event(0x%02x) -(0x%08x) in the bottom half handler\n",
2053
+
fwevt->event_id, fwevt->evt_ctx);
2060
2054
2061
2055
switch (fwevt->event_id) {
2062
2056
case MPI3_EVENT_DEVICE_ADDED:
···
2872
2866
"prepare for reset event top half with rc=start\n");
2873
2867
if (mrioc->prepare_for_reset)
2874
2868
return;
2869
+
scsi_block_requests(mrioc->shost);
2875
2870
mrioc->prepare_for_reset = 1;
2876
2871
mrioc->prepare_for_reset_timeout_counter = 0;
2877
2872
} else if (evtdata->reason_code == MPI3_EVENT_PREPARE_RESET_RC_ABORT) {
2878
2873
dprint_event_th(mrioc,
2879
2874
"prepare for reset top half with rc=abort\n");
2880
2875
mrioc->prepare_for_reset = 0;
2876
+
scsi_unblock_requests(mrioc->shost);
2881
2877
mrioc->prepare_for_reset_timeout_counter = 0;
2882
2878
}
2883
2879
if ((event_reply->msg_flags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK)
···
3084
3076
}
3085
3077
if (process_evt_bh || ack_req) {
3086
3078
dprint_event_th(mrioc,
3087
-
"scheduling bottom half handler for event(0x%02x),ack_required=%d\n",
3088
-
evt_type, ack_req);
3079
+
"scheduling bottom half handler for event(0x%02x) - (0x%08x), ack_required=%d\n",
3080
+
evt_type, le32_to_cpu(event_reply->event_context), ack_req);
3089
3081
sz = event_reply->event_data_length * 4;
3090
3082
fwevt = mpi3mr_alloc_fwevt(sz);
3091
3083
if (!fwevt) {
···
3923
3915
if (scsi_tgt_priv_data)
3924
3916
atomic_inc(&scsi_tgt_priv_data->block_io);
3925
3917
3926
-
if (tgtdev && (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)) {
3927
-
if (cmd_priv && tgtdev->dev_spec.pcie_inf.abort_to)
3928
-
timeout = tgtdev->dev_spec.pcie_inf.abort_to;
3929
-
else if (!cmd_priv && tgtdev->dev_spec.pcie_inf.reset_to)
3930
-
timeout = tgtdev->dev_spec.pcie_inf.reset_to;
3918
+
if (tgtdev) {
3919
+
if (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)
3920
+
timeout = cmd_priv ? tgtdev->dev_spec.pcie_inf.abort_to
3921
+
: tgtdev->dev_spec.pcie_inf.reset_to;
3922
+
else if (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_VD)
3923
+
timeout = cmd_priv ? tgtdev->dev_spec.vd_inf.abort_to
3924
+
: tgtdev->dev_spec.vd_inf.reset_to;
3931
3925
}
3932
3926
3933
3927
init_completion(&drv_cmd->done);
+9
-2
drivers/scsi/mpi3mr/mpi3mr_transport.c
+9
-2
drivers/scsi/mpi3mr/mpi3mr_transport.c
···
413
413
sas_address, hba_port);
414
414
if (tgtdev) {
415
415
if (!list_empty(&tgtdev->list)) {
416
-
list_del_init(&tgtdev->list);
417
416
was_on_tgtdev_list = 1;
418
-
mpi3mr_tgtdev_put(tgtdev);
417
+
if (tgtdev->state == MPI3MR_DEV_REMOVE_HS_STARTED) {
418
+
list_del_init(&tgtdev->list);
419
+
mpi3mr_tgtdev_put(tgtdev);
420
+
}
419
421
}
420
422
}
421
423
spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
···
2081
2079
link_rate = (expander_pg1.negotiated_link_rate &
2082
2080
MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK) >>
2083
2081
MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT;
2082
+
if (link_rate < MPI3_SAS_NEG_LINK_RATE_1_5)
2083
+
link_rate = MPI3_SAS_NEG_LINK_RATE_1_5;
2084
2084
mpi3mr_update_links(mrioc, sas_address_parent,
2085
2085
handle, i, link_rate, hba_port);
2086
2086
}
···
2391
2387
tgtdev->dev_spec.sas_sata_inf.hba_port = hba_port;
2392
2388
2393
2389
link_rate = mpi3mr_get_sas_negotiated_logical_linkrate(mrioc, tgtdev);
2390
+
2391
+
if (link_rate < MPI3_SAS_NEG_LINK_RATE_1_5)
2392
+
link_rate = MPI3_SAS_NEG_LINK_RATE_1_5;
2394
2393
2395
2394
mpi3mr_update_links(mrioc, sas_address_parent, tgtdev->dev_handle,
2396
2395
parent_phy_number, link_rate, hba_port);
+7
-1
drivers/scsi/mpt3sas/mpt3sas_base.c
+7
-1
drivers/scsi/mpt3sas/mpt3sas_base.c
···
1420
1420
1421
1421
if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
1422
1422
loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
1423
-
_base_sas_log_info(ioc, loginfo);
1423
+
if (ioc->logging_level & MPT_DEBUG_REPLY)
1424
+
_base_sas_log_info(ioc, loginfo);
1425
+
else {
1426
+
if (!((ioc_status & MPI2_IOCSTATUS_MASK) &
1427
+
MPI2_IOCSTATUS_CONFIG_INVALID_PAGE))
1428
+
_base_sas_log_info(ioc, loginfo);
1429
+
}
1424
1430
}
1425
1431
1426
1432
if (ioc_status || loginfo) {
+2
-2
drivers/scsi/mpt3sas/mpt3sas_base.h
+2
-2
drivers/scsi/mpt3sas/mpt3sas_base.h
···
77
77
#define MPT3SAS_DRIVER_NAME "mpt3sas"
78
78
#define MPT3SAS_AUTHOR "Avago Technologies <MPT-FusionLinux.pdl@avagotech.com>"
79
79
#define MPT3SAS_DESCRIPTION "LSI MPT Fusion SAS 3.0 Device Driver"
80
-
#define MPT3SAS_DRIVER_VERSION "52.100.00.00"
81
-
#define MPT3SAS_MAJOR_VERSION 52
80
+
#define MPT3SAS_DRIVER_VERSION "54.100.00.00"
81
+
#define MPT3SAS_MAJOR_VERSION 54
82
82
#define MPT3SAS_MINOR_VERSION 100
83
83
#define MPT3SAS_BUILD_VERSION 00
84
84
#define MPT3SAS_RELEASE_VERSION 00
+6
-5
drivers/scsi/mpt3sas/mpt3sas_transport.c
+6
-5
drivers/scsi/mpt3sas/mpt3sas_transport.c
···
166
166
case MPI25_SAS_NEG_LINK_RATE_12_0:
167
167
rc = SAS_LINK_RATE_12_0_GBPS;
168
168
break;
169
+
case MPI26_SAS_NEG_LINK_RATE_22_5:
170
+
rc = SAS_LINK_RATE_22_5_GBPS;
171
+
break;
169
172
case MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED:
170
173
rc = SAS_PHY_DISABLED;
171
174
break;
···
990
987
list_for_each_entry_safe(mpt3sas_phy, next_phy,
991
988
&mpt3sas_port->phy_list, port_siblings) {
992
989
if ((ioc->logging_level & MPT_DEBUG_TRANSPORT))
993
-
dev_printk(KERN_INFO, &mpt3sas_port->port->dev,
994
-
"remove: sas_addr(0x%016llx), phy(%d)\n",
995
-
(unsigned long long)
996
-
mpt3sas_port->remote_identify.sas_address,
997
-
mpt3sas_phy->phy_id);
990
+
ioc_info(ioc, "remove: sas_addr(0x%016llx), phy(%d)\n",
991
+
(unsigned long long) mpt3sas_port->remote_identify.sas_address,
992
+
mpt3sas_phy->phy_id);
998
993
mpt3sas_phy->phy_belongs_to_port = 0;
999
994
if (!ioc->remove_host)
1000
995
sas_port_delete_phy(mpt3sas_port->port,
+1
-1
drivers/scsi/mvsas/mv_sas.c
+1
-1
drivers/scsi/mvsas/mv_sas.c
···
1175
1175
mvi_device->dev_type = dev->dev_type;
1176
1176
mvi_device->mvi_info = mvi;
1177
1177
mvi_device->sas_device = dev;
1178
-
if (parent_dev && dev_is_expander(parent_dev->dev_type)) {
1178
+
if (dev_parent_is_expander(dev)) {
1179
1179
int phy_id;
1180
1180
1181
1181
phy_id = sas_find_attached_phy_id(&parent_dev->ex_dev, dev);
+4
-4
drivers/scsi/myrs.c
+4
-4
drivers/scsi/myrs.c
···
498
498
/* Temporary dma mapping, used only in the scope of this function */
499
499
mbox = dma_alloc_coherent(&pdev->dev, sizeof(union myrs_cmd_mbox),
500
500
&mbox_addr, GFP_KERNEL);
501
-
if (dma_mapping_error(&pdev->dev, mbox_addr))
501
+
if (!mbox)
502
502
return false;
503
503
504
504
/* These are the base addresses for the command memory mailbox array */
505
505
cs->cmd_mbox_size = MYRS_MAX_CMD_MBOX * sizeof(union myrs_cmd_mbox);
506
506
cmd_mbox = dma_alloc_coherent(&pdev->dev, cs->cmd_mbox_size,
507
507
&cs->cmd_mbox_addr, GFP_KERNEL);
508
-
if (dma_mapping_error(&pdev->dev, cs->cmd_mbox_addr)) {
508
+
if (!cmd_mbox) {
509
509
dev_err(&pdev->dev, "Failed to map command mailbox\n");
510
510
goto out_free;
511
511
}
···
520
520
cs->stat_mbox_size = MYRS_MAX_STAT_MBOX * sizeof(struct myrs_stat_mbox);
521
521
stat_mbox = dma_alloc_coherent(&pdev->dev, cs->stat_mbox_size,
522
522
&cs->stat_mbox_addr, GFP_KERNEL);
523
-
if (dma_mapping_error(&pdev->dev, cs->stat_mbox_addr)) {
523
+
if (!stat_mbox) {
524
524
dev_err(&pdev->dev, "Failed to map status mailbox\n");
525
525
goto out_free;
526
526
}
···
533
533
cs->fwstat_buf = dma_alloc_coherent(&pdev->dev,
534
534
sizeof(struct myrs_fwstat),
535
535
&cs->fwstat_addr, GFP_KERNEL);
536
-
if (dma_mapping_error(&pdev->dev, cs->fwstat_addr)) {
536
+
if (!cs->fwstat_buf) {
537
537
dev_err(&pdev->dev, "Failed to map firmware health buffer\n");
538
538
cs->fwstat_buf = NULL;
539
539
goto out_free;
+13
-11
drivers/scsi/pm8001/pm8001_ctl.c
+13
-11
drivers/scsi/pm8001/pm8001_ctl.c
···
534
534
char *str = buf;
535
535
u32 read_size =
536
536
pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size / 1024;
537
-
static u32 start, end, count;
538
537
u32 max_read_times = 32;
539
538
u32 max_count = (read_size * 1024) / (max_read_times * 4);
540
539
u32 *temp = (u32 *)pm8001_ha->memoryMap.region[IOP].virt_ptr;
541
540
542
-
if ((count % max_count) == 0) {
543
-
start = 0;
544
-
end = max_read_times;
545
-
count = 0;
541
+
mutex_lock(&pm8001_ha->iop_log_lock);
542
+
543
+
if ((pm8001_ha->iop_log_count % max_count) == 0) {
544
+
pm8001_ha->iop_log_start = 0;
545
+
pm8001_ha->iop_log_end = max_read_times;
546
+
pm8001_ha->iop_log_count = 0;
546
547
} else {
547
-
start = end;
548
-
end = end + max_read_times;
548
+
pm8001_ha->iop_log_start = pm8001_ha->iop_log_end;
549
+
pm8001_ha->iop_log_end = pm8001_ha->iop_log_end + max_read_times;
549
550
}
550
551
551
-
for (; start < end; start++)
552
-
str += sprintf(str, "%08x ", *(temp+start));
553
-
count++;
552
+
for (; pm8001_ha->iop_log_start < pm8001_ha->iop_log_end; pm8001_ha->iop_log_start++)
553
+
str += sprintf(str, "%08x ", *(temp+pm8001_ha->iop_log_start));
554
+
pm8001_ha->iop_log_count++;
555
+
mutex_unlock(&pm8001_ha->iop_log_lock);
554
556
return str - buf;
555
557
}
556
558
static DEVICE_ATTR(iop_log, S_IRUGO, pm8001_ctl_iop_log_show, NULL);
···
682
680
struct pm8001_ioctl_payload *payload;
683
681
DECLARE_COMPLETION_ONSTACK(completion);
684
682
u8 *ioctlbuffer;
685
-
u32 ret;
683
+
int ret;
686
684
u32 length = 1024 * 5 + sizeof(*payload) - 1;
687
685
688
686
if (pm8001_ha->fw_image->size > 4096) {
+4
-7
drivers/scsi/pm8001/pm8001_hwi.c
+4
-7
drivers/scsi/pm8001/pm8001_hwi.c
···
2163
2163
/* Print sas address of IO failed device */
2164
2164
if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2165
2165
(status != IO_UNDERFLOW)) {
2166
-
if (!((t->dev->parent) &&
2167
-
(dev_is_expander(t->dev->parent->dev_type)))) {
2166
+
if (!dev_parent_is_expander(t->dev)) {
2168
2167
for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++)
2169
2168
sata_addr_low[i] = pm8001_ha->sas_addr[j];
2170
2169
for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++)
···
4167
4168
u16 firstBurstSize = 0;
4168
4169
u16 ITNT = 2000;
4169
4170
struct domain_device *dev = pm8001_dev->sas_device;
4170
-
struct domain_device *parent_dev = dev->parent;
4171
4171
struct pm8001_port *port = dev->port->lldd_port;
4172
4172
4173
4173
memset(&payload, 0, sizeof(payload));
···
4184
4186
dev_is_expander(pm8001_dev->dev_type))
4185
4187
stp_sspsmp_sata = 0x01; /*ssp or smp*/
4186
4188
}
4187
-
if (parent_dev && dev_is_expander(parent_dev->dev_type))
4188
-
phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4189
-
else
4190
-
phy_id = pm8001_dev->attached_phy;
4189
+
4190
+
phy_id = pm80xx_get_local_phy_id(dev);
4191
+
4191
4192
opc = OPC_INB_REG_DEV;
4192
4193
linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4193
4194
pm8001_dev->sas_device->linkrate : dev->port->linkrate;
+3
-1
drivers/scsi/pm8001/pm8001_hwi.h
+3
-1
drivers/scsi/pm8001/pm8001_hwi.h
···
339
339
__le32 status;
340
340
__le32 param;
341
341
__le32 ssptag_rescv_rescpad;
342
+
343
+
/* Must be last --ends in a flexible-array member. */
342
344
struct ssp_response_iu ssp_resp_iu;
343
-
__le32 residual_count;
345
+
/* __le32 residual_count; */
344
346
} __attribute__((packed, aligned(4)));
345
347
346
348
+1
drivers/scsi/pm8001/pm8001_init.c
+1
drivers/scsi/pm8001/pm8001_init.c
+26
-8
drivers/scsi/pm8001/pm8001_sas.c
+26
-8
drivers/scsi/pm8001/pm8001_sas.c
···
130
130
}
131
131
}
132
132
133
+
u32 pm80xx_get_local_phy_id(struct domain_device *dev)
134
+
{
135
+
struct pm8001_device *pm8001_dev = dev->lldd_dev;
136
+
137
+
if (dev_parent_is_expander(dev))
138
+
return dev->parent->ex_dev.ex_phy->phy_id;
139
+
140
+
return pm8001_dev->attached_phy;
141
+
}
142
+
133
143
void pm80xx_show_pending_commands(struct pm8001_hba_info *pm8001_ha,
134
144
struct pm8001_device *target_pm8001_dev)
135
145
{
···
487
477
struct pm8001_device *pm8001_dev = dev->lldd_dev;
488
478
bool internal_abort = sas_is_internal_abort(task);
489
479
struct pm8001_hba_info *pm8001_ha;
490
-
struct pm8001_port *port = NULL;
480
+
struct pm8001_port *port;
491
481
struct pm8001_ccb_info *ccb;
492
482
unsigned long flags;
493
483
u32 n_elem = 0;
···
512
502
513
503
spin_lock_irqsave(&pm8001_ha->lock, flags);
514
504
515
-
pm8001_dev = dev->lldd_dev;
516
-
port = pm8001_ha->phy[pm8001_dev->attached_phy].port;
505
+
port = dev->port->lldd_port;
517
506
518
507
if (!internal_abort &&
519
508
(DEV_IS_GONE(pm8001_dev) || !port || !port->port_attached)) {
···
710
701
dev->lldd_dev = pm8001_device;
711
702
pm8001_device->dev_type = dev->dev_type;
712
703
pm8001_device->dcompletion = &completion;
713
-
if (parent_dev && dev_is_expander(parent_dev->dev_type)) {
704
+
if (dev_parent_is_expander(dev)) {
714
705
int phy_id;
715
706
716
707
phy_id = sas_find_attached_phy_id(&parent_dev->ex_dev, dev);
···
775
766
spin_lock_irqsave(&pm8001_ha->lock, flags);
776
767
}
777
768
PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
778
-
pm8001_ha->phy[pm8001_dev->attached_phy].phy_attached = 0;
769
+
770
+
/*
771
+
* The phy array only contains local phys. Thus, we cannot clear
772
+
* phy_attached for a device behind an expander.
773
+
*/
774
+
if (!dev_parent_is_expander(dev)) {
775
+
u32 phy_id = pm80xx_get_local_phy_id(dev);
776
+
777
+
pm8001_ha->phy[phy_id].phy_attached = 0;
778
+
}
779
779
pm8001_free_dev(pm8001_dev);
780
780
} else {
781
781
pm8001_dbg(pm8001_ha, DISC, "Found dev has gone.\n");
···
1066
1048
struct pm8001_hba_info *pm8001_ha;
1067
1049
struct pm8001_device *pm8001_dev;
1068
1050
int rc = TMF_RESP_FUNC_FAILED, ret;
1069
-
u32 phy_id, port_id;
1051
+
u32 port_id;
1070
1052
struct sas_task_slow slow_task;
1071
1053
1072
1054
if (!task->lldd_task || !task->dev)
···
1075
1057
dev = task->dev;
1076
1058
pm8001_dev = dev->lldd_dev;
1077
1059
pm8001_ha = pm8001_find_ha_by_dev(dev);
1078
-
phy_id = pm8001_dev->attached_phy;
1079
1060
1080
1061
if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) {
1081
1062
// If the controller is seeing fatal errors
···
1106
1089
if (pm8001_ha->chip_id == chip_8006) {
1107
1090
DECLARE_COMPLETION_ONSTACK(completion_reset);
1108
1091
DECLARE_COMPLETION_ONSTACK(completion);
1109
-
struct pm8001_phy *phy = pm8001_ha->phy + phy_id;
1092
+
u32 phy_id = pm80xx_get_local_phy_id(dev);
1093
+
struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
1110
1094
port_id = phy->port->port_id;
1111
1095
1112
1096
/* 1. Set Device state as Recovery */
+5
drivers/scsi/pm8001/pm8001_sas.h
+5
drivers/scsi/pm8001/pm8001_sas.h
···
547
547
u32 ci_offset;
548
548
u32 pi_offset;
549
549
u32 max_memcnt;
550
+
u32 iop_log_start;
551
+
u32 iop_log_end;
552
+
u32 iop_log_count;
553
+
struct mutex iop_log_lock;
550
554
};
551
555
552
556
struct pm8001_work {
···
802
798
void pm8001_tmf_aborted(struct sas_task *task);
803
799
void pm80xx_show_pending_commands(struct pm8001_hba_info *pm8001_ha,
804
800
struct pm8001_device *dev);
801
+
u32 pm80xx_get_local_phy_id(struct domain_device *dev);
805
802
806
803
#endif
807
804
+3
-7
drivers/scsi/pm8001/pm80xx_hwi.c
+3
-7
drivers/scsi/pm8001/pm80xx_hwi.c
···
2340
2340
/* Print sas address of IO failed device */
2341
2341
if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2342
2342
(status != IO_UNDERFLOW)) {
2343
-
if (!((t->dev->parent) &&
2344
-
(dev_is_expander(t->dev->parent->dev_type)))) {
2343
+
if (!dev_parent_is_expander(t->dev)) {
2345
2344
for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)
2346
2345
sata_addr_low[i] = pm8001_ha->sas_addr[j];
2347
2346
for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)
···
4779
4780
u16 firstBurstSize = 0;
4780
4781
u16 ITNT = 2000;
4781
4782
struct domain_device *dev = pm8001_dev->sas_device;
4782
-
struct domain_device *parent_dev = dev->parent;
4783
4783
struct pm8001_port *port = dev->port->lldd_port;
4784
4784
4785
4785
memset(&payload, 0, sizeof(payload));
···
4797
4799
dev_is_expander(pm8001_dev->dev_type))
4798
4800
stp_sspsmp_sata = 0x01; /*ssp or smp*/
4799
4801
}
4800
-
if (parent_dev && dev_is_expander(parent_dev->dev_type))
4801
-
phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4802
-
else
4803
-
phy_id = pm8001_dev->attached_phy;
4802
+
4803
+
phy_id = pm80xx_get_local_phy_id(dev);
4804
4804
4805
4805
opc = OPC_INB_REG_DEV;
4806
4806
+3
-1
drivers/scsi/pm8001/pm80xx_hwi.h
+3
-1
drivers/scsi/pm8001/pm80xx_hwi.h
···
558
558
__le32 status;
559
559
__le32 param;
560
560
__le32 ssptag_rescv_rescpad;
561
+
562
+
/* Must be last --ends in a flexible-array member. */
561
563
struct ssp_response_iu ssp_resp_iu;
562
-
__le32 residual_count;
564
+
/* __le32 residual_count; */
563
565
} __attribute__((packed, aligned(4)));
564
566
565
567
#define SSP_RESCV_BIT 0x00010000
+2
-2
drivers/scsi/qla2xxx/qla_bsg.c
+2
-2
drivers/scsi/qla2xxx/qla_bsg.c
···
3106
3106
switch (rval) {
3107
3107
case QLA_SUCCESS:
3108
3108
/* Wait for the command completion. */
3109
-
ratov_j = ha->r_a_tov / 10 * 4 * 1000;
3110
-
ratov_j = msecs_to_jiffies(ratov_j);
3109
+
ratov_j = ha->r_a_tov / 10 * 4;
3110
+
ratov_j = secs_to_jiffies(ratov_j);
3111
3111
3112
3112
if (!wait_for_completion_timeout(&comp, ratov_j)) {
3113
3113
ql_log(ql_log_info, vha, 0x7089,
+6
-4
drivers/scsi/qla2xxx/qla_def.h
+6
-4
drivers/scsi/qla2xxx/qla_def.h
···
4890
4890
struct purex_item *pkt);
4891
4891
atomic_t in_use;
4892
4892
uint16_t size;
4893
-
struct {
4894
-
uint8_t iocb[64];
4895
-
} iocb;
4893
+
uint8_t iocb[] __counted_by(size);
4896
4894
};
4897
4895
4898
4896
#include "qla_edif.h"
···
5099
5101
struct list_head head;
5100
5102
spinlock_t lock;
5101
5103
} purex_list;
5102
-
struct purex_item default_item;
5103
5104
5104
5105
struct name_list_extended gnl;
5105
5106
/* Count of active session/fcport */
···
5127
5130
#define DPORT_DIAG_IN_PROGRESS BIT_0
5128
5131
#define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1
5129
5132
uint16_t dport_status;
5133
+
5134
+
/* Must be last --ends in a flexible-array member. */
5135
+
TRAILING_OVERLAP(struct purex_item, default_item, iocb,
5136
+
uint8_t __default_item_iocb[QLA_DEFAULT_PAYLOAD_SIZE];
5137
+
);
5130
5138
} scsi_qla_host_t;
5131
5139
5132
5140
struct qla27xx_image_status {
+2
-2
drivers/scsi/qla2xxx/qla_edif.c
+2
-2
drivers/scsi/qla2xxx/qla_edif.c
···
1798
1798
switch (rval) {
1799
1799
case QLA_SUCCESS:
1800
1800
break;
1801
-
case EAGAIN:
1801
+
case -EAGAIN:
1802
1802
msleep(EDIF_MSLEEP_INTERVAL);
1803
1803
cnt++;
1804
1804
if (cnt < EDIF_RETRY_COUNT)
···
3649
3649
p->e.extra_rx_xchg_address, p->e.extra_control_flags,
3650
3650
sp->handle, sp->remap.req.len, bsg_job);
3651
3651
break;
3652
-
case EAGAIN:
3652
+
case -EAGAIN:
3653
3653
msleep(EDIF_MSLEEP_INTERVAL);
3654
3654
cnt++;
3655
3655
if (cnt < EDIF_RETRY_COUNT)
+2
-2
drivers/scsi/qla2xxx/qla_init.c
+2
-2
drivers/scsi/qla2xxx/qla_init.c
···
2059
2059
int cnt = 5; \
2060
2060
do { \
2061
2061
if (_chip_gen != sp->vha->hw->chip_reset || _login_gen != sp->fcport->login_gen) {\
2062
-
_rval = EINVAL; \
2062
+
_rval = -EINVAL; \
2063
2063
break; \
2064
2064
} \
2065
2065
_rval = qla2x00_start_sp(_sp); \
2066
-
if (_rval == EAGAIN) \
2066
+
if (_rval == -EAGAIN) \
2067
2067
msleep(1); \
2068
2068
else \
2069
2069
break; \
+8
-9
drivers/scsi/qla2xxx/qla_isr.c
+8
-9
drivers/scsi/qla2xxx/qla_isr.c
···
1077
1077
qla24xx_alloc_purex_item(scsi_qla_host_t *vha, uint16_t size)
1078
1078
{
1079
1079
struct purex_item *item = NULL;
1080
-
uint8_t item_hdr_size = sizeof(*item);
1081
1080
1082
1081
if (size > QLA_DEFAULT_PAYLOAD_SIZE) {
1083
-
item = kzalloc(item_hdr_size +
1084
-
(size - QLA_DEFAULT_PAYLOAD_SIZE), GFP_ATOMIC);
1082
+
item = kzalloc(struct_size(item, iocb, size), GFP_ATOMIC);
1085
1083
} else {
1086
1084
if (atomic_inc_return(&vha->default_item.in_use) == 1) {
1087
1085
item = &vha->default_item;
1088
1086
goto initialize_purex_header;
1089
1087
} else {
1090
-
item = kzalloc(item_hdr_size, GFP_ATOMIC);
1088
+
item = kzalloc(
1089
+
struct_size(item, iocb, QLA_DEFAULT_PAYLOAD_SIZE),
1090
+
GFP_ATOMIC);
1091
1091
}
1092
1092
}
1093
1093
if (!item) {
···
1127
1127
* @vha: SCSI driver HA context
1128
1128
* @pkt: ELS packet
1129
1129
*/
1130
-
static struct purex_item
1131
-
*qla24xx_copy_std_pkt(struct scsi_qla_host *vha, void *pkt)
1130
+
static struct purex_item *
1131
+
qla24xx_copy_std_pkt(struct scsi_qla_host *vha, void *pkt)
1132
1132
{
1133
1133
struct purex_item *item;
1134
1134
1135
-
item = qla24xx_alloc_purex_item(vha,
1136
-
QLA_DEFAULT_PAYLOAD_SIZE);
1135
+
item = qla24xx_alloc_purex_item(vha, QLA_DEFAULT_PAYLOAD_SIZE);
1137
1136
if (!item)
1138
1137
return item;
1139
1138
1140
-
memcpy(&item->iocb, pkt, sizeof(item->iocb));
1139
+
memcpy(&item->iocb, pkt, QLA_DEFAULT_PAYLOAD_SIZE);
1141
1140
return item;
1142
1141
}
1143
1142
+2
-2
drivers/scsi/qla2xxx/qla_nvme.c
+2
-2
drivers/scsi/qla2xxx/qla_nvme.c
···
419
419
switch (rval) {
420
420
case QLA_SUCCESS:
421
421
break;
422
-
case EAGAIN:
422
+
case -EAGAIN:
423
423
msleep(PURLS_MSLEEP_INTERVAL);
424
424
cnt++;
425
425
if (cnt < PURLS_RETRY_COUNT)
···
1308
1308
1309
1309
ql_dbg(ql_dbg_unsol, vha, 0x2121,
1310
1310
"PURLS OP[%01x] size %d xchg addr 0x%x portid %06x\n",
1311
-
item->iocb.iocb[3], item->size, uctx->exchange_address,
1311
+
item->iocb[3], item->size, uctx->exchange_address,
1312
1312
fcport->d_id.b24);
1313
1313
/* +48 0 1 2 3 4 5 6 7 8 9 A B C D E F
1314
1314
* ----- -----------------------------------------------
+7
-6
drivers/scsi/qla2xxx/qla_os.c
+7
-6
drivers/scsi/qla2xxx/qla_os.c
···
1291
1291
"Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1292
1292
1293
1293
/* Wait for the command completion. */
1294
-
ratov_j = ha->r_a_tov/10 * 4 * 1000;
1295
-
ratov_j = msecs_to_jiffies(ratov_j);
1294
+
ratov_j = ha->r_a_tov / 10 * 4;
1295
+
ratov_j = secs_to_jiffies(ratov_j);
1296
1296
switch (rval) {
1297
1297
case QLA_SUCCESS:
1298
1298
if (!wait_for_completion_timeout(&comp, ratov_j)) {
···
1806
1806
rval = ha->isp_ops->abort_command(sp);
1807
1807
/* Wait for command completion. */
1808
1808
ret_cmd = false;
1809
-
ratov_j = ha->r_a_tov/10 * 4 * 1000;
1810
-
ratov_j = msecs_to_jiffies(ratov_j);
1809
+
ratov_j = ha->r_a_tov / 10 * 4;
1810
+
ratov_j = secs_to_jiffies(ratov_j);
1811
1811
switch (rval) {
1812
1812
case QLA_SUCCESS:
1813
1813
if (wait_for_completion_timeout(&comp, ratov_j)) {
···
6459
6459
void
6460
6460
qla24xx_free_purex_item(struct purex_item *item)
6461
6461
{
6462
-
if (item == &item->vha->default_item)
6462
+
if (item == &item->vha->default_item) {
6463
6463
memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6464
-
else
6464
+
memset(&item->vha->__default_item_iocb, 0, QLA_DEFAULT_PAYLOAD_SIZE);
6465
+
} else
6465
6466
kfree(item);
6466
6467
}
6467
6468
+5
-12
drivers/scsi/scsi_debug.c
+5
-12
drivers/scsi/scsi_debug.c
···
1155
1155
struct sdebug_err_inject *inject;
1156
1156
struct scsi_device *sdev = (struct scsi_device *)file->f_inode->i_private;
1157
1157
1158
-
buf = kzalloc(count + 1, GFP_KERNEL);
1159
-
if (!buf)
1160
-
return -ENOMEM;
1161
-
1162
-
if (copy_from_user(buf, ubuf, count)) {
1163
-
kfree(buf);
1164
-
return -EFAULT;
1165
-
}
1158
+
buf = memdup_user_nul(ubuf, count);
1159
+
if (IS_ERR(buf))
1160
+
return PTR_ERR(buf);
1166
1161
1167
1162
if (buf[0] == '-')
1168
1163
return sdebug_err_remove(sdev, buf, count);
···
8800
8805
/* Logical Block Provisioning */
8801
8806
if (scsi_debug_lbp()) {
8802
8807
map_size = lba_to_map_index(sdebug_store_sectors - 1) + 1;
8803
-
sip->map_storep = vmalloc(array_size(sizeof(long),
8804
-
BITS_TO_LONGS(map_size)));
8808
+
sip->map_storep = vcalloc(BITS_TO_LONGS(map_size),
8809
+
sizeof(long));
8805
8810
8806
8811
pr_info("%lu provisioning blocks\n", map_size);
8807
8812
···
8809
8814
pr_err("LBP map oom\n");
8810
8815
goto err;
8811
8816
}
8812
-
8813
-
bitmap_zero(sip->map_storep, map_size);
8814
8817
8815
8818
/* Map first 1KB for partition table */
8816
8819
if (sdebug_num_parts)
+30
-28
drivers/scsi/sd.c
+30
-28
drivers/scsi/sd.c
···
106
106
unsigned int mode);
107
107
static void sd_config_write_same(struct scsi_disk *sdkp,
108
108
struct queue_limits *lim);
109
-
static int sd_revalidate_disk(struct gendisk *);
109
+
static void sd_revalidate_disk(struct gendisk *);
110
110
static void sd_unlock_native_capacity(struct gendisk *disk);
111
111
static void sd_shutdown(struct device *);
112
112
static void scsi_disk_release(struct device *cdev);
···
3691
3691
* performs disk spin up, read_capacity, etc.
3692
3692
* @disk: struct gendisk we care about
3693
3693
**/
3694
-
static int sd_revalidate_disk(struct gendisk *disk)
3694
+
static void sd_revalidate_disk(struct gendisk *disk)
3695
3695
{
3696
3696
struct scsi_disk *sdkp = scsi_disk(disk);
3697
3697
struct scsi_device *sdp = sdkp->device;
3698
3698
sector_t old_capacity = sdkp->capacity;
3699
-
struct queue_limits lim;
3700
-
unsigned char *buffer;
3699
+
struct queue_limits *lim = NULL;
3700
+
unsigned char *buffer = NULL;
3701
3701
unsigned int dev_max;
3702
3702
int err;
3703
3703
···
3709
3709
* of the other niceties.
3710
3710
*/
3711
3711
if (!scsi_device_online(sdp))
3712
-
goto out;
3712
+
return;
3713
+
3714
+
lim = kmalloc(sizeof(*lim), GFP_KERNEL);
3715
+
if (!lim)
3716
+
return;
3713
3717
3714
3718
buffer = kmalloc(SD_BUF_SIZE, GFP_KERNEL);
3715
-
if (!buffer) {
3716
-
sd_printk(KERN_WARNING, sdkp, "sd_revalidate_disk: Memory "
3717
-
"allocation failure.\n");
3719
+
if (!buffer)
3718
3720
goto out;
3719
-
}
3720
3721
3721
3722
sd_spinup_disk(sdkp);
3722
3723
3723
-
lim = queue_limits_start_update(sdkp->disk->queue);
3724
+
*lim = queue_limits_start_update(sdkp->disk->queue);
3724
3725
3725
3726
/*
3726
3727
* Without media there is no reason to ask; moreover, some devices
3727
3728
* react badly if we do.
3728
3729
*/
3729
3730
if (sdkp->media_present) {
3730
-
sd_read_capacity(sdkp, &lim, buffer);
3731
+
sd_read_capacity(sdkp, lim, buffer);
3731
3732
/*
3732
3733
* Some USB/UAS devices return generic values for mode pages
3733
3734
* until the media has been accessed. Trigger a READ operation
···
3742
3741
* cause this to be updated correctly and any device which
3743
3742
* doesn't support it should be treated as rotational.
3744
3743
*/
3745
-
lim.features |= (BLK_FEAT_ROTATIONAL | BLK_FEAT_ADD_RANDOM);
3744
+
lim->features |= (BLK_FEAT_ROTATIONAL | BLK_FEAT_ADD_RANDOM);
3746
3745
3747
3746
if (scsi_device_supports_vpd(sdp)) {
3748
3747
sd_read_block_provisioning(sdkp);
3749
-
sd_read_block_limits(sdkp, &lim);
3748
+
sd_read_block_limits(sdkp, lim);
3750
3749
sd_read_block_limits_ext(sdkp);
3751
-
sd_read_block_characteristics(sdkp, &lim);
3752
-
sd_zbc_read_zones(sdkp, &lim, buffer);
3750
+
sd_read_block_characteristics(sdkp, lim);
3751
+
sd_zbc_read_zones(sdkp, lim, buffer);
3753
3752
}
3754
3753
3755
-
sd_config_discard(sdkp, &lim, sd_discard_mode(sdkp));
3754
+
sd_config_discard(sdkp, lim, sd_discard_mode(sdkp));
3756
3755
3757
3756
sd_print_capacity(sdkp, old_capacity);
3758
3757
···
3762
3761
sd_read_app_tag_own(sdkp, buffer);
3763
3762
sd_read_write_same(sdkp, buffer);
3764
3763
sd_read_security(sdkp, buffer);
3765
-
sd_config_protection(sdkp, &lim);
3764
+
sd_config_protection(sdkp, lim);
3766
3765
}
3767
3766
3768
3767
/*
3769
3768
* We now have all cache related info, determine how we deal
3770
3769
* with flush requests.
3771
3770
*/
3772
-
sd_set_flush_flag(sdkp, &lim);
3771
+
sd_set_flush_flag(sdkp, lim);
3773
3772
3774
3773
/* Initial block count limit based on CDB TRANSFER LENGTH field size. */
3775
3774
dev_max = sdp->use_16_for_rw ? SD_MAX_XFER_BLOCKS : SD_DEF_XFER_BLOCKS;
3776
3775
3777
3776
/* Some devices report a maximum block count for READ/WRITE requests. */
3778
3777
dev_max = min_not_zero(dev_max, sdkp->max_xfer_blocks);
3779
-
lim.max_dev_sectors = logical_to_sectors(sdp, dev_max);
3778
+
lim->max_dev_sectors = logical_to_sectors(sdp, dev_max);
3780
3779
3781
3780
if (sd_validate_min_xfer_size(sdkp))
3782
-
lim.io_min = logical_to_bytes(sdp, sdkp->min_xfer_blocks);
3781
+
lim->io_min = logical_to_bytes(sdp, sdkp->min_xfer_blocks);
3783
3782
else
3784
-
lim.io_min = 0;
3783
+
lim->io_min = 0;
3785
3784
3786
3785
/*
3787
3786
* Limit default to SCSI host optimal sector limit if set. There may be
3788
3787
* an impact on performance for when the size of a request exceeds this
3789
3788
* host limit.
3790
3789
*/
3791
-
lim.io_opt = sdp->host->opt_sectors << SECTOR_SHIFT;
3790
+
lim->io_opt = sdp->host->opt_sectors << SECTOR_SHIFT;
3792
3791
if (sd_validate_opt_xfer_size(sdkp, dev_max)) {
3793
-
lim.io_opt = min_not_zero(lim.io_opt,
3792
+
lim->io_opt = min_not_zero(lim->io_opt,
3794
3793
logical_to_bytes(sdp, sdkp->opt_xfer_blocks));
3795
3794
}
3796
3795
3797
3796
sdkp->first_scan = 0;
3798
3797
3799
3798
set_capacity_and_notify(disk, logical_to_sectors(sdp, sdkp->capacity));
3800
-
sd_config_write_same(sdkp, &lim);
3801
-
kfree(buffer);
3799
+
sd_config_write_same(sdkp, lim);
3802
3800
3803
-
err = queue_limits_commit_update_frozen(sdkp->disk->queue, &lim);
3801
+
err = queue_limits_commit_update_frozen(sdkp->disk->queue, lim);
3804
3802
if (err)
3805
-
return err;
3803
+
goto out;
3806
3804
3807
3805
/*
3808
3806
* Query concurrent positioning ranges after
···
3820
3820
set_capacity_and_notify(disk, 0);
3821
3821
3822
3822
out:
3823
-
return 0;
3823
+
kfree(buffer);
3824
+
kfree(lim);
3825
+
3824
3826
}
3825
3827
3826
3828
/**
+8
-9
drivers/scsi/smartpqi/smartpqi_init.c
+8
-9
drivers/scsi/smartpqi/smartpqi_init.c
···
20
20
#include <linux/reboot.h>
21
21
#include <linux/cciss_ioctl.h>
22
22
#include <linux/crash_dump.h>
23
+
#include <linux/string.h>
23
24
#include <scsi/scsi_host.h>
24
25
#include <scsi/scsi_cmnd.h>
25
26
#include <scsi/scsi_device.h>
···
6775
6774
}
6776
6775
6777
6776
if (iocommand.buf_size > 0) {
6778
-
kernel_buffer = kmalloc(iocommand.buf_size, GFP_KERNEL);
6779
-
if (!kernel_buffer)
6780
-
return -ENOMEM;
6781
6777
if (iocommand.Request.Type.Direction & XFER_WRITE) {
6782
-
if (copy_from_user(kernel_buffer, iocommand.buf,
6783
-
iocommand.buf_size)) {
6784
-
rc = -EFAULT;
6785
-
goto out;
6786
-
}
6778
+
kernel_buffer = memdup_user(iocommand.buf,
6779
+
iocommand.buf_size);
6780
+
if (IS_ERR(kernel_buffer))
6781
+
return PTR_ERR(kernel_buffer);
6787
6782
} else {
6788
-
memset(kernel_buffer, 0, iocommand.buf_size);
6783
+
kernel_buffer = kzalloc(iocommand.buf_size, GFP_KERNEL);
6784
+
if (!kernel_buffer)
6785
+
return -ENOMEM;
6789
6786
}
6790
6787
}
6791
6788
+2
-2
drivers/scsi/storvsc_drv.c
+2
-2
drivers/scsi/storvsc_drv.c
···
1941
1941
int num_present_cpus = num_present_cpus();
1942
1942
struct Scsi_Host *host;
1943
1943
struct hv_host_device *host_dev;
1944
-
bool dev_is_ide = ((dev_id->driver_data == IDE_GUID) ? true : false);
1945
-
bool is_fc = ((dev_id->driver_data == SFC_GUID) ? true : false);
1944
+
bool dev_is_ide = dev_id->driver_data == IDE_GUID;
1945
+
bool is_fc = dev_id->driver_data == SFC_GUID;
1946
1946
int target = 0;
1947
1947
struct storvsc_device *stor_device;
1948
1948
int max_sub_channels = 0;
+3
-3
drivers/target/iscsi/iscsi_target_configfs.c
+3
-3
drivers/target/iscsi/iscsi_target_configfs.c
···
665
665
}
666
666
acl_ci = &se_nacl->acl_group.cg_item;
667
667
if (!acl_ci) {
668
-
pr_err("Unable to locatel acl_ci\n");
668
+
pr_err("Unable to locate acl_ci\n");
669
669
return -EINVAL;
670
670
}
671
671
tpg_ci = &acl_ci->ci_parent->ci_group->cg_item;
···
684
684
685
685
ret = core_tpg_set_initiator_node_queue_depth(se_nacl, cmdsn_depth);
686
686
687
-
pr_debug("LIO_Target_ConfigFS: %s/%s Set CmdSN Window: %u for"
687
+
pr_debug("LIO_Target_ConfigFS: %s/%s Set CmdSN Window: %u for "
688
688
"InitiatorName: %s\n", config_item_name(wwn_ci),
689
689
config_item_name(tpg_ci), cmdsn_depth,
690
690
config_item_name(acl_ci));
···
1131
1131
1132
1132
/* End items for lio_target_tiqn_cit */
1133
1133
1134
-
/* Start LIO-Target TIQN struct contig_item lio_target_cit */
1134
+
/* Start LIO-Target TIQN struct config_item lio_target_cit */
1135
1135
1136
1136
static ssize_t lio_target_wwn_lio_version_show(struct config_item *item,
1137
1137
char *page)
+2
-1
drivers/target/iscsi/iscsi_target_tmr.c
+2
-1
drivers/target/iscsi/iscsi_target_tmr.c
···
112
112
struct iscsi_tmr_req *tmr_req = cmd->tmr_req;
113
113
struct se_tmr_req *se_tmr = cmd->se_cmd.se_tmr_req;
114
114
struct iscsi_tm *hdr = (struct iscsi_tm *) buf;
115
-
u64 ret, ref_lun;
115
+
u64 ref_lun;
116
+
int ret;
116
117
117
118
pr_debug("Got TASK_REASSIGN TMR ITT: 0x%08x,"
118
119
" RefTaskTag: 0x%08x, ExpDataSN: 0x%08x, CID: %hu\n",
+11
drivers/ufs/core/ufs-mcq.c
+11
drivers/ufs/core/ufs-mcq.c
···
29
29
#define MCQ_ENTRY_SIZE_IN_DWORD 8
30
30
#define CQE_UCD_BA GENMASK_ULL(63, 7)
31
31
32
+
#define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\
33
+
UFSHCD_ERROR_MASK |\
34
+
MCQ_CQ_EVENT_STATUS)
35
+
32
36
/* Max mcq register polling time in microseconds */
33
37
#define MCQ_POLL_US 500000
34
38
···
359
355
void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba)
360
356
{
361
357
struct ufs_hw_queue *hwq;
358
+
u32 intrs;
362
359
u16 qsize;
363
360
int i;
361
+
362
+
/* Enable required interrupts */
363
+
intrs = UFSHCD_ENABLE_MCQ_INTRS;
364
+
if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)
365
+
intrs &= ~MCQ_CQ_EVENT_STATUS;
366
+
ufshcd_enable_intr(hba, intrs);
364
367
365
368
for (i = 0; i < hba->nr_hw_queues; i++) {
366
369
hwq = &hba->uhq[i];
+2
drivers/ufs/core/ufs-sysfs.c
+2
drivers/ufs/core/ufs-sysfs.c
+1
drivers/ufs/core/ufs_trace.h
+1
drivers/ufs/core/ufs_trace.h
+24
drivers/ufs/core/ufs_trace_types.h
+24
drivers/ufs/core/ufs_trace_types.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
#ifndef _UFS_TRACE_TYPES_H_
3
+
#define _UFS_TRACE_TYPES_H_
4
+
5
+
enum ufs_trace_str_t {
6
+
UFS_CMD_SEND,
7
+
UFS_CMD_COMP,
8
+
UFS_DEV_COMP,
9
+
UFS_QUERY_SEND,
10
+
UFS_QUERY_COMP,
11
+
UFS_QUERY_ERR,
12
+
UFS_TM_SEND,
13
+
UFS_TM_COMP,
14
+
UFS_TM_ERR
15
+
};
16
+
17
+
enum ufs_trace_tsf_t {
18
+
UFS_TSF_CDB,
19
+
UFS_TSF_OSF,
20
+
UFS_TSF_TM_INPUT,
21
+
UFS_TSF_TM_OUTPUT
22
+
};
23
+
24
+
#endif /* _UFS_TRACE_TYPES_H_ */
+36
-24
drivers/ufs/core/ufshcd.c
+36
-24
drivers/ufs/core/ufshcd.c
···
45
45
UTP_TASK_REQ_COMPL |\
46
46
UFSHCD_ERROR_MASK)
47
47
48
-
#define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\
49
-
UFSHCD_ERROR_MASK |\
50
-
MCQ_CQ_EVENT_STATUS)
51
-
52
-
53
48
/* UIC command timeout, unit: ms */
54
49
enum {
55
50
UIC_CMD_TIMEOUT_DEFAULT = 500,
···
311
316
{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
312
317
.model = "THGLF2G9D8KBADG",
313
318
.quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
319
+
{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
320
+
.model = "THGJFJT1E45BATP",
321
+
.quirk = UFS_DEVICE_QUIRK_NO_TIMESTAMP_SUPPORT },
314
322
{}
315
323
};
316
324
···
367
369
* @hba: per adapter instance
368
370
* @intrs: interrupt bits
369
371
*/
370
-
static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
372
+
void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
371
373
{
372
374
u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
373
375
u32 new_val = old_val | intrs;
···
604
606
605
607
lrbp = &hba->lrb[tag];
606
608
607
-
dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
608
-
tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000));
609
-
dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
610
-
tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000));
609
+
if (hba->monitor.enabled) {
610
+
dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", tag,
611
+
div_u64(lrbp->issue_time_stamp_local_clock, 1000));
612
+
dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", tag,
613
+
div_u64(lrbp->compl_time_stamp_local_clock, 1000));
614
+
}
611
615
dev_err(hba->dev,
612
616
"UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
613
617
tag, (u64)lrbp->utrd_dma_addr);
···
1045
1045
*/
1046
1046
void ufshcd_pm_qos_init(struct ufs_hba *hba)
1047
1047
{
1048
+
guard(mutex)(&hba->pm_qos_mutex);
1048
1049
1049
1050
if (hba->pm_qos_enabled)
1050
1051
return;
···
1062
1061
*/
1063
1062
void ufshcd_pm_qos_exit(struct ufs_hba *hba)
1064
1063
{
1064
+
guard(mutex)(&hba->pm_qos_mutex);
1065
+
1065
1066
if (!hba->pm_qos_enabled)
1066
1067
return;
1067
1068
···
1078
1075
*/
1079
1076
static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on)
1080
1077
{
1078
+
guard(mutex)(&hba->pm_qos_mutex);
1079
+
1081
1080
if (!hba->pm_qos_enabled)
1082
1081
return;
1083
1082
···
2235
2230
static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2236
2231
{
2237
2232
bool queue_resume_work = false;
2238
-
ktime_t curr_t = ktime_get();
2233
+
ktime_t curr_t;
2239
2234
2240
2235
if (!ufshcd_is_clkscaling_supported(hba))
2241
2236
return;
2237
+
2238
+
curr_t = ktime_get();
2242
2239
2243
2240
guard(spinlock_irqsave)(&hba->clk_scaling.lock);
2244
2241
···
2361
2354
struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2362
2355
unsigned long flags;
2363
2356
2364
-
lrbp->issue_time_stamp = ktime_get();
2365
-
lrbp->issue_time_stamp_local_clock = local_clock();
2366
-
lrbp->compl_time_stamp = ktime_set(0, 0);
2367
-
lrbp->compl_time_stamp_local_clock = 0;
2357
+
if (hba->monitor.enabled) {
2358
+
lrbp->issue_time_stamp = ktime_get();
2359
+
lrbp->issue_time_stamp_local_clock = local_clock();
2360
+
lrbp->compl_time_stamp = ktime_set(0, 0);
2361
+
lrbp->compl_time_stamp_local_clock = 0;
2362
+
}
2368
2363
ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2369
2364
if (lrbp->cmd)
2370
2365
ufshcd_clk_scaling_start_busy(hba);
···
5631
5622
enum utp_ocs ocs;
5632
5623
5633
5624
lrbp = &hba->lrb[task_tag];
5634
-
lrbp->compl_time_stamp = ktime_get();
5635
-
lrbp->compl_time_stamp_local_clock = local_clock();
5625
+
if (hba->monitor.enabled) {
5626
+
lrbp->compl_time_stamp = ktime_get();
5627
+
lrbp->compl_time_stamp_local_clock = local_clock();
5628
+
}
5636
5629
cmd = lrbp->cmd;
5637
5630
if (cmd) {
5638
5631
if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
···
6468
6457
}
6469
6458
}
6470
6459
6471
-
static void ufshcd_force_error_recovery(struct ufs_hba *hba)
6460
+
void ufshcd_force_error_recovery(struct ufs_hba *hba)
6472
6461
{
6473
6462
spin_lock_irq(hba->host->host_lock);
6474
6463
hba->force_reset = true;
6475
6464
ufshcd_schedule_eh_work(hba);
6476
6465
spin_unlock_irq(hba->host->host_lock);
6477
6466
}
6467
+
EXPORT_SYMBOL_GPL(ufshcd_force_error_recovery);
6478
6468
6479
6469
static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6480
6470
{
···
8798
8786
struct ufs_dev_info *dev_info = &hba->dev_info;
8799
8787
struct utp_upiu_query_v4_0 *upiu_data;
8800
8788
8801
-
if (dev_info->wspecversion < 0x400)
8789
+
if (dev_info->wspecversion < 0x400 ||
8790
+
hba->dev_quirks & UFS_DEVICE_QUIRK_NO_TIMESTAMP_SUPPORT)
8802
8791
return;
8803
8792
8804
8793
ufshcd_dev_man_lock(hba);
···
8926
8913
static void ufshcd_config_mcq(struct ufs_hba *hba)
8927
8914
{
8928
8915
int ret;
8929
-
u32 intrs;
8930
8916
8931
8917
ret = ufshcd_mcq_vops_config_esi(hba);
8932
8918
hba->mcq_esi_enabled = !ret;
8933
8919
dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");
8934
8920
8935
-
intrs = UFSHCD_ENABLE_MCQ_INTRS;
8936
-
if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)
8937
-
intrs &= ~MCQ_CQ_EVENT_STATUS;
8938
-
ufshcd_enable_intr(hba, intrs);
8939
8921
ufshcd_mcq_make_queues_operational(hba);
8940
8922
ufshcd_mcq_config_mac(hba, hba->nutrs);
8941
8923
···
10764
10756
mutex_init(&hba->ee_ctrl_mutex);
10765
10757
10766
10758
mutex_init(&hba->wb_mutex);
10759
+
10760
+
/* Initialize mutex for PM QoS request synchronization */
10761
+
mutex_init(&hba->pm_qos_mutex);
10762
+
10767
10763
init_rwsem(&hba->clk_scaling_lock);
10768
10764
10769
10765
ufshcd_init_clk_gating(hba);
+9
-1
drivers/ufs/host/ufs-exynos.c
+9
-1
drivers/ufs/host/ufs-exynos.c
···
776
776
u32 mask, sync_len;
777
777
enum {
778
778
SYNC_LEN_G1 = 80 * 1000, /* 80us */
779
-
SYNC_LEN_G2 = 40 * 1000, /* 44us */
779
+
SYNC_LEN_G2 = 40 * 1000, /* 40us */
780
780
SYNC_LEN_G3 = 20 * 1000, /* 20us */
781
781
};
782
782
int i;
···
1896
1896
return 0;
1897
1897
}
1898
1898
1899
+
static int fsd_ufs_suspend(struct exynos_ufs *ufs)
1900
+
{
1901
+
exynos_ufs_gate_clks(ufs);
1902
+
hci_writel(ufs, 0, HCI_GPIO_OUT);
1903
+
return 0;
1904
+
}
1905
+
1899
1906
static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs)
1900
1907
{
1901
1908
return (16 * 1000 * 1000000UL / ufs->mclk_rate);
···
2169
2162
.pre_link = fsd_ufs_pre_link,
2170
2163
.post_link = fsd_ufs_post_link,
2171
2164
.pre_pwr_change = fsd_ufs_pre_pwr_change,
2165
+
.suspend = fsd_ufs_suspend,
2172
2166
};
2173
2167
2174
2168
static const struct exynos_ufs_drv_data gs101_ufs_drvs = {
+296
-58
drivers/ufs/host/ufs-mediatek.c
+296
-58
drivers/ufs/host/ufs-mediatek.c
···
29
29
#include "ufs-mediatek-sip.h"
30
30
31
31
static int ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq);
32
+
static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up);
32
33
33
34
#define CREATE_TRACE_POINTS
34
35
#include "ufs-mediatek-trace.h"
···
416
415
}
417
416
}
418
417
419
-
static void ufs_mtk_wait_idle_state(struct ufs_hba *hba,
418
+
static int ufs_mtk_wait_idle_state(struct ufs_hba *hba,
420
419
unsigned long retry_ms)
421
420
{
422
421
u64 timeout, time_checked;
···
452
451
break;
453
452
} while (time_checked < timeout);
454
453
455
-
if (wait_idle && sm != VS_HCE_BASE)
454
+
if (wait_idle && sm != VS_HCE_BASE) {
456
455
dev_info(hba->dev, "wait idle tmo: 0x%x\n", val);
456
+
return -ETIMEDOUT;
457
+
}
458
+
459
+
return 0;
457
460
}
458
461
459
462
static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
···
803
798
clk_pwr_off = true;
804
799
}
805
800
806
-
if (clk_pwr_off)
801
+
if (clk_pwr_off) {
807
802
ufs_mtk_pwr_ctrl(hba, false);
803
+
} else {
804
+
dev_warn(hba->dev, "Clock is not turned off, hba->ahit = 0x%x, AHIT = 0x%x\n",
805
+
hba->ahit,
806
+
ufshcd_readl(hba,
807
+
REG_AUTO_HIBERNATE_IDLE_TIMER));
808
+
}
808
809
ufs_mtk_mcq_disable_irq(hba);
809
810
} else if (on && status == POST_CHANGE) {
810
811
ufs_mtk_pwr_ctrl(hba, true);
···
1029
1018
struct arm_smccc_res res;
1030
1019
int err, ver;
1031
1020
1032
-
if (hba->vreg_info.vcc)
1021
+
if (info->vcc)
1033
1022
return 0;
1034
1023
1035
1024
if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) {
···
1083
1072
devm_kfree(hba->dev, (*vreg_off)->name);
1084
1073
devm_kfree(hba->dev, *vreg_off);
1085
1074
*vreg_off = NULL;
1075
+
}
1076
+
}
1077
+
1078
+
static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
1079
+
{
1080
+
unsigned long flags;
1081
+
u32 ah_ms = 10;
1082
+
u32 ah_scale, ah_timer;
1083
+
u32 scale_us[] = {1, 10, 100, 1000, 10000, 100000};
1084
+
1085
+
if (ufshcd_is_clkgating_allowed(hba)) {
1086
+
if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit) {
1087
+
ah_scale = FIELD_GET(UFSHCI_AHIBERN8_SCALE_MASK,
1088
+
hba->ahit);
1089
+
ah_timer = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
1090
+
hba->ahit);
1091
+
if (ah_scale <= 5)
1092
+
ah_ms = ah_timer * scale_us[ah_scale] / 1000;
1093
+
}
1094
+
1095
+
spin_lock_irqsave(hba->host->host_lock, flags);
1096
+
hba->clk_gating.delay_ms = max(ah_ms, 10U);
1097
+
spin_unlock_irqrestore(hba->host->host_lock, flags);
1098
+
}
1099
+
}
1100
+
1101
+
/* Convert microseconds to Auto-Hibernate Idle Timer register value */
1102
+
static u32 ufs_mtk_us_to_ahit(unsigned int timer)
1103
+
{
1104
+
unsigned int scale;
1105
+
1106
+
for (scale = 0; timer > UFSHCI_AHIBERN8_TIMER_MASK; ++scale)
1107
+
timer /= UFSHCI_AHIBERN8_SCALE_FACTOR;
1108
+
1109
+
return FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, timer) |
1110
+
FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, scale);
1111
+
}
1112
+
1113
+
static void ufs_mtk_fix_ahit(struct ufs_hba *hba)
1114
+
{
1115
+
unsigned int us;
1116
+
1117
+
if (ufshcd_is_auto_hibern8_supported(hba)) {
1118
+
switch (hba->dev_info.wmanufacturerid) {
1119
+
case UFS_VENDOR_SAMSUNG:
1120
+
/* configure auto-hibern8 timer to 3.5 ms */
1121
+
us = 3500;
1122
+
break;
1123
+
1124
+
case UFS_VENDOR_MICRON:
1125
+
/* configure auto-hibern8 timer to 2 ms */
1126
+
us = 2000;
1127
+
break;
1128
+
1129
+
default:
1130
+
/* configure auto-hibern8 timer to 1 ms */
1131
+
us = 1000;
1132
+
break;
1133
+
}
1134
+
1135
+
hba->ahit = ufs_mtk_us_to_ahit(us);
1136
+
}
1137
+
1138
+
ufs_mtk_setup_clk_gating(hba);
1139
+
}
1140
+
1141
+
static void ufs_mtk_fix_clock_scaling(struct ufs_hba *hba)
1142
+
{
1143
+
/* UFS version is below 4.0, clock scaling is not necessary */
1144
+
if ((hba->dev_info.wspecversion < 0x0400) &&
1145
+
ufs_mtk_is_clk_scale_ready(hba)) {
1146
+
hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
1147
+
1148
+
_ufs_mtk_clk_scale(hba, false);
1086
1149
}
1087
1150
}
1088
1151
···
1325
1240
dev_req_params->gear_rx < UFS_HS_G4)
1326
1241
return false;
1327
1242
1243
+
if (dev_req_params->pwr_tx == SLOW_MODE ||
1244
+
dev_req_params->pwr_rx == SLOW_MODE)
1245
+
return false;
1246
+
1328
1247
return true;
1329
1248
}
1330
1249
···
1343
1254
ufshcd_init_host_params(&host_params);
1344
1255
host_params.hs_rx_gear = UFS_HS_G5;
1345
1256
host_params.hs_tx_gear = UFS_HS_G5;
1257
+
1258
+
if (dev_max_params->pwr_rx == SLOW_MODE ||
1259
+
dev_max_params->pwr_tx == SLOW_MODE)
1260
+
host_params.desired_working_mode = UFS_PWM_MODE;
1346
1261
1347
1262
ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params);
1348
1263
if (ret) {
···
1371
1278
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE),
1372
1279
PA_NO_ADAPT);
1373
1280
1281
+
if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
1282
+
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
1283
+
DL_FC0ProtectionTimeOutVal_Default);
1284
+
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
1285
+
DL_TC0ReplayTimeOutVal_Default);
1286
+
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
1287
+
DL_AFC0ReqTimeOutVal_Default);
1288
+
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
1289
+
DL_FC1ProtectionTimeOutVal_Default);
1290
+
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
1291
+
DL_TC1ReplayTimeOutVal_Default);
1292
+
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
1293
+
DL_AFC1ReqTimeOutVal_Default);
1294
+
1295
+
ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
1296
+
DL_FC0ProtectionTimeOutVal_Default);
1297
+
ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
1298
+
DL_TC0ReplayTimeOutVal_Default);
1299
+
ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
1300
+
DL_AFC0ReqTimeOutVal_Default);
1301
+
}
1302
+
1374
1303
ret = ufshcd_uic_change_pwr_mode(hba,
1375
1304
FASTAUTO_MODE << 4 | FASTAUTO_MODE);
1376
1305
···
1402
1287
}
1403
1288
}
1404
1289
1405
-
if (host->hw_ver.major >= 3) {
1290
+
/* if already configured to the requested pwr_mode, skip adapt */
1291
+
if (dev_req_params->gear_rx == hba->pwr_info.gear_rx &&
1292
+
dev_req_params->gear_tx == hba->pwr_info.gear_tx &&
1293
+
dev_req_params->lane_rx == hba->pwr_info.lane_rx &&
1294
+
dev_req_params->lane_tx == hba->pwr_info.lane_tx &&
1295
+
dev_req_params->pwr_rx == hba->pwr_info.pwr_rx &&
1296
+
dev_req_params->pwr_tx == hba->pwr_info.pwr_tx &&
1297
+
dev_req_params->hs_rate == hba->pwr_info.hs_rate) {
1298
+
return ret;
1299
+
}
1300
+
1301
+
if (dev_req_params->pwr_rx == FAST_MODE ||
1302
+
dev_req_params->pwr_rx == FASTAUTO_MODE) {
1303
+
if (host->hw_ver.major >= 3) {
1304
+
ret = ufshcd_dme_configure_adapt(hba,
1305
+
dev_req_params->gear_tx,
1306
+
PA_INITIAL_ADAPT);
1307
+
} else {
1308
+
ret = ufshcd_dme_configure_adapt(hba,
1309
+
dev_req_params->gear_tx,
1310
+
PA_NO_ADAPT);
1311
+
}
1312
+
} else {
1406
1313
ret = ufshcd_dme_configure_adapt(hba,
1407
-
dev_req_params->gear_tx,
1408
-
PA_INITIAL_ADAPT);
1314
+
dev_req_params->gear_tx,
1315
+
PA_NO_ADAPT);
1316
+
}
1317
+
1318
+
return ret;
1319
+
}
1320
+
1321
+
static int ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
1322
+
{
1323
+
int ret;
1324
+
1325
+
/* disable auto-hibern8 */
1326
+
ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
1327
+
1328
+
/* wait host return to idle state when auto-hibern8 off */
1329
+
ret = ufs_mtk_wait_idle_state(hba, 5);
1330
+
if (ret)
1331
+
goto out;
1332
+
1333
+
ret = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
1334
+
1335
+
out:
1336
+
if (ret) {
1337
+
dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret);
1338
+
1339
+
ufshcd_force_error_recovery(hba);
1340
+
1341
+
/* trigger error handler and break suspend */
1342
+
ret = -EBUSY;
1409
1343
}
1410
1344
1411
1345
return ret;
···
1466
1302
struct ufs_pa_layer_attr *dev_req_params)
1467
1303
{
1468
1304
int ret = 0;
1305
+
static u32 reg;
1469
1306
1470
1307
switch (stage) {
1471
1308
case PRE_CHANGE:
1309
+
if (ufshcd_is_auto_hibern8_supported(hba)) {
1310
+
reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
1311
+
ufs_mtk_auto_hibern8_disable(hba);
1312
+
}
1472
1313
ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
1473
1314
dev_req_params);
1474
1315
break;
1475
1316
case POST_CHANGE:
1317
+
if (ufshcd_is_auto_hibern8_supported(hba))
1318
+
ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
1476
1319
break;
1477
1320
default:
1478
1321
ret = -EINVAL;
···
1513
1342
{
1514
1343
int ret;
1515
1344
u32 tmp;
1345
+
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1516
1346
1517
1347
ufs_mtk_get_controller_version(hba);
1518
1348
···
1539
1367
1540
1368
ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
1541
1369
1542
-
return ret;
1543
-
}
1370
+
/* Enable the 1144 functions setting */
1371
+
if (host->ip_ver == IP_VER_MT6989) {
1372
+
ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_DEBUGOMC), &tmp);
1373
+
if (ret)
1374
+
return ret;
1544
1375
1545
-
static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
1546
-
{
1547
-
u32 ah_ms;
1548
-
1549
-
if (ufshcd_is_clkgating_allowed(hba)) {
1550
-
if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
1551
-
ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
1552
-
hba->ahit);
1553
-
else
1554
-
ah_ms = 10;
1555
-
ufshcd_clkgate_delay_set(hba->dev, ah_ms + 5);
1376
+
tmp |= 0x10;
1377
+
ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), tmp);
1556
1378
}
1379
+
1380
+
return ret;
1557
1381
}
1558
1382
1559
1383
static void ufs_mtk_post_link(struct ufs_hba *hba)
1560
1384
{
1385
+
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1386
+
u32 tmp;
1387
+
1388
+
/* fix device PA_INIT no adapt */
1389
+
if (host->ip_ver >= IP_VER_MT6899) {
1390
+
ufshcd_dme_get(hba, UIC_ARG_MIB(VS_DEBUGOMC), &tmp);
1391
+
tmp |= 0x100;
1392
+
ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), tmp);
1393
+
}
1394
+
1561
1395
/* enable unipro clock gating feature */
1562
1396
ufs_mtk_cfg_unipro_cg(hba, true);
1563
-
1564
-
/* will be configured during probe hba */
1565
-
if (ufshcd_is_auto_hibern8_supported(hba))
1566
-
hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
1567
-
FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
1568
-
1569
-
ufs_mtk_setup_clk_gating(hba);
1570
1397
}
1571
1398
1572
1399
static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
···
1592
1421
{
1593
1422
struct arm_smccc_res res;
1594
1423
1595
-
/* disable hba before device reset */
1596
-
ufshcd_hba_stop(hba);
1597
-
1598
1424
ufs_mtk_device_reset_ctrl(0, res);
1425
+
1426
+
/* disable hba in middle of device reset */
1427
+
ufshcd_hba_stop(hba);
1599
1428
1600
1429
/*
1601
1430
* The reset signal is active low. UFS devices shall detect
···
1633
1462
return err;
1634
1463
1635
1464
/* Check link state to make sure exit h8 success */
1636
-
ufs_mtk_wait_idle_state(hba, 5);
1465
+
err = ufs_mtk_wait_idle_state(hba, 5);
1466
+
if (err) {
1467
+
dev_warn(hba->dev, "wait idle fail, err=%d\n", err);
1468
+
return err;
1469
+
}
1637
1470
err = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
1638
1471
if (err) {
1639
1472
dev_warn(hba->dev, "exit h8 state fail, err=%d\n", err);
···
1681
1506
static void ufs_mtk_vccqx_set_lpm(struct ufs_hba *hba, bool lpm)
1682
1507
{
1683
1508
struct ufs_vreg *vccqx = NULL;
1509
+
1510
+
if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
1511
+
return;
1684
1512
1685
1513
if (hba->vreg_info.vccq)
1686
1514
vccqx = hba->vreg_info.vccq;
···
1739
1561
}
1740
1562
}
1741
1563
1742
-
static void ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
1743
-
{
1744
-
int ret;
1745
-
1746
-
/* disable auto-hibern8 */
1747
-
ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
1748
-
1749
-
/* wait host return to idle state when auto-hibern8 off */
1750
-
ufs_mtk_wait_idle_state(hba, 5);
1751
-
1752
-
ret = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
1753
-
if (ret)
1754
-
dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret);
1755
-
}
1756
-
1757
1564
static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1758
1565
enum ufs_notify_change_status status)
1759
1566
{
···
1747
1584
1748
1585
if (status == PRE_CHANGE) {
1749
1586
if (ufshcd_is_auto_hibern8_supported(hba))
1750
-
ufs_mtk_auto_hibern8_disable(hba);
1587
+
return ufs_mtk_auto_hibern8_disable(hba);
1751
1588
return 0;
1752
1589
}
1753
1590
···
1805
1642
}
1806
1643
1807
1644
return 0;
1645
+
1808
1646
fail:
1809
-
return ufshcd_link_recovery(hba);
1647
+
/*
1648
+
* Check if the platform (parent) device has resumed, and ensure that
1649
+
* power, clock, and MTCMOS are all turned on.
1650
+
*/
1651
+
err = ufshcd_link_recovery(hba);
1652
+
if (err) {
1653
+
dev_err(hba->dev, "Device PM: req=%d, status:%d, err:%d\n",
1654
+
hba->dev->power.request,
1655
+
hba->dev->power.runtime_status,
1656
+
hba->dev->power.runtime_error);
1657
+
}
1658
+
1659
+
return 0; /* Cannot return a failure, otherwise, the I/O will hang. */
1810
1660
}
1811
1661
1812
1662
static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
···
1902
1726
1903
1727
ufs_mtk_vreg_fix_vcc(hba);
1904
1728
ufs_mtk_vreg_fix_vccqx(hba);
1729
+
ufs_mtk_fix_ahit(hba);
1730
+
ufs_mtk_fix_clock_scaling(hba);
1905
1731
}
1906
1732
1907
1733
static void ufs_mtk_event_notify(struct ufs_hba *hba,
···
2190
2012
return ret;
2191
2013
}
2192
2014
}
2015
+
host->is_mcq_intr_enabled = true;
2193
2016
2194
2017
return 0;
2195
2018
}
···
2274
2095
static int ufs_mtk_probe(struct platform_device *pdev)
2275
2096
{
2276
2097
int err;
2277
-
struct device *dev = &pdev->dev;
2278
-
struct device_node *reset_node;
2279
-
struct platform_device *reset_pdev;
2098
+
struct device *dev = &pdev->dev, *phy_dev = NULL;
2099
+
struct device_node *reset_node, *phy_node = NULL;
2100
+
struct platform_device *reset_pdev, *phy_pdev = NULL;
2280
2101
struct device_link *link;
2102
+
struct ufs_hba *hba;
2103
+
struct ufs_mtk_host *host;
2281
2104
2282
2105
reset_node = of_find_compatible_node(NULL, NULL,
2283
2106
"ti,syscon-reset");
···
2306
2125
}
2307
2126
2308
2127
skip_reset:
2128
+
/* find phy node */
2129
+
phy_node = of_parse_phandle(dev->of_node, "phys", 0);
2130
+
2131
+
if (phy_node) {
2132
+
phy_pdev = of_find_device_by_node(phy_node);
2133
+
if (!phy_pdev)
2134
+
goto skip_phy;
2135
+
phy_dev = &phy_pdev->dev;
2136
+
2137
+
pm_runtime_set_active(phy_dev);
2138
+
pm_runtime_enable(phy_dev);
2139
+
pm_runtime_get_sync(phy_dev);
2140
+
2141
+
put_device(phy_dev);
2142
+
dev_info(dev, "phys node found\n");
2143
+
} else {
2144
+
dev_notice(dev, "phys node not found\n");
2145
+
}
2146
+
2147
+
skip_phy:
2309
2148
/* perform generic probe */
2310
2149
err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
2150
+
if (err) {
2151
+
dev_err(dev, "probe failed %d\n", err);
2152
+
goto out;
2153
+
}
2154
+
2155
+
hba = platform_get_drvdata(pdev);
2156
+
if (!hba)
2157
+
goto out;
2158
+
2159
+
if (phy_node && phy_dev) {
2160
+
host = ufshcd_get_variant(hba);
2161
+
host->phy_dev = phy_dev;
2162
+
}
2163
+
2164
+
/*
2165
+
* Because the default power setting of VSx (the upper layer of
2166
+
* VCCQ/VCCQ2) is HWLP, we need to prevent VCCQ/VCCQ2 from
2167
+
* entering LPM.
2168
+
*/
2169
+
ufs_mtk_dev_vreg_set_lpm(hba, false);
2311
2170
2312
2171
out:
2313
-
if (err)
2314
-
dev_err(dev, "probe failed %d\n", err);
2315
-
2172
+
of_node_put(phy_node);
2316
2173
of_node_put(reset_node);
2317
2174
return err;
2318
2175
}
···
2375
2156
2376
2157
ret = ufshcd_system_suspend(dev);
2377
2158
if (ret)
2378
-
return ret;
2159
+
goto out;
2160
+
2161
+
if (pm_runtime_suspended(hba->dev))
2162
+
goto out;
2379
2163
2380
2164
ufs_mtk_dev_vreg_set_lpm(hba, true);
2381
2165
2382
2166
if (ufs_mtk_is_rtff_mtcmos(hba))
2383
2167
ufs_mtk_mtcmos_ctrl(false, res);
2384
2168
2385
-
return 0;
2169
+
out:
2170
+
return ret;
2386
2171
}
2387
2172
2388
2173
static int ufs_mtk_system_resume(struct device *dev)
2389
2174
{
2175
+
int ret = 0;
2390
2176
struct ufs_hba *hba = dev_get_drvdata(dev);
2391
2177
struct arm_smccc_res res;
2392
2178
2393
-
ufs_mtk_dev_vreg_set_lpm(hba, false);
2179
+
if (pm_runtime_suspended(hba->dev))
2180
+
goto out;
2394
2181
2395
2182
if (ufs_mtk_is_rtff_mtcmos(hba))
2396
2183
ufs_mtk_mtcmos_ctrl(true, res);
2397
2184
2398
-
return ufshcd_system_resume(dev);
2185
+
ufs_mtk_dev_vreg_set_lpm(hba, false);
2186
+
2187
+
out:
2188
+
ret = ufshcd_system_resume(dev);
2189
+
2190
+
return ret;
2399
2191
}
2400
2192
#endif
2401
2193
···
2414
2184
static int ufs_mtk_runtime_suspend(struct device *dev)
2415
2185
{
2416
2186
struct ufs_hba *hba = dev_get_drvdata(dev);
2187
+
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2417
2188
struct arm_smccc_res res;
2418
2189
int ret = 0;
2419
2190
···
2427
2196
if (ufs_mtk_is_rtff_mtcmos(hba))
2428
2197
ufs_mtk_mtcmos_ctrl(false, res);
2429
2198
2199
+
if (host->phy_dev)
2200
+
pm_runtime_put_sync(host->phy_dev);
2201
+
2430
2202
return 0;
2431
2203
}
2432
2204
2433
2205
static int ufs_mtk_runtime_resume(struct device *dev)
2434
2206
{
2435
2207
struct ufs_hba *hba = dev_get_drvdata(dev);
2208
+
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2436
2209
struct arm_smccc_res res;
2437
2210
2438
2211
if (ufs_mtk_is_rtff_mtcmos(hba))
2439
2212
ufs_mtk_mtcmos_ctrl(true, res);
2213
+
2214
+
if (host->phy_dev)
2215
+
pm_runtime_get_sync(host->phy_dev);
2440
2216
2441
2217
ufs_mtk_dev_vreg_set_lpm(hba, false);
2442
2218
+1
drivers/ufs/host/ufs-mediatek.h
+1
drivers/ufs/host/ufs-mediatek.h
+109
-117
drivers/ufs/host/ufs-qcom.c
+109
-117
drivers/ufs/host/ufs-qcom.c
···
38
38
#define DEEMPHASIS_3_5_dB 0x04
39
39
#define NO_DEEMPHASIS 0x0
40
40
41
+
#define UFS_ICE_SYNC_RST_SEL BIT(3)
42
+
#define UFS_ICE_SYNC_RST_SW BIT(4)
43
+
41
44
enum {
42
45
TSTBUS_UAWM,
43
46
TSTBUS_UARM,
···
497
494
* If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
498
495
* so that the subsequent power mode change shall stick to Rate-A.
499
496
*/
500
-
if (host->hw_ver.major == 0x5) {
501
-
if (host->phy_gear == UFS_HS_G5)
502
-
host_params->hs_rate = PA_HS_MODE_A;
503
-
else
504
-
host_params->hs_rate = PA_HS_MODE_B;
505
-
}
497
+
if (host->hw_ver.major == 0x5 && host->phy_gear == UFS_HS_G5)
498
+
host_params->hs_rate = PA_HS_MODE_A;
506
499
507
500
mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
508
501
···
750
751
{
751
752
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
752
753
int err;
754
+
u32 reg_val;
753
755
754
756
err = ufs_qcom_enable_lane_clks(host);
755
757
if (err)
756
758
return err;
759
+
760
+
if ((!ufs_qcom_is_link_active(hba)) &&
761
+
host->hw_ver.major == 5 &&
762
+
host->hw_ver.minor == 0 &&
763
+
host->hw_ver.step == 0) {
764
+
ufshcd_writel(hba, UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW, UFS_MEM_ICE_CFG);
765
+
reg_val = ufshcd_readl(hba, UFS_MEM_ICE_CFG);
766
+
reg_val &= ~(UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW);
767
+
/*
768
+
* HW documentation doesn't recommend any delay between the
769
+
* reset set and clear. But we are enforcing an arbitrary delay
770
+
* to give flops enough time to settle in.
771
+
*/
772
+
usleep_range(50, 100);
773
+
ufshcd_writel(hba, reg_val, UFS_MEM_ICE_CFG);
774
+
ufshcd_readl(hba, UFS_MEM_ICE_CFG);
775
+
}
757
776
758
777
return ufs_qcom_ice_resume(host);
759
778
}
···
1113
1096
}
1114
1097
}
1115
1098
1099
+
static void ufs_qcom_parse_gear_limits(struct ufs_hba *hba)
1100
+
{
1101
+
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1102
+
struct ufs_host_params *host_params = &host->host_params;
1103
+
u32 hs_gear_old = host_params->hs_tx_gear;
1104
+
1105
+
ufshcd_parse_gear_limits(hba, host_params);
1106
+
if (host_params->hs_tx_gear != hs_gear_old) {
1107
+
host->phy_gear = host_params->hs_tx_gear;
1108
+
}
1109
+
}
1110
+
1116
1111
static void ufs_qcom_set_host_params(struct ufs_hba *hba)
1117
1112
{
1118
1113
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
···
1191
1162
case PRE_CHANGE:
1192
1163
if (on) {
1193
1164
ufs_qcom_icc_update_bw(host);
1165
+
if (ufs_qcom_is_link_hibern8(hba)) {
1166
+
err = ufs_qcom_enable_lane_clks(host);
1167
+
if (err) {
1168
+
dev_err(hba->dev, "enable lane clks failed, ret=%d\n", err);
1169
+
return err;
1170
+
}
1171
+
}
1194
1172
} else {
1195
1173
if (!ufs_qcom_is_link_active(hba)) {
1196
1174
/* disable device ref_clk */
···
1223
1187
if (ufshcd_is_hs_mode(&hba->pwr_info))
1224
1188
ufs_qcom_dev_ref_clk_ctrl(host, true);
1225
1189
} else {
1190
+
if (ufs_qcom_is_link_hibern8(hba))
1191
+
ufs_qcom_disable_lane_clks(host);
1192
+
1226
1193
ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
1227
1194
ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
1228
1195
}
···
1376
1337
ufs_qcom_advertise_quirks(hba);
1377
1338
ufs_qcom_set_host_params(hba);
1378
1339
ufs_qcom_set_phy_gear(host);
1340
+
ufs_qcom_parse_gear_limits(hba);
1379
1341
1380
1342
err = ufs_qcom_ice_init(host);
1381
1343
if (err)
···
1782
1742
}
1783
1743
1784
1744
static int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1785
-
const char *prefix, enum ufshcd_res id)
1745
+
const char *prefix, void __iomem *base)
1786
1746
{
1787
1747
u32 *regs __free(kfree) = NULL;
1788
1748
size_t pos;
···
1795
1755
return -ENOMEM;
1796
1756
1797
1757
for (pos = 0; pos < len; pos += 4)
1798
-
regs[pos / 4] = readl(hba->res[id].base + offset + pos);
1758
+
regs[pos / 4] = readl(base + offset + pos);
1799
1759
1800
1760
print_hex_dump(KERN_ERR, prefix,
1801
1761
len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,
···
1806
1766
1807
1767
static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba)
1808
1768
{
1769
+
struct ufshcd_mcq_opr_info_t *opr = &hba->mcq_opr[0];
1770
+
void __iomem *mcq_vs_base = hba->mcq_base + UFS_MEM_VS_BASE;
1771
+
1809
1772
struct dump_info {
1773
+
void __iomem *base;
1810
1774
size_t offset;
1811
1775
size_t len;
1812
1776
const char *prefix;
1813
-
enum ufshcd_res id;
1814
1777
};
1815
1778
1816
1779
struct dump_info mcq_dumps[] = {
1817
-
{0x0, 256 * 4, "MCQ HCI-0 ", RES_MCQ},
1818
-
{0x400, 256 * 4, "MCQ HCI-1 ", RES_MCQ},
1819
-
{0x0, 5 * 4, "MCQ VS-0 ", RES_MCQ_VS},
1820
-
{0x0, 256 * 4, "MCQ SQD-0 ", RES_MCQ_SQD},
1821
-
{0x400, 256 * 4, "MCQ SQD-1 ", RES_MCQ_SQD},
1822
-
{0x800, 256 * 4, "MCQ SQD-2 ", RES_MCQ_SQD},
1823
-
{0xc00, 256 * 4, "MCQ SQD-3 ", RES_MCQ_SQD},
1824
-
{0x1000, 256 * 4, "MCQ SQD-4 ", RES_MCQ_SQD},
1825
-
{0x1400, 256 * 4, "MCQ SQD-5 ", RES_MCQ_SQD},
1826
-
{0x1800, 256 * 4, "MCQ SQD-6 ", RES_MCQ_SQD},
1827
-
{0x1c00, 256 * 4, "MCQ SQD-7 ", RES_MCQ_SQD},
1780
+
{hba->mcq_base, 0x0, 256 * 4, "MCQ HCI-0 "},
1781
+
{hba->mcq_base, 0x400, 256 * 4, "MCQ HCI-1 "},
1782
+
{mcq_vs_base, 0x0, 5 * 4, "MCQ VS-0 "},
1783
+
{opr->base, 0x0, 256 * 4, "MCQ SQD-0 "},
1784
+
{opr->base, 0x400, 256 * 4, "MCQ SQD-1 "},
1785
+
{opr->base, 0x800, 256 * 4, "MCQ SQD-2 "},
1786
+
{opr->base, 0xc00, 256 * 4, "MCQ SQD-3 "},
1787
+
{opr->base, 0x1000, 256 * 4, "MCQ SQD-4 "},
1788
+
{opr->base, 0x1400, 256 * 4, "MCQ SQD-5 "},
1789
+
{opr->base, 0x1800, 256 * 4, "MCQ SQD-6 "},
1790
+
{opr->base, 0x1c00, 256 * 4, "MCQ SQD-7 "},
1791
+
1828
1792
};
1829
1793
1830
1794
for (int i = 0; i < ARRAY_SIZE(mcq_dumps); i++) {
1831
1795
ufs_qcom_dump_regs(hba, mcq_dumps[i].offset, mcq_dumps[i].len,
1832
-
mcq_dumps[i].prefix, mcq_dumps[i].id);
1796
+
mcq_dumps[i].prefix, mcq_dumps[i].base);
1833
1797
cond_resched();
1834
1798
}
1835
1799
}
···
1954
1910
hba->clk_scaling.suspend_on_no_request = true;
1955
1911
}
1956
1912
1957
-
/* Resources */
1958
-
static const struct ufshcd_res_info ufs_res_info[RES_MAX] = {
1959
-
{.name = "ufs_mem",},
1960
-
{.name = "mcq",},
1961
-
/* Submission Queue DAO */
1962
-
{.name = "mcq_sqd",},
1963
-
/* Submission Queue Interrupt Status */
1964
-
{.name = "mcq_sqis",},
1965
-
/* Completion Queue DAO */
1966
-
{.name = "mcq_cqd",},
1967
-
/* Completion Queue Interrupt Status */
1968
-
{.name = "mcq_cqis",},
1969
-
/* MCQ vendor specific */
1970
-
{.name = "mcq_vs",},
1971
-
};
1972
-
1973
1913
static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1974
1914
{
1975
1915
struct platform_device *pdev = to_platform_device(hba->dev);
1976
-
struct ufshcd_res_info *res;
1977
-
struct resource *res_mem, *res_mcq;
1978
-
int i, ret;
1916
+
struct resource *res;
1979
1917
1980
-
memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info));
1981
-
1982
-
for (i = 0; i < RES_MAX; i++) {
1983
-
res = &hba->res[i];
1984
-
res->resource = platform_get_resource_byname(pdev,
1985
-
IORESOURCE_MEM,
1986
-
res->name);
1987
-
if (!res->resource) {
1988
-
dev_info(hba->dev, "Resource %s not provided\n", res->name);
1989
-
if (i == RES_UFS)
1990
-
return -ENODEV;
1991
-
continue;
1992
-
} else if (i == RES_UFS) {
1993
-
res_mem = res->resource;
1994
-
res->base = hba->mmio_base;
1995
-
continue;
1996
-
}
1997
-
1998
-
res->base = devm_ioremap_resource(hba->dev, res->resource);
1999
-
if (IS_ERR(res->base)) {
2000
-
dev_err(hba->dev, "Failed to map res %s, err=%d\n",
2001
-
res->name, (int)PTR_ERR(res->base));
2002
-
ret = PTR_ERR(res->base);
2003
-
res->base = NULL;
2004
-
return ret;
2005
-
}
1918
+
/* Map the MCQ configuration region */
1919
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mcq");
1920
+
if (!res) {
1921
+
dev_err(hba->dev, "MCQ resource not found in device tree\n");
1922
+
return -ENODEV;
2006
1923
}
2007
1924
2008
-
/* MCQ resource provided in DT */
2009
-
res = &hba->res[RES_MCQ];
2010
-
/* Bail if MCQ resource is provided */
2011
-
if (res->base)
2012
-
goto out;
2013
-
2014
-
/* Explicitly allocate MCQ resource from ufs_mem */
2015
-
res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
2016
-
if (!res_mcq)
2017
-
return -ENOMEM;
2018
-
2019
-
res_mcq->start = res_mem->start +
2020
-
MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
2021
-
res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
2022
-
res_mcq->flags = res_mem->flags;
2023
-
res_mcq->name = "mcq";
2024
-
2025
-
ret = insert_resource(&iomem_resource, res_mcq);
2026
-
if (ret) {
2027
-
dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
2028
-
ret);
2029
-
return ret;
1925
+
hba->mcq_base = devm_ioremap_resource(hba->dev, res);
1926
+
if (IS_ERR(hba->mcq_base)) {
1927
+
dev_err(hba->dev, "Failed to map MCQ region: %ld\n",
1928
+
PTR_ERR(hba->mcq_base));
1929
+
return PTR_ERR(hba->mcq_base);
2030
1930
}
2031
1931
2032
-
res->base = devm_ioremap_resource(hba->dev, res_mcq);
2033
-
if (IS_ERR(res->base)) {
2034
-
dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
2035
-
(int)PTR_ERR(res->base));
2036
-
ret = PTR_ERR(res->base);
2037
-
goto ioremap_err;
2038
-
}
2039
-
2040
-
out:
2041
-
hba->mcq_base = res->base;
2042
1932
return 0;
2043
-
ioremap_err:
2044
-
res->base = NULL;
2045
-
remove_resource(res_mcq);
2046
-
return ret;
2047
1933
}
2048
1934
2049
1935
static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
2050
1936
{
2051
-
struct ufshcd_res_info *mem_res, *sqdao_res;
2052
1937
struct ufshcd_mcq_opr_info_t *opr;
2053
1938
int i;
1939
+
u32 doorbell_offsets[OPR_MAX];
2054
1940
2055
-
mem_res = &hba->res[RES_UFS];
2056
-
sqdao_res = &hba->res[RES_MCQ_SQD];
1941
+
/*
1942
+
* Configure doorbell address offsets in MCQ configuration registers.
1943
+
* These values are offsets relative to mmio_base (UFS_HCI_BASE).
1944
+
*
1945
+
* Memory Layout:
1946
+
* - mmio_base = UFS_HCI_BASE
1947
+
* - mcq_base = MCQ_CONFIG_BASE = mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x200)
1948
+
* - Doorbell registers are at: mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) +
1949
+
* - UFS_QCOM_MCQ_SQD_OFFSET
1950
+
* - Which is also: mcq_base + UFS_QCOM_MCQ_SQD_OFFSET
1951
+
*/
2057
1952
2058
-
if (!mem_res->base || !sqdao_res->base)
2059
-
return -EINVAL;
1953
+
doorbell_offsets[OPR_SQD] = UFS_QCOM_SQD_ADDR_OFFSET;
1954
+
doorbell_offsets[OPR_SQIS] = UFS_QCOM_SQIS_ADDR_OFFSET;
1955
+
doorbell_offsets[OPR_CQD] = UFS_QCOM_CQD_ADDR_OFFSET;
1956
+
doorbell_offsets[OPR_CQIS] = UFS_QCOM_CQIS_ADDR_OFFSET;
2060
1957
1958
+
/*
1959
+
* Configure MCQ operation registers.
1960
+
*
1961
+
* The doorbell registers are physically located within the MCQ region:
1962
+
* - doorbell_physical_addr = mmio_base + doorbell_offset
1963
+
* - doorbell_physical_addr = mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET)
1964
+
*/
2061
1965
for (i = 0; i < OPR_MAX; i++) {
2062
1966
opr = &hba->mcq_opr[i];
2063
-
opr->offset = sqdao_res->resource->start -
2064
-
mem_res->resource->start + 0x40 * i;
2065
-
opr->stride = 0x100;
2066
-
opr->base = sqdao_res->base + 0x40 * i;
1967
+
opr->offset = doorbell_offsets[i]; /* Offset relative to mmio_base */
1968
+
opr->stride = UFS_QCOM_MCQ_STRIDE; /* 256 bytes between queues */
1969
+
1970
+
/*
1971
+
* Calculate the actual doorbell base address within MCQ region:
1972
+
* base = mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET)
1973
+
*/
1974
+
opr->base = hba->mcq_base + (opr->offset - UFS_QCOM_MCQ_CONFIG_OFFSET);
2067
1975
}
2068
1976
2069
1977
return 0;
···
2030
2034
static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
2031
2035
unsigned long *ocqs)
2032
2036
{
2033
-
struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS];
2034
-
2035
-
if (!mcq_vs_res->base)
2036
-
return -EINVAL;
2037
-
2038
-
*ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS);
2037
+
/* Read from MCQ vendor-specific register in MCQ region */
2038
+
*ocqs = readl(hba->mcq_base + UFS_MEM_CQIS_VS);
2039
2039
2040
2040
return 0;
2041
2041
}
+23
-5
drivers/ufs/host/ufs-qcom.h
+23
-5
drivers/ufs/host/ufs-qcom.h
···
33
33
#define DL_VS_CLK_CFG_MASK GENMASK(9, 0)
34
34
#define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9)
35
35
36
+
/* Qualcomm MCQ Configuration */
37
+
#define UFS_QCOM_MCQCAP_QCFGPTR 224 /* 0xE0 in hex */
38
+
#define UFS_QCOM_MCQ_CONFIG_OFFSET (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) /* 0x1C000 */
39
+
40
+
/* Doorbell offsets within MCQ region (relative to MCQ_CONFIG_BASE) */
41
+
#define UFS_QCOM_MCQ_SQD_OFFSET 0x5000
42
+
#define UFS_QCOM_MCQ_CQD_OFFSET 0x5080
43
+
#define UFS_QCOM_MCQ_SQIS_OFFSET 0x5040
44
+
#define UFS_QCOM_MCQ_CQIS_OFFSET 0x50C0
45
+
#define UFS_QCOM_MCQ_STRIDE 0x100
46
+
47
+
/* Calculated doorbell address offsets (relative to mmio_base) */
48
+
#define UFS_QCOM_SQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_SQD_OFFSET)
49
+
#define UFS_QCOM_CQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_CQD_OFFSET)
50
+
#define UFS_QCOM_SQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_SQIS_OFFSET)
51
+
#define UFS_QCOM_CQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_CQIS_OFFSET)
52
+
#define REG_UFS_MCQ_STRIDE UFS_QCOM_MCQ_STRIDE
53
+
54
+
/* MCQ Vendor specific address offsets (relative to MCQ_CONFIG_BASE) */
55
+
#define UFS_MEM_VS_BASE 0x4000
56
+
#define UFS_MEM_CQIS_VS 0x4008
57
+
36
58
/* QCOM UFS host controller vendor specific registers */
37
59
enum {
38
60
REG_UFS_SYS1CLK_1US = 0xC0,
···
82
60
UFS_AH8_CFG = 0xFC,
83
61
84
62
UFS_RD_REG_MCQ = 0xD00,
85
-
63
+
UFS_MEM_ICE_CFG = 0x2600,
86
64
REG_UFS_MEM_ICE_CONFIG = 0x260C,
87
65
REG_UFS_MEM_ICE_NUM_CORE = 0x2664,
88
66
···
115
93
REG_UFS_SW_AFTER_HW_H8_ENTER_CNT = 0x2708,
116
94
REG_UFS_HW_H8_EXIT_CNT = 0x270C,
117
95
REG_UFS_SW_H8_EXIT_CNT = 0x2710,
118
-
};
119
-
120
-
enum {
121
-
UFS_MEM_CQIS_VS = 0x8,
122
96
};
123
97
124
98
#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
+33
drivers/ufs/host/ufshcd-pltfrm.c
+33
drivers/ufs/host/ufshcd-pltfrm.c
···
430
430
}
431
431
EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_params);
432
432
433
+
/**
434
+
* ufshcd_parse_gear_limits - Parse DT-based gear and rate limits for UFS
435
+
* @hba: Pointer to UFS host bus adapter instance
436
+
* @host_params: Pointer to UFS host parameters structure to be updated
437
+
*
438
+
* This function reads optional device tree properties to apply
439
+
* platform-specific constraints.
440
+
*
441
+
* "limit-hs-gear": Specifies the max HS gear.
442
+
* "limit-gear-rate": Specifies the max High-Speed rate.
443
+
*/
444
+
void ufshcd_parse_gear_limits(struct ufs_hba *hba, struct ufs_host_params *host_params)
445
+
{
446
+
struct device_node *np = hba->dev->of_node;
447
+
u32 hs_gear;
448
+
const char *hs_rate;
449
+
450
+
if (!of_property_read_u32(np, "limit-hs-gear", &hs_gear)) {
451
+
host_params->hs_tx_gear = hs_gear;
452
+
host_params->hs_rx_gear = hs_gear;
453
+
}
454
+
455
+
if (!of_property_read_string(np, "limit-gear-rate", &hs_rate)) {
456
+
if (!strcmp(hs_rate, "rate-a"))
457
+
host_params->hs_rate = PA_HS_MODE_A;
458
+
else if (!strcmp(hs_rate, "rate-b"))
459
+
host_params->hs_rate = PA_HS_MODE_B;
460
+
else
461
+
dev_warn(hba->dev, "Invalid rate: %s\n", hs_rate);
462
+
}
463
+
}
464
+
EXPORT_SYMBOL_GPL(ufshcd_parse_gear_limits);
465
+
433
466
void ufshcd_init_host_params(struct ufs_host_params *host_params)
434
467
{
435
468
*host_params = (struct ufs_host_params){
+1
drivers/ufs/host/ufshcd-pltfrm.h
+1
drivers/ufs/host/ufshcd-pltfrm.h
···
29
29
const struct ufs_pa_layer_attr *dev_max,
30
30
struct ufs_pa_layer_attr *agreed_pwr);
31
31
void ufshcd_init_host_params(struct ufs_host_params *host_params);
32
+
void ufshcd_parse_gear_limits(struct ufs_hba *hba, struct ufs_host_params *host_params);
32
33
int ufshcd_pltfrm_init(struct platform_device *pdev,
33
34
const struct ufs_hba_variant_ops *vops);
34
35
void ufshcd_pltfrm_remove(struct platform_device *pdev);
+8
include/scsi/libsas.h
+8
include/scsi/libsas.h
···
203
203
type == SAS_FANOUT_EXPANDER_DEVICE;
204
204
}
205
205
206
+
static inline bool dev_parent_is_expander(struct domain_device *dev)
207
+
{
208
+
if (!dev->parent)
209
+
return false;
210
+
211
+
return dev_is_expander(dev->parent->dev_type);
212
+
}
213
+
206
214
static inline void INIT_SAS_WORK(struct sas_work *sw, void (*fn)(struct work_struct *))
207
215
{
208
216
INIT_WORK(&sw->work, fn);
+39
-19
include/uapi/scsi/fc/fc_els.h
+39
-19
include/uapi/scsi/fc/fc_els.h
···
11
11
#include <linux/types.h>
12
12
#include <asm/byteorder.h>
13
13
14
+
#ifdef __KERNEL__
15
+
#include <linux/stddef.h> /* for offsetof */
16
+
#else
17
+
#include <stddef.h> /* for offsetof */
18
+
#endif
19
+
14
20
/*
15
21
* Fibre Channel Switch - Enhanced Link Services definitions.
16
22
* From T11 FC-LS Rev 1.2 June 7, 2005.
···
1115
1109
1116
1110
/* Diagnostic Function Descriptor - FPIN Registration */
1117
1111
struct fc_df_desc_fpin_reg {
1118
-
__be32 desc_tag; /* FPIN Registration (0x00030001) */
1119
-
__be32 desc_len; /* Length of Descriptor (in bytes).
1120
-
* Size of descriptor excluding
1121
-
* desc_tag and desc_len fields.
1122
-
*/
1123
-
__be32 count; /* Number of desc_tags elements */
1112
+
/* New members MUST be added within the __struct_group() macro below. */
1113
+
__struct_group(fc_df_desc_fpin_reg_hdr, __hdr, /* no attrs */,
1114
+
__be32 desc_tag; /* FPIN Registration (0x00030001) */
1115
+
__be32 desc_len; /* Length of Descriptor (in bytes).
1116
+
* Size of descriptor excluding
1117
+
* desc_tag and desc_len fields.
1118
+
*/
1119
+
__be32 count; /* Number of desc_tags elements */
1120
+
);
1124
1121
__be32 desc_tags[]; /* Array of Descriptor Tags.
1125
1122
* Each tag indicates a function
1126
1123
* supported by the N_Port (request)
···
1133
1124
* See ELS_FN_DTAG_xxx for tag values.
1134
1125
*/
1135
1126
};
1127
+
_Static_assert(offsetof(struct fc_df_desc_fpin_reg, desc_tags) == sizeof(struct fc_df_desc_fpin_reg_hdr),
1128
+
"struct member likely outside of __struct_group()");
1136
1129
1137
1130
/*
1138
1131
* ELS_RDF - Register Diagnostic Functions
1139
1132
*/
1140
1133
struct fc_els_rdf {
1141
-
__u8 fpin_cmd; /* command (0x19) */
1142
-
__u8 fpin_zero[3]; /* specified as zero - part of cmd */
1143
-
__be32 desc_len; /* Length of Descriptor List (in bytes).
1144
-
* Size of ELS excluding fpin_cmd,
1145
-
* fpin_zero and desc_len fields.
1146
-
*/
1134
+
/* New members MUST be added within the __struct_group() macro below. */
1135
+
__struct_group(fc_els_rdf_hdr, __hdr, /* no attrs */,
1136
+
__u8 fpin_cmd; /* command (0x19) */
1137
+
__u8 fpin_zero[3]; /* specified as zero - part of cmd */
1138
+
__be32 desc_len; /* Length of Descriptor List (in bytes).
1139
+
* Size of ELS excluding fpin_cmd,
1140
+
* fpin_zero and desc_len fields.
1141
+
*/
1142
+
);
1147
1143
struct fc_tlv_desc desc[]; /* Descriptor list */
1148
1144
};
1145
+
_Static_assert(offsetof(struct fc_els_rdf, desc) == sizeof(struct fc_els_rdf_hdr),
1146
+
"struct member likely outside of __struct_group()");
1149
1147
1150
1148
/*
1151
1149
* ELS RDF LS_ACC Response.
1152
1150
*/
1153
1151
struct fc_els_rdf_resp {
1154
-
struct fc_els_ls_acc acc_hdr;
1155
-
__be32 desc_list_len; /* Length of response (in
1156
-
* bytes). Excludes acc_hdr
1157
-
* and desc_list_len fields.
1158
-
*/
1159
-
struct fc_els_lsri_desc lsri;
1152
+
/* New members MUST be added within the __struct_group() macro below. */
1153
+
__struct_group(fc_els_rdf_resp_hdr, __hdr, /* no attrs */,
1154
+
struct fc_els_ls_acc acc_hdr;
1155
+
__be32 desc_list_len; /* Length of response (in
1156
+
* bytes). Excludes acc_hdr
1157
+
* and desc_list_len fields.
1158
+
*/
1159
+
struct fc_els_lsri_desc lsri;
1160
+
);
1160
1161
struct fc_tlv_desc desc[]; /* Supported Descriptor list */
1161
1162
};
1162
-
1163
+
_Static_assert(offsetof(struct fc_els_rdf_resp, desc) == sizeof(struct fc_els_rdf_resp_hdr),
1164
+
"struct member likely outside of __struct_group()");
1163
1165
1164
1166
/*
1165
1167
* Diagnostic Capability Descriptors for EDC ELS
-17
include/ufs/ufs.h
-17
include/ufs/ufs.h
···
653
653
bool hid_sup;
654
654
};
655
655
656
-
/*
657
-
* This enum is used in string mapping in ufs_trace.h.
658
-
*/
659
-
enum ufs_trace_str_t {
660
-
UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
661
-
UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
662
-
UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
663
-
};
664
-
665
-
/*
666
-
* Transaction Specific Fields (TSF) type in the UPIU package, this enum is
667
-
* used in ufs_trace.h for UFS command trace.
668
-
*/
669
-
enum ufs_trace_tsf_t {
670
-
UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
671
-
};
672
-
673
656
#endif /* End of Header */
+3
include/ufs/ufs_quirks.h
+3
include/ufs/ufs_quirks.h
+7
-28
include/ufs/ufshcd.h
+7
-28
include/ufs/ufshcd.h
···
167
167
* @task_tag: Task tag of the command
168
168
* @lun: LUN of the command
169
169
* @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
170
+
* @req_abort_skip: skip request abort task flag
170
171
* @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
171
172
* @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
172
173
* @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
173
174
* @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
174
175
* @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
175
176
* @data_unit_num: the data unit number for the first block for inline crypto
176
-
* @req_abort_skip: skip request abort task flag
177
177
*/
178
178
struct ufshcd_lrb {
179
179
struct utp_transfer_req_desc *utr_descriptor_ptr;
···
193
193
int task_tag;
194
194
u8 lun; /* UPIU LUN id field is only 8-bit wide */
195
195
bool intr_cmd;
196
+
bool req_abort_skip;
196
197
ktime_t issue_time_stamp;
197
198
u64 issue_time_stamp_local_clock;
198
199
ktime_t compl_time_stamp;
···
202
201
int crypto_key_slot;
203
202
u64 data_unit_num;
204
203
#endif
205
-
206
-
bool req_abort_skip;
207
204
};
208
205
209
206
/**
···
794
795
};
795
796
796
797
/**
797
-
* struct ufshcd_res_info_t - MCQ related resource regions
798
-
*
799
-
* @name: resource name
800
-
* @resource: pointer to resource region
801
-
* @base: register base address
802
-
*/
803
-
struct ufshcd_res_info {
804
-
const char *name;
805
-
struct resource *resource;
806
-
void __iomem *base;
807
-
};
808
-
809
-
enum ufshcd_res {
810
-
RES_UFS,
811
-
RES_MCQ,
812
-
RES_MCQ_SQD,
813
-
RES_MCQ_SQIS,
814
-
RES_MCQ_CQD,
815
-
RES_MCQ_CQIS,
816
-
RES_MCQ_VS,
817
-
RES_MAX,
818
-
};
819
-
820
-
/**
821
798
* struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
822
799
*
823
800
* @offset: Doorbell Address Offset
···
938
963
* @ufs_rtc_update_work: A work for UFS RTC periodic update
939
964
* @pm_qos_req: PM QoS request handle
940
965
* @pm_qos_enabled: flag to check if pm qos is enabled
966
+
* @pm_qos_mutex: synchronizes PM QoS request and status updates
941
967
* @critical_health_count: count of critical health exceptions
942
968
* @dev_lvl_exception_count: count of device level exceptions since last reset
943
969
* @dev_lvl_exception_id: vendor specific information about the
···
1103
1127
bool lsdb_sup;
1104
1128
bool mcq_enabled;
1105
1129
bool mcq_esi_enabled;
1106
-
struct ufshcd_res_info res[RES_MAX];
1107
1130
void __iomem *mcq_base;
1108
1131
struct ufs_hw_queue *uhq;
1109
1132
struct ufs_hw_queue *dev_cmd_queue;
···
1111
1136
struct delayed_work ufs_rtc_update_work;
1112
1137
struct pm_qos_request pm_qos_req;
1113
1138
bool pm_qos_enabled;
1139
+
/* synchronizes PM QoS request and status updates */
1140
+
struct mutex pm_qos_mutex;
1114
1141
1115
1142
int critical_health_count;
1116
1143
atomic_t dev_lvl_exception_count;
···
1295
1318
1296
1319
void ufshcd_enable_irq(struct ufs_hba *hba);
1297
1320
void ufshcd_disable_irq(struct ufs_hba *hba);
1321
+
void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs);
1298
1322
int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1299
1323
int ufshcd_hba_enable(struct ufs_hba *hba);
1300
1324
int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
···
1486
1508
int ufshcd_write_ee_control(struct ufs_hba *hba);
1487
1509
int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1488
1510
const u16 *other_mask, u16 set, u16 clr);
1511
+
void ufshcd_force_error_recovery(struct ufs_hba *hba);
1489
1512
1490
1513
#endif /* End of Header */