Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar:
"On the kernel side there's a bunch of ring-buffer ordering fixes for a
reproducible bug, plus a PEBS constraints regression fix.
Plus tooling fixes"
* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
tools headers UAPI: Sync kvm.h headers with the kernel sources
perf record: Fix s390 missing module symbol and warning for non-root users
perf machine: Read also the end of the kernel
perf test vmlinux-kallsyms: Ignore aliases to _etext when searching on kallsyms
perf session: Add missing swap ops for namespace events
perf namespace: Protect reading thread's namespace
tools headers UAPI: Sync drm/drm.h with the kernel
tools headers UAPI: Sync drm/i915_drm.h with the kernel
tools headers UAPI: Sync linux/fs.h with the kernel
tools headers UAPI: Sync linux/sched.h with the kernel
tools arch x86: Sync asm/cpufeatures.h with the with the kernel
tools include UAPI: Update copy of files related to new fspick, fsmount, fsconfig, fsopen, move_mount and open_tree syscalls
perf arm64: Fix mksyscalltbl when system kernel headers are ahead of the kernel
perf data: Fix 'strncat may truncate' build failure with recent gcc
perf/ring-buffer: Use regular variables for nesting
perf/ring-buffer: Always use {READ,WRITE}_ONCE() for rb->user_page data
perf/ring_buffer: Add ordering to rb->nest increment
perf/ring_buffer: Fix exposing a temporarily decreased data_head
perf/x86/intel/ds: Fix EVENT vs. UEVENT PEBS constraints
+572
-149
+14
-14
arch/x86/events/intel/ds.c
+14
-14
arch/x86/events/intel/ds.c
···
684
684
INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
685
685
INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
686
686
/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
687
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
687
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
688
688
EVENT_CONSTRAINT_END
689
689
};
690
690
···
693
693
INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
694
694
INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
695
695
/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
696
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
696
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
697
697
/* Allow all events as PEBS with no flags */
698
698
INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
699
699
EVENT_CONSTRAINT_END
···
701
701
702
702
struct event_constraint intel_slm_pebs_event_constraints[] = {
703
703
/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
704
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
704
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
705
705
/* Allow all events as PEBS with no flags */
706
706
INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
707
707
EVENT_CONSTRAINT_END
···
726
726
INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
727
727
INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
728
728
/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
729
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
729
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
730
730
EVENT_CONSTRAINT_END
731
731
};
732
732
···
743
743
INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
744
744
INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
745
745
/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
746
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
746
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
747
747
EVENT_CONSTRAINT_END
748
748
};
749
749
···
752
752
INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
753
753
INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
754
754
/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
755
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
755
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
756
756
INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
757
757
INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
758
758
INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
···
767
767
INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
768
768
INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
769
769
/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
770
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
770
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
771
771
/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
772
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
772
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
773
773
INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
774
774
INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
775
775
INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
···
783
783
INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
784
784
INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
785
785
/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
786
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
786
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
787
787
/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
788
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
788
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
789
789
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
790
790
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
791
791
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
···
806
806
INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
807
807
INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
808
808
/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
809
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
809
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
810
810
/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
811
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
811
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
812
812
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
813
813
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
814
814
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
···
829
829
struct event_constraint intel_skl_pebs_event_constraints[] = {
830
830
INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
831
831
/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
832
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
832
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
833
833
/* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
834
-
INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
834
+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
835
835
INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
836
836
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
837
837
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
+2
-2
kernel/events/internal.h
+2
-2
kernel/events/internal.h
···
24
24
atomic_t poll; /* POLL_ for wakeups */
25
25
26
26
local_t head; /* write position */
27
-
local_t nest; /* nested writers */
27
+
unsigned int nest; /* nested writers */
28
28
local_t events; /* event limit */
29
29
local_t wakeup; /* wakeup stamp */
30
30
local_t lost; /* nr records lost */
···
41
41
42
42
/* AUX area */
43
43
long aux_head;
44
-
local_t aux_nest;
44
+
unsigned int aux_nest;
45
45
long aux_wakeup; /* last aux_watermark boundary crossed by aux_head */
46
46
unsigned long aux_pgoff;
47
47
int aux_nr_pages;
+50
-14
kernel/events/ring_buffer.c
+50
-14
kernel/events/ring_buffer.c
···
38
38
struct ring_buffer *rb = handle->rb;
39
39
40
40
preempt_disable();
41
-
local_inc(&rb->nest);
41
+
42
+
/*
43
+
* Avoid an explicit LOAD/STORE such that architectures with memops
44
+
* can use them.
45
+
*/
46
+
(*(volatile unsigned int *)&rb->nest)++;
42
47
handle->wakeup = local_read(&rb->wakeup);
43
48
}
44
49
···
51
46
{
52
47
struct ring_buffer *rb = handle->rb;
53
48
unsigned long head;
49
+
unsigned int nest;
50
+
51
+
/*
52
+
* If this isn't the outermost nesting, we don't have to update
53
+
* @rb->user_page->data_head.
54
+
*/
55
+
nest = READ_ONCE(rb->nest);
56
+
if (nest > 1) {
57
+
WRITE_ONCE(rb->nest, nest - 1);
58
+
goto out;
59
+
}
54
60
55
61
again:
62
+
/*
63
+
* In order to avoid publishing a head value that goes backwards,
64
+
* we must ensure the load of @rb->head happens after we've
65
+
* incremented @rb->nest.
66
+
*
67
+
* Otherwise we can observe a @rb->head value before one published
68
+
* by an IRQ/NMI happening between the load and the increment.
69
+
*/
70
+
barrier();
56
71
head = local_read(&rb->head);
57
72
58
73
/*
59
-
* IRQ/NMI can happen here, which means we can miss a head update.
74
+
* IRQ/NMI can happen here and advance @rb->head, causing our
75
+
* load above to be stale.
60
76
*/
61
-
62
-
if (!local_dec_and_test(&rb->nest))
63
-
goto out;
64
77
65
78
/*
66
79
* Since the mmap() consumer (userspace) can run on a different CPU:
···
107
84
* See perf_output_begin().
108
85
*/
109
86
smp_wmb(); /* B, matches C */
110
-
rb->user_page->data_head = head;
87
+
WRITE_ONCE(rb->user_page->data_head, head);
111
88
112
89
/*
113
-
* Now check if we missed an update -- rely on previous implied
114
-
* compiler barriers to force a re-read.
90
+
* We must publish the head before decrementing the nest count,
91
+
* otherwise an IRQ/NMI can publish a more recent head value and our
92
+
* write will (temporarily) publish a stale value.
115
93
*/
94
+
barrier();
95
+
WRITE_ONCE(rb->nest, 0);
96
+
97
+
/*
98
+
* Ensure we decrement @rb->nest before we validate the @rb->head.
99
+
* Otherwise we cannot be sure we caught the 'last' nested update.
100
+
*/
101
+
barrier();
116
102
if (unlikely(head != local_read(&rb->head))) {
117
-
local_inc(&rb->nest);
103
+
WRITE_ONCE(rb->nest, 1);
118
104
goto again;
119
105
}
120
106
···
362
330
struct perf_event *output_event = event;
363
331
unsigned long aux_head, aux_tail;
364
332
struct ring_buffer *rb;
333
+
unsigned int nest;
365
334
366
335
if (output_event->parent)
367
336
output_event = output_event->parent;
···
393
360
if (!refcount_inc_not_zero(&rb->aux_refcount))
394
361
goto err;
395
362
363
+
nest = READ_ONCE(rb->aux_nest);
396
364
/*
397
365
* Nesting is not supported for AUX area, make sure nested
398
366
* writers are caught early
399
367
*/
400
-
if (WARN_ON_ONCE(local_xchg(&rb->aux_nest, 1)))
368
+
if (WARN_ON_ONCE(nest))
401
369
goto err_put;
370
+
371
+
WRITE_ONCE(rb->aux_nest, nest + 1);
402
372
403
373
aux_head = rb->aux_head;
404
374
···
430
394
if (!handle->size) { /* A, matches D */
431
395
event->pending_disable = smp_processor_id();
432
396
perf_output_wakeup(handle);
433
-
local_set(&rb->aux_nest, 0);
397
+
WRITE_ONCE(rb->aux_nest, 0);
434
398
goto err_put;
435
399
}
436
400
}
···
507
471
perf_event_aux_event(handle->event, aux_head, size,
508
472
handle->aux_flags);
509
473
510
-
rb->user_page->aux_head = rb->aux_head;
474
+
WRITE_ONCE(rb->user_page->aux_head, rb->aux_head);
511
475
if (rb_need_aux_wakeup(rb))
512
476
wakeup = true;
513
477
···
519
483
520
484
handle->event = NULL;
521
485
522
-
local_set(&rb->aux_nest, 0);
486
+
WRITE_ONCE(rb->aux_nest, 0);
523
487
/* can't be last */
524
488
rb_free_aux(rb);
525
489
ring_buffer_put(rb);
···
539
503
540
504
rb->aux_head += size;
541
505
542
-
rb->user_page->aux_head = rb->aux_head;
506
+
WRITE_ONCE(rb->user_page->aux_head, rb->aux_head);
543
507
if (rb_need_aux_wakeup(rb)) {
544
508
perf_output_wakeup(handle);
545
509
handle->wakeup = rb->aux_wakeup + rb->aux_watermark;
+43
tools/arch/arm64/include/uapi/asm/kvm.h
+43
tools/arch/arm64/include/uapi/asm/kvm.h
···
35
35
#include <linux/psci.h>
36
36
#include <linux/types.h>
37
37
#include <asm/ptrace.h>
38
+
#include <asm/sve_context.h>
38
39
39
40
#define __KVM_HAVE_GUEST_DEBUG
40
41
#define __KVM_HAVE_IRQ_LINE
···
103
102
#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
104
103
#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
105
104
#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
105
+
#define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */
106
+
#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */
107
+
#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
106
108
107
109
struct kvm_vcpu_init {
108
110
__u32 target;
···
229
225
#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
230
226
KVM_REG_ARM_FW | ((r) & 0xffff))
231
227
#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
228
+
229
+
/* SVE registers */
230
+
#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT)
231
+
232
+
/* Z- and P-regs occupy blocks at the following offsets within this range: */
233
+
#define KVM_REG_ARM64_SVE_ZREG_BASE 0
234
+
#define KVM_REG_ARM64_SVE_PREG_BASE 0x400
235
+
#define KVM_REG_ARM64_SVE_FFR_BASE 0x600
236
+
237
+
#define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS
238
+
#define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS
239
+
240
+
#define KVM_ARM64_SVE_MAX_SLICES 32
241
+
242
+
#define KVM_REG_ARM64_SVE_ZREG(n, i) \
243
+
(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
244
+
KVM_REG_SIZE_U2048 | \
245
+
(((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \
246
+
((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
247
+
248
+
#define KVM_REG_ARM64_SVE_PREG(n, i) \
249
+
(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
250
+
KVM_REG_SIZE_U256 | \
251
+
(((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \
252
+
((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
253
+
254
+
#define KVM_REG_ARM64_SVE_FFR(i) \
255
+
(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
256
+
KVM_REG_SIZE_U256 | \
257
+
((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
258
+
259
+
#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
260
+
#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
261
+
262
+
/* Vector lengths pseudo-register: */
263
+
#define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
264
+
KVM_REG_SIZE_U512 | 0xffff)
265
+
#define KVM_ARM64_SVE_VLS_WORDS \
266
+
((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
232
267
233
268
/* Device Control API: ARM VGIC */
234
269
#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
+46
tools/arch/powerpc/include/uapi/asm/kvm.h
+46
tools/arch/powerpc/include/uapi/asm/kvm.h
···
482
482
#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */
483
483
#define KVM_REG_PPC_ICP_PPRI_MASK 0xff
484
484
485
+
#define KVM_REG_PPC_VP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x8d)
486
+
485
487
/* Device control API: PPC-specific devices */
486
488
#define KVM_DEV_MPIC_GRP_MISC 1
487
489
#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
···
678
676
#define KVM_XICS_PENDING (1ULL << 42)
679
677
#define KVM_XICS_PRESENTED (1ULL << 43)
680
678
#define KVM_XICS_QUEUED (1ULL << 44)
679
+
680
+
/* POWER9 XIVE Native Interrupt Controller */
681
+
#define KVM_DEV_XIVE_GRP_CTRL 1
682
+
#define KVM_DEV_XIVE_RESET 1
683
+
#define KVM_DEV_XIVE_EQ_SYNC 2
684
+
#define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */
685
+
#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
686
+
#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
687
+
#define KVM_DEV_XIVE_GRP_SOURCE_SYNC 5 /* 64-bit source identifier */
688
+
689
+
/* Layout of 64-bit XIVE source attribute values */
690
+
#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
691
+
#define KVM_XIVE_LEVEL_ASSERTED (1ULL << 1)
692
+
693
+
/* Layout of 64-bit XIVE source configuration attribute values */
694
+
#define KVM_XIVE_SOURCE_PRIORITY_SHIFT 0
695
+
#define KVM_XIVE_SOURCE_PRIORITY_MASK 0x7
696
+
#define KVM_XIVE_SOURCE_SERVER_SHIFT 3
697
+
#define KVM_XIVE_SOURCE_SERVER_MASK 0xfffffff8ULL
698
+
#define KVM_XIVE_SOURCE_MASKED_SHIFT 32
699
+
#define KVM_XIVE_SOURCE_MASKED_MASK 0x100000000ULL
700
+
#define KVM_XIVE_SOURCE_EISN_SHIFT 33
701
+
#define KVM_XIVE_SOURCE_EISN_MASK 0xfffffffe00000000ULL
702
+
703
+
/* Layout of 64-bit EQ identifier */
704
+
#define KVM_XIVE_EQ_PRIORITY_SHIFT 0
705
+
#define KVM_XIVE_EQ_PRIORITY_MASK 0x7
706
+
#define KVM_XIVE_EQ_SERVER_SHIFT 3
707
+
#define KVM_XIVE_EQ_SERVER_MASK 0xfffffff8ULL
708
+
709
+
/* Layout of EQ configuration values (64 bytes) */
710
+
struct kvm_ppc_xive_eq {
711
+
__u32 flags;
712
+
__u32 qshift;
713
+
__u64 qaddr;
714
+
__u32 qtoggle;
715
+
__u32 qindex;
716
+
__u8 pad[40];
717
+
};
718
+
719
+
#define KVM_XIVE_EQ_ALWAYS_NOTIFY 0x00000001
720
+
721
+
#define KVM_XIVE_TIMA_PAGE_OFFSET 0
722
+
#define KVM_XIVE_ESB_PAGE_OFFSET 4
681
723
682
724
#endif /* __LINUX_KVM_POWERPC_H */
+3
-1
tools/arch/s390/include/uapi/asm/kvm.h
+3
-1
tools/arch/s390/include/uapi/asm/kvm.h
···
153
153
__u8 ppno[16]; /* with MSA5 */
154
154
__u8 kma[16]; /* with MSA8 */
155
155
__u8 kdsa[16]; /* with MSA9 */
156
-
__u8 reserved[1792];
156
+
__u8 sortl[32]; /* with STFLE.150 */
157
+
__u8 dfltcc[32]; /* with STFLE.151 */
158
+
__u8 reserved[1728];
157
159
};
158
160
159
161
/* kvm attributes for crypto */
+3
tools/arch/x86/include/asm/cpufeatures.h
+3
tools/arch/x86/include/asm/cpufeatures.h
···
344
344
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
345
345
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
346
346
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
347
+
#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
347
348
#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
348
349
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
349
350
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
···
383
382
#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
384
383
#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */
385
384
#define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
385
+
#define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
386
+
#define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */
386
387
387
388
#endif /* _ASM_X86_CPUFEATURES_H */
+13
-1
tools/include/uapi/asm-generic/unistd.h
+13
-1
tools/include/uapi/asm-generic/unistd.h
···
832
832
__SYSCALL(__NR_io_uring_enter, sys_io_uring_enter)
833
833
#define __NR_io_uring_register 427
834
834
__SYSCALL(__NR_io_uring_register, sys_io_uring_register)
835
+
#define __NR_open_tree 428
836
+
__SYSCALL(__NR_open_tree, sys_open_tree)
837
+
#define __NR_move_mount 429
838
+
__SYSCALL(__NR_move_mount, sys_move_mount)
839
+
#define __NR_fsopen 430
840
+
__SYSCALL(__NR_fsopen, sys_fsopen)
841
+
#define __NR_fsconfig 431
842
+
__SYSCALL(__NR_fsconfig, sys_fsconfig)
843
+
#define __NR_fsmount 432
844
+
__SYSCALL(__NR_fsmount, sys_fsmount)
845
+
#define __NR_fspick 433
846
+
__SYSCALL(__NR_fspick, sys_fspick)
835
847
836
848
#undef __NR_syscalls
837
-
#define __NR_syscalls 428
849
+
#define __NR_syscalls 434
838
850
839
851
/*
840
852
* 32 bit systems traditionally used different
+37
tools/include/uapi/drm/drm.h
+37
tools/include/uapi/drm/drm.h
···
649
649
#define DRM_CAP_PAGE_FLIP_TARGET 0x11
650
650
#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
651
651
#define DRM_CAP_SYNCOBJ 0x13
652
+
#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
652
653
653
654
/** DRM_IOCTL_GET_CAP ioctl argument type */
654
655
struct drm_get_cap {
···
736
735
__u32 pad;
737
736
};
738
737
738
+
struct drm_syncobj_transfer {
739
+
__u32 src_handle;
740
+
__u32 dst_handle;
741
+
__u64 src_point;
742
+
__u64 dst_point;
743
+
__u32 flags;
744
+
__u32 pad;
745
+
};
746
+
739
747
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
740
748
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
749
+
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
741
750
struct drm_syncobj_wait {
742
751
__u64 handles;
743
752
/* absolute timeout */
···
758
747
__u32 pad;
759
748
};
760
749
750
+
struct drm_syncobj_timeline_wait {
751
+
__u64 handles;
752
+
/* wait on specific timeline point for every handles*/
753
+
__u64 points;
754
+
/* absolute timeout */
755
+
__s64 timeout_nsec;
756
+
__u32 count_handles;
757
+
__u32 flags;
758
+
__u32 first_signaled; /* only valid when not waiting all */
759
+
__u32 pad;
760
+
};
761
+
762
+
761
763
struct drm_syncobj_array {
762
764
__u64 handles;
763
765
__u32 count_handles;
764
766
__u32 pad;
765
767
};
768
+
769
+
struct drm_syncobj_timeline_array {
770
+
__u64 handles;
771
+
__u64 points;
772
+
__u32 count_handles;
773
+
__u32 pad;
774
+
};
775
+
766
776
767
777
/* Query current scanout sequence number */
768
778
struct drm_crtc_get_sequence {
···
940
908
#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)
941
909
#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
942
910
#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
911
+
912
+
#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
913
+
#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
914
+
#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
915
+
#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
943
916
944
917
/**
945
918
* Device specific ioctls should only be in their respective headers
+206
-98
tools/include/uapi/drm/i915_drm.h
+206
-98
tools/include/uapi/drm/i915_drm.h
···
63
63
#define I915_RESET_UEVENT "RESET"
64
64
65
65
/*
66
+
* i915_user_extension: Base class for defining a chain of extensions
67
+
*
68
+
* Many interfaces need to grow over time. In most cases we can simply
69
+
* extend the struct and have userspace pass in more data. Another option,
70
+
* as demonstrated by Vulkan's approach to providing extensions for forward
71
+
* and backward compatibility, is to use a list of optional structs to
72
+
* provide those extra details.
73
+
*
74
+
* The key advantage to using an extension chain is that it allows us to
75
+
* redefine the interface more easily than an ever growing struct of
76
+
* increasing complexity, and for large parts of that interface to be
77
+
* entirely optional. The downside is more pointer chasing; chasing across
78
+
* the __user boundary with pointers encapsulated inside u64.
79
+
*/
80
+
struct i915_user_extension {
81
+
__u64 next_extension;
82
+
__u32 name;
83
+
__u32 flags; /* All undefined bits must be zero. */
84
+
__u32 rsvd[4]; /* Reserved for future use; must be zero. */
85
+
};
86
+
87
+
/*
66
88
* MOCS indexes used for GPU surfaces, defining the cacheability of the
67
89
* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
68
90
*/
···
121
99
I915_ENGINE_CLASS_VIDEO = 2,
122
100
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
123
101
102
+
/* should be kept compact */
103
+
124
104
I915_ENGINE_CLASS_INVALID = -1
105
+
};
106
+
107
+
/*
108
+
* There may be more than one engine fulfilling any role within the system.
109
+
* Each engine of a class is given a unique instance number and therefore
110
+
* any engine can be specified by its class:instance tuplet. APIs that allow
111
+
* access to any engine in the system will use struct i915_engine_class_instance
112
+
* for this identification.
113
+
*/
114
+
struct i915_engine_class_instance {
115
+
__u16 engine_class; /* see enum drm_i915_gem_engine_class */
116
+
__u16 engine_instance;
125
117
};
126
118
127
119
/**
···
355
319
#define DRM_I915_PERF_ADD_CONFIG 0x37
356
320
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
357
321
#define DRM_I915_QUERY 0x39
322
+
/* Must be kept compact -- no holes */
358
323
359
324
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
360
325
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
···
404
367
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
405
368
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
406
369
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
370
+
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
407
371
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
408
372
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
409
373
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
···
514
476
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
515
477
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
516
478
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
479
+
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
517
480
518
481
#define I915_PARAM_HUC_STATUS 42
519
482
···
598
559
*/
599
560
#define I915_PARAM_MMAP_GTT_COHERENT 52
600
561
562
+
/* Must be kept compact -- no holes and well documented */
563
+
601
564
typedef struct drm_i915_getparam {
602
565
__s32 param;
603
566
/*
···
615
574
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
616
575
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
617
576
#define I915_SETPARAM_NUM_USED_FENCES 4
577
+
/* Must be kept compact -- no holes */
618
578
619
579
typedef struct drm_i915_setparam {
620
580
int param;
···
1014
972
* struct drm_i915_gem_exec_fence *fences.
1015
973
*/
1016
974
__u64 cliprects_ptr;
1017
-
#define I915_EXEC_RING_MASK (7<<0)
975
+
#define I915_EXEC_RING_MASK (0x3f)
1018
976
#define I915_EXEC_DEFAULT (0<<0)
1019
977
#define I915_EXEC_RENDER (1<<0)
1020
978
#define I915_EXEC_BSD (2<<0)
···
1162
1120
* as busy may become idle before the ioctl is completed.
1163
1121
*
1164
1122
* Furthermore, if the object is busy, which engine is busy is only
1165
-
* provided as a guide. There are race conditions which prevent the
1166
-
* report of which engines are busy from being always accurate.
1167
-
* However, the converse is not true. If the object is idle, the
1168
-
* result of the ioctl, that all engines are idle, is accurate.
1123
+
* provided as a guide and only indirectly by reporting its class
1124
+
* (there may be more than one engine in each class). There are race
1125
+
* conditions which prevent the report of which engines are busy from
1126
+
* being always accurate. However, the converse is not true. If the
1127
+
* object is idle, the result of the ioctl, that all engines are idle,
1128
+
* is accurate.
1169
1129
*
1170
1130
* The returned dword is split into two fields to indicate both
1171
-
* the engines on which the object is being read, and the
1172
-
* engine on which it is currently being written (if any).
1131
+
* the engine classess on which the object is being read, and the
1132
+
* engine class on which it is currently being written (if any).
1173
1133
*
1174
1134
* The low word (bits 0:15) indicate if the object is being written
1175
1135
* to by any engine (there can only be one, as the GEM implicit
1176
1136
* synchronisation rules force writes to be serialised). Only the
1177
-
* engine for the last write is reported.
1137
+
* engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1138
+
* 1 not 0 etc) for the last write is reported.
1178
1139
*
1179
-
* The high word (bits 16:31) are a bitmask of which engines are
1180
-
* currently reading from the object. Multiple engines may be
1140
+
* The high word (bits 16:31) are a bitmask of which engines classes
1141
+
* are currently reading from the object. Multiple engines may be
1181
1142
* reading from the object simultaneously.
1182
1143
*
1183
-
* The value of each engine is the same as specified in the
1184
-
* EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
1185
-
* Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
1186
-
* the I915_EXEC_RENDER engine for execution, and so it is never
1144
+
* The value of each engine class is the same as specified in the
1145
+
* I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1146
+
* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1187
1147
* reported as active itself. Some hardware may have parallel
1188
1148
* execution engines, e.g. multiple media engines, which are
1189
-
* mapped to the same identifier in the EXECBUFFER2 ioctl and
1190
-
* so are not separately reported for busyness.
1149
+
* mapped to the same class identifier and so are not separately
1150
+
* reported for busyness.
1191
1151
*
1192
1152
* Caveat emptor:
1193
1153
* Only the boolean result of this query is reliable; that is whether
···
1456
1412
};
1457
1413
1458
1414
struct drm_i915_gem_context_create {
1459
-
/* output: id of new context*/
1460
-
__u32 ctx_id;
1415
+
__u32 ctx_id; /* output: id of new context*/
1461
1416
__u32 pad;
1417
+
};
1418
+
1419
+
struct drm_i915_gem_context_create_ext {
1420
+
__u32 ctx_id; /* output: id of new context*/
1421
+
__u32 flags;
1422
+
#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1423
+
#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1424
+
(-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
1425
+
__u64 extensions;
1426
+
};
1427
+
1428
+
struct drm_i915_gem_context_param {
1429
+
__u32 ctx_id;
1430
+
__u32 size;
1431
+
__u64 param;
1432
+
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1433
+
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1434
+
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1435
+
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1436
+
#define I915_CONTEXT_PARAM_BANNABLE 0x5
1437
+
#define I915_CONTEXT_PARAM_PRIORITY 0x6
1438
+
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1439
+
#define I915_CONTEXT_DEFAULT_PRIORITY 0
1440
+
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1441
+
/*
1442
+
* When using the following param, value should be a pointer to
1443
+
* drm_i915_gem_context_param_sseu.
1444
+
*/
1445
+
#define I915_CONTEXT_PARAM_SSEU 0x7
1446
+
1447
+
/*
1448
+
* Not all clients may want to attempt automatic recover of a context after
1449
+
* a hang (for example, some clients may only submit very small incremental
1450
+
* batches relying on known logical state of previous batches which will never
1451
+
* recover correctly and each attempt will hang), and so would prefer that
1452
+
* the context is forever banned instead.
1453
+
*
1454
+
* If set to false (0), after a reset, subsequent (and in flight) rendering
1455
+
* from this context is discarded, and the client will need to create a new
1456
+
* context to use instead.
1457
+
*
1458
+
* If set to true (1), the kernel will automatically attempt to recover the
1459
+
* context by skipping the hanging batch and executing the next batch starting
1460
+
* from the default context state (discarding the incomplete logical context
1461
+
* state lost due to the reset).
1462
+
*
1463
+
* On creation, all new contexts are marked as recoverable.
1464
+
*/
1465
+
#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1466
+
/* Must be kept compact -- no holes and well documented */
1467
+
1468
+
__u64 value;
1469
+
};
1470
+
1471
+
/**
1472
+
* Context SSEU programming
1473
+
*
1474
+
* It may be necessary for either functional or performance reason to configure
1475
+
* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1476
+
* Sub-slice/EU).
1477
+
*
1478
+
* This is done by configuring SSEU configuration using the below
1479
+
* @struct drm_i915_gem_context_param_sseu for every supported engine which
1480
+
* userspace intends to use.
1481
+
*
1482
+
* Not all GPUs or engines support this functionality in which case an error
1483
+
* code -ENODEV will be returned.
1484
+
*
1485
+
* Also, flexibility of possible SSEU configuration permutations varies between
1486
+
* GPU generations and software imposed limitations. Requesting such a
1487
+
* combination will return an error code of -EINVAL.
1488
+
*
1489
+
* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1490
+
* favour of a single global setting.
1491
+
*/
1492
+
struct drm_i915_gem_context_param_sseu {
1493
+
/*
1494
+
* Engine class & instance to be configured or queried.
1495
+
*/
1496
+
struct i915_engine_class_instance engine;
1497
+
1498
+
/*
1499
+
* Unused for now. Must be cleared to zero.
1500
+
*/
1501
+
__u32 flags;
1502
+
1503
+
/*
1504
+
* Mask of slices to enable for the context. Valid values are a subset
1505
+
* of the bitmask value returned for I915_PARAM_SLICE_MASK.
1506
+
*/
1507
+
__u64 slice_mask;
1508
+
1509
+
/*
1510
+
* Mask of subslices to enable for the context. Valid values are a
1511
+
* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1512
+
*/
1513
+
__u64 subslice_mask;
1514
+
1515
+
/*
1516
+
* Minimum/Maximum number of EUs to enable per subslice for the
1517
+
* context. min_eus_per_subslice must be inferior or equal to
1518
+
* max_eus_per_subslice.
1519
+
*/
1520
+
__u16 min_eus_per_subslice;
1521
+
__u16 max_eus_per_subslice;
1522
+
1523
+
/*
1524
+
* Unused for now. Must be cleared to zero.
1525
+
*/
1526
+
__u32 rsvd;
1527
+
};
1528
+
1529
+
struct drm_i915_gem_context_create_ext_setparam {
1530
+
#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1531
+
struct i915_user_extension base;
1532
+
struct drm_i915_gem_context_param param;
1462
1533
};
1463
1534
1464
1535
struct drm_i915_gem_context_destroy {
1465
1536
__u32 ctx_id;
1466
1537
__u32 pad;
1538
+
};
1539
+
1540
+
/*
1541
+
* DRM_I915_GEM_VM_CREATE -
1542
+
*
1543
+
* Create a new virtual memory address space (ppGTT) for use within a context
1544
+
* on the same file. Extensions can be provided to configure exactly how the
1545
+
* address space is setup upon creation.
1546
+
*
1547
+
* The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
1548
+
* returned in the outparam @id.
1549
+
*
1550
+
* No flags are defined, with all bits reserved and must be zero.
1551
+
*
1552
+
* An extension chain maybe provided, starting with @extensions, and terminated
1553
+
* by the @next_extension being 0. Currently, no extensions are defined.
1554
+
*
1555
+
* DRM_I915_GEM_VM_DESTROY -
1556
+
*
1557
+
* Destroys a previously created VM id, specified in @id.
1558
+
*
1559
+
* No extensions or flags are allowed currently, and so must be zero.
1560
+
*/
1561
+
struct drm_i915_gem_vm_control {
1562
+
__u64 extensions;
1563
+
__u32 flags;
1564
+
__u32 vm_id;
1467
1565
};
1468
1566
1469
1567
struct drm_i915_reg_read {
···
1620
1434
1621
1435
__u64 val; /* Return value */
1622
1436
};
1437
+
1623
1438
/* Known registers:
1624
1439
*
1625
1440
* Render engine timestamp - 0x2358 + 64bit - gen7+
···
1658
1471
* Object handles are nonzero.
1659
1472
*/
1660
1473
__u32 handle;
1661
-
};
1662
-
1663
-
struct drm_i915_gem_context_param {
1664
-
__u32 ctx_id;
1665
-
__u32 size;
1666
-
__u64 param;
1667
-
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1668
-
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1669
-
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1670
-
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1671
-
#define I915_CONTEXT_PARAM_BANNABLE 0x5
1672
-
#define I915_CONTEXT_PARAM_PRIORITY 0x6
1673
-
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1674
-
#define I915_CONTEXT_DEFAULT_PRIORITY 0
1675
-
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1676
-
/*
1677
-
* When using the following param, value should be a pointer to
1678
-
* drm_i915_gem_context_param_sseu.
1679
-
*/
1680
-
#define I915_CONTEXT_PARAM_SSEU 0x7
1681
-
__u64 value;
1682
-
};
1683
-
1684
-
/**
1685
-
* Context SSEU programming
1686
-
*
1687
-
* It may be necessary for either functional or performance reason to configure
1688
-
* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1689
-
* Sub-slice/EU).
1690
-
*
1691
-
* This is done by configuring SSEU configuration using the below
1692
-
* @struct drm_i915_gem_context_param_sseu for every supported engine which
1693
-
* userspace intends to use.
1694
-
*
1695
-
* Not all GPUs or engines support this functionality in which case an error
1696
-
* code -ENODEV will be returned.
1697
-
*
1698
-
* Also, flexibility of possible SSEU configuration permutations varies between
1699
-
* GPU generations and software imposed limitations. Requesting such a
1700
-
* combination will return an error code of -EINVAL.
1701
-
*
1702
-
* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1703
-
* favour of a single global setting.
1704
-
*/
1705
-
struct drm_i915_gem_context_param_sseu {
1706
-
/*
1707
-
* Engine class & instance to be configured or queried.
1708
-
*/
1709
-
__u16 engine_class;
1710
-
__u16 engine_instance;
1711
-
1712
-
/*
1713
-
* Unused for now. Must be cleared to zero.
1714
-
*/
1715
-
__u32 flags;
1716
-
1717
-
/*
1718
-
* Mask of slices to enable for the context. Valid values are a subset
1719
-
* of the bitmask value returned for I915_PARAM_SLICE_MASK.
1720
-
*/
1721
-
__u64 slice_mask;
1722
-
1723
-
/*
1724
-
* Mask of subslices to enable for the context. Valid values are a
1725
-
* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1726
-
*/
1727
-
__u64 subslice_mask;
1728
-
1729
-
/*
1730
-
* Minimum/Maximum number of EUs to enable per subslice for the
1731
-
* context. min_eus_per_subslice must be inferior or equal to
1732
-
* max_eus_per_subslice.
1733
-
*/
1734
-
__u16 min_eus_per_subslice;
1735
-
__u16 max_eus_per_subslice;
1736
-
1737
-
/*
1738
-
* Unused for now. Must be cleared to zero.
1739
-
*/
1740
-
__u32 rsvd;
1741
1474
};
1742
1475
1743
1476
enum drm_i915_oa_format {
···
1821
1714
struct drm_i915_query_item {
1822
1715
__u64 query_id;
1823
1716
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
1717
+
/* Must be kept compact -- no holes and well documented */
1824
1718
1825
1719
/*
1826
1720
* When set to zero by userspace, this is filled with the size of the
+2
tools/include/uapi/linux/fcntl.h
+2
tools/include/uapi/linux/fcntl.h
···
91
91
#define AT_STATX_FORCE_SYNC 0x2000 /* - Force the attributes to be sync'd with the server */
92
92
#define AT_STATX_DONT_SYNC 0x4000 /* - Don't sync attributes with the server */
93
93
94
+
#define AT_RECURSIVE 0x8000 /* Apply to the entire subtree */
95
+
94
96
95
97
#endif /* _UAPI_LINUX_FCNTL_H */
+3
tools/include/uapi/linux/fs.h
+3
tools/include/uapi/linux/fs.h
···
320
320
#define SYNC_FILE_RANGE_WAIT_BEFORE 1
321
321
#define SYNC_FILE_RANGE_WRITE 2
322
322
#define SYNC_FILE_RANGE_WAIT_AFTER 4
323
+
#define SYNC_FILE_RANGE_WRITE_AND_WAIT (SYNC_FILE_RANGE_WRITE | \
324
+
SYNC_FILE_RANGE_WAIT_BEFORE | \
325
+
SYNC_FILE_RANGE_WAIT_AFTER)
323
326
324
327
/*
325
328
* Flags for preadv2/pwritev2:
+13
-2
tools/include/uapi/linux/kvm.h
+13
-2
tools/include/uapi/linux/kvm.h
···
986
986
#define KVM_CAP_HYPERV_ENLIGHTENED_VMCS 163
987
987
#define KVM_CAP_EXCEPTION_PAYLOAD 164
988
988
#define KVM_CAP_ARM_VM_IPA_SIZE 165
989
-
#define KVM_CAP_MANUAL_DIRTY_LOG_PROTECT 166
989
+
#define KVM_CAP_MANUAL_DIRTY_LOG_PROTECT 166 /* Obsolete */
990
990
#define KVM_CAP_HYPERV_CPUID 167
991
+
#define KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 168
992
+
#define KVM_CAP_PPC_IRQ_XIVE 169
993
+
#define KVM_CAP_ARM_SVE 170
994
+
#define KVM_CAP_ARM_PTRAUTH_ADDRESS 171
995
+
#define KVM_CAP_ARM_PTRAUTH_GENERIC 172
991
996
992
997
#ifdef KVM_CAP_IRQ_ROUTING
993
998
···
1150
1145
#define KVM_REG_SIZE_U256 0x0050000000000000ULL
1151
1146
#define KVM_REG_SIZE_U512 0x0060000000000000ULL
1152
1147
#define KVM_REG_SIZE_U1024 0x0070000000000000ULL
1148
+
#define KVM_REG_SIZE_U2048 0x0080000000000000ULL
1153
1149
1154
1150
struct kvm_reg_list {
1155
1151
__u64 n; /* number of regs */
···
1217
1211
#define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3
1218
1212
KVM_DEV_TYPE_ARM_VGIC_ITS,
1219
1213
#define KVM_DEV_TYPE_ARM_VGIC_ITS KVM_DEV_TYPE_ARM_VGIC_ITS
1214
+
KVM_DEV_TYPE_XIVE,
1215
+
#define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE
1220
1216
KVM_DEV_TYPE_MAX,
1221
1217
};
1222
1218
···
1442
1434
#define KVM_GET_NESTED_STATE _IOWR(KVMIO, 0xbe, struct kvm_nested_state)
1443
1435
#define KVM_SET_NESTED_STATE _IOW(KVMIO, 0xbf, struct kvm_nested_state)
1444
1436
1445
-
/* Available with KVM_CAP_MANUAL_DIRTY_LOG_PROTECT */
1437
+
/* Available with KVM_CAP_MANUAL_DIRTY_LOG_PROTECT_2 */
1446
1438
#define KVM_CLEAR_DIRTY_LOG _IOWR(KVMIO, 0xc0, struct kvm_clear_dirty_log)
1447
1439
1448
1440
/* Available with KVM_CAP_HYPERV_CPUID */
1449
1441
#define KVM_GET_SUPPORTED_HV_CPUID _IOWR(KVMIO, 0xc1, struct kvm_cpuid2)
1442
+
1443
+
/* Available with KVM_CAP_ARM_SVE */
1444
+
#define KVM_ARM_VCPU_FINALIZE _IOW(KVMIO, 0xc2, int)
1450
1445
1451
1446
/* Secure Encrypted Virtualization command */
1452
1447
enum sev_cmd_id {
+62
tools/include/uapi/linux/mount.h
+62
tools/include/uapi/linux/mount.h
···
55
55
#define MS_MGC_VAL 0xC0ED0000
56
56
#define MS_MGC_MSK 0xffff0000
57
57
58
+
/*
59
+
* open_tree() flags.
60
+
*/
61
+
#define OPEN_TREE_CLONE 1 /* Clone the target tree and attach the clone */
62
+
#define OPEN_TREE_CLOEXEC O_CLOEXEC /* Close the file on execve() */
63
+
64
+
/*
65
+
* move_mount() flags.
66
+
*/
67
+
#define MOVE_MOUNT_F_SYMLINKS 0x00000001 /* Follow symlinks on from path */
68
+
#define MOVE_MOUNT_F_AUTOMOUNTS 0x00000002 /* Follow automounts on from path */
69
+
#define MOVE_MOUNT_F_EMPTY_PATH 0x00000004 /* Empty from path permitted */
70
+
#define MOVE_MOUNT_T_SYMLINKS 0x00000010 /* Follow symlinks on to path */
71
+
#define MOVE_MOUNT_T_AUTOMOUNTS 0x00000020 /* Follow automounts on to path */
72
+
#define MOVE_MOUNT_T_EMPTY_PATH 0x00000040 /* Empty to path permitted */
73
+
#define MOVE_MOUNT__MASK 0x00000077
74
+
75
+
/*
76
+
* fsopen() flags.
77
+
*/
78
+
#define FSOPEN_CLOEXEC 0x00000001
79
+
80
+
/*
81
+
* fspick() flags.
82
+
*/
83
+
#define FSPICK_CLOEXEC 0x00000001
84
+
#define FSPICK_SYMLINK_NOFOLLOW 0x00000002
85
+
#define FSPICK_NO_AUTOMOUNT 0x00000004
86
+
#define FSPICK_EMPTY_PATH 0x00000008
87
+
88
+
/*
89
+
* The type of fsconfig() call made.
90
+
*/
91
+
enum fsconfig_command {
92
+
FSCONFIG_SET_FLAG = 0, /* Set parameter, supplying no value */
93
+
FSCONFIG_SET_STRING = 1, /* Set parameter, supplying a string value */
94
+
FSCONFIG_SET_BINARY = 2, /* Set parameter, supplying a binary blob value */
95
+
FSCONFIG_SET_PATH = 3, /* Set parameter, supplying an object by path */
96
+
FSCONFIG_SET_PATH_EMPTY = 4, /* Set parameter, supplying an object by (empty) path */
97
+
FSCONFIG_SET_FD = 5, /* Set parameter, supplying an object by fd */
98
+
FSCONFIG_CMD_CREATE = 6, /* Invoke superblock creation */
99
+
FSCONFIG_CMD_RECONFIGURE = 7, /* Invoke superblock reconfiguration */
100
+
};
101
+
102
+
/*
103
+
* fsmount() flags.
104
+
*/
105
+
#define FSMOUNT_CLOEXEC 0x00000001
106
+
107
+
/*
108
+
* Mount attributes.
109
+
*/
110
+
#define MOUNT_ATTR_RDONLY 0x00000001 /* Mount read-only */
111
+
#define MOUNT_ATTR_NOSUID 0x00000002 /* Ignore suid and sgid bits */
112
+
#define MOUNT_ATTR_NODEV 0x00000004 /* Disallow access to device special files */
113
+
#define MOUNT_ATTR_NOEXEC 0x00000008 /* Disallow program execution */
114
+
#define MOUNT_ATTR__ATIME 0x00000070 /* Setting on how atime should be updated */
115
+
#define MOUNT_ATTR_RELATIME 0x00000000 /* - Update atime relative to mtime/ctime. */
116
+
#define MOUNT_ATTR_NOATIME 0x00000010 /* - Do not update access times. */
117
+
#define MOUNT_ATTR_STRICTATIME 0x00000020 /* - Always perform atime updates */
118
+
#define MOUNT_ATTR_NODIRATIME 0x00000080 /* Do not update directory access times */
119
+
58
120
#endif /* _UAPI_LINUX_MOUNT_H */
+1
tools/include/uapi/linux/sched.h
+1
tools/include/uapi/linux/sched.h
···
10
10
#define CLONE_FS 0x00000200 /* set if fs info shared between processes */
11
11
#define CLONE_FILES 0x00000400 /* set if open files shared between processes */
12
12
#define CLONE_SIGHAND 0x00000800 /* set if signal handlers and blocked signals shared */
13
+
#define CLONE_PIDFD 0x00001000 /* set if a pidfd should be placed in parent */
13
14
#define CLONE_PTRACE 0x00002000 /* set if we want to let tracing continue on the child too */
14
15
#define CLONE_VFORK 0x00004000 /* set if the parent wants the child to wake it up on mm_release */
15
16
#define CLONE_PARENT 0x00008000 /* set if we want to have the same parent as the cloner */
+1
-1
tools/perf/arch/arm64/entry/syscalls/mksyscalltbl
+1
-1
tools/perf/arch/arm64/entry/syscalls/mksyscalltbl
+6
-3
tools/perf/arch/s390/util/machine.c
+6
-3
tools/perf/arch/s390/util/machine.c
···
5
5
#include "util.h"
6
6
#include "machine.h"
7
7
#include "api/fs/fs.h"
8
+
#include "debug.h"
8
9
9
10
int arch__fix_module_text_start(u64 *start, const char *name)
10
11
{
12
+
u64 m_start = *start;
11
13
char path[PATH_MAX];
12
14
13
15
snprintf(path, PATH_MAX, "module/%.*s/sections/.text",
14
16
(int)strlen(name) - 2, name + 1);
15
-
16
-
if (sysfs__read_ull(path, (unsigned long long *)start) < 0)
17
-
return -1;
17
+
if (sysfs__read_ull(path, (unsigned long long *)start) < 0) {
18
+
pr_debug2("Using module %s start:%#lx\n", path, m_start);
19
+
*start = m_start;
20
+
}
18
21
19
22
return 0;
20
23
}
+6
tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
+6
tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
···
349
349
425 common io_uring_setup __x64_sys_io_uring_setup
350
350
426 common io_uring_enter __x64_sys_io_uring_enter
351
351
427 common io_uring_register __x64_sys_io_uring_register
352
+
428 common open_tree __x64_sys_open_tree
353
+
429 common move_mount __x64_sys_move_mount
354
+
430 common fsopen __x64_sys_fsopen
355
+
431 common fsconfig __x64_sys_fsconfig
356
+
432 common fsmount __x64_sys_fsmount
357
+
433 common fspick __x64_sys_fspick
352
358
353
359
#
354
360
# x32-specific system call numbers start at 512 to avoid cache impact
+8
-1
tools/perf/tests/vmlinux-kallsyms.c
+8
-1
tools/perf/tests/vmlinux-kallsyms.c
···
161
161
162
162
continue;
163
163
}
164
-
} else
164
+
} else if (mem_start == kallsyms.vmlinux_map->end) {
165
+
/*
166
+
* Ignore aliases to _etext, i.e. to the end of the kernel text area,
167
+
* such as __indirect_thunk_end.
168
+
*/
169
+
continue;
170
+
} else {
165
171
pr_debug("ERR : %#" PRIx64 ": %s not on kallsyms\n",
166
172
mem_start, sym->name);
173
+
}
167
174
168
175
err = -1;
169
176
}
+1
-1
tools/perf/util/data-convert-bt.c
+1
-1
tools/perf/util/data-convert-bt.c
+18
-9
tools/perf/util/machine.c
+18
-9
tools/perf/util/machine.c
···
924
924
* symbol_name if it's not that important.
925
925
*/
926
926
static int machine__get_running_kernel_start(struct machine *machine,
927
-
const char **symbol_name, u64 *start)
927
+
const char **symbol_name,
928
+
u64 *start, u64 *end)
928
929
{
929
930
char filename[PATH_MAX];
930
931
int i, err = -1;
···
950
949
*symbol_name = name;
951
950
952
951
*start = addr;
952
+
953
+
err = kallsyms__get_function_start(filename, "_etext", &addr);
954
+
if (!err)
955
+
*end = addr;
956
+
953
957
return 0;
954
958
}
955
959
···
1447
1441
struct dso *kernel = machine__get_kernel(machine);
1448
1442
const char *name = NULL;
1449
1443
struct map *map;
1450
-
u64 addr = 0;
1444
+
u64 start = 0, end = ~0ULL;
1451
1445
int ret;
1452
1446
1453
1447
if (kernel == NULL)
···
1466
1460
"continuing anyway...\n", machine->pid);
1467
1461
}
1468
1462
1469
-
if (!machine__get_running_kernel_start(machine, &name, &addr)) {
1463
+
if (!machine__get_running_kernel_start(machine, &name, &start, &end)) {
1470
1464
if (name &&
1471
-
map__set_kallsyms_ref_reloc_sym(machine->vmlinux_map, name, addr)) {
1465
+
map__set_kallsyms_ref_reloc_sym(machine->vmlinux_map, name, start)) {
1472
1466
machine__destroy_kernel_maps(machine);
1473
1467
ret = -1;
1474
1468
goto out_put;
···
1478
1472
* we have a real start address now, so re-order the kmaps
1479
1473
* assume it's the last in the kmaps
1480
1474
*/
1481
-
machine__update_kernel_mmap(machine, addr, ~0ULL);
1475
+
machine__update_kernel_mmap(machine, start, end);
1482
1476
}
1483
1477
1484
1478
if (machine__create_extra_kernel_maps(machine, kernel))
1485
1479
pr_debug("Problems creating extra kernel maps, continuing anyway...\n");
1486
1480
1487
-
/* update end address of the kernel map using adjacent module address */
1488
-
map = map__next(machine__kernel_map(machine));
1489
-
if (map)
1490
-
machine__set_kernel_mmap(machine, addr, map->start);
1481
+
if (end == ~0ULL) {
1482
+
/* update end address of the kernel map using adjacent module address */
1483
+
map = map__next(machine__kernel_map(machine));
1484
+
if (map)
1485
+
machine__set_kernel_mmap(machine, start, map->start);
1486
+
}
1487
+
1491
1488
out_put:
1492
1489
dso__put(kernel);
1493
1490
return ret;
+21
tools/perf/util/session.c
+21
tools/perf/util/session.c
···
647
647
swap_sample_id_all(event, &event->throttle + 1);
648
648
}
649
649
650
+
static void perf_event__namespaces_swap(union perf_event *event,
651
+
bool sample_id_all)
652
+
{
653
+
u64 i;
654
+
655
+
event->namespaces.pid = bswap_32(event->namespaces.pid);
656
+
event->namespaces.tid = bswap_32(event->namespaces.tid);
657
+
event->namespaces.nr_namespaces = bswap_64(event->namespaces.nr_namespaces);
658
+
659
+
for (i = 0; i < event->namespaces.nr_namespaces; i++) {
660
+
struct perf_ns_link_info *ns = &event->namespaces.link_info[i];
661
+
662
+
ns->dev = bswap_64(ns->dev);
663
+
ns->ino = bswap_64(ns->ino);
664
+
}
665
+
666
+
if (sample_id_all)
667
+
swap_sample_id_all(event, &event->namespaces.link_info[i]);
668
+
}
669
+
650
670
static u8 revbyte(u8 b)
651
671
{
652
672
int rev = (b >> 4) | ((b & 0xf) << 4);
···
907
887
[PERF_RECORD_LOST_SAMPLES] = perf_event__all64_swap,
908
888
[PERF_RECORD_SWITCH] = perf_event__switch_swap,
909
889
[PERF_RECORD_SWITCH_CPU_WIDE] = perf_event__switch_swap,
890
+
[PERF_RECORD_NAMESPACES] = perf_event__namespaces_swap,
910
891
[PERF_RECORD_HEADER_ATTR] = perf_event__hdr_attr_swap,
911
892
[PERF_RECORD_HEADER_EVENT_TYPE] = perf_event__event_type_swap,
912
893
[PERF_RECORD_HEADER_TRACING_DATA] = perf_event__tracing_data_swap,
+13
-2
tools/perf/util/thread.c
+13
-2
tools/perf/util/thread.c
···
133
133
}
134
134
}
135
135
136
-
struct namespaces *thread__namespaces(const struct thread *thread)
136
+
static struct namespaces *__thread__namespaces(const struct thread *thread)
137
137
{
138
138
if (list_empty(&thread->namespaces_list))
139
139
return NULL;
···
141
141
return list_first_entry(&thread->namespaces_list, struct namespaces, list);
142
142
}
143
143
144
+
struct namespaces *thread__namespaces(const struct thread *thread)
145
+
{
146
+
struct namespaces *ns;
147
+
148
+
down_read((struct rw_semaphore *)&thread->namespaces_lock);
149
+
ns = __thread__namespaces(thread);
150
+
up_read((struct rw_semaphore *)&thread->namespaces_lock);
151
+
152
+
return ns;
153
+
}
154
+
144
155
static int __thread__set_namespaces(struct thread *thread, u64 timestamp,
145
156
struct namespaces_event *event)
146
157
{
147
-
struct namespaces *new, *curr = thread__namespaces(thread);
158
+
struct namespaces *new, *curr = __thread__namespaces(thread);
148
159
149
160
new = namespaces__new(event);
150
161
if (!new)