tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

phy: cadence: Sierra: Add PCIe + USB PHY multilink configuration

Add register sequences for PCIe + USB multilink configuration for
Sierra PHY.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250610130133.2102196-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Swapnil Jakhade and committed by
Vinod Koul 6767df73 543f5e31

+180
+180
drivers/phy/cadence/phy-cadence-sierra.c
··· 58 58 #define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 59 59 #define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3 60 60 #define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG 0xC5 61 + #define SIERRA_CMN_PLLLC1_MODE_PREG 0xC8 62 + #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE1_PREG 0xC9 61 63 #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA 62 64 #define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE 65 + #define SIERRA_CMN_PLLLC1_BWCAL_MODE1_PREG 0xCF 63 66 #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0 64 67 #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2 65 68 ··· 1544 1541 cdns_sierra_clk_unregister(phy); 1545 1542 } 1546 1543 1544 + /* USB refclk 100MHz, 20b, SuperSpeed opt2, ext ssc, PLL LC1, multilink */ 1545 + static const struct cdns_reg_pairs usb_100_ext_ssc_plllc1_cmn_regs[] = { 1546 + {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG}, 1547 + {0x2086, SIERRA_CMN_PLLLC1_LF_COEFF_MODE1_PREG}, 1548 + {0x2086, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, 1549 + {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG}, 1550 + {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE1_PREG}, 1551 + {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, 1552 + {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} 1553 + }; 1554 + 1555 + /* USB refclk 100MHz, 20b, SuperSpeed opt2, int ssc, PLL LC1, multilink */ 1556 + static const struct cdns_reg_pairs usb_100_int_ssc_plllc1_cmn_regs[] = { 1557 + {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG}, 1558 + {0x000E, SIERRA_CMN_PLLLC1_MODE_PREG}, 1559 + {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG} 1560 + }; 1561 + 1562 + static const struct cdns_reg_pairs usb_100_ml_ln_regs[] = { 1563 + {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 1564 + {0x000F, SIERRA_DET_STANDEC_B_PREG}, 1565 + {0x55A5, SIERRA_DET_STANDEC_C_PREG}, 1566 + {0x69AD, SIERRA_DET_STANDEC_D_PREG}, 1567 + {0x0241, SIERRA_DET_STANDEC_E_PREG}, 1568 + {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 1569 + {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 1570 + {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1571 + {0x0004, SIERRA_PSC_LN_A3_PREG}, 1572 + {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1573 + {0x001F, SIERRA_PSC_TX_A0_PREG}, 1574 + {0x0007, SIERRA_PSC_TX_A1_PREG}, 1575 + {0x0003, SIERRA_PSC_TX_A2_PREG}, 1576 + {0x0003, SIERRA_PSC_TX_A3_PREG}, 1577 + {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 1578 + {0x0619, SIERRA_PSC_RX_A1_PREG}, 1579 + {0x0003, SIERRA_PSC_RX_A2_PREG}, 1580 + {0x0001, SIERRA_PSC_RX_A3_PREG}, 1581 + {0x0606, SIERRA_PLLCTRL_FBDIV_MODE01_PREG}, 1582 + {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 1583 + {0x0003, SIERRA_PLLCTRL_GEN_A_PREG}, 1584 + {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 1585 + {0x5211, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 1586 + {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 1587 + {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 1588 + {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1589 + {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1590 + {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1591 + {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1592 + {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1593 + {0x023F, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1594 + {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1595 + {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1596 + {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1597 + {0x8452, SIERRA_CTLELUT_CTRL_PREG}, 1598 + {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, 1599 + {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, 1600 + {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 1601 + {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 1602 + {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1603 + {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1604 + {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1605 + {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1606 + {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 1607 + {0xA9A9, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 1608 + {0x0014, SIERRA_DEQ_GLUT0}, 1609 + {0x0014, SIERRA_DEQ_GLUT1}, 1610 + {0x0014, SIERRA_DEQ_GLUT2}, 1611 + {0x0014, SIERRA_DEQ_GLUT3}, 1612 + {0x0014, SIERRA_DEQ_GLUT4}, 1613 + {0x0014, SIERRA_DEQ_GLUT5}, 1614 + {0x0014, SIERRA_DEQ_GLUT6}, 1615 + {0x0014, SIERRA_DEQ_GLUT7}, 1616 + {0x0014, SIERRA_DEQ_GLUT8}, 1617 + {0x0014, SIERRA_DEQ_GLUT9}, 1618 + {0x0014, SIERRA_DEQ_GLUT10}, 1619 + {0x0014, SIERRA_DEQ_GLUT11}, 1620 + {0x0014, SIERRA_DEQ_GLUT12}, 1621 + {0x0014, SIERRA_DEQ_GLUT13}, 1622 + {0x0014, SIERRA_DEQ_GLUT14}, 1623 + {0x0014, SIERRA_DEQ_GLUT15}, 1624 + {0x0014, SIERRA_DEQ_GLUT16}, 1625 + {0x0BAE, SIERRA_DEQ_ALUT0}, 1626 + {0x0AEB, SIERRA_DEQ_ALUT1}, 1627 + {0x0A28, SIERRA_DEQ_ALUT2}, 1628 + {0x0965, SIERRA_DEQ_ALUT3}, 1629 + {0x08A2, SIERRA_DEQ_ALUT4}, 1630 + {0x07DF, SIERRA_DEQ_ALUT5}, 1631 + {0x071C, SIERRA_DEQ_ALUT6}, 1632 + {0x0659, SIERRA_DEQ_ALUT7}, 1633 + {0x0596, SIERRA_DEQ_ALUT8}, 1634 + {0x0514, SIERRA_DEQ_ALUT9}, 1635 + {0x0492, SIERRA_DEQ_ALUT10}, 1636 + {0x0410, SIERRA_DEQ_ALUT11}, 1637 + {0x038E, SIERRA_DEQ_ALUT12}, 1638 + {0x030C, SIERRA_DEQ_ALUT13}, 1639 + {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1640 + {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 1641 + {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1642 + {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1643 + {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 1644 + {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1645 + {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 1646 + {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 1647 + {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1648 + {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 1649 + {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 1650 + {0x000F, SIERRA_LFPSFILT_NS_PREG}, 1651 + {0x0009, SIERRA_LFPSFILT_RD_PREG}, 1652 + {0x0001, SIERRA_LFPSFILT_MP_PREG}, 1653 + {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 1654 + {0x8009, SIERRA_SDFILT_L2H_PREG}, 1655 + {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1656 + {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1657 + {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 1658 + }; 1659 + 1660 + static const struct cdns_sierra_vals usb_100_ext_ssc_plllc1_cmn_vals = { 1661 + .reg_pairs = usb_100_ext_ssc_plllc1_cmn_regs, 1662 + .num_regs = ARRAY_SIZE(usb_100_ext_ssc_plllc1_cmn_regs), 1663 + }; 1664 + 1665 + static const struct cdns_sierra_vals usb_100_int_ssc_plllc1_cmn_vals = { 1666 + .reg_pairs = usb_100_int_ssc_plllc1_cmn_regs, 1667 + .num_regs = ARRAY_SIZE(usb_100_int_ssc_plllc1_cmn_regs), 1668 + }; 1669 + 1670 + static const struct cdns_sierra_vals usb_100_ml_ln_vals = { 1671 + .reg_pairs = usb_100_ml_ln_regs, 1672 + .num_regs = ARRAY_SIZE(usb_100_ml_ln_regs), 1673 + }; 1674 + 1547 1675 /* SGMII PHY PMA lane configuration */ 1548 1676 static const struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = { 1549 1677 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} ··· 2647 2513 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2648 2514 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2649 2515 }, 2516 + [TYPE_USB] = { 2517 + [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2518 + [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2519 + [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2520 + }, 2650 2521 }, 2651 2522 }, 2652 2523 .pma_cmn_vals = { ··· 2671 2532 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2672 2533 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2673 2534 }, 2535 + [TYPE_USB] = { 2536 + [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2537 + [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2538 + [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2539 + }, 2674 2540 }, 2675 2541 [TYPE_USB] = { 2676 2542 [TYPE_NONE] = { 2677 2543 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 2544 + }, 2545 + [TYPE_PCIE] = { 2546 + [EXTERNAL_SSC] = &usb_100_ext_ssc_plllc1_cmn_vals, 2547 + [INTERNAL_SSC] = &usb_100_int_ssc_plllc1_cmn_vals, 2678 2548 }, 2679 2549 }, 2680 2550 [TYPE_SGMII] = { ··· 2721 2573 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 2722 2574 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 2723 2575 }, 2576 + [TYPE_USB] = { 2577 + [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 2578 + [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 2579 + [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 2580 + }, 2724 2581 }, 2725 2582 [TYPE_USB] = { 2726 2583 [TYPE_NONE] = { 2727 2584 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 2585 + }, 2586 + [TYPE_PCIE] = { 2587 + [EXTERNAL_SSC] = &usb_100_ml_ln_vals, 2588 + [INTERNAL_SSC] = &usb_100_ml_ln_vals, 2728 2589 }, 2729 2590 }, 2730 2591 [TYPE_SGMII] = { ··· 2777 2620 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2778 2621 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2779 2622 }, 2623 + [TYPE_USB] = { 2624 + [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2625 + [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2626 + [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2627 + }, 2780 2628 }, 2781 2629 }, 2782 2630 .phy_pma_ln_vals = { ··· 2817 2655 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2818 2656 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2819 2657 }, 2658 + [TYPE_USB] = { 2659 + [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2660 + [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2661 + [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2662 + }, 2820 2663 }, 2821 2664 [TYPE_USB] = { 2822 2665 [TYPE_NONE] = { 2823 2666 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 2667 + }, 2668 + [TYPE_PCIE] = { 2669 + [EXTERNAL_SSC] = &usb_100_ext_ssc_plllc1_cmn_vals, 2670 + [INTERNAL_SSC] = &usb_100_int_ssc_plllc1_cmn_vals, 2824 2671 }, 2825 2672 }, 2826 2673 [TYPE_SGMII] = { ··· 2864 2693 [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, 2865 2694 [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, 2866 2695 }, 2696 + [TYPE_USB] = { 2697 + [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, 2698 + [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, 2699 + [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, 2700 + }, 2867 2701 }, 2868 2702 [TYPE_USB] = { 2869 2703 [TYPE_NONE] = { 2870 2704 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 2705 + }, 2706 + [TYPE_PCIE] = { 2707 + [EXTERNAL_SSC] = &usb_100_ml_ln_vals, 2708 + [INTERNAL_SSC] = &usb_100_ml_ln_vals, 2871 2709 }, 2872 2710 }, 2873 2711 [TYPE_SGMII] = {