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dt-bindings: pinctrl: Update pinctrl-single to use yaml

Update binding for yaml and remove the old related txt bindings. Note that
we are also adding the undocumented pinctrl-single,slew-rate property. And
we only use the first example from the old binding.

As we are mostly using a generic compatible across various SoCs, let's not
start adding matches for random pin group node naming. Let's standardize on
pin group node name ending in -pins with an optional instance number
suffix.

As a pin group may have additional pins added to it later on, let's always
use -pins rather than -pin for the gropu name.

Most of the dts files have been updated already for the pin group node
names with a few changes still pending.

Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230721082654.27036-1-tony@atomide.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Tony Lindgren and committed by
Linus Walleij 677a6248 0a80e1d3

+207 -276
+1 -1
Documentation/devicetree/bindings/arm/omap/ctrl.txt
··· 8 8 9 9 See [2] for documentation about clock/clockdomain nodes. 10 10 11 - [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt 11 + [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml 12 12 [2] Documentation/devicetree/bindings/clock/ti/* 13 13 14 14 Required properties:
-262
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
··· 1 - One-register-per-pin type device tree based pinctrl driver 2 - 3 - Required properties: 4 - - compatible : "pinctrl-single" or "pinconf-single". 5 - "pinctrl-single" means that pinconf isn't supported. 6 - "pinconf-single" means that generic pinconf is supported. 7 - 8 - - reg : offset and length of the register set for the mux registers 9 - 10 - - #pinctrl-cells : number of cells in addition to the index, set to 1 11 - or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits 12 - 13 - - pinctrl-single,register-width : pinmux register access width in bits 14 - 15 - - pinctrl-single,function-mask : mask of allowed pinmux function bits 16 - in the pinmux register 17 - 18 - Optional properties: 19 - - pinctrl-single,function-off : function off mode for disabled state if 20 - available and same for all registers; if not specified, disabling of 21 - pin functions is ignored 22 - 23 - - pinctrl-single,bit-per-mux : boolean to indicate that one register controls 24 - more than one pin, for which "pinctrl-single,function-mask" property specifies 25 - position mask of pin. 26 - 27 - - pinctrl-single,drive-strength : array of value that are used to configure 28 - drive strength in the pinmux register. They're value of drive strength 29 - current and drive strength mask. 30 - 31 - /* drive strength current, mask */ 32 - pinctrl-single,power-source = <0x30 0xf0>; 33 - 34 - - pinctrl-single,bias-pullup : array of value that are used to configure the 35 - input bias pullup in the pinmux register. 36 - 37 - /* input, enabled pullup bits, disabled pullup bits, mask */ 38 - pinctrl-single,bias-pullup = <0 1 0 1>; 39 - 40 - - pinctrl-single,bias-pulldown : array of value that are used to configure the 41 - input bias pulldown in the pinmux register. 42 - 43 - /* input, enabled pulldown bits, disabled pulldown bits, mask */ 44 - pinctrl-single,bias-pulldown = <2 2 0 2>; 45 - 46 - * Two bits to control input bias pullup and pulldown: User should use 47 - pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means 48 - pullup, and the other one bit means pulldown. 49 - * Three bits to control input bias enable, pullup and pulldown. User should 50 - use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias 51 - enable bit should be included in pullup or pulldown bits. 52 - * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as 53 - pinctrl-single,bias-disable. Because pinctrl single driver could implement 54 - it by calling pulldown, pullup disabled. 55 - 56 - - pinctrl-single,input-schmitt : array of value that are used to configure 57 - input schmitt in the pinmux register. In some silicons, there're two input 58 - schmitt value (rising-edge & falling-edge) in the pinmux register. 59 - 60 - /* input schmitt value, mask */ 61 - pinctrl-single,input-schmitt = <0x30 0x70>; 62 - 63 - - pinctrl-single,input-schmitt-enable : array of value that are used to 64 - configure input schmitt enable or disable in the pinmux register. 65 - 66 - /* input, enable bits, disable bits, mask */ 67 - pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; 68 - 69 - - pinctrl-single,low-power-mode : array of value that are used to configure 70 - low power mode of this pin. For some silicons, the low power mode will 71 - control the output of the pin when the pad including the pin enter low 72 - power mode. 73 - /* low power mode value, mask */ 74 - pinctrl-single,low-power-mode = <0x288 0x388>; 75 - 76 - - pinctrl-single,gpio-range : list of value that are used to configure a GPIO 77 - range. They're value of subnode phandle, pin base in pinctrl device, pin 78 - number in this range, GPIO function value of this GPIO range. 79 - The number of parameters is depend on #pinctrl-single,gpio-range-cells 80 - property. 81 - 82 - /* pin base, nr pins & gpio function */ 83 - pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>; 84 - 85 - - interrupt-controller : standard interrupt controller binding if using 86 - interrupts for wake-up events for example. In this case pinctrl-single 87 - is set up as a chained interrupt controller and the wake-up interrupts 88 - can be requested by the drivers using request_irq(). 89 - 90 - - #interrupt-cells : standard interrupt binding if using interrupts 91 - 92 - This driver assumes that there is only one register for each pin (unless the 93 - pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as 94 - specified in the pinctrl-bindings.txt document in this directory. 95 - 96 - The pin configuration nodes for pinctrl-single are specified as pinctrl 97 - register offset and values using pinctrl-single,pins. Only the bits specified 98 - in pinctrl-single,function-mask are updated. 99 - 100 - When #pinctrl-cells = 1, then setting a pin for a device could be done with: 101 - 102 - pinctrl-single,pins = <0xdc 0x118>; 103 - 104 - Where 0xdc is the offset from the pinctrl register base address for the device 105 - pinctrl register, and 0x118 contains the desired value of the pinctrl register. 106 - 107 - When #pinctrl-cells = 2, then setting a pin for a device could be done with: 108 - 109 - pinctrl-single,pins = <0xdc 0x30 0x07>; 110 - 111 - Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value. 112 - These two values are OR'd together to produce the value stored at offset 0xdc. 113 - See the device example and static board pins example below for more information. 114 - 115 - In case when one register changes more than one pin's mux the 116 - pinctrl-single,bits need to be used which takes three parameters: 117 - 118 - pinctrl-single,bits = <0xdc 0x18 0xff>; 119 - 120 - Where 0xdc is the offset from the pinctrl register base address for the 121 - device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to 122 - be used when applying this change to the register. 123 - 124 - 125 - Optional sub-node: In case some pins could be configured as GPIO in the pinmux 126 - register, those pins could be defined as a GPIO range. This sub-node is required 127 - by pinctrl-single,gpio-range property. 128 - 129 - Required properties in sub-node: 130 - - #pinctrl-single,gpio-range-cells : the number of parameters after phandle in 131 - pinctrl-single,gpio-range property. 132 - 133 - range: gpio-range { 134 - #pinctrl-single,gpio-range-cells = <3>; 135 - }; 136 - 137 - 138 - Example: 139 - 140 - /* SoC common file */ 141 - 142 - /* first controller instance for pins in core domain */ 143 - pmx_core: pinmux@4a100040 { 144 - compatible = "pinctrl-single"; 145 - reg = <0x4a100040 0x0196>; 146 - #address-cells = <1>; 147 - #size-cells = <0>; 148 - #interrupt-cells = <1>; 149 - interrupt-controller; 150 - pinctrl-single,register-width = <16>; 151 - pinctrl-single,function-mask = <0xffff>; 152 - }; 153 - 154 - /* second controller instance for pins in wkup domain */ 155 - pmx_wkup: pinmux@4a31e040 { 156 - compatible = "pinctrl-single"; 157 - reg = <0x4a31e040 0x0038>; 158 - #address-cells = <1>; 159 - #size-cells = <0>; 160 - #interrupt-cells = <1>; 161 - interrupt-controller; 162 - pinctrl-single,register-width = <16>; 163 - pinctrl-single,function-mask = <0xffff>; 164 - }; 165 - 166 - control_devconf0: pinmux@48002274 { 167 - compatible = "pinctrl-single"; 168 - reg = <0x48002274 4>; /* Single register */ 169 - #address-cells = <1>; 170 - #size-cells = <0>; 171 - pinctrl-single,bit-per-mux; 172 - pinctrl-single,register-width = <32>; 173 - pinctrl-single,function-mask = <0x5F>; 174 - }; 175 - 176 - /* third controller instance for pins in gpio domain */ 177 - pmx_gpio: pinmux@d401e000 { 178 - compatible = "pinconf-single"; 179 - reg = <0xd401e000 0x0330>; 180 - #address-cells = <1>; 181 - #size-cells = <1>; 182 - ranges; 183 - 184 - pinctrl-single,register-width = <32>; 185 - pinctrl-single,function-mask = <7>; 186 - 187 - /* sparse GPIO range could be supported */ 188 - pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>, 189 - <&range 12 1 0>, <&range 13 29 1>, 190 - <&range 43 1 0>, <&range 44 49 1>, 191 - <&range 94 1 1>, <&range 96 2 1>; 192 - 193 - range: gpio-range { 194 - #pinctrl-single,gpio-range-cells = <3>; 195 - }; 196 - }; 197 - 198 - 199 - /* board specific .dts file */ 200 - 201 - &pmx_core { 202 - 203 - /* 204 - * map all board specific static pins enabled by the pinctrl driver 205 - * itself during the boot (or just set them up in the bootloader) 206 - */ 207 - pinctrl-names = "default"; 208 - pinctrl-0 = <&board_pins>; 209 - 210 - board_pins: pinmux_board_pins { 211 - pinctrl-single,pins = < 212 - 0x6c 0xf 213 - 0x6e 0xf 214 - 0x70 0xf 215 - 0x72 0xf 216 - >; 217 - }; 218 - 219 - uart0_pins: pinmux_uart0_pins { 220 - pinctrl-single,pins = < 221 - 0x208 0 /* UART0_RXD (IOCFG138) */ 222 - 0x20c 0 /* UART0_TXD (IOCFG139) */ 223 - >; 224 - pinctrl-single,bias-pulldown = <0 2 2>; 225 - pinctrl-single,bias-pullup = <0 1 1>; 226 - }; 227 - 228 - /* map uart2 pins */ 229 - uart2_pins: pinmux_uart2_pins { 230 - pinctrl-single,pins = < 231 - 0xd8 0x118 232 - 0xda 0 233 - 0xdc 0x118 234 - 0xde 0 235 - >; 236 - }; 237 - }; 238 - 239 - &control_devconf0 { 240 - mcbsp1_pins: pinmux_mcbsp1_pins { 241 - pinctrl-single,bits = < 242 - 0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */ 243 - >; 244 - }; 245 - 246 - mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins { 247 - pinctrl-single,bits = < 248 - 0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */ 249 - >; 250 - }; 251 - 252 - }; 253 - 254 - &uart1 { 255 - pinctrl-names = "default"; 256 - pinctrl-0 = <&uart0_pins>; 257 - }; 258 - 259 - &uart2 { 260 - pinctrl-names = "default"; 261 - pinctrl-0 = <&uart2_pins>; 262 - };
+206
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Generic Pin Controller with a Single Register for One or More Pins 8 + 9 + maintainers: 10 + - Tony Lindgren <tony@atomide.com> 11 + 12 + description: 13 + Some pin controller devices use a single register for one or more pins. The 14 + range of pin control registers can vary from one to many for each controller 15 + instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this 16 + kind of pin controller instances. 17 + 18 + properties: 19 + compatible: 20 + oneOf: 21 + - enum: 22 + - pinctrl-single 23 + - pinconf-single 24 + - items: 25 + - enum: 26 + - ti,am437-padconf 27 + - ti,dra7-padconf 28 + - ti,omap2420-padconf 29 + - ti,omap2430-padconf 30 + - ti,omap3-padconf 31 + - ti,omap4-padconf 32 + - ti,omap5-padconf 33 + - const: pinctrl-single 34 + 35 + reg: 36 + maxItems: 1 37 + 38 + interrupt-controller: true 39 + 40 + '#interrupt-cells': 41 + const: 1 42 + 43 + '#address-cells': 44 + const: 1 45 + 46 + '#size-cells': 47 + const: 0 48 + 49 + '#pinctrl-cells': 50 + description: 51 + Number of cells. Usually 2, consisting of register offset, pin configuration 52 + value, and pinmux mode. Some controllers may use 1 for just offset and value. 53 + enum: [ 1, 2 ] 54 + 55 + pinctrl-single,bit-per-mux: 56 + description: Optional flag to indicate register controls more than one pin 57 + type: boolean 58 + 59 + pinctrl-single,function-mask: 60 + description: Mask of the allowed register bits 61 + $ref: /schemas/types.yaml#/definitions/uint32 62 + 63 + pinctrl-single,function-off: 64 + description: Optional function off mode for disabled state 65 + $ref: /schemas/types.yaml#/definitions/uint32 66 + 67 + pinctrl-single,register-width: 68 + description: Width of pin specific bits in the register 69 + $ref: /schemas/types.yaml#/definitions/uint32 70 + enum: [ 8, 16, 32 ] 71 + 72 + pinctrl-single,gpio-range: 73 + description: Optional list of pin base, nr pins & gpio function 74 + $ref: /schemas/types.yaml#/definitions/phandle-array 75 + items: 76 + - items: 77 + - description: phandle of a gpio-range node 78 + - description: pin base 79 + - description: number of pins 80 + - description: gpio function 81 + 82 + '#gpio-range-cells': 83 + description: No longer needed, may exist in older files for gpio-ranges 84 + deprecated: true 85 + const: 3 86 + 87 + gpio-range: 88 + description: Optional node for gpio range cells 89 + type: object 90 + additionalProperties: false 91 + properties: 92 + '#pinctrl-single,gpio-range-cells': 93 + description: Number of gpio range cells 94 + const: 3 95 + $ref: /schemas/types.yaml#/definitions/uint32 96 + 97 + patternProperties: 98 + '-pins(-[0-9]+)?$|-pin$': 99 + description: 100 + Pin group node name using naming ending in -pins followed by an optional 101 + instance number 102 + type: object 103 + additionalProperties: false 104 + 105 + properties: 106 + pinctrl-single,pins: 107 + description: 108 + Array of pins as described in pinmux-node.yaml for pinctrl-pin-array 109 + $ref: /schemas/types.yaml#/definitions/uint32-array 110 + 111 + pinctrl-single,bits: 112 + description: Register bit configuration for pinctrl-single,bit-per-mux 113 + $ref: /schemas/types.yaml#/definitions/uint32-array 114 + items: 115 + - description: register offset 116 + - description: value 117 + - description: pin bitmask in the register 118 + 119 + pinctrl-single,bias-pullup: 120 + description: Optional bias pull up configuration 121 + $ref: /schemas/types.yaml#/definitions/uint32-array 122 + items: 123 + - description: input 124 + - description: enabled pull up bits 125 + - description: disabled pull up bits 126 + - description: bias pull up mask 127 + 128 + pinctrl-single,bias-pulldown: 129 + description: Optional bias pull down configuration 130 + $ref: /schemas/types.yaml#/definitions/uint32-array 131 + items: 132 + - description: input 133 + - description: enabled pull down bits 134 + - description: disabled pull down bits 135 + - description: bias pull down mask 136 + 137 + pinctrl-single,drive-strength: 138 + description: Optional drive strength configuration 139 + $ref: /schemas/types.yaml#/definitions/uint32-array 140 + items: 141 + - description: drive strength current 142 + - description: drive strength mask 143 + 144 + pinctrl-single,input-schmitt: 145 + description: Optional input schmitt configuration 146 + $ref: /schemas/types.yaml#/definitions/uint32-array 147 + items: 148 + - description: input 149 + - description: enable bits 150 + - description: disable bits 151 + - description: input schmitt mask 152 + 153 + pinctrl-single,low-power-mode: 154 + description: Optional low power mode configuration 155 + $ref: /schemas/types.yaml#/definitions/uint32-array 156 + items: 157 + - description: low power mode value 158 + - description: low power mode mask 159 + 160 + pinctrl-single,slew-rate: 161 + description: Optional slew rate configuration 162 + $ref: /schemas/types.yaml#/definitions/uint32-array 163 + items: 164 + - description: slew rate 165 + - description: slew rate mask 166 + 167 + allOf: 168 + - $ref: pinctrl.yaml# 169 + 170 + required: 171 + - compatible 172 + - reg 173 + - pinctrl-single,register-width 174 + 175 + additionalProperties: false 176 + 177 + examples: 178 + - | 179 + soc { 180 + #address-cells = <1>; 181 + #size-cells = <1>; 182 + 183 + pinmux@4a100040 { 184 + compatible = "pinctrl-single"; 185 + reg = <0x4a100040 0x0196>; 186 + #address-cells = <1>; 187 + #size-cells = <0>; 188 + #pinctrl-cells = <2>; 189 + #interrupt-cells = <1>; 190 + interrupt-controller; 191 + pinctrl-single,register-width = <16>; 192 + pinctrl-single,function-mask = <0xffff>; 193 + pinctrl-single,gpio-range = <&range 0 3 0>; 194 + range: gpio-range { 195 + #pinctrl-single,gpio-range-cells = <3>; 196 + }; 197 + 198 + uart2-pins { 199 + pinctrl-single,pins = 200 + <0xd8 0x118>, 201 + <0xda 0>, 202 + <0xdc 0x118>, 203 + <0xde 0>; 204 + }; 205 + }; 206 + };
-13
Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
··· 1 - OMAP Pinctrl definitions 2 - 3 - Required properties: 4 - - compatible : Should be one of: 5 - "ti,omap2420-padconf" - OMAP2420 compatible pinctrl 6 - "ti,omap2430-padconf" - OMAP2430 compatible pinctrl 7 - "ti,omap3-padconf" - OMAP3 compatible pinctrl 8 - "ti,omap4-padconf" - OMAP4 compatible pinctrl 9 - "ti,omap5-padconf" - OMAP5 compatible pinctrl 10 - "ti,dra7-padconf" - DRA7 compatible pinctrl 11 - "ti,am437-padconf" - AM437x compatible pinctrl 12 - 13 - See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.