tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'soc-fixes-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC fixes from Arnd Bergmann:
"The device tree changes this time are all for NXP i.MX platforms,
addressing issues with clocks and regulators on i.MX7 and i.MX8.

The old OMAP2 based Nokia N8x0 tablet get a couple of code fixes for
regressions that came in.

The ARM SCMI and FF-A firmware interfaces get a couple of minor bug
fixes.

A regression fix for RISC-V cache management addresses a problem with
probe order on Sifive cores"

* tag 'soc-fixes-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (23 commits)
MAINTAINERS: Change Krzysztof Kozlowski's email address
arm64: dts: imx8qm-ss-dma: fix can lpcg indices
arm64: dts: imx8-ss-dma: fix can lpcg indices
arm64: dts: imx8-ss-dma: fix adc lpcg indices
arm64: dts: imx8-ss-dma: fix pwm lpcg indices
arm64: dts: imx8-ss-dma: fix spi lpcg indices
arm64: dts: imx8-ss-conn: fix usb lpcg indices
arm64: dts: imx8-ss-lsio: fix pwm lpcg indices
ARM: dts: imx7s-warp: Pass OV2680 link-frequencies
ARM: dts: imx7-mba7: Use 'no-mmc' property
arm64: dts: imx8-ss-conn: fix usdhc wrong lpcg clock order
arm64: dts: freescale: imx8mp-venice-gw73xx-2x: fix USB vbus regulator
arm64: dts: freescale: imx8mp-venice-gw72xx-2x: fix USB vbus regulator
cache: sifive_ccache: Partially convert to a platform driver
firmware: arm_scmi: Make raw debugfs entries non-seekable
firmware: arm_scmi: Fix wrong fastchannel initialization
firmware: arm_ffa: Fix the partition ID check in ffa_notification_info_get()
ARM: OMAP2+: fix USB regression on Nokia N8x0
mmc: omap: restore original power up/down steps
mmc: omap: fix deferred probe
...

Linus Torvalds 678e14c7 c7c4e130

+158 -121
+19 -19
MAINTAINERS
··· 2707 2707 N: rockchip 2708 2708 2709 2709 ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES 2710 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 2710 + M: Krzysztof Kozlowski <krzk@kernel.org> 2711 2711 R: Alim Akhtar <alim.akhtar@samsung.com> 2712 2712 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 2713 2713 L: linux-samsung-soc@vger.kernel.org ··· 5555 5555 CPUIDLE DRIVER - ARM EXYNOS 5556 5556 M: Daniel Lezcano <daniel.lezcano@linaro.org> 5557 5557 M: Kukjin Kim <kgene@kernel.org> 5558 - R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 5558 + R: Krzysztof Kozlowski <krzk@kernel.org> 5559 5559 L: linux-pm@vger.kernel.org 5560 5560 L: linux-samsung-soc@vger.kernel.org 5561 5561 S: Maintained ··· 8994 8994 F: include/linux/platform_data/i2c-mux-gpio.h 8995 8995 8996 8996 GENERIC GPIO RESET DRIVER 8997 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 8997 + M: Krzysztof Kozlowski <krzk@kernel.org> 8998 8998 S: Maintained 8999 8999 F: drivers/reset/reset-gpio.c 9000 9000 ··· 13289 13289 13290 13290 MAXIM MAX17040 FAMILY FUEL GAUGE DRIVERS 13291 13291 R: Iskren Chernev <iskren.chernev@gmail.com> 13292 - R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 13292 + R: Krzysztof Kozlowski <krzk@kernel.org> 13293 13293 R: Marek Szyprowski <m.szyprowski@samsung.com> 13294 13294 R: Matheus Castello <matheus@castello.eng.br> 13295 13295 L: linux-pm@vger.kernel.org ··· 13299 13299 13300 13300 MAXIM MAX17042 FAMILY FUEL GAUGE DRIVERS 13301 13301 R: Hans de Goede <hdegoede@redhat.com> 13302 - R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 13302 + R: Krzysztof Kozlowski <krzk@kernel.org> 13303 13303 R: Marek Szyprowski <m.szyprowski@samsung.com> 13304 13304 R: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> 13305 13305 R: Purism Kernel Team <kernel@puri.sm> ··· 13357 13357 F: drivers/power/supply/max77976_charger.c 13358 13358 13359 13359 MAXIM MUIC CHARGER DRIVERS FOR EXYNOS BASED BOARDS 13360 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 13360 + M: Krzysztof Kozlowski <krzk@kernel.org> 13361 13361 L: linux-pm@vger.kernel.org 13362 13362 S: Maintained 13363 13363 B: mailto:linux-samsung-soc@vger.kernel.org ··· 13368 13368 13369 13369 MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BOARDS 13370 13370 M: Chanwoo Choi <cw00.choi@samsung.com> 13371 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 13371 + M: Krzysztof Kozlowski <krzk@kernel.org> 13372 13372 L: linux-kernel@vger.kernel.org 13373 13373 S: Maintained 13374 13374 B: mailto:linux-samsung-soc@vger.kernel.org ··· 14152 14152 F: tools/testing/memblock/ 14153 14153 14154 14154 MEMORY CONTROLLER DRIVERS 14155 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 14155 + M: Krzysztof Kozlowski <krzk@kernel.org> 14156 14156 L: linux-kernel@vger.kernel.org 14157 14157 S: Maintained 14158 14158 B: mailto:krzysztof.kozlowski@linaro.org ··· 15533 15533 F: net/ipv4/nexthop.c 15534 15534 15535 15535 NFC SUBSYSTEM 15536 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 15536 + M: Krzysztof Kozlowski <krzk@kernel.org> 15537 15537 L: netdev@vger.kernel.org 15538 15538 S: Maintained 15539 15539 F: Documentation/devicetree/bindings/net/nfc/ ··· 15910 15910 F: drivers/regulator/pf8x00-regulator.c 15911 15911 15912 15912 NXP PTN5150A CC LOGIC AND EXTCON DRIVER 15913 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 15913 + M: Krzysztof Kozlowski <krzk@kernel.org> 15914 15914 L: linux-kernel@vger.kernel.org 15915 15915 S: Maintained 15916 15916 F: Documentation/devicetree/bindings/extcon/extcon-ptn5150.yaml ··· 16521 16521 16522 16522 OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS 16523 16523 M: Rob Herring <robh@kernel.org> 16524 - M: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> 16524 + M: Krzysztof Kozlowski <krzk+dt@kernel.org> 16525 16525 M: Conor Dooley <conor+dt@kernel.org> 16526 16526 L: devicetree@vger.kernel.org 16527 16527 S: Maintained ··· 17478 17478 F: drivers/pinctrl/renesas/ 17479 17479 17480 17480 PIN CONTROLLER - SAMSUNG 17481 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 17481 + M: Krzysztof Kozlowski <krzk@kernel.org> 17482 17482 M: Sylwester Nawrocki <s.nawrocki@samsung.com> 17483 17483 R: Alim Akhtar <alim.akhtar@samsung.com> 17484 17484 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) ··· 19446 19446 F: sound/soc/samsung/ 19447 19447 19448 19448 SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER 19449 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 19449 + M: Krzysztof Kozlowski <krzk@kernel.org> 19450 19450 L: linux-crypto@vger.kernel.org 19451 19451 L: linux-samsung-soc@vger.kernel.org 19452 19452 S: Maintained ··· 19481 19481 F: drivers/platform/x86/samsung-laptop.c 19482 19482 19483 19483 SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS 19484 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 19484 + M: Krzysztof Kozlowski <krzk@kernel.org> 19485 19485 L: linux-kernel@vger.kernel.org 19486 19486 L: linux-samsung-soc@vger.kernel.org 19487 19487 S: Maintained ··· 19507 19507 F: include/media/drv-intf/s3c_camif.h 19508 19508 19509 19509 SAMSUNG S3FWRN5 NFC DRIVER 19510 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 19510 + M: Krzysztof Kozlowski <krzk@kernel.org> 19511 19511 S: Maintained 19512 19512 F: Documentation/devicetree/bindings/net/nfc/samsung,s3fwrn5.yaml 19513 19513 F: drivers/nfc/s3fwrn5 ··· 19528 19528 F: drivers/media/i2c/s5k5baf.c 19529 19529 19530 19530 SAMSUNG S5P Security SubSystem (SSS) DRIVER 19531 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 19531 + M: Krzysztof Kozlowski <krzk@kernel.org> 19532 19532 M: Vladimir Zapolskiy <vz@mleia.com> 19533 19533 L: linux-crypto@vger.kernel.org 19534 19534 L: linux-samsung-soc@vger.kernel.org ··· 19550 19550 F: drivers/media/platform/samsung/exynos4-is/ 19551 19551 19552 19552 SAMSUNG SOC CLOCK DRIVERS 19553 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 19553 + M: Krzysztof Kozlowski <krzk@kernel.org> 19554 19554 M: Sylwester Nawrocki <s.nawrocki@samsung.com> 19555 19555 M: Chanwoo Choi <cw00.choi@samsung.com> 19556 19556 R: Alim Akhtar <alim.akhtar@samsung.com> ··· 19582 19582 19583 19583 SAMSUNG THERMAL DRIVER 19584 19584 M: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 19585 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 19585 + M: Krzysztof Kozlowski <krzk@kernel.org> 19586 19586 L: linux-pm@vger.kernel.org 19587 19587 L: linux-samsung-soc@vger.kernel.org 19588 19588 S: Maintained ··· 23779 23779 F: drivers/mmc/host/vub300.c 23780 23780 23781 23781 W1 DALLAS'S 1-WIRE BUS 23782 - M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 23782 + M: Krzysztof Kozlowski <krzk@kernel.org> 23783 23783 S: Maintained 23784 23784 F: Documentation/devicetree/bindings/w1/ 23785 23785 F: Documentation/w1/
+1 -1
arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi
··· 666 666 bus-width = <4>; 667 667 no-1-8-v; 668 668 no-sdio; 669 - no-emmc; 669 + no-mmc; 670 670 status = "okay"; 671 671 }; 672 672
+1
arch/arm/boot/dts/nxp/imx/imx7s-warp.dts
··· 210 210 remote-endpoint = <&mipi_from_sensor>; 211 211 clock-lanes = <0>; 212 212 data-lanes = <1>; 213 + link-frequencies = /bits/ 64 <330000000>; 213 214 }; 214 215 }; 215 216 };
+10 -13
arch/arm/mach-omap2/board-n8x0.c
··· 79 79 static struct gpiod_lookup_table tusb_gpio_table = { 80 80 .dev_id = "musb-tusb", 81 81 .table = { 82 - GPIO_LOOKUP("gpio-0-15", 0, "enable", 83 - GPIO_ACTIVE_HIGH), 84 - GPIO_LOOKUP("gpio-48-63", 10, "int", 85 - GPIO_ACTIVE_HIGH), 82 + GPIO_LOOKUP("gpio-0-31", 0, "enable", GPIO_ACTIVE_HIGH), 83 + GPIO_LOOKUP("gpio-32-63", 26, "int", GPIO_ACTIVE_HIGH), 86 84 { } 87 85 }, 88 86 }; ··· 138 140 static int slot2_cover_open; 139 141 static struct device *mmc_device; 140 142 141 - static struct gpiod_lookup_table nokia8xx_mmc_gpio_table = { 143 + static struct gpiod_lookup_table nokia800_mmc_gpio_table = { 142 144 .dev_id = "mmci-omap.0", 143 145 .table = { 144 146 /* Slot switch, GPIO 96 */ 145 - GPIO_LOOKUP("gpio-80-111", 16, 146 - "switch", GPIO_ACTIVE_HIGH), 147 + GPIO_LOOKUP("gpio-96-127", 0, "switch", GPIO_ACTIVE_HIGH), 147 148 { } 148 149 }, 149 150 }; ··· 150 153 static struct gpiod_lookup_table nokia810_mmc_gpio_table = { 151 154 .dev_id = "mmci-omap.0", 152 155 .table = { 156 + /* Slot switch, GPIO 96 */ 157 + GPIO_LOOKUP("gpio-96-127", 0, "switch", GPIO_ACTIVE_HIGH), 153 158 /* Slot index 1, VSD power, GPIO 23 */ 154 - GPIO_LOOKUP_IDX("gpio-16-31", 7, 155 - "vsd", 1, GPIO_ACTIVE_HIGH), 159 + GPIO_LOOKUP_IDX("gpio-0-31", 23, "vsd", 1, GPIO_ACTIVE_HIGH), 156 160 /* Slot index 1, VIO power, GPIO 9 */ 157 - GPIO_LOOKUP_IDX("gpio-0-15", 9, 158 - "vio", 1, GPIO_ACTIVE_HIGH), 161 + GPIO_LOOKUP_IDX("gpio-0-31", 9, "vio", 1, GPIO_ACTIVE_HIGH), 159 162 { } 160 163 }, 161 164 }; ··· 412 415 413 416 static void __init n8x0_mmc_init(void) 414 417 { 415 - gpiod_add_lookup_table(&nokia8xx_mmc_gpio_table); 416 - 417 418 if (board_is_n810()) { 418 419 mmc1_data.slots[0].name = "external"; 419 420 ··· 424 429 mmc1_data.slots[1].name = "internal"; 425 430 mmc1_data.slots[1].ban_openended = 1; 426 431 gpiod_add_lookup_table(&nokia810_mmc_gpio_table); 432 + } else { 433 + gpiod_add_lookup_table(&nokia800_mmc_gpio_table); 427 434 } 428 435 429 436 mmc1_data.nr_slots = 2;
+8 -8
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
··· 41 41 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 42 42 fsl,usbphy = <&usbphy1>; 43 43 fsl,usbmisc = <&usbmisc1 0>; 44 - clocks = <&usb2_lpcg 0>; 44 + clocks = <&usb2_lpcg IMX_LPCG_CLK_6>; 45 45 ahb-burst-config = <0x0>; 46 46 tx-burst-size-dword = <0x10>; 47 47 rx-burst-size-dword = <0x10>; ··· 58 58 usbphy1: usbphy@5b100000 { 59 59 compatible = "fsl,imx7ulp-usbphy"; 60 60 reg = <0x5b100000 0x1000>; 61 - clocks = <&usb2_lpcg 1>; 61 + clocks = <&usb2_lpcg IMX_LPCG_CLK_7>; 62 62 power-domains = <&pd IMX_SC_R_USB_0_PHY>; 63 63 status = "disabled"; 64 64 }; ··· 67 67 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 68 68 reg = <0x5b010000 0x10000>; 69 69 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, 70 - <&sdhc0_lpcg IMX_LPCG_CLK_0>, 71 - <&sdhc0_lpcg IMX_LPCG_CLK_5>; 70 + <&sdhc0_lpcg IMX_LPCG_CLK_5>, 71 + <&sdhc0_lpcg IMX_LPCG_CLK_0>; 72 72 clock-names = "ipg", "ahb", "per"; 73 73 power-domains = <&pd IMX_SC_R_SDHC_0>; 74 74 status = "disabled"; ··· 78 78 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 79 79 reg = <0x5b020000 0x10000>; 80 80 clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, 81 - <&sdhc1_lpcg IMX_LPCG_CLK_0>, 82 - <&sdhc1_lpcg IMX_LPCG_CLK_5>; 81 + <&sdhc1_lpcg IMX_LPCG_CLK_5>, 82 + <&sdhc1_lpcg IMX_LPCG_CLK_0>; 83 83 clock-names = "ipg", "ahb", "per"; 84 84 power-domains = <&pd IMX_SC_R_SDHC_1>; 85 85 fsl,tuning-start-tap = <20>; ··· 91 91 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 92 92 reg = <0x5b030000 0x10000>; 93 93 clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, 94 - <&sdhc2_lpcg IMX_LPCG_CLK_0>, 95 - <&sdhc2_lpcg IMX_LPCG_CLK_5>; 94 + <&sdhc2_lpcg IMX_LPCG_CLK_5>, 95 + <&sdhc2_lpcg IMX_LPCG_CLK_0>; 96 96 clock-names = "ipg", "ahb", "per"; 97 97 power-domains = <&pd IMX_SC_R_SDHC_2>; 98 98 status = "disabled";
+20 -20
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
··· 28 28 #size-cells = <0>; 29 29 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 30 30 interrupt-parent = <&gic>; 31 - clocks = <&spi0_lpcg 0>, 32 - <&spi0_lpcg 1>; 31 + clocks = <&spi0_lpcg IMX_LPCG_CLK_0>, 32 + <&spi0_lpcg IMX_LPCG_CLK_4>; 33 33 clock-names = "per", "ipg"; 34 34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; 35 35 assigned-clock-rates = <60000000>; ··· 44 44 #size-cells = <0>; 45 45 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 46 46 interrupt-parent = <&gic>; 47 - clocks = <&spi1_lpcg 0>, 48 - <&spi1_lpcg 1>; 47 + clocks = <&spi1_lpcg IMX_LPCG_CLK_0>, 48 + <&spi1_lpcg IMX_LPCG_CLK_4>; 49 49 clock-names = "per", "ipg"; 50 50 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; 51 51 assigned-clock-rates = <60000000>; ··· 60 60 #size-cells = <0>; 61 61 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 62 62 interrupt-parent = <&gic>; 63 - clocks = <&spi2_lpcg 0>, 64 - <&spi2_lpcg 1>; 63 + clocks = <&spi2_lpcg IMX_LPCG_CLK_0>, 64 + <&spi2_lpcg IMX_LPCG_CLK_4>; 65 65 clock-names = "per", "ipg"; 66 66 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; 67 67 assigned-clock-rates = <60000000>; ··· 76 76 #size-cells = <0>; 77 77 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 78 78 interrupt-parent = <&gic>; 79 - clocks = <&spi3_lpcg 0>, 80 - <&spi3_lpcg 1>; 79 + clocks = <&spi3_lpcg IMX_LPCG_CLK_0>, 80 + <&spi3_lpcg IMX_LPCG_CLK_4>; 81 81 clock-names = "per", "ipg"; 82 82 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; 83 83 assigned-clock-rates = <60000000>; ··· 145 145 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; 146 146 reg = <0x5a190000 0x1000>; 147 147 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 148 - clocks = <&adma_pwm_lpcg 1>, 149 - <&adma_pwm_lpcg 0>; 148 + clocks = <&adma_pwm_lpcg IMX_LPCG_CLK_4>, 149 + <&adma_pwm_lpcg IMX_LPCG_CLK_0>; 150 150 clock-names = "ipg", "per"; 151 151 assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; 152 152 assigned-clock-rates = <24000000>; ··· 355 355 reg = <0x5a880000 0x10000>; 356 356 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 357 357 interrupt-parent = <&gic>; 358 - clocks = <&adc0_lpcg 0>, 359 - <&adc0_lpcg 1>; 358 + clocks = <&adc0_lpcg IMX_LPCG_CLK_0>, 359 + <&adc0_lpcg IMX_LPCG_CLK_4>; 360 360 clock-names = "per", "ipg"; 361 361 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; 362 362 assigned-clock-rates = <24000000>; ··· 370 370 reg = <0x5a890000 0x10000>; 371 371 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 372 372 interrupt-parent = <&gic>; 373 - clocks = <&adc1_lpcg 0>, 374 - <&adc1_lpcg 1>; 373 + clocks = <&adc1_lpcg IMX_LPCG_CLK_0>, 374 + <&adc1_lpcg IMX_LPCG_CLK_4>; 375 375 clock-names = "per", "ipg"; 376 376 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; 377 377 assigned-clock-rates = <24000000>; ··· 384 384 reg = <0x5a8d0000 0x10000>; 385 385 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 386 386 interrupt-parent = <&gic>; 387 - clocks = <&can0_lpcg 1>, 388 - <&can0_lpcg 0>; 387 + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 388 + <&can0_lpcg IMX_LPCG_CLK_0>; 389 389 clock-names = "ipg", "per"; 390 390 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 391 391 assigned-clock-rates = <40000000>; ··· 405 405 * CAN1 shares CAN0's clock and to enable CAN0's clock it 406 406 * has to be powered on. 407 407 */ 408 - clocks = <&can0_lpcg 1>, 409 - <&can0_lpcg 0>; 408 + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 409 + <&can0_lpcg IMX_LPCG_CLK_0>; 410 410 clock-names = "ipg", "per"; 411 411 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 412 412 assigned-clock-rates = <40000000>; ··· 426 426 * CAN2 shares CAN0's clock and to enable CAN0's clock it 427 427 * has to be powered on. 428 428 */ 429 - clocks = <&can0_lpcg 1>, 430 - <&can0_lpcg 0>; 429 + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 430 + <&can0_lpcg IMX_LPCG_CLK_0>; 431 431 clock-names = "ipg", "per"; 432 432 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 433 433 assigned-clock-rates = <40000000>;
+8 -8
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
··· 25 25 compatible = "fsl,imx27-pwm"; 26 26 reg = <0x5d000000 0x10000>; 27 27 clock-names = "ipg", "per"; 28 - clocks = <&pwm0_lpcg 4>, 29 - <&pwm0_lpcg 1>; 28 + clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>, 29 + <&pwm0_lpcg IMX_LPCG_CLK_1>; 30 30 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; 31 31 assigned-clock-rates = <24000000>; 32 32 #pwm-cells = <3>; ··· 38 38 compatible = "fsl,imx27-pwm"; 39 39 reg = <0x5d010000 0x10000>; 40 40 clock-names = "ipg", "per"; 41 - clocks = <&pwm1_lpcg 4>, 42 - <&pwm1_lpcg 1>; 41 + clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>, 42 + <&pwm1_lpcg IMX_LPCG_CLK_1>; 43 43 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; 44 44 assigned-clock-rates = <24000000>; 45 45 #pwm-cells = <3>; ··· 51 51 compatible = "fsl,imx27-pwm"; 52 52 reg = <0x5d020000 0x10000>; 53 53 clock-names = "ipg", "per"; 54 - clocks = <&pwm2_lpcg 4>, 55 - <&pwm2_lpcg 1>; 54 + clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>, 55 + <&pwm2_lpcg IMX_LPCG_CLK_1>; 56 56 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; 57 57 assigned-clock-rates = <24000000>; 58 58 #pwm-cells = <3>; ··· 64 64 compatible = "fsl,imx27-pwm"; 65 65 reg = <0x5d030000 0x10000>; 66 66 clock-names = "ipg", "per"; 67 - clocks = <&pwm3_lpcg 4>, 68 - <&pwm3_lpcg 1>; 67 + clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>, 68 + <&pwm3_lpcg IMX_LPCG_CLK_1>; 69 69 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; 70 70 assigned-clock-rates = <24000000>; 71 71 #pwm-cells = <3>;
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
··· 14 14 pinctrl-0 = <&pinctrl_usbcon1>; 15 15 type = "micro"; 16 16 label = "otg"; 17 + vbus-supply = <&reg_usb1_vbus>; 17 18 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 18 19 19 20 port { ··· 184 183 }; 185 184 186 185 &usb3_phy0 { 187 - vbus-supply = <&reg_usb1_vbus>; 188 186 status = "okay"; 189 187 }; 190 188
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
··· 14 14 pinctrl-0 = <&pinctrl_usbcon1>; 15 15 type = "micro"; 16 16 label = "otg"; 17 + vbus-supply = <&reg_usb1_vbus>; 17 18 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 18 19 19 20 port { ··· 203 202 }; 204 203 205 204 &usb3_phy0 { 206 - vbus-supply = <&reg_usb1_vbus>; 207 205 status = "okay"; 208 206 }; 209 207
+4 -4
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
··· 153 153 }; 154 154 155 155 &flexcan2 { 156 - clocks = <&can1_lpcg 1>, 157 - <&can1_lpcg 0>; 156 + clocks = <&can1_lpcg IMX_LPCG_CLK_4>, 157 + <&can1_lpcg IMX_LPCG_CLK_0>; 158 158 assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; 159 159 fsl,clk-source = /bits/ 8 <1>; 160 160 }; 161 161 162 162 &flexcan3 { 163 - clocks = <&can2_lpcg 1>, 164 - <&can2_lpcg 0>; 163 + clocks = <&can2_lpcg IMX_LPCG_CLK_4>, 164 + <&can2_lpcg IMX_LPCG_CLK_0>; 165 165 assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; 166 166 fsl,clk-source = /bits/ 8 <1>; 167 167 };
+46 -26
drivers/cache/sifive_ccache.c
··· 15 15 #include <linux/of_address.h> 16 16 #include <linux/device.h> 17 17 #include <linux/bitfield.h> 18 + #include <linux/platform_device.h> 19 + #include <linux/property.h> 18 20 #include <asm/cacheflush.h> 19 21 #include <asm/cacheinfo.h> 20 22 #include <asm/dma-noncoherent.h> ··· 249 247 return IRQ_HANDLED; 250 248 } 251 249 250 + static int sifive_ccache_probe(struct platform_device *pdev) 251 + { 252 + struct device *dev = &pdev->dev; 253 + unsigned long quirks; 254 + int intr_num, rc; 255 + 256 + quirks = (unsigned long)device_get_match_data(dev); 257 + 258 + intr_num = platform_irq_count(pdev); 259 + if (!intr_num) 260 + return dev_err_probe(dev, -ENODEV, "No interrupts property\n"); 261 + 262 + for (int i = 0; i < intr_num; i++) { 263 + if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR)) 264 + continue; 265 + 266 + g_irq[i] = platform_get_irq(pdev, i); 267 + if (g_irq[i] < 0) 268 + return g_irq[i]; 269 + 270 + rc = devm_request_irq(dev, g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL); 271 + if (rc) 272 + return dev_err_probe(dev, rc, "Could not request IRQ %d\n", g_irq[i]); 273 + } 274 + 275 + return 0; 276 + } 277 + 278 + static struct platform_driver sifive_ccache_driver = { 279 + .probe = sifive_ccache_probe, 280 + .driver = { 281 + .name = "sifive_ccache", 282 + .of_match_table = sifive_ccache_ids, 283 + }, 284 + }; 285 + 252 286 static int __init sifive_ccache_init(void) 253 287 { 254 288 struct device_node *np; 255 289 struct resource res; 256 - int i, rc, intr_num; 257 290 const struct of_device_id *match; 258 291 unsigned long quirks; 292 + int rc; 259 293 260 294 np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match); 261 295 if (!np) ··· 315 277 goto err_unmap; 316 278 } 317 279 318 - intr_num = of_property_count_u32_elems(np, "interrupts"); 319 - if (!intr_num) { 320 - pr_err("No interrupts property\n"); 321 - rc = -ENODEV; 322 - goto err_unmap; 323 - } 324 - 325 - for (i = 0; i < intr_num; i++) { 326 - g_irq[i] = irq_of_parse_and_map(np, i); 327 - 328 - if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR)) 329 - continue; 330 - 331 - rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", 332 - NULL); 333 - if (rc) { 334 - pr_err("Could not request IRQ %d\n", g_irq[i]); 335 - goto err_free_irq; 336 - } 337 - } 338 - of_node_put(np); 339 - 340 280 #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS 341 281 if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) { 342 282 riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE; ··· 331 315 #ifdef CONFIG_DEBUG_FS 332 316 setup_sifive_debug(); 333 317 #endif 318 + 319 + rc = platform_driver_register(&sifive_ccache_driver); 320 + if (rc) 321 + goto err_unmap; 322 + 323 + of_node_put(np); 324 + 334 325 return 0; 335 326 336 - err_free_irq: 337 - while (--i >= 0) 338 - free_irq(g_irq[i], NULL); 339 327 err_unmap: 340 328 iounmap(ccache_base); 341 329 err_node_put:
+1 -1
drivers/firmware/arm_ffa/driver.c
··· 790 790 791 791 part_id = packed_id_list[ids_processed++]; 792 792 793 - if (!ids_count[list]) { /* Global Notification */ 793 + if (ids_count[list] == 1) { /* Global Notification */ 794 794 __do_sched_recv_cb(part_id, 0, false); 795 795 continue; 796 796 }
+1 -1
drivers/firmware/arm_scmi/powercap.c
··· 736 736 ph->hops->fastchannel_init(ph, POWERCAP_DESCRIBE_FASTCHANNEL, 737 737 POWERCAP_PAI_GET, 4, domain, 738 738 &fc[POWERCAP_FC_PAI].get_addr, NULL, 739 - &fc[POWERCAP_PAI_GET].rate_limit); 739 + &fc[POWERCAP_FC_PAI].rate_limit); 740 740 741 741 *p_fc = fc; 742 742 }
+6 -1
drivers/firmware/arm_scmi/raw_mode.c
··· 921 921 rd->raw = raw; 922 922 filp->private_data = rd; 923 923 924 - return 0; 924 + return nonseekable_open(inode, filp); 925 925 } 926 926 927 927 static int scmi_dbg_raw_mode_release(struct inode *inode, struct file *filp) ··· 950 950 .open = scmi_dbg_raw_mode_open, 951 951 .release = scmi_dbg_raw_mode_release, 952 952 .write = scmi_dbg_raw_mode_reset_write, 953 + .llseek = no_llseek, 953 954 .owner = THIS_MODULE, 954 955 }; 955 956 ··· 960 959 .read = scmi_dbg_raw_mode_message_read, 961 960 .write = scmi_dbg_raw_mode_message_write, 962 961 .poll = scmi_dbg_raw_mode_message_poll, 962 + .llseek = no_llseek, 963 963 .owner = THIS_MODULE, 964 964 }; 965 965 ··· 977 975 .read = scmi_dbg_raw_mode_message_read, 978 976 .write = scmi_dbg_raw_mode_message_async_write, 979 977 .poll = scmi_dbg_raw_mode_message_poll, 978 + .llseek = no_llseek, 980 979 .owner = THIS_MODULE, 981 980 }; 982 981 ··· 1001 998 .release = scmi_dbg_raw_mode_release, 1002 999 .read = scmi_test_dbg_raw_mode_notif_read, 1003 1000 .poll = scmi_test_dbg_raw_mode_notif_poll, 1001 + .llseek = no_llseek, 1004 1002 .owner = THIS_MODULE, 1005 1003 }; 1006 1004 ··· 1025 1021 .release = scmi_dbg_raw_mode_release, 1026 1022 .read = scmi_test_dbg_raw_mode_errors_read, 1027 1023 .poll = scmi_test_dbg_raw_mode_errors_poll, 1024 + .llseek = no_llseek, 1028 1025 .owner = THIS_MODULE, 1029 1026 }; 1030 1027
+31 -17
drivers/mmc/host/omap.c
··· 1114 1114 1115 1115 host = slot->host; 1116 1116 1117 - if (slot->vsd) 1118 - gpiod_set_value(slot->vsd, power_on); 1119 - if (slot->vio) 1120 - gpiod_set_value(slot->vio, power_on); 1117 + if (power_on) { 1118 + if (slot->vsd) { 1119 + gpiod_set_value(slot->vsd, power_on); 1120 + msleep(1); 1121 + } 1122 + if (slot->vio) { 1123 + gpiod_set_value(slot->vio, power_on); 1124 + msleep(1); 1125 + } 1126 + } else { 1127 + if (slot->vio) { 1128 + gpiod_set_value(slot->vio, power_on); 1129 + msleep(50); 1130 + } 1131 + if (slot->vsd) { 1132 + gpiod_set_value(slot->vsd, power_on); 1133 + msleep(50); 1134 + } 1135 + } 1121 1136 1122 1137 if (slot->pdata->set_power != NULL) 1123 1138 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on, ··· 1269 1254 slot->pdata = &host->pdata->slots[id]; 1270 1255 1271 1256 /* Check for some optional GPIO controls */ 1272 - slot->vsd = gpiod_get_index_optional(host->dev, "vsd", 1273 - id, GPIOD_OUT_LOW); 1257 + slot->vsd = devm_gpiod_get_index_optional(host->dev, "vsd", 1258 + id, GPIOD_OUT_LOW); 1274 1259 if (IS_ERR(slot->vsd)) 1275 1260 return dev_err_probe(host->dev, PTR_ERR(slot->vsd), 1276 1261 "error looking up VSD GPIO\n"); 1277 - slot->vio = gpiod_get_index_optional(host->dev, "vio", 1278 - id, GPIOD_OUT_LOW); 1262 + slot->vio = devm_gpiod_get_index_optional(host->dev, "vio", 1263 + id, GPIOD_OUT_LOW); 1279 1264 if (IS_ERR(slot->vio)) 1280 1265 return dev_err_probe(host->dev, PTR_ERR(slot->vio), 1281 1266 "error looking up VIO GPIO\n"); 1282 - slot->cover = gpiod_get_index_optional(host->dev, "cover", 1283 - id, GPIOD_IN); 1267 + slot->cover = devm_gpiod_get_index_optional(host->dev, "cover", 1268 + id, GPIOD_IN); 1284 1269 if (IS_ERR(slot->cover)) 1285 1270 return dev_err_probe(host->dev, PTR_ERR(slot->cover), 1286 1271 "error looking up cover switch GPIO\n"); ··· 1394 1379 if (IS_ERR(host->virt_base)) 1395 1380 return PTR_ERR(host->virt_base); 1396 1381 1397 - host->slot_switch = gpiod_get_optional(host->dev, "switch", 1398 - GPIOD_OUT_LOW); 1399 - if (IS_ERR(host->slot_switch)) 1400 - return dev_err_probe(host->dev, PTR_ERR(host->slot_switch), 1401 - "error looking up slot switch GPIO\n"); 1402 - 1403 - 1404 1382 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); 1405 1383 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); 1406 1384 ··· 1411 1403 host->features = host->pdata->slots[0].features; 1412 1404 host->dev = &pdev->dev; 1413 1405 platform_set_drvdata(pdev, host); 1406 + 1407 + host->slot_switch = devm_gpiod_get_optional(host->dev, "switch", 1408 + GPIOD_OUT_LOW); 1409 + if (IS_ERR(host->slot_switch)) 1410 + return dev_err_probe(host->dev, PTR_ERR(host->slot_switch), 1411 + "error looking up slot switch GPIO\n"); 1414 1412 1415 1413 host->id = pdev->id; 1416 1414 host->irq = irq;