Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'iommu-fixes-v4.8-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU fixes from Joerg Roedel:
"Fixes from Will Deacon:
- fix a couple of thinkos in the CMDQ error handling and
short-descriptor page table code that have been there since day one
- disable stalling faults, since they may result in hardware deadlock
- fix an accidental BUG() when passing disable_bypass=1 on the
cmdline"
* tag 'iommu-fixes-v4.8-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/arm-smmu: Don't BUG() if we find aborting STEs with disable_bypass
iommu/arm-smmu: Disable stalling faults for all endpoints
iommu/arm-smmu: Fix CMDQ error handling
iommu/io-pgtable-arm-v7s: Fix attributes when splitting blocks
+15
-30
+5
-2
drivers/iommu/arm-smmu-v3.c
+5
-2
drivers/iommu/arm-smmu-v3.c
···
879
879
* We may have concurrent producers, so we need to be careful
880
880
* not to touch any of the shadow cmdq state.
881
881
*/
882
-
queue_read(cmd, Q_ENT(q, idx), q->ent_dwords);
882
+
queue_read(cmd, Q_ENT(q, cons), q->ent_dwords);
883
883
dev_err(smmu->dev, "skipping command in error state:\n");
884
884
for (i = 0; i < ARRAY_SIZE(cmd); ++i)
885
885
dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
···
890
890
return;
891
891
}
892
892
893
-
queue_write(cmd, Q_ENT(q, idx), q->ent_dwords);
893
+
queue_write(Q_ENT(q, cons), cmd, q->ent_dwords);
894
894
}
895
895
896
896
static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
···
1034
1034
case STRTAB_STE_0_CFG_S2_TRANS:
1035
1035
ste_live = true;
1036
1036
break;
1037
+
case STRTAB_STE_0_CFG_ABORT:
1038
+
if (disable_bypass)
1039
+
break;
1037
1040
default:
1038
1041
BUG(); /* STE corruption */
1039
1042
}
+7
-27
drivers/iommu/arm-smmu.c
+7
-27
drivers/iommu/arm-smmu.c
···
686
686
687
687
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
688
688
{
689
-
int flags, ret;
690
-
u32 fsr, fsynr, resume;
689
+
u32 fsr, fsynr;
691
690
unsigned long iova;
692
691
struct iommu_domain *domain = dev;
693
692
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
···
700
701
if (!(fsr & FSR_FAULT))
701
702
return IRQ_NONE;
702
703
703
-
if (fsr & FSR_IGN)
704
-
dev_err_ratelimited(smmu->dev,
705
-
"Unexpected context fault (fsr 0x%x)\n",
706
-
fsr);
707
-
708
704
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
709
-
flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
710
-
711
705
iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
712
-
if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
713
-
ret = IRQ_HANDLED;
714
-
resume = RESUME_RETRY;
715
-
} else {
716
-
dev_err_ratelimited(smmu->dev,
717
-
"Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
718
-
iova, fsynr, cfg->cbndx);
719
-
ret = IRQ_NONE;
720
-
resume = RESUME_TERMINATE;
721
-
}
722
706
723
-
/* Clear the faulting FSR */
707
+
dev_err_ratelimited(smmu->dev,
708
+
"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
709
+
fsr, iova, fsynr, cfg->cbndx);
710
+
724
711
writel(fsr, cb_base + ARM_SMMU_CB_FSR);
725
-
726
-
/* Retry or terminate any stalled transactions */
727
-
if (fsr & FSR_SS)
728
-
writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
729
-
730
-
return ret;
712
+
return IRQ_HANDLED;
731
713
}
732
714
733
715
static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
···
817
837
}
818
838
819
839
/* SCTLR */
820
-
reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
840
+
reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
821
841
if (stage1)
822
842
reg |= SCTLR_S1_ASIDPNE;
823
843
#ifdef __BIG_ENDIAN
+3
-1
drivers/iommu/io-pgtable-arm-v7s.c
+3
-1
drivers/iommu/io-pgtable-arm-v7s.c
···
286
286
int prot = IOMMU_READ;
287
287
arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
288
288
289
-
if (attr & ARM_V7S_PTE_AP_RDONLY)
289
+
if (!(attr & ARM_V7S_PTE_AP_RDONLY))
290
290
prot |= IOMMU_WRITE;
291
291
if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
292
292
prot |= IOMMU_MMIO;
293
293
else if (pte & ARM_V7S_ATTR_C)
294
294
prot |= IOMMU_CACHE;
295
+
if (pte & ARM_V7S_ATTR_XN(lvl))
296
+
prot |= IOMMU_NOEXEC;
295
297
296
298
return prot;
297
299
}