tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
"Three fixes, one for the clk framework and two for clk drivers:

- Avoid an oops in possible_parent_show() by checking for no parent
properly when a DT index based lookup is used

- Handle errors returned from divider_ro_round_rate() in
clk_stm32_composite_determine_rate()

- Fix clk_ops::determine_rate() implementation of socfpga's
gateclk_ops that was ruining uart output because the divider
was forgotten about"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate()
clk: Sanitize possible_parent_show to Handle Return Value of of_clk_get_parent_name
clk: socfpga: gate: Account for the divider in determine_rate

Linus Torvalds 67d4c879 d1b0949f

+36 -14
+12 -9
drivers/clk/clk.c
··· 3416 3416 unsigned int i, char terminator) 3417 3417 { 3418 3418 struct clk_core *parent; 3419 + const char *name = NULL; 3419 3420 3420 3421 /* 3421 3422 * Go through the following options to fetch a parent's name. ··· 3431 3430 * registered (yet). 3432 3431 */ 3433 3432 parent = clk_core_get_parent_by_index(core, i); 3434 - if (parent) 3433 + if (parent) { 3435 3434 seq_puts(s, parent->name); 3436 - else if (core->parents[i].name) 3435 + } else if (core->parents[i].name) { 3437 3436 seq_puts(s, core->parents[i].name); 3438 - else if (core->parents[i].fw_name) 3437 + } else if (core->parents[i].fw_name) { 3439 3438 seq_printf(s, "<%s>(fw)", core->parents[i].fw_name); 3440 - else if (core->parents[i].index >= 0) 3441 - seq_puts(s, 3442 - of_clk_get_parent_name(core->of_node, 3443 - core->parents[i].index)); 3444 - else 3445 - seq_puts(s, "(missing)"); 3439 + } else { 3440 + if (core->parents[i].index >= 0) 3441 + name = of_clk_get_parent_name(core->of_node, core->parents[i].index); 3442 + if (!name) 3443 + name = "(missing)"; 3444 + 3445 + seq_puts(s, name); 3446 + } 3446 3447 3447 3448 seq_putc(s, terminator); 3448 3449 }
+23 -4
drivers/clk/socfpga/clk-gate.c
··· 87 87 return 0; 88 88 } 89 89 90 - static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, 91 - unsigned long parent_rate) 90 + static u32 socfpga_clk_get_div(struct socfpga_gate_clk *socfpgaclk) 92 91 { 93 - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 94 92 u32 div = 1, val; 95 93 96 94 if (socfpgaclk->fixed_div) ··· 103 105 div = (1 << val); 104 106 } 105 107 108 + return div; 109 + } 110 + 111 + static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, 112 + unsigned long parent_rate) 113 + { 114 + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 115 + u32 div = socfpga_clk_get_div(socfpgaclk); 116 + 106 117 return parent_rate / div; 118 + } 119 + 120 + 121 + static int socfpga_clk_determine_rate(struct clk_hw *hwclk, 122 + struct clk_rate_request *req) 123 + { 124 + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 125 + u32 div = socfpga_clk_get_div(socfpgaclk); 126 + 127 + req->rate = req->best_parent_rate / div; 128 + 129 + return 0; 107 130 } 108 131 109 132 static struct clk_ops gateclk_ops = { 110 133 .recalc_rate = socfpga_clk_recalc_rate, 111 - .determine_rate = clk_hw_determine_rate_no_reparent, 134 + .determine_rate = socfpga_clk_determine_rate, 112 135 .get_parent = socfpga_clk_get_parent, 113 136 .set_parent = socfpga_clk_set_parent, 114 137 };
+1 -1
drivers/clk/stm32/clk-stm32-core.c
··· 431 431 { 432 432 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw); 433 433 const struct stm32_div_cfg *divider; 434 - unsigned long rate; 434 + long rate; 435 435 436 436 if (composite->div_id == NO_STM32_DIV) 437 437 return 0;