tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'riscv-for-linus-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:
"A handful of build fixes, all found by Huawei's autobuilder.

None of these patches should have any functional impact on kernels
that build, and they're mostly related to various features
intermingling with !MMU.

While some of these might be better hoisted to generic code, it seems
better to have the simple fixes in the meanwhile.

As far as I know these are the only outstanding patches for 5.7"

* tag 'riscv-for-linus-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'
riscv: pgtable: Fix __kernel_map_pages build error if NOMMU
riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU
riscv: Disable ARCH_HAS_DEBUG_VIRTUAL if NOMMU
riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if NOMMU
riscv: stacktrace: Fix undefined reference to `walk_stackframe'
riscv: Fix unmet direct dependencies built based on SOC_VIRT
riscv: perf: RISCV_BASE_PMU should be independent
riscv: perf_event: Make some funciton static

Linus Torvalds 67e45621 01d8a748

+25 -21
+2 -1
arch/riscv/Kconfig
··· 54 54 select GENERIC_ARCH_TOPOLOGY if SMP 55 55 select ARCH_HAS_PTE_SPECIAL 56 56 select ARCH_HAS_MMIOWB 57 - select ARCH_HAS_DEBUG_VIRTUAL 57 + select ARCH_HAS_DEBUG_VIRTUAL if MMU 58 58 select HAVE_EBPF_JIT if MMU 59 59 select EDAC_SUPPORT 60 60 select ARCH_HAS_GIGANTIC_PAGE ··· 136 136 def_bool y 137 137 138 138 config SYS_SUPPORTS_HUGETLBFS 139 + depends on MMU 139 140 def_bool y 140 141 141 142 config STACKTRACE_SUPPORT
+9 -8
arch/riscv/Kconfig.socs
··· 11 11 This enables support for SiFive SoC platform hardware. 12 12 13 13 config SOC_VIRT 14 - bool "QEMU Virt Machine" 15 - select POWER_RESET_SYSCON 16 - select POWER_RESET_SYSCON_POWEROFF 17 - select GOLDFISH 18 - select RTC_DRV_GOLDFISH 19 - select SIFIVE_PLIC 20 - help 21 - This enables support for QEMU Virt Machine. 14 + bool "QEMU Virt Machine" 15 + select POWER_RESET 16 + select POWER_RESET_SYSCON 17 + select POWER_RESET_SYSCON_POWEROFF 18 + select GOLDFISH 19 + select RTC_DRV_GOLDFISH if RTC_CLASS 20 + select SIFIVE_PLIC 21 + help 22 + This enables support for QEMU Virt Machine. 22 23 23 24 config SOC_KENDRYTE 24 25 bool "Kendryte K210 SoC"
+2
arch/riscv/include/asm/mmio.h
··· 16 16 17 17 #ifndef CONFIG_MMU 18 18 #define pgprot_noncached(x) (x) 19 + #define pgprot_writecombine(x) (x) 20 + #define pgprot_device(x) (x) 19 21 #endif /* CONFIG_MMU */ 20 22 21 23 /* Generic IO read/write. These perform native-endian accesses. */
+1
arch/riscv/include/asm/mmiowb.h
··· 9 9 */ 10 10 #define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); 11 11 12 + #include <linux/smp.h> 12 13 #include <asm-generic/mmiowb.h> 13 14 14 15 #endif /* _ASM_RISCV_MMIOWB_H */
+2 -6
arch/riscv/include/asm/perf_event.h
··· 12 12 #include <linux/ptrace.h> 13 13 #include <linux/interrupt.h> 14 14 15 + #ifdef CONFIG_RISCV_BASE_PMU 15 16 #define RISCV_BASE_COUNTERS 2 16 17 17 18 /* 18 19 * The RISCV_MAX_COUNTERS parameter should be specified. 19 20 */ 20 21 21 - #ifdef CONFIG_RISCV_BASE_PMU 22 22 #define RISCV_MAX_COUNTERS 2 23 - #endif 24 - 25 - #ifndef RISCV_MAX_COUNTERS 26 - #error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." 27 - #endif 28 23 29 24 /* 30 25 * These are the indexes of bits in counteren register *minus* 1, ··· 77 82 int irq; 78 83 }; 79 84 85 + #endif 80 86 #ifdef CONFIG_PERF_EVENTS 81 87 #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs 82 88 #endif
+3
arch/riscv/include/asm/pgtable.h
··· 470 470 471 471 #else /* CONFIG_MMU */ 472 472 473 + #define PAGE_SHARED __pgprot(0) 473 474 #define PAGE_KERNEL __pgprot(0) 474 475 #define swapper_pg_dir NULL 475 476 #define VMALLOC_START 0 476 477 477 478 #define TASK_SIZE 0xffffffffUL 479 + 480 + static inline void __kernel_map_pages(struct page *page, int numpages, int enable) {} 478 481 479 482 #endif /* !CONFIG_MMU */ 480 483
+1 -1
arch/riscv/kernel/Makefile
··· 43 43 obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o 44 44 obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o 45 45 46 - obj-$(CONFIG_PERF_EVENTS) += perf_event.o 46 + obj-$(CONFIG_RISCV_BASE_PMU) += perf_event.o 47 47 obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o 48 48 obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o 49 49 obj-$(CONFIG_RISCV_SBI) += sbi.o
+4 -4
arch/riscv/kernel/perf_event.c
··· 147 147 return riscv_pmu->hw_events[config]; 148 148 } 149 149 150 - int riscv_map_cache_decode(u64 config, unsigned int *type, 150 + static int riscv_map_cache_decode(u64 config, unsigned int *type, 151 151 unsigned int *op, unsigned int *result) 152 152 { 153 153 return -ENOENT; ··· 342 342 343 343 static DEFINE_MUTEX(pmc_reserve_mutex); 344 344 345 - irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev) 345 + static irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev) 346 346 { 347 347 return IRQ_NONE; 348 348 } ··· 361 361 return err; 362 362 } 363 363 364 - void release_pmc_hardware(void) 364 + static void release_pmc_hardware(void) 365 365 { 366 366 mutex_lock(&pmc_reserve_mutex); 367 367 if (riscv_pmu->irq >= 0) ··· 464 464 { /* sentinel value */ } 465 465 }; 466 466 467 - int __init init_hw_perf_events(void) 467 + static int __init init_hw_perf_events(void) 468 468 { 469 469 struct device_node *node = of_find_node_by_type(NULL, "pmu"); 470 470 const struct of_device_id *of_id;
+1 -1
arch/riscv/kernel/stacktrace.c
··· 65 65 66 66 #else /* !CONFIG_FRAME_POINTER */ 67 67 68 - static void notrace walk_stackframe(struct task_struct *task, 68 + void notrace walk_stackframe(struct task_struct *task, 69 69 struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg) 70 70 { 71 71 unsigned long sp, pc;