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Merge tag 'drm-intel-next-fixes-2023-06-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

- Allow DC states along with PW2 only for PWB functionality [adlp+] (Imre Deak)
- Fix SSC selection for MPLLA [mtl] (Radhakrishna Sripada)
- Use hw.adjusted mode when calculating io/fast wake times [psr] (Jouni Högander)
- Apply min softlimit correctly [guc/slpc] (Vinay Belgaumkar)
- Assign correct hdcp content type [hdcp] (Suraj Kandpal)
- Add missing forward declarations/includes to display power headers (Imre Deak)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZJ1WpY+GF9NcsWXp@tursulin-desk

+20 -13
+2 -1
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 2435 2435 2436 2436 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2437 2437 XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | 2438 - XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLB, val); 2438 + XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA | 2439 + XELPDP_SSC_ENABLE_PLLB, val); 2439 2440 } 2440 2441 2441 2442 static u32 intel_cx0_get_powerdown_update(u8 lane_mask)
+4
drivers/gpu/drm/i915/display/intel_display_power.h
··· 6 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 7 #define __INTEL_DISPLAY_POWER_H__ 8 8 9 + #include <linux/mutex.h> 10 + #include <linux/workqueue.h> 11 + 9 12 #include "intel_wakeref.h" 10 13 11 14 enum aux_ch; ··· 19 16 struct drm_i915_private; 20 17 struct i915_power_well; 21 18 struct intel_encoder; 19 + struct seq_file; 22 20 23 21 /* 24 22 * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
+8 -8
drivers/gpu/drm/i915/display/intel_display_power_map.c
··· 1252 1252 POWER_DOMAIN_INIT); 1253 1253 1254 1254 #define XELPD_DC_OFF_PORT_POWER_DOMAINS \ 1255 + POWER_DOMAIN_PORT_DDI_LANES_C, \ 1256 + POWER_DOMAIN_PORT_DDI_LANES_D, \ 1257 + POWER_DOMAIN_PORT_DDI_LANES_E, \ 1255 1258 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1256 1259 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1257 1260 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 1258 1261 POWER_DOMAIN_PORT_DDI_LANES_TC4, \ 1262 + POWER_DOMAIN_VGA, \ 1263 + POWER_DOMAIN_AUDIO_PLAYBACK, \ 1264 + POWER_DOMAIN_AUX_IO_C, \ 1265 + POWER_DOMAIN_AUX_IO_D, \ 1266 + POWER_DOMAIN_AUX_IO_E, \ 1259 1267 POWER_DOMAIN_AUX_C, \ 1260 1268 POWER_DOMAIN_AUX_D, \ 1261 1269 POWER_DOMAIN_AUX_E, \ ··· 1280 1272 XELPD_PW_B_POWER_DOMAINS, \ 1281 1273 XELPD_PW_C_POWER_DOMAINS, \ 1282 1274 XELPD_PW_D_POWER_DOMAINS, \ 1283 - POWER_DOMAIN_PORT_DDI_LANES_C, \ 1284 - POWER_DOMAIN_PORT_DDI_LANES_D, \ 1285 - POWER_DOMAIN_PORT_DDI_LANES_E, \ 1286 - POWER_DOMAIN_VGA, \ 1287 - POWER_DOMAIN_AUDIO_PLAYBACK, \ 1288 - POWER_DOMAIN_AUX_IO_C, \ 1289 - POWER_DOMAIN_AUX_IO_D, \ 1290 - POWER_DOMAIN_AUX_IO_E, \ 1291 1275 XELPD_DC_OFF_PORT_POWER_DOMAINS 1292 1276 1293 1277 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
+2
drivers/gpu/drm/i915/display/intel_display_power_well.h
··· 12 12 13 13 struct drm_i915_private; 14 14 struct i915_power_well; 15 + struct i915_power_well_ops; 16 + struct intel_encoder; 15 17 16 18 #define for_each_power_well(__dev_priv, __power_well) \ 17 19 for ((__power_well) = (__dev_priv)->display.power.domains.power_wells; \
+1 -1
drivers/gpu/drm/i915/display/intel_hdcp.c
··· 2358 2358 mutex_lock(&dig_port->hdcp_mutex); 2359 2359 drm_WARN_ON(&i915->drm, 2360 2360 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2361 - hdcp->content_type = (u8)conn_state->content_type; 2361 + hdcp->content_type = (u8)conn_state->hdcp_content_type; 2362 2362 2363 2363 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2364 2364 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+2 -2
drivers/gpu/drm/i915/display/intel_psr.c
··· 933 933 } 934 934 935 935 io_wake_lines = intel_usecs_to_scanlines( 936 - &crtc_state->uapi.adjusted_mode, io_wake_time); 936 + &crtc_state->hw.adjusted_mode, io_wake_time); 937 937 fast_wake_lines = intel_usecs_to_scanlines( 938 - &crtc_state->uapi.adjusted_mode, fast_wake_time); 938 + &crtc_state->hw.adjusted_mode, fast_wake_time); 939 939 940 940 if (io_wake_lines > max_wake_lines || 941 941 fast_wake_lines > max_wake_lines)
+1 -1
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
··· 606 606 if (unlikely(ret)) 607 607 return ret; 608 608 slpc_to_gt(slpc)->defaults.min_freq = slpc->min_freq_softlimit; 609 - } else if (slpc->min_freq_softlimit != slpc->min_freq) { 609 + } else { 610 610 return intel_guc_slpc_set_min_freq(slpc, 611 611 slpc->min_freq_softlimit); 612 612 }