Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mips_6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- Added support for EcoNet platform
- Added support for parallel CPU bring up on EyeQ
- Other cleanups and fixes
* tag 'mips_6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (23 commits)
MIPS: loongson2ef: lemote-2f: add missing function prototypes
MIPS: loongson2ef: cs5536: add missing function prototypes
MIPS: SMP: Move the AP sync point before the calibration delay
mips: econet: Fix incorrect Kconfig dependencies
MAINTAINERS: Add entry for newly added EcoNet platform.
mips: dts: Add EcoNet DTS with EN751221 and SmartFiber XP8421-B board
dt-bindings: vendor-prefixes: Add SmartFiber
mips: Add EcoNet MIPS platform support
dt-bindings: mips: Add EcoNet platform binding
MIPS: bcm63xx: nvram: avoid inefficient use of crc32_le_combine()
mips: dts: pic32: pic32mzda: Rename the sdhci nodename to match with common mmc-controller binding
MIPS: SMP: Move the AP sync point before the non-parallel aware functions
MIPS: Replace strcpy() with strscpy() in vpe_elfload()
MIPS: BCM63XX: Replace strcpy() with strscpy() in board_prom_init()
mips: ptrace: Improve code formatting and indentation
MIPS: SMP: Implement parallel CPU bring up for EyeQ
mips: Add -std= flag specified in KBUILD_CFLAGS to vdso CFLAGS
MIPS: Loongson64: Add missing '#interrupt-cells' for loongson64c_ls7a
mips: dts: realtek: Add MDIO controller
MIPS: txx9: gpio: use new line value setter callbacks
...
+434
-43
+26
Documentation/devicetree/bindings/mips/econet.yaml
+26
Documentation/devicetree/bindings/mips/econet.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mips/econet.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: EcoNet MIPS SoCs
8
+
9
+
maintainers:
10
+
- Caleb James DeLisle <cjd@cjdns.fr>
11
+
12
+
properties:
13
+
$nodename:
14
+
const: '/'
15
+
16
+
compatible:
17
+
oneOf:
18
+
- description: Boards with EcoNet EN751221 family SoC
19
+
items:
20
+
- enum:
21
+
- smartfiber,xp8421-b
22
+
- const: econet,en751221
23
+
24
+
additionalProperties: true
25
+
26
+
...
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+12
MAINTAINERS
+12
MAINTAINERS
···
8477
8477
Q: http://patchwork.linuxtv.org/project/linux-media/list/
8478
8478
F: drivers/media/dvb-frontends/ec100*
8479
8479
8480
+
ECONET MIPS PLATFORM
8481
+
M: Caleb James DeLisle <cjd@cjdns.fr>
8482
+
L: linux-mips@vger.kernel.org
8483
+
S: Maintained
8484
+
F: Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
8485
+
F: Documentation/devicetree/bindings/mips/econet.yaml
8486
+
F: Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
8487
+
F: arch/mips/boot/dts/econet/
8488
+
F: arch/mips/econet/
8489
+
F: drivers/clocksource/timer-econet-en751221.c
8490
+
F: drivers/irqchip/irq-econet-en751221.c
8491
+
8480
8492
ECRYPT FILE SYSTEM
8481
8493
M: Tyler Hicks <code@tyhicks.com>
8482
8494
L: ecryptfs@vger.kernel.org
+1
arch/mips/Kbuild.platforms
+1
arch/mips/Kbuild.platforms
···
11
11
platform-$(CONFIG_EYEQ) += mobileye/
12
12
platform-$(CONFIG_MIPS_COBALT) += cobalt/
13
13
platform-$(CONFIG_MACH_DECSTATION) += dec/
14
+
platform-$(CONFIG_ECONET) += econet/
14
15
platform-$(CONFIG_MIPS_GENERIC) += generic/
15
16
platform-$(CONFIG_MACH_JAZZ) += jazz/
16
17
platform-$(CONFIG_LANTIQ) += lantiq/
+28
arch/mips/Kconfig
+28
arch/mips/Kconfig
···
391
391
392
392
otherwise choose R3000.
393
393
394
+
config ECONET
395
+
bool "EcoNet MIPS family"
396
+
select BOOT_RAW
397
+
select CPU_BIG_ENDIAN
398
+
select DEBUG_ZBOOT if DEBUG_KERNEL
399
+
select EARLY_PRINTK_8250
400
+
select ECONET_EN751221_TIMER
401
+
select SERIAL_8250
402
+
select SERIAL_OF_PLATFORM
403
+
select SYS_SUPPORTS_BIG_ENDIAN
404
+
select SYS_HAS_CPU_MIPS32_R1
405
+
select SYS_HAS_CPU_MIPS32_R2
406
+
select SYS_HAS_EARLY_PRINTK
407
+
select SYS_SUPPORTS_32BIT_KERNEL
408
+
select SYS_SUPPORTS_MIPS16
409
+
select SYS_SUPPORTS_ZBOOT_UART16550
410
+
select USE_GENERIC_EARLY_PRINTK_8250
411
+
select USE_OF
412
+
help
413
+
EcoNet EN75xx MIPS devices are big endian MIPS machines used
414
+
in XPON (fiber) and DSL applications. They have SPI, PCI, USB,
415
+
GPIO, and Ethernet, with optional XPON, DSL, and VoIP DSP cores.
416
+
Don't confuse these with the Airoha ARM devices sometimes referred
417
+
to as "EcoNet", this family is for MIPS based devices only.
418
+
394
419
config MACH_JAZZ
395
420
bool "Jazz family of machines"
396
421
select ARC_MEMORY
···
642
617
select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
643
618
select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
644
619
select USE_OF
620
+
select HOTPLUG_PARALLEL if SMP
645
621
help
646
622
Select this to build a kernel supporting EyeQ SoC from Mobileye.
647
623
···
1046
1020
source "arch/mips/bcm47xx/Kconfig"
1047
1021
source "arch/mips/bcm63xx/Kconfig"
1048
1022
source "arch/mips/bmips/Kconfig"
1023
+
source "arch/mips/econet/Kconfig"
1049
1024
source "arch/mips/generic/Kconfig"
1050
1025
source "arch/mips/ingenic/Kconfig"
1051
1026
source "arch/mips/jazz/Kconfig"
···
2314
2287
select MIPS_CM
2315
2288
select MIPS_CPS_PM if HOTPLUG_CPU
2316
2289
select SMP
2290
+
select HOTPLUG_SMT if HOTPLUG_PARALLEL
2317
2291
select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
2318
2292
select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
2319
2293
select SYS_SUPPORTS_HOTPLUG_CPU
+4
-2
arch/mips/alchemy/common/gpiolib.c
+4
-2
arch/mips/alchemy/common/gpiolib.c
···
119
119
return !!au1300_gpio_get_value(off + AU1300_GPIO_BASE);
120
120
}
121
121
122
-
static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
122
+
static int alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
123
123
{
124
124
au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
125
+
126
+
return 0;
125
127
}
126
128
127
129
static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
···
147
145
.direction_input = alchemy_gpic_dir_input,
148
146
.direction_output = alchemy_gpic_dir_output,
149
147
.get = alchemy_gpic_get,
150
-
.set = alchemy_gpic_set,
148
+
.set_rv = alchemy_gpic_set,
151
149
.to_irq = alchemy_gpic_gpio_to_irq,
152
150
.base = AU1300_GPIO_BASE,
153
151
.ngpio = AU1300_GPIO_NUM,
+1
-1
arch/mips/bcm63xx/boards/board_bcm963xx.c
+1
-1
arch/mips/bcm63xx/boards/board_bcm963xx.c
+4
-3
arch/mips/bcm63xx/gpio.c
+4
-3
arch/mips/bcm63xx/gpio.c
···
35
35
static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
36
36
static u32 gpio_out_low, gpio_out_high;
37
37
38
-
static void bcm63xx_gpio_set(struct gpio_chip *chip,
39
-
unsigned gpio, int val)
38
+
static int bcm63xx_gpio_set(struct gpio_chip *chip, unsigned int gpio, int val)
40
39
{
41
40
u32 reg;
42
41
u32 mask;
···
61
62
*v &= ~mask;
62
63
bcm_gpio_writel(*v, reg);
63
64
spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
65
+
66
+
return 0;
64
67
}
65
68
66
69
static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
···
131
130
.direction_input = bcm63xx_gpio_direction_input,
132
131
.direction_output = bcm63xx_gpio_direction_output,
133
132
.get = bcm63xx_gpio_get,
134
-
.set = bcm63xx_gpio_set,
133
+
.set_rv = bcm63xx_gpio_set,
135
134
.base = 0,
136
135
};
137
136
+5
arch/mips/boot/compressed/uart-16550.c
+5
arch/mips/boot/compressed/uart-16550.c
···
20
20
#define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
21
21
#endif
22
22
23
+
#ifdef CONFIG_ECONET
24
+
#define EN75_UART_BASE 0x1fbf0003
25
+
#define PORT(offset) (CKSEG1ADDR(EN75_UART_BASE) + (4 * (offset)))
26
+
#endif
27
+
23
28
#ifndef IOTYPE
24
29
#define IOTYPE char
25
30
#endif
+1
arch/mips/boot/dts/Makefile
+1
arch/mips/boot/dts/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
subdir-$(CONFIG_BMIPS_GENERIC) += brcm
3
3
subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon
4
+
subdir-$(CONFIG_ECONET) += econet
4
5
subdir-$(CONFIG_EYEQ) += mobileye
5
6
subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += img
6
7
subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
+2
arch/mips/boot/dts/econet/Makefile
+2
arch/mips/boot/dts/econet/Makefile
+67
arch/mips/boot/dts/econet/en751221.dtsi
+67
arch/mips/boot/dts/econet/en751221.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/dts-v1/;
3
+
4
+
/ {
5
+
compatible = "econet,en751221";
6
+
#address-cells = <1>;
7
+
#size-cells = <1>;
8
+
9
+
hpt_clock: clock {
10
+
compatible = "fixed-clock";
11
+
#clock-cells = <0>;
12
+
clock-frequency = <200000000>; /* 200 MHz */
13
+
};
14
+
15
+
cpus: cpus {
16
+
#address-cells = <1>;
17
+
#size-cells = <0>;
18
+
19
+
cpu@0 {
20
+
device_type = "cpu";
21
+
compatible = "mips,mips24KEc";
22
+
reg = <0>;
23
+
};
24
+
};
25
+
26
+
cpuintc: interrupt-controller {
27
+
compatible = "mti,cpu-interrupt-controller";
28
+
interrupt-controller;
29
+
#address-cells = <0>;
30
+
#interrupt-cells = <1>;
31
+
};
32
+
33
+
intc: interrupt-controller@1fb40000 {
34
+
compatible = "econet,en751221-intc";
35
+
reg = <0x1fb40000 0x100>;
36
+
interrupt-parent = <&cpuintc>;
37
+
interrupts = <2>;
38
+
39
+
interrupt-controller;
40
+
#interrupt-cells = <1>;
41
+
econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
42
+
};
43
+
44
+
uart: serial@1fbf0000 {
45
+
compatible = "ns16550";
46
+
reg = <0x1fbf0000 0x30>;
47
+
reg-io-width = <4>;
48
+
reg-shift = <2>;
49
+
interrupt-parent = <&intc>;
50
+
interrupts = <0>;
51
+
/*
52
+
* Conversion of baud rate to clock frequency requires a
53
+
* computation that is not in the ns16550 driver, so this
54
+
* uart is fixed at 115200 baud.
55
+
*/
56
+
clock-frequency = <1843200>;
57
+
};
58
+
59
+
timer_hpt: timer@1fbf0400 {
60
+
compatible = "econet,en751221-timer";
61
+
reg = <0x1fbf0400 0x100>;
62
+
63
+
interrupt-parent = <&intc>;
64
+
interrupts = <30>;
65
+
clocks = <&hpt_clock>;
66
+
};
67
+
};
+19
arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
+19
arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/dts-v1/;
3
+
4
+
#include "en751221.dtsi"
5
+
6
+
/ {
7
+
model = "SmartFiber XP8421-B";
8
+
compatible = "smartfiber,xp8421-b", "econet,en751221";
9
+
10
+
memory@0 {
11
+
device_type = "memory";
12
+
reg = <0x00000000 0x1c000000>;
13
+
};
14
+
15
+
chosen {
16
+
stdout-path = "/serial@1fbf0000:115200";
17
+
linux,usable-memory-range = <0x00020000 0x1bfe0000>;
18
+
};
19
+
};
+1
arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
+1
arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
+1
-1
arch/mips/boot/dts/pic32/pic32mzda.dtsi
+1
-1
arch/mips/boot/dts/pic32/pic32mzda.dtsi
+33
arch/mips/boot/dts/realtek/rtl930x.dtsi
+33
arch/mips/boot/dts/realtek/rtl930x.dtsi
···
69
69
#size-cells = <0>;
70
70
status = "disabled";
71
71
};
72
+
73
+
mdio_controller: mdio-controller@ca00 {
74
+
compatible = "realtek,rtl9301-mdio";
75
+
reg = <0xca00 0x200>;
76
+
#address-cells = <1>;
77
+
#size-cells = <0>;
78
+
status = "disabled";
79
+
80
+
mdio0: mdio-bus@0 {
81
+
reg = <0>;
82
+
#address-cells = <1>;
83
+
#size-cells = <0>;
84
+
status = "disabled";
85
+
};
86
+
mdio1: mdio-bus@1 {
87
+
reg = <1>;
88
+
#address-cells = <1>;
89
+
#size-cells = <0>;
90
+
status = "disabled";
91
+
};
92
+
mdio2: mdio-bus@2 {
93
+
reg = <2>;
94
+
#address-cells = <1>;
95
+
#size-cells = <0>;
96
+
status = "disabled";
97
+
};
98
+
mdio3: mdio-bus@3 {
99
+
reg = <3>;
100
+
#address-cells = <1>;
101
+
#size-cells = <0>;
102
+
status = "disabled";
103
+
};
104
+
};
72
105
};
73
106
74
107
soc: soc@18000000 {
+48
arch/mips/econet/Kconfig
+48
arch/mips/econet/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
if ECONET
3
+
4
+
choice
5
+
prompt "EcoNet SoC selection"
6
+
default SOC_ECONET_EN751221
7
+
help
8
+
Select EcoNet MIPS SoC type. Individual SoCs within a family are
9
+
very similar, so is it enough to select the right family, and
10
+
then customize to the specific SoC using the device tree only.
11
+
12
+
config SOC_ECONET_EN751221
13
+
bool "EN751221 family"
14
+
select COMMON_CLK
15
+
select ECONET_EN751221_INTC
16
+
select IRQ_MIPS_CPU
17
+
select SMP
18
+
select SMP_UP
19
+
select SYS_SUPPORTS_SMP
20
+
help
21
+
The EN751221 family includes EN7512, RN7513, EN7521, EN7526.
22
+
They are based on single core MIPS 34Kc processors. To boot
23
+
this kernel, you will need a device tree such as
24
+
MIPS_RAW_APPENDED_DTB=y, and a root filesystem.
25
+
endchoice
26
+
27
+
choice
28
+
prompt "Devicetree selection"
29
+
default DTB_ECONET_NONE
30
+
help
31
+
Select the devicetree.
32
+
33
+
config DTB_ECONET_NONE
34
+
bool "None"
35
+
36
+
config DTB_ECONET_SMARTFIBER_XP8421_B
37
+
bool "EN751221 SmartFiber XP8421-B"
38
+
depends on SOC_ECONET_EN751221
39
+
select BUILTIN_DTB
40
+
help
41
+
The SmartFiber XP8421-B is a device based on the EN751221 SoC.
42
+
It has 512MB of memory and 256MB of NAND flash. This kernel
43
+
needs only an appended initramfs to boot. It can be loaded
44
+
through XMODEM and booted from memory in the bootloader, or
45
+
it can be packed in tclinux.trx format and written to flash.
46
+
endchoice
47
+
48
+
endif
+5
arch/mips/econet/Platform
+5
arch/mips/econet/Platform
···
1
+
# To address a 7.2MB kernel size limit in the EcoNet SDK bootloader,
2
+
# we put the load address well above where the bootloader loads and then use
3
+
# zboot. So please set CONFIG_ZBOOT_LOAD_ADDRESS to the address where your
4
+
# bootloader actually places the kernel.
5
+
load-$(CONFIG_ECONET) += 0xffffffff81000000
+78
arch/mips/econet/init.c
+78
arch/mips/econet/init.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* EcoNet setup code
4
+
*
5
+
* Copyright (C) 2025 Caleb James DeLisle <cjd@cjdns.fr>
6
+
*/
7
+
8
+
#include <linux/init.h>
9
+
#include <linux/of_clk.h>
10
+
#include <linux/irqchip.h>
11
+
12
+
#include <asm/addrspace.h>
13
+
#include <asm/io.h>
14
+
#include <asm/bootinfo.h>
15
+
#include <asm/time.h>
16
+
#include <asm/prom.h>
17
+
#include <asm/smp-ops.h>
18
+
#include <asm/reboot.h>
19
+
20
+
#define CR_AHB_RSTCR ((void __iomem *)CKSEG1ADDR(0x1fb00040))
21
+
#define RESET BIT(31)
22
+
23
+
#define UART_BASE CKSEG1ADDR(0x1fbf0003)
24
+
#define UART_REG_SHIFT 2
25
+
26
+
static void hw_reset(char *command)
27
+
{
28
+
iowrite32(RESET, CR_AHB_RSTCR);
29
+
}
30
+
31
+
/* 1. Bring up early printk. */
32
+
void __init prom_init(void)
33
+
{
34
+
setup_8250_early_printk_port(UART_BASE, UART_REG_SHIFT, 0);
35
+
_machine_restart = hw_reset;
36
+
}
37
+
38
+
/* 2. Parse the DT and find memory */
39
+
void __init plat_mem_setup(void)
40
+
{
41
+
void *dtb;
42
+
43
+
set_io_port_base(KSEG1);
44
+
45
+
dtb = get_fdt();
46
+
if (!dtb)
47
+
panic("no dtb found");
48
+
49
+
__dt_setup_arch(dtb);
50
+
51
+
early_init_dt_scan_memory();
52
+
}
53
+
54
+
/* 3. Overload __weak device_tree_init(), add SMP_UP ops */
55
+
void __init device_tree_init(void)
56
+
{
57
+
unflatten_and_copy_device_tree();
58
+
59
+
register_up_smp_ops();
60
+
}
61
+
62
+
const char *get_system_type(void)
63
+
{
64
+
return "EcoNet-EN75xx";
65
+
}
66
+
67
+
/* 4. Initialize the IRQ subsystem */
68
+
void __init arch_init_irq(void)
69
+
{
70
+
irqchip_init();
71
+
}
72
+
73
+
/* 5. Timers */
74
+
void __init plat_time_init(void)
75
+
{
76
+
of_clk_init(NULL);
77
+
timer_probe();
78
+
}
+20
arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
+20
arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
···
12
12
#ifndef _CS5536_PCI_H
13
13
#define _CS5536_PCI_H
14
14
15
+
#include <linux/init.h>
15
16
#include <linux/types.h>
16
17
#include <linux/pci_regs.h>
17
18
18
19
extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
19
20
extern u32 cs5536_pci_conf_read4(int function, int reg);
21
+
22
+
extern void pci_ehci_write_reg(int reg, u32 value);
23
+
extern u32 pci_ehci_read_reg(int reg);
24
+
25
+
extern void pci_ide_write_reg(int reg, u32 value);
26
+
extern u32 pci_ide_read_reg(int reg);
27
+
28
+
extern void pci_acc_write_reg(int reg, u32 value);
29
+
extern u32 pci_acc_read_reg(int reg);
30
+
31
+
extern void pci_ohci_write_reg(int reg, u32 value);
32
+
extern u32 pci_ohci_read_reg(int reg);
33
+
34
+
extern void pci_isa_write_bar(int n, u32 value);
35
+
extern u32 pci_isa_read_bar(int n);
36
+
extern void pci_isa_write_reg(int reg, u32 value);
37
+
extern u32 pci_isa_read_reg(int reg);
38
+
39
+
extern int __init init_mfgpt_clocksource(void);
20
40
21
41
#define CS5536_ACC_INTR 9
22
42
#define CS5536_IDE_INTR 14
+9
arch/mips/include/asm/mach-loongson2ef/loongson.h
+9
arch/mips/include/asm/mach-loongson2ef/loongson.h
···
18
18
extern void mach_prepare_reboot(void);
19
19
extern void mach_prepare_shutdown(void);
20
20
21
+
/* machine-specific PROM functions */
22
+
extern void __init mach_prom_init_machtype(void);
23
+
21
24
/* environment arguments from bootloader */
22
25
extern u32 cpu_clock_freq;
23
26
extern u32 memsize, highmemsize;
···
47
44
extern void __init mach_init_irq(void);
48
45
extern void mach_irq_dispatch(unsigned int pending);
49
46
extern int mach_i8259_irq(void);
47
+
48
+
/* power management functions */
49
+
extern void setup_wakeup_events(void);
50
+
extern int wakeup_loongson(void);
51
+
extern void __weak mach_suspend(void);
52
+
extern void __weak mach_resume(void);
50
53
51
54
/* We need this in some places... */
52
55
#define delay() ({ \
+3
arch/mips/include/asm/topology.h
+3
arch/mips/include/asm/topology.h
···
16
16
#define topology_core_id(cpu) (cpu_core(&cpu_data[cpu]))
17
17
#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
18
18
#define topology_sibling_cpumask(cpu) (&cpu_sibling_map[cpu])
19
+
20
+
extern struct cpumask __cpu_primary_thread_mask;
21
+
#define cpu_primary_thread_mask ((const struct cpumask *)&__cpu_primary_thread_mask)
19
22
#endif
20
23
21
24
#endif /* __ASM_TOPOLOGY_H */
+5
-3
arch/mips/kernel/gpio_txx9.c
+5
-3
arch/mips/kernel/gpio_txx9.c
···
32
32
__raw_writel(val, &txx9_pioptr->dout);
33
33
}
34
34
35
-
static void txx9_gpio_set(struct gpio_chip *chip, unsigned int offset,
36
-
int value)
35
+
static int txx9_gpio_set(struct gpio_chip *chip, unsigned int offset,
36
+
int value)
37
37
{
38
38
unsigned long flags;
39
39
spin_lock_irqsave(&txx9_gpio_lock, flags);
40
40
txx9_gpio_set_raw(offset, value);
41
41
mmiowb();
42
42
spin_unlock_irqrestore(&txx9_gpio_lock, flags);
43
+
44
+
return 0;
43
45
}
44
46
45
47
static int txx9_gpio_dir_in(struct gpio_chip *chip, unsigned int offset)
···
70
68
71
69
static struct gpio_chip txx9_gpio_chip = {
72
70
.get = txx9_gpio_get,
73
-
.set = txx9_gpio_set,
71
+
.set_rv = txx9_gpio_set,
74
72
.direction_input = txx9_gpio_dir_in,
75
73
.direction_output = txx9_gpio_dir_out,
76
74
.label = "TXx9",
+18
-16
arch/mips/kernel/ptrace.c
+18
-16
arch/mips/kernel/ptrace.c
···
922
922
*/
923
923
int regs_query_register_offset(const char *name)
924
924
{
925
-
const struct pt_regs_offset *roff;
926
-
for (roff = regoffset_table; roff->name != NULL; roff++)
927
-
if (!strcmp(roff->name, name))
928
-
return roff->offset;
929
-
return -EINVAL;
925
+
const struct pt_regs_offset *roff;
926
+
927
+
for (roff = regoffset_table; roff->name != NULL; roff++)
928
+
if (!strcmp(roff->name, name))
929
+
return roff->offset;
930
+
931
+
return -EINVAL;
930
932
}
931
933
932
934
#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
···
939
937
.n = ELF_NGREG,
940
938
.size = sizeof(unsigned int),
941
939
.align = sizeof(unsigned int),
942
-
.regset_get = gpr32_get,
940
+
.regset_get = gpr32_get,
943
941
.set = gpr32_set,
944
942
},
945
943
[REGSET_DSP] = {
···
947
945
.n = NUM_DSP_REGS + 1,
948
946
.size = sizeof(u32),
949
947
.align = sizeof(u32),
950
-
.regset_get = dsp32_get,
948
+
.regset_get = dsp32_get,
951
949
.set = dsp32_set,
952
950
.active = dsp_active,
953
951
},
···
957
955
.n = ELF_NFPREG,
958
956
.size = sizeof(elf_fpreg_t),
959
957
.align = sizeof(elf_fpreg_t),
960
-
.regset_get = fpr_get,
958
+
.regset_get = fpr_get,
961
959
.set = fpr_set,
962
960
},
963
961
[REGSET_FP_MODE] = {
···
965
963
.n = 1,
966
964
.size = sizeof(int),
967
965
.align = sizeof(int),
968
-
.regset_get = fp_mode_get,
966
+
.regset_get = fp_mode_get,
969
967
.set = fp_mode_set,
970
968
},
971
969
#endif
···
975
973
.n = NUM_FPU_REGS + 1,
976
974
.size = 16,
977
975
.align = 16,
978
-
.regset_get = msa_get,
976
+
.regset_get = msa_get,
979
977
.set = msa_set,
980
978
},
981
979
#endif
···
999
997
.n = ELF_NGREG,
1000
998
.size = sizeof(unsigned long),
1001
999
.align = sizeof(unsigned long),
1002
-
.regset_get = gpr64_get,
1000
+
.regset_get = gpr64_get,
1003
1001
.set = gpr64_set,
1004
1002
},
1005
1003
[REGSET_DSP] = {
···
1007
1005
.n = NUM_DSP_REGS + 1,
1008
1006
.size = sizeof(u64),
1009
1007
.align = sizeof(u64),
1010
-
.regset_get = dsp64_get,
1008
+
.regset_get = dsp64_get,
1011
1009
.set = dsp64_set,
1012
1010
.active = dsp_active,
1013
1011
},
···
1017
1015
.n = 1,
1018
1016
.size = sizeof(int),
1019
1017
.align = sizeof(int),
1020
-
.regset_get = fp_mode_get,
1018
+
.regset_get = fp_mode_get,
1021
1019
.set = fp_mode_set,
1022
1020
},
1023
1021
[REGSET_FPR] = {
···
1025
1023
.n = ELF_NFPREG,
1026
1024
.size = sizeof(elf_fpreg_t),
1027
1025
.align = sizeof(elf_fpreg_t),
1028
-
.regset_get = fpr_get,
1026
+
.regset_get = fpr_get,
1029
1027
.set = fpr_set,
1030
1028
},
1031
1029
#endif
···
1035
1033
.n = NUM_FPU_REGS + 1,
1036
1034
.size = 16,
1037
1035
.align = 16,
1038
-
.regset_get = msa_get,
1036
+
.regset_get = msa_get,
1039
1037
.set = msa_set,
1040
1038
},
1041
1039
#endif
···
1353
1351
*/
1354
1352
asmlinkage void syscall_trace_leave(struct pt_regs *regs)
1355
1353
{
1356
-
/*
1354
+
/*
1357
1355
* We may come here right after calling schedule_user()
1358
1356
* or do_notify_resume(), in which case we can be in RCU
1359
1357
* user mode.
+2
arch/mips/kernel/smp-cps.c
+2
arch/mips/kernel/smp-cps.c
···
236
236
/* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
237
237
if (!cl && !c)
238
238
smp_num_siblings = core_vpes;
239
+
cpumask_set_cpu(nvpes, &__cpu_primary_thread_mask);
239
240
240
241
for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
241
242
cpu_set_cluster(&cpu_data[nvpes + v], cl);
···
369
368
cl = cpu_cluster(¤t_cpu_data);
370
369
c = cpu_core(¤t_cpu_data);
371
370
cluster_bootcfg = &mips_cps_cluster_bootcfg[cl];
371
+
cpu_smt_set_num_threads(core_vpes, core_vpes);
372
372
core_bootcfg = &cluster_bootcfg->core_config[c];
373
373
bitmap_set(cluster_bootcfg->core_power, cpu_core(¤t_cpu_data), 1);
374
374
atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data));
+18
arch/mips/kernel/smp.c
+18
arch/mips/kernel/smp.c
···
56
56
cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
57
57
EXPORT_SYMBOL(cpu_core_map);
58
58
59
+
#ifndef CONFIG_HOTPLUG_PARALLEL
59
60
static DECLARE_COMPLETION(cpu_starting);
60
61
static DECLARE_COMPLETION(cpu_running);
62
+
#endif
61
63
62
64
/*
63
65
* A logical cpu mask containing only one VPE per core to
···
75
73
static cpumask_t cpu_core_setup_map;
76
74
77
75
cpumask_t cpu_coherent_mask;
76
+
77
+
struct cpumask __cpu_primary_thread_mask __read_mostly;
78
78
79
79
unsigned int smp_max_threads __initdata = UINT_MAX;
80
80
···
371
367
* to an option instead of something based on .cputype
372
368
*/
373
369
370
+
#ifdef CONFIG_HOTPLUG_PARALLEL
371
+
cpuhp_ap_sync_alive();
372
+
#endif
374
373
calibrate_delay();
375
374
cpu_data[cpu].udelay_val = loops_per_jiffy;
376
375
···
383
376
cpumask_set_cpu(cpu, &cpu_coherent_mask);
384
377
notify_cpu_starting(cpu);
385
378
379
+
#ifndef CONFIG_HOTPLUG_PARALLEL
386
380
/* Notify boot CPU that we're starting & ready to sync counters */
387
381
complete(&cpu_starting);
382
+
#endif
388
383
389
384
synchronise_count_slave(cpu);
390
385
···
395
386
396
387
calculate_cpu_foreign_map();
397
388
389
+
#ifndef CONFIG_HOTPLUG_PARALLEL
398
390
/*
399
391
* Notify boot CPU that we're up & online and it can safely return
400
392
* from __cpu_up
401
393
*/
402
394
complete(&cpu_running);
395
+
#endif
403
396
404
397
/*
405
398
* irq will be enabled in ->smp_finish(), enabling it too early
···
458
447
set_cpu_online(0, true);
459
448
}
460
449
450
+
#ifdef CONFIG_HOTPLUG_PARALLEL
451
+
int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
452
+
{
453
+
return mp_ops->boot_secondary(cpu, tidle);
454
+
}
455
+
#else
461
456
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
462
457
{
463
458
int err;
···
483
466
wait_for_completion(&cpu_running);
484
467
return 0;
485
468
}
469
+
#endif
486
470
487
471
#ifdef CONFIG_PROFILING
488
472
/* Not really SMP stuff ... */
+2
-1
arch/mips/kernel/vpe.c
+2
-1
arch/mips/kernel/vpe.c
···
22
22
#include <linux/vmalloc.h>
23
23
#include <linux/elf.h>
24
24
#include <linux/seq_file.h>
25
+
#include <linux/string.h>
25
26
#include <linux/syscalls.h>
26
27
#include <linux/moduleloader.h>
27
28
#include <linux/interrupt.h>
···
583
582
struct module mod; /* so we can re-use the relocations code */
584
583
585
584
memset(&mod, 0, sizeof(struct module));
586
-
strcpy(mod.name, "VPE loader");
585
+
strscpy(mod.name, "VPE loader");
587
586
588
587
hdr = (Elf_Ehdr *) v->pbuffer;
589
588
len = v->plen;
+5
-3
arch/mips/rb532/gpio.c
+5
-3
arch/mips/rb532/gpio.c
···
105
105
/*
106
106
* Set output GPIO level
107
107
*/
108
-
static void rb532_gpio_set(struct gpio_chip *chip,
109
-
unsigned offset, int value)
108
+
static int rb532_gpio_set(struct gpio_chip *chip, unsigned int offset,
109
+
int value)
110
110
{
111
111
struct rb532_gpio_chip *gpch;
112
112
113
113
gpch = gpiochip_get_data(chip);
114
114
rb532_set_bit(value, offset, gpch->regbase + GPIOD);
115
+
116
+
return 0;
115
117
}
116
118
117
119
/*
···
164
162
.direction_input = rb532_gpio_direction_input,
165
163
.direction_output = rb532_gpio_direction_output,
166
164
.get = rb532_gpio_get,
167
-
.set = rb532_gpio_set,
165
+
.set_rv = rb532_gpio_set,
168
166
.to_irq = rb532_gpio_to_irq,
169
167
.base = 0,
170
168
.ngpio = 32,
+5
-3
arch/mips/txx9/generic/setup.c
+5
-3
arch/mips/txx9/generic/setup.c
···
603
603
return !!(data->cur_val & (1 << offset));
604
604
}
605
605
606
-
static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
607
-
int value)
606
+
static int txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
607
+
int value)
608
608
{
609
609
struct txx9_iocled_data *data = gpiochip_get_data(chip);
610
610
unsigned long flags;
···
616
616
writeb(data->cur_val, data->mmioaddr);
617
617
mmiowb();
618
618
spin_unlock_irqrestore(&txx9_iocled_lock, flags);
619
+
620
+
return 0;
619
621
}
620
622
621
623
static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
···
655
653
if (!iocled->mmioaddr)
656
654
goto out_free;
657
655
iocled->chip.get = txx9_iocled_get;
658
-
iocled->chip.set = txx9_iocled_set;
656
+
iocled->chip.set_rv = txx9_iocled_set;
659
657
iocled->chip.direction_input = txx9_iocled_dir_in;
660
658
iocled->chip.direction_output = txx9_iocled_dir_out;
661
659
iocled->chip.label = "iocled";
+1
arch/mips/vdso/Makefile
+1
arch/mips/vdso/Makefile
···
27
27
# offsets.
28
28
cflags-vdso := $(ccflags-vdso) \
29
29
$(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \
30
+
$(filter -std=%,$(KBUILD_CFLAGS)) \
30
31
-O3 -g -fPIC -fno-strict-aliasing -fno-common -fno-builtin -G 0 \
31
32
-mrelax-pic-calls $(call cc-option, -mexplicit-relocs) \
32
33
-fno-stack-protector -fno-jump-tables -DDISABLE_BRANCH_PROFILING \
+6
-10
include/linux/bcm963xx_nvram.h
+6
-10
include/linux/bcm963xx_nvram.h
···
81
81
const struct bcm963xx_nvram *nvram,
82
82
u32 *expected_out, u32 *actual_out)
83
83
{
84
+
const u32 zero = 0;
84
85
u32 expected, actual;
85
86
size_t len;
86
87
87
88
if (nvram->version <= 4) {
88
89
expected = nvram->checksum_v4;
89
-
len = BCM963XX_NVRAM_V4_SIZE - sizeof(u32);
90
+
len = BCM963XX_NVRAM_V4_SIZE;
90
91
} else {
91
92
expected = nvram->checksum_v5;
92
-
len = BCM963XX_NVRAM_V5_SIZE - sizeof(u32);
93
+
len = BCM963XX_NVRAM_V5_SIZE;
93
94
}
94
95
95
-
/*
96
-
* Calculate the CRC32 value for the nvram with a checksum value
97
-
* of 0 without modifying or copying the nvram by combining:
98
-
* - The CRC32 of the nvram without the checksum value
99
-
* - The CRC32 of a zero checksum value (which is also 0)
100
-
*/
101
-
actual = crc32_le_combine(
102
-
crc32_le(~0, (u8 *)nvram, len), 0, sizeof(u32));
96
+
/* Calculate the CRC32 of the nvram with the checksum field set to 0. */
97
+
actual = crc32_le(~0, nvram, len - sizeof(u32));
98
+
actual = crc32_le(actual, &zero, sizeof(u32));
103
99
104
100
if (expected_out)
105
101
*expected_out = expected;