Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'v6.20-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: Anberic RG-DS game console, Radxa CM3J module + baseboard
for the Rpi CM4 IO board, QNAP TS133 from the RK3568 NAS series.
2 display outputs for the Lion board (old RK3368), TPS65185 pmic for the
PineNote and fixes for the PCIe ranges on both RK356x and RK3588.
These came quite late, so I wanted to give them the time till 6.20-rc1
and have them migrate to stable-kernels afterwards.
The rest is small stuff on a number of boards wrt gpios and compatibles.
* tag 'v6.20-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (25 commits)
arm64: dts: rockchip: Fix rk3588 PCIe range mappings
arm64: dts: rockchip: Fix rk356x PCIe range mappings
arm64: dts: rockchip: Add Anbernic RG-DS
dt-bindings: input: touchscreen: goodix: Add "panel" property
dt-bindings: arm: rockchip: Add Anbernic RG-DS
arm64: dts: rockchip: Explicitly request UFS reset pin on RK3576
arm64: dts: rockchip: Add TPS65185 for PineNote
arm64: dts: rockchip: Do not enable hdmi_sound node on Pinebook Pro
arm64: dts: rockchip: Fix imx258 variant on pinephone pro
arm64: dts: rockchip: Add the Video-Demo overlay for Lion Haikou
arm64: dts: rockchip: Enable pwm1 on rk3368-lion-haikou
arm64: dts: rockchip: Enable HDMI output on RK3368-Lion-Haikou
arm64: dts: rockchip: Add HDMI node to RK3368
arm64: dts: rockchip: Use phandle for i2c_lvds_blc on rk3368-lion haikou
arm64: dts: rockchip: Fix SD card support for RK3576 Nanopi R76s
arm64: dts: rockchip: Fix SD card support for RK3576 EVB1
arm64: dts: rockchip: Add Radxa CM3J on RPi CM4 IO Board
arm64: dts: rockchip: Add Radxa CM3J
dt-bindings: arm: rockchip: Add Radxa CM3J on RPi CM4 IO Board
arm64: dts: rockchip: Make eeprom read-only for Radxa ROCK 3C/5A/5C
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+2498
-50
+22
-5
Documentation/devicetree/bindings/arm/rockchip.yaml
+22
-5
Documentation/devicetree/bindings/arm/rockchip.yaml
···
60
60
- anbernic,rg-arc-s
61
61
- const: rockchip,rk3566
62
62
63
+
- description: Anbernic RK3568 Handheld Gaming Console
64
+
items:
65
+
- enum:
66
+
- anbernic,rg-ds
67
+
- const: rockchip,rk3568
68
+
63
69
- description: Ariaboard Photonicat
64
70
items:
65
71
- const: ariaboard,photonicat
···
900
894
- const: rockchip,rk3568
901
895
902
896
- description: QNAP TS-x33 NAS devices
903
-
items:
904
-
- enum:
905
-
- qnap,ts233
906
-
- qnap,ts433
907
-
- const: rockchip,rk3568
897
+
oneOf:
898
+
- items:
899
+
- const: qnap,ts133
900
+
- const: rockchip,rk3566
901
+
- items:
902
+
- enum:
903
+
- qnap,ts233
904
+
- qnap,ts433
905
+
- const: rockchip,rk3568
908
906
909
907
- description: Radxa Compute Module 3 (CM3)
910
908
items:
···
922
912
- enum:
923
913
- radxa,e25
924
914
- const: radxa,cm3i
915
+
- const: rockchip,rk3568
916
+
917
+
- description: Radxa CM3J
918
+
items:
919
+
- enum:
920
+
- radxa,cm3j-rpi-cm4
921
+
- const: radxa,cm3j
925
922
- const: rockchip,rk3568
926
923
927
924
- description: Radxa CM5
+2
Documentation/devicetree/bindings/input/touchscreen/goodix.yaml
+2
Documentation/devicetree/bindings/input/touchscreen/goodix.yaml
+8
arch/arm64/boot/dts/rockchip/Makefile
+8
arch/arm64/boot/dts/rockchip/Makefile
···
42
42
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
43
43
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lba3368.dtb
44
44
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
45
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou-video-demo.dtbo
45
46
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
46
47
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
47
48
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
···
115
114
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb30.dtb
116
115
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rk2023.dtb
117
116
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb
117
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133.dtb
118
118
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
119
119
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
120
120
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
···
135
133
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3.dtb
136
134
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3s.dtb
137
135
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-9tripod-x3568-v4.dtb
136
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-anbernic-rg-ds.dtb
138
137
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
139
138
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb
140
139
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
···
151
148
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb
152
149
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233.dtb
153
150
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb
151
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-cm3j-rpi-cm4.dtb
154
152
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
155
153
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
156
154
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
···
244
240
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-video-demo.dtb
245
241
px30-ringneck-haikou-haikou-video-demo-dtbs := px30-ringneck-haikou.dtb \
246
242
px30-ringneck-haikou-video-demo.dtbo
243
+
244
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou-haikou-video-demo.dtb
245
+
rk3368-lion-haikou-haikou-video-demo-dtbs := rk3368-lion-haikou.dtb \
246
+
rk3368-lion-haikou-video-demo.dtbo
247
247
248
248
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou-haikou-video-demo.dtb
249
249
rk3399-puma-haikou-haikou-video-demo-dtbs := rk3399-puma-haikou.dtb \
+170
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso
+170
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Cherry Embedded Solutions GmbH
4
+
*
5
+
* DEVKIT ADDON CAM-TS-A01
6
+
* https://embedded.cherry.de/product/development-kit/
7
+
*
8
+
* DT-overlay for the camera / DSI demo appliance for Haikou boards.
9
+
* In the flavour for use with a Lion system-on-module.
10
+
*/
11
+
12
+
/dts-v1/;
13
+
/plugin/;
14
+
15
+
#include <dt-bindings/clock/rk3368-cru.h>
16
+
#include <dt-bindings/gpio/gpio.h>
17
+
#include <dt-bindings/interrupt-controller/irq.h>
18
+
#include <dt-bindings/leds/common.h>
19
+
#include <dt-bindings/pinctrl/rockchip.h>
20
+
21
+
&{/} {
22
+
backlight: backlight {
23
+
compatible = "pwm-backlight";
24
+
power-supply = <&dc_12v>;
25
+
pwms = <&pwm1 0 25000 0>;
26
+
};
27
+
28
+
cam_afvdd_2v8: regulator-cam-afvdd-2v8 {
29
+
compatible = "regulator-fixed";
30
+
gpio = <&pca9670 2 GPIO_ACTIVE_LOW>;
31
+
regulator-max-microvolt = <2800000>;
32
+
regulator-min-microvolt = <2800000>;
33
+
regulator-name = "cam-afvdd-2v8";
34
+
vin-supply = <&vcc2v8_video>;
35
+
};
36
+
37
+
cam_avdd_2v8: regulator-cam-avdd-2v8 {
38
+
compatible = "regulator-fixed";
39
+
gpio = <&pca9670 4 GPIO_ACTIVE_LOW>;
40
+
regulator-max-microvolt = <2800000>;
41
+
regulator-min-microvolt = <2800000>;
42
+
regulator-name = "cam-avdd-2v8";
43
+
vin-supply = <&vcc2v8_video>;
44
+
};
45
+
46
+
cam_dovdd_1v8: regulator-cam-dovdd-1v8 {
47
+
compatible = "regulator-fixed";
48
+
gpio = <&pca9670 3 GPIO_ACTIVE_LOW>;
49
+
regulator-max-microvolt = <1800000>;
50
+
regulator-min-microvolt = <1800000>;
51
+
regulator-name = "cam-dovdd-1v8";
52
+
vin-supply = <&vcc1v8_video>;
53
+
};
54
+
55
+
cam_dvdd_1v2: regulator-cam-dvdd-1v2 {
56
+
compatible = "regulator-fixed";
57
+
enable-active-high;
58
+
gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>;
59
+
regulator-max-microvolt = <1200000>;
60
+
regulator-min-microvolt = <1200000>;
61
+
regulator-name = "cam-dvdd-1v2";
62
+
vin-supply = <&vcc3v3_baseboard>;
63
+
};
64
+
65
+
vcc1v8_video: regulator-vcc1v8-video {
66
+
compatible = "regulator-fixed";
67
+
regulator-always-on;
68
+
regulator-boot-on;
69
+
regulator-max-microvolt = <1800000>;
70
+
regulator-min-microvolt = <1800000>;
71
+
regulator-name = "vcc1v8-video";
72
+
vin-supply = <&vcc3v3_baseboard>;
73
+
};
74
+
75
+
vcc2v8_video: regulator-vcc2v8-video {
76
+
compatible = "regulator-fixed";
77
+
regulator-always-on;
78
+
regulator-boot-on;
79
+
regulator-max-microvolt = <2800000>;
80
+
regulator-min-microvolt = <2800000>;
81
+
regulator-name = "vcc2v8-video";
82
+
vin-supply = <&vcc3v3_baseboard>;
83
+
};
84
+
85
+
video-adapter-leds {
86
+
compatible = "gpio-leds";
87
+
88
+
video-adapter-led {
89
+
color = <LED_COLOR_ID_BLUE>;
90
+
gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>;
91
+
label = "video-adapter-led";
92
+
linux,default-trigger = "none";
93
+
};
94
+
};
95
+
};
96
+
97
+
&dphy {
98
+
status = "okay";
99
+
};
100
+
101
+
&i2c_gp2 {
102
+
#address-cells = <1>;
103
+
#size-cells = <0>;
104
+
/* OV5675, GT911, DW9714 are limited to 400KHz */
105
+
clock-frequency = <400000>;
106
+
107
+
touchscreen@14 {
108
+
compatible = "goodix,gt911";
109
+
reg = <0x14>;
110
+
interrupt-parent = <&gpio1>;
111
+
interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
112
+
irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
113
+
pinctrl-0 = <&touch_int>;
114
+
pinctrl-names = "default";
115
+
reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>;
116
+
AVDD28-supply = <&vcc2v8_video>;
117
+
VDDIO-supply = <&vcc3v3_baseboard>;
118
+
};
119
+
120
+
pca9670: gpio@27 {
121
+
compatible = "nxp,pca9670";
122
+
reg = <0x27>;
123
+
gpio-controller;
124
+
#gpio-cells = <2>;
125
+
pinctrl-0 = <&pca9670_resetn>;
126
+
pinctrl-names = "default";
127
+
reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
128
+
};
129
+
};
130
+
131
+
&mipi_dsi {
132
+
#address-cells = <1>;
133
+
#size-cells = <0>;
134
+
status = "okay";
135
+
136
+
panel@0 {
137
+
compatible = "leadtek,ltk050h3148w";
138
+
reg = <0>;
139
+
backlight = <&backlight>;
140
+
iovcc-supply = <&vcc1v8_video>;
141
+
reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>;
142
+
vci-supply = <&vcc2v8_video>;
143
+
144
+
port {
145
+
mipi_in_panel: endpoint {
146
+
remote-endpoint = <&mipi_out_panel>;
147
+
};
148
+
};
149
+
};
150
+
};
151
+
152
+
&mipi_out {
153
+
mipi_out_panel: endpoint {
154
+
remote-endpoint = <&mipi_in_panel>;
155
+
};
156
+
};
157
+
158
+
&pinctrl {
159
+
pca9670 {
160
+
pca9670_resetn: pca9670-resetn {
161
+
rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
162
+
};
163
+
};
164
+
165
+
touch {
166
+
touch_int: touch-int {
167
+
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
168
+
};
169
+
};
170
+
};
+28
-10
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
+28
-10
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
···
18
18
stdout-path = "serial0:115200n8";
19
19
};
20
20
21
-
i2cmux2 {
22
-
i2c@0 {
23
-
eeprom: eeprom@50 {
24
-
compatible = "atmel,24c01";
25
-
pagesize = <8>;
26
-
reg = <0x50>;
27
-
};
28
-
};
29
-
};
30
-
31
21
leds {
32
22
pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
33
23
···
58
68
};
59
69
};
60
70
71
+
&display_subsystem {
72
+
status = "okay";
73
+
};
74
+
75
+
&hdmi {
76
+
status = "okay";
77
+
};
78
+
79
+
&i2c_lvds_blc {
80
+
eeprom: eeprom@50 {
81
+
compatible = "atmel,24c01";
82
+
pagesize = <8>;
83
+
reg = <0x50>;
84
+
};
85
+
};
86
+
87
+
&pwm1 {
88
+
status = "okay";
89
+
};
90
+
61
91
&sdmmc {
62
92
bus-width = <4>;
63
93
cap-mmc-highspeed;
···
111
101
&uart1 {
112
102
/* alternate function of GPIO5/6 */
113
103
status = "disabled";
104
+
};
105
+
106
+
&vop {
107
+
status = "okay";
108
+
};
109
+
110
+
&vop_mmu {
111
+
status = "okay";
114
112
};
115
113
116
114
&pinctrl {
+5
arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
+5
arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
+43
arch/arm64/boot/dts/rockchip/rk3368.dtsi
+43
arch/arm64/boot/dts/rockchip/rk3368.dtsi
···
883
883
reg = <0>;
884
884
remote-endpoint = <&dsi_in_vop>;
885
885
};
886
+
887
+
vop_out_hdmi: endpoint@1 {
888
+
reg = <1>;
889
+
remote-endpoint = <&hdmi_in_vop>;
890
+
};
886
891
};
887
892
};
888
893
···
944
939
resets = <&cru SRST_MIPIDPHYTX>;
945
940
reset-names = "apb";
946
941
status = "disabled";
942
+
};
943
+
944
+
hdmi: hdmi@ff980000 {
945
+
compatible = "rockchip,rk3368-dw-hdmi";
946
+
reg = <0x0 0xff980000 0x0 0x20000>;
947
+
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
948
+
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
949
+
clock-names = "iahb", "isfr", "cec";
950
+
pinctrl-names = "default";
951
+
pinctrl-0 = <&hdmi_i2c_xfer>;
952
+
power-domains = <&power RK3368_PD_VIO>;
953
+
reg-io-width = <4>;
954
+
rockchip,grf = <&grf>;
955
+
status = "disabled";
956
+
957
+
ports {
958
+
#address-cells = <1>;
959
+
#size-cells = <0>;
960
+
961
+
hdmi_in: port@0 {
962
+
reg = <0>;
963
+
964
+
hdmi_in_vop: endpoint {
965
+
remote-endpoint = <&vop_out_hdmi>;
966
+
};
967
+
};
968
+
969
+
hdmi_out: port@1 {
970
+
reg = <1>;
971
+
};
972
+
};
947
973
};
948
974
949
975
hevc_mmu: iommu@ff9a0440 {
···
1237
1201
<3 RK_PC0 1 &pcfg_pull_none>,
1238
1202
<3 RK_PC4 1 &pcfg_pull_none>,
1239
1203
<3 RK_PC5 1 &pcfg_pull_none>;
1204
+
};
1205
+
};
1206
+
1207
+
hdmi {
1208
+
hdmi_i2c_xfer: hdmi-i2c-xfer {
1209
+
rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>,
1210
+
<3 RK_PD3 1 &pcfg_pull_none>;
1240
1211
};
1241
1212
};
1242
1213
-4
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-4
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+49
arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+49
arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
···
499
499
};
500
500
};
501
501
};
502
+
503
+
ebc_pmic: pmic@68 {
504
+
compatible = "ti,tps65185";
505
+
reg = <0x68>;
506
+
interrupt-parent = <&gpio3>;
507
+
interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
508
+
enable-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
509
+
pinctrl-0 = <&ebc_pmic_pins>;
510
+
pinctrl-names = "default";
511
+
pwr-good-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
512
+
vcom-ctrl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
513
+
vin-supply = <&vcc_bat>;
514
+
wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
515
+
516
+
regulators {
517
+
v3p3: v3p3 {
518
+
regulator-name = "v3p3";
519
+
/* Keep it always on because IRQ is pulled up against this line */
520
+
regulator-always-on;
521
+
regulator-min-microvolt = <3300000>;
522
+
regulator-max-microvolt = <3300000>;
523
+
};
524
+
525
+
vcom: vcom {
526
+
regulator-name = "vcom";
527
+
};
528
+
529
+
vposneg: vposneg {
530
+
regulator-name = "vposneg";
531
+
regulator-min-microvolt = <15000000>;
532
+
regulator-max-microvolt = <15000000>;
533
+
};
534
+
};
535
+
};
502
536
};
503
537
504
538
&i2c5 {
···
594
560
595
561
bt_wake_h: bt-wake-h {
596
562
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
563
+
};
564
+
};
565
+
566
+
ebc-pmic {
567
+
ebc_pmic_pins: ebc-pmic-pins {
568
+
rockchip,pins = /* wakeup */
569
+
<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
570
+
/* int */
571
+
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
572
+
/* pwr_good */
573
+
<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
574
+
/* pwrup */
575
+
<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
576
+
/* vcom_ctrl */
577
+
<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
597
578
};
598
579
};
599
580
+71
arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts
+71
arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4
+
* Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
5
+
*/
6
+
7
+
/dts-v1/;
8
+
9
+
#include "rk3566.dtsi"
10
+
#include "rk3568-qnap-tsx33.dtsi"
11
+
12
+
/ {
13
+
model = "Qnap TS-133-2G NAS System 1-Bay";
14
+
compatible = "qnap,ts133", "rockchip,rk3566";
15
+
16
+
aliases {
17
+
ethernet0 = &gmac1;
18
+
};
19
+
};
20
+
21
+
&gmac1 {
22
+
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
23
+
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
24
+
assigned-clock-rates = <0>, <125000000>;
25
+
clock_in_out = "output";
26
+
phy-handle = <&rgmii_phy0>;
27
+
phy-mode = "rgmii-id";
28
+
pinctrl-names = "default";
29
+
pinctrl-0 = <&gmac1m1_miim
30
+
&gmac1m1_tx_bus2
31
+
&gmac1m1_rx_bus2
32
+
&gmac1m1_rgmii_clk
33
+
&gmac1m1_rgmii_bus>;
34
+
status = "okay";
35
+
};
36
+
37
+
&mcu {
38
+
compatible = "qnap,ts133-mcu";
39
+
};
40
+
41
+
&mdio1 {
42
+
rgmii_phy0: ethernet-phy@3 {
43
+
/* Motorcomm YT8521 phy */
44
+
compatible = "ethernet-phy-ieee802.3-c22";
45
+
reg = <0x3>;
46
+
pinctrl-0 = <ð_phy0_reset_pin>;
47
+
pinctrl-names = "default";
48
+
reset-assert-us = <10000>;
49
+
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
50
+
};
51
+
};
52
+
53
+
&pinctrl {
54
+
gmac1 {
55
+
eth_phy0_reset_pin: eth-phy0-reset-pin {
56
+
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
57
+
};
58
+
};
59
+
};
60
+
61
+
/* connected to usb_host1_xhci */
62
+
&usb2phy0_host {
63
+
phy-supply = <&vcc5v0_otg>;
64
+
status = "okay";
65
+
};
66
+
67
+
/* USB3 port on backside */
68
+
&usb_host1_xhci {
69
+
dr_mode = "host";
70
+
status = "okay";
71
+
};
+1
arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
+1
arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
+1237
arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts
+1237
arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
3
+
/dts-v1/;
4
+
5
+
#include <dt-bindings/gpio/gpio.h>
6
+
#include <dt-bindings/input/gpio-keys.h>
7
+
#include <dt-bindings/input/linux-event-codes.h>
8
+
#include <dt-bindings/leds/common.h>
9
+
#include <dt-bindings/pinctrl/rockchip.h>
10
+
#include <dt-bindings/soc/rockchip,vop2.h>
11
+
#include "rk3568.dtsi"
12
+
13
+
/ {
14
+
model = "Anbernic RG DS";
15
+
chassis-type = "handset";
16
+
compatible = "anbernic,rg-ds", "rockchip,rk3568";
17
+
18
+
aliases {
19
+
mmc0 = &sdhci;
20
+
mmc1 = &sdmmc0;
21
+
mmc2 = &sdmmc2;
22
+
};
23
+
24
+
chosen: chosen {
25
+
stdout-path = "serial2:1500000n8";
26
+
};
27
+
28
+
adc_keys_home: adc-keys-home {
29
+
compatible = "adc-keys";
30
+
io-channel-names = "buttons";
31
+
io-channels = <&saradc 0>;
32
+
keyup-threshold-microvolt = <1800000>;
33
+
poll-interval = <60>;
34
+
35
+
button-home {
36
+
label = "HOME";
37
+
linux,code = <BTN_MODE>;
38
+
press-threshold-microvolt = <1750>;
39
+
};
40
+
};
41
+
42
+
adc_keys_play: adc-keys-play {
43
+
compatible = "adc-keys";
44
+
io-channel-names = "buttons";
45
+
io-channels = <&saradc 2>;
46
+
keyup-threshold-microvolt = <1300000>;
47
+
poll-interval = <60>;
48
+
49
+
button-play {
50
+
label = "PLAY";
51
+
linux,code = <KEY_PLAYPAUSE>;
52
+
press-threshold-microvolt = <1750>;
53
+
};
54
+
};
55
+
56
+
adc_mux: adc-mux {
57
+
compatible = "io-channel-mux";
58
+
channels = "left_x", "right_x", "left_y", "right_y";
59
+
#io-channel-cells = <1>;
60
+
io-channels = <&saradc 3>;
61
+
io-channel-names = "parent";
62
+
mux-controls = <&gpio_mux>;
63
+
settle-time-us = <100>;
64
+
};
65
+
66
+
adc-joystick {
67
+
compatible = "adc-joystick";
68
+
#address-cells = <1>;
69
+
io-channels = <&adc_mux 0>,
70
+
<&adc_mux 1>,
71
+
<&adc_mux 2>,
72
+
<&adc_mux 3>;
73
+
pinctrl-0 = <&joy_mux_en>;
74
+
pinctrl-names = "default";
75
+
poll-interval = <60>;
76
+
#size-cells = <0>;
77
+
78
+
axis@0 {
79
+
reg = <0>;
80
+
abs-flat = <32>;
81
+
abs-fuzz = <32>;
82
+
abs-range = <1023 15>;
83
+
linux,code = <ABS_X>;
84
+
};
85
+
86
+
axis@1 {
87
+
reg = <1>;
88
+
abs-flat = <32>;
89
+
abs-fuzz = <32>;
90
+
abs-range = <15 1023>;
91
+
linux,code = <ABS_RY>;
92
+
};
93
+
94
+
axis@2 {
95
+
reg = <2>;
96
+
abs-flat = <32>;
97
+
abs-fuzz = <32>;
98
+
abs-range = <15 1023>;
99
+
linux,code = <ABS_Y>;
100
+
};
101
+
102
+
axis@3 {
103
+
reg = <3>;
104
+
abs-flat = <32>;
105
+
abs-fuzz = <32>;
106
+
abs-range = <15 1023>;
107
+
linux,code = <ABS_RX>;
108
+
};
109
+
};
110
+
111
+
backlight0: backlight0 {
112
+
compatible = "pwm-backlight";
113
+
enable-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
114
+
pwms = <&pwm12 0 25000 0>;
115
+
};
116
+
117
+
backlight1: backlight1 {
118
+
compatible = "pwm-backlight";
119
+
enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
120
+
pwms = <&pwm13 0 25000 0>;
121
+
};
122
+
123
+
/*
124
+
* Values taken from BSP device-tree except for
125
+
* "charge-full-design-microamp-hours" which was set
126
+
* incorrectly at 2500000 (based on markings on the battery it
127
+
* should be 4000000), "factory-internal-resistance-micro-ohms"
128
+
* which was set at 8 but based on context should likely be 80000.
129
+
*
130
+
* "constant-charge-current-max-microamp" is set at 10 AMPs
131
+
* which is likely incorrect but I cannot validate; furthermore
132
+
* the onboard charger of the rk817 cannot charge past 3.5A
133
+
* anyway.
134
+
*/
135
+
battery: battery {
136
+
compatible = "simple-battery";
137
+
charge-full-design-microamp-hours = <4000000>;
138
+
charge-term-current-microamp = <300000>;
139
+
constant-charge-current-max-microamp = <10000000>;
140
+
constant-charge-voltage-max-microvolt = <4350000>;
141
+
factory-internal-resistance-micro-ohms = <80000>;
142
+
precharge-current-microamp = <180000>;
143
+
precharge-upper-limit-microvolt = <3600000>;
144
+
voltage-max-design-microvolt = <4350000>;
145
+
voltage-min-design-microvolt = <3000000>;
146
+
147
+
/*
148
+
* BSP device-tree missing value for 5 percent, so I
149
+
* picked a value between 10 and 0.
150
+
*/
151
+
ocv-capacity-celsius = <20>;
152
+
ocv-capacity-table-0 = <4338000 100>, <4251000 95>,
153
+
<4191000 90>, <4136000 85>,
154
+
<4083000 80>, <4039000 75>,
155
+
<3978000 70>, <3947000 65>,
156
+
<3908000 60>, <3861000 55>,
157
+
<3826000 50>, <3786000 45>,
158
+
<3772000 40>, <3761000 35>,
159
+
<3749000 30>, <3731000 25>,
160
+
<3707000 20>, <3677000 15>,
161
+
<3663000 10>, <3446000 5>,
162
+
<3400000 0>;
163
+
};
164
+
165
+
gpio_keys_control: gpio-keys-control {
166
+
compatible = "gpio-keys";
167
+
pinctrl-0 = <&gamepad_keys_l>;
168
+
pinctrl-names = "default";
169
+
170
+
button-a {
171
+
gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
172
+
label = "EAST";
173
+
linux,code = <BTN_EAST>;
174
+
};
175
+
176
+
button-b {
177
+
gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
178
+
label = "SOUTH";
179
+
linux,code = <BTN_SOUTH>;
180
+
};
181
+
182
+
button-down {
183
+
gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
184
+
label = "DPAD-DOWN";
185
+
linux,code = <BTN_DPAD_DOWN>;
186
+
};
187
+
188
+
button-l1 {
189
+
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
190
+
label = "TL";
191
+
linux,code = <BTN_TL>;
192
+
};
193
+
194
+
button-l2 {
195
+
gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
196
+
label = "TL2";
197
+
linux,code = <BTN_TL2>;
198
+
};
199
+
200
+
button-left {
201
+
gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>;
202
+
label = "DPAD-LEFT";
203
+
linux,code = <BTN_DPAD_LEFT>;
204
+
};
205
+
206
+
button-menu {
207
+
gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
208
+
label = "HOME";
209
+
linux,code = <KEY_HOME>;
210
+
};
211
+
212
+
button-right {
213
+
gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;
214
+
label = "DPAD-RIGHT";
215
+
linux,code = <BTN_DPAD_RIGHT>;
216
+
};
217
+
218
+
button-r1 {
219
+
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
220
+
label = "T2";
221
+
linux,code = <BTN_TR>;
222
+
};
223
+
224
+
button-r2 {
225
+
gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
226
+
label = "TR2";
227
+
linux,code = <BTN_TR2>;
228
+
};
229
+
230
+
button-select {
231
+
gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
232
+
label = "SELECT";
233
+
linux,code = <BTN_SELECT>;
234
+
};
235
+
236
+
button-start {
237
+
gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
238
+
label = "START";
239
+
linux,code = <BTN_START>;
240
+
};
241
+
242
+
button-thumbl {
243
+
gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
244
+
label = "THUMBL";
245
+
linux,code = <BTN_THUMBL>;
246
+
};
247
+
248
+
button-thumbr {
249
+
gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
250
+
label = "THUMBR";
251
+
linux,code = <BTN_THUMBR>;
252
+
};
253
+
254
+
button-up {
255
+
gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
256
+
label = "DPAD-UP";
257
+
linux,code = <BTN_DPAD_UP>;
258
+
};
259
+
260
+
button-x {
261
+
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
262
+
label = "NORTH";
263
+
linux,code = <BTN_NORTH>;
264
+
};
265
+
266
+
button-y {
267
+
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
268
+
label = "WEST";
269
+
linux,code = <BTN_WEST>;
270
+
};
271
+
};
272
+
273
+
gpio_keys_hall: gpio-keys-hall {
274
+
compatible = "gpio-keys";
275
+
pinctrl-0 = <&hall_int_l>;
276
+
pinctrl-names = "default";
277
+
278
+
lid-switch {
279
+
gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
280
+
label = "LID";
281
+
linux,code = <SW_LID>;
282
+
linux,input-type = <EV_SW>;
283
+
wakeup-event-action = <EV_ACT_DEASSERTED>;
284
+
wakeup-source;
285
+
};
286
+
};
287
+
288
+
gpio_keys_volume: gpio-keys-volume {
289
+
compatible = "gpio-keys";
290
+
autorepeat;
291
+
pinctrl-0 = <&vol_keys_l>;
292
+
pinctrl-names = "default";
293
+
294
+
vol-down-key {
295
+
gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
296
+
label = "VOLUMEDOWN";
297
+
linux,code = <KEY_VOLUMEDOWN>;
298
+
};
299
+
300
+
vol-up-key {
301
+
gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
302
+
label = "VOLUMEUP";
303
+
linux,code = <KEY_VOLUMEUP>;
304
+
};
305
+
};
306
+
307
+
gpio_mux: mux-controller {
308
+
compatible = "gpio-mux";
309
+
#mux-control-cells = <0>;
310
+
mux-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>,
311
+
<&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
312
+
pinctrl-0 = <&joy_mux_config>;
313
+
pinctrl-names = "default";
314
+
};
315
+
316
+
leds: pwm-leds {
317
+
compatible = "pwm-leds";
318
+
319
+
green_led: led-0 {
320
+
color = <LED_COLOR_ID_GREEN>;
321
+
default-state = "on";
322
+
function = LED_FUNCTION_POWER;
323
+
max-brightness = <255>;
324
+
pwms = <&pwm5 0 25000 0>;
325
+
};
326
+
327
+
amber_led: led-1 {
328
+
color = <LED_COLOR_ID_AMBER>;
329
+
function = LED_FUNCTION_CHARGING;
330
+
max-brightness = <255>;
331
+
pwms = <&pwm6 0 25000 0>;
332
+
};
333
+
334
+
red_led: led-2 {
335
+
color = <LED_COLOR_ID_RED>;
336
+
default-state = "off";
337
+
function = LED_FUNCTION_STATUS;
338
+
max-brightness = <255>;
339
+
pwms = <&pwm7 0 25000 0>;
340
+
};
341
+
};
342
+
343
+
sdio_pwrseq: sdio-pwrseq {
344
+
compatible = "mmc-pwrseq-simple";
345
+
clock-names = "ext_clock";
346
+
clocks = <&rk817 1>;
347
+
pinctrl-0 = <&wifi_enable_h>;
348
+
pinctrl-names = "default";
349
+
post-power-on-delay-ms = <200>;
350
+
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
351
+
};
352
+
353
+
sound {
354
+
compatible = "simple-audio-card";
355
+
pinctrl-0 = <&hp_det>;
356
+
pinctrl-names = "default";
357
+
simple-audio-card,format = "i2s";
358
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
359
+
simple-audio-card,mclk-fs = <256>;
360
+
simple-audio-card,name = "rk817_ext";
361
+
simple-audio-card,pin-switches = "Internal Speakers";
362
+
simple-audio-card,routing =
363
+
"MICL", "Mic Jack",
364
+
"Headphones", "HPOL",
365
+
"Headphones", "HPOR",
366
+
"Internal Speakers", "HPOL",
367
+
"Internal Speakers", "HPOR";
368
+
simple-audio-card,widgets =
369
+
"Microphone", "Mic Jack",
370
+
"Headphone", "Headphones",
371
+
"Speaker", "Internal Speakers";
372
+
373
+
simple-audio-card,codec {
374
+
sound-dai = <&rk817>;
375
+
};
376
+
377
+
simple-audio-card,cpu {
378
+
sound-dai = <&i2s1_8ch>;
379
+
};
380
+
};
381
+
382
+
vdd_lcd0: regulator-vdd-lcd0 {
383
+
compatible = "regulator-fixed";
384
+
enable-active-high;
385
+
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
386
+
pinctrl-0 = <&vdd_lcd0_h>;
387
+
pinctrl-names = "default";
388
+
regulator-name = "vdd_lcd0";
389
+
regulator-state-mem {
390
+
regulator-off-in-suspend;
391
+
};
392
+
};
393
+
394
+
vccio_lcd0: regulator-vccio-lcd0 {
395
+
compatible = "regulator-fixed";
396
+
enable-active-high;
397
+
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
398
+
pinctrl-0 = <&vccio_lcd0_h>;
399
+
pinctrl-names = "default";
400
+
regulator-name = "vccio_lcd0";
401
+
regulator-state-mem {
402
+
regulator-off-in-suspend;
403
+
};
404
+
};
405
+
406
+
vdd_lcd1: regulator-vdd-lcd1 {
407
+
compatible = "regulator-fixed";
408
+
enable-active-high;
409
+
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
410
+
pinctrl-0 = <&vdd_lcd1_h>;
411
+
pinctrl-names = "default";
412
+
regulator-name = "vdd_lcd1";
413
+
regulator-state-mem {
414
+
regulator-off-in-suspend;
415
+
};
416
+
};
417
+
418
+
vccio_lcd1: regulator-vccio-lcd1 {
419
+
compatible = "regulator-fixed";
420
+
enable-active-high;
421
+
gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
422
+
pinctrl-0 = <&vccio_lcd1_h>;
423
+
pinctrl-names = "default";
424
+
regulator-name = "vccio_lcd1";
425
+
regulator-state-mem {
426
+
regulator-off-in-suspend;
427
+
};
428
+
};
429
+
430
+
vcc3v3_sd: regulator-vcc3v3-sd {
431
+
compatible = "regulator-fixed";
432
+
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
433
+
pinctrl-0 = <&sdmmc_pwren_l>;
434
+
pinctrl-names = "default";
435
+
regulator-always-on;
436
+
regulator-boot-on;
437
+
regulator-name = "vcc3v3_sd";
438
+
regulator-min-microvolt = <3300000>;
439
+
regulator-max-microvolt = <3300000>;
440
+
vin-supply = <&vccio_sd>;
441
+
};
442
+
443
+
vcc_sys: regulator-vcc-sys {
444
+
compatible = "regulator-fixed";
445
+
regulator-always-on;
446
+
regulator-boot-on;
447
+
regulator-min-microvolt = <3800000>;
448
+
regulator-max-microvolt = <3800000>;
449
+
regulator-name = "vcc_sys";
450
+
};
451
+
452
+
vibrator: pwm-vibrator {
453
+
compatible = "pwm-vibrator";
454
+
pwm-names = "enable";
455
+
pwms = <&pwm14 0 100000 0>;
456
+
vcc-supply = <&vcc_sys>;
457
+
};
458
+
459
+
vcc_wifi: regulator-vcc-wifi {
460
+
compatible = "regulator-fixed";
461
+
enable-active-high;
462
+
gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
463
+
pinctrl-0 = <&vcc_wifi_h>;
464
+
pinctrl-names = "default";
465
+
regulator-always-on;
466
+
regulator-boot-on;
467
+
regulator-min-microvolt = <3300000>;
468
+
regulator-max-microvolt = <3300000>;
469
+
regulator-name = "vcc_wifi";
470
+
};
471
+
};
472
+
473
+
&cpu0 {
474
+
cpu-supply = <&vdd_cpu>;
475
+
};
476
+
477
+
&cpu1 {
478
+
cpu-supply = <&vdd_cpu>;
479
+
};
480
+
481
+
&cpu2 {
482
+
cpu-supply = <&vdd_cpu>;
483
+
};
484
+
485
+
&cpu3 {
486
+
cpu-supply = <&vdd_cpu>;
487
+
};
488
+
489
+
&cru {
490
+
assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
491
+
<&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
492
+
assigned-clock-rates = <32768>, <1200000000>,
493
+
<200000000>, <292500000>;
494
+
};
495
+
496
+
&dsi0 {
497
+
status = "okay";
498
+
#address-cells = <1>;
499
+
#size-cells = <0>;
500
+
501
+
ports {
502
+
dsi0_in: port@0 {
503
+
reg = <0>;
504
+
dsi0_in_vp0: endpoint {
505
+
remote-endpoint = <&vp0_out_dsi0>;
506
+
};
507
+
};
508
+
509
+
dsi0_out: port@1 {
510
+
reg = <1>;
511
+
mipi_out_panel0: endpoint {
512
+
remote-endpoint = <&mipi_in_panel0>;
513
+
};
514
+
};
515
+
};
516
+
517
+
panel0: panel@0 {
518
+
compatible = "anbernic,rg-ds-display-bottom", "jadard,jd9365da-h3";
519
+
reg = <0>;
520
+
backlight = <&backlight0>;
521
+
pinctrl-0 = <&lcd0_rst>;
522
+
pinctrl-names = "default";
523
+
reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
524
+
vdd-supply = <&vdd_lcd0>;
525
+
vccio-supply = <&vccio_lcd0>;
526
+
527
+
port {
528
+
mipi_in_panel0: endpoint {
529
+
remote-endpoint = <&mipi_out_panel0>;
530
+
};
531
+
};
532
+
};
533
+
};
534
+
535
+
&dsi1 {
536
+
status = "okay";
537
+
#address-cells = <1>;
538
+
#size-cells = <0>;
539
+
540
+
ports {
541
+
dsi1_in: port@0 {
542
+
reg = <0>;
543
+
dsi1_in_vp1: endpoint {
544
+
remote-endpoint = <&vp1_out_dsi1>;
545
+
};
546
+
};
547
+
548
+
dsi1_out: port@1 {
549
+
reg = <1>;
550
+
mipi_out_panel1: endpoint {
551
+
remote-endpoint = <&mipi_in_panel1>;
552
+
};
553
+
};
554
+
};
555
+
556
+
panel1: panel@0 {
557
+
compatible = "anbernic,rg-ds-display-top", "jadard,jd9365da-h3";
558
+
reg = <0>;
559
+
backlight = <&backlight1>;
560
+
pinctrl-0 = <&lcd1_rst>;
561
+
pinctrl-names = "default";
562
+
reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>;
563
+
vdd-supply = <&vdd_lcd1>;
564
+
vccio-supply = <&vccio_lcd1>;
565
+
566
+
port {
567
+
mipi_in_panel1: endpoint {
568
+
remote-endpoint = <&mipi_out_panel1>;
569
+
};
570
+
};
571
+
};
572
+
};
573
+
574
+
&dsi_dphy0 {
575
+
status = "okay";
576
+
};
577
+
578
+
&dsi_dphy1 {
579
+
status = "okay";
580
+
};
581
+
582
+
&gpu {
583
+
mali-supply = <&vdd_gpu>;
584
+
status = "okay";
585
+
};
586
+
587
+
&i2c0 {
588
+
status = "okay";
589
+
590
+
rk817: pmic@20 {
591
+
compatible = "rockchip,rk817";
592
+
reg = <0x20>;
593
+
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
594
+
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
595
+
#clock-cells = <1>;
596
+
clock-names = "mclk";
597
+
clock-output-names = "rk808-clkout1", "rk808-clkout2";
598
+
clocks = <&cru I2S1_MCLKOUT_TX>;
599
+
interrupt-parent = <&gpio0>;
600
+
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
601
+
pinctrl-0 = <&i2s1m0_mclk &pmic_int_l>;
602
+
pinctrl-names = "default";
603
+
#sound-dai-cells = <0>;
604
+
system-power-controller;
605
+
wakeup-source;
606
+
607
+
vcc1-supply = <&vcc_sys>;
608
+
vcc2-supply = <&vcc_sys>;
609
+
vcc3-supply = <&vcc_sys>;
610
+
vcc4-supply = <&vcc_sys>;
611
+
vcc5-supply = <&vcc_sys>;
612
+
vcc6-supply = <&vcc_sys>;
613
+
vcc7-supply = <&vcc_sys>;
614
+
vcc8-supply = <&vcc_sys>;
615
+
vcc9-supply = <&dcdc_boost>;
616
+
617
+
regulators {
618
+
vdd_logic: DCDC_REG1 {
619
+
regulator-always-on;
620
+
regulator-boot-on;
621
+
regulator-initial-mode = <0x2>;
622
+
regulator-max-microvolt = <1350000>;
623
+
regulator-min-microvolt = <900000>;
624
+
regulator-name = "vdd_logic";
625
+
regulator-ramp-delay = <6001>;
626
+
regulator-state-mem {
627
+
regulator-on-in-suspend;
628
+
regulator-suspend-microvolt = <900000>;
629
+
};
630
+
};
631
+
632
+
vdd_gpu: DCDC_REG2 {
633
+
regulator-always-on;
634
+
regulator-boot-on;
635
+
regulator-initial-mode = <0x2>;
636
+
regulator-max-microvolt = <1350000>;
637
+
regulator-min-microvolt = <825000>;
638
+
regulator-name = "vdd_gpu";
639
+
regulator-ramp-delay = <6001>;
640
+
regulator-state-mem {
641
+
regulator-off-in-suspend;
642
+
};
643
+
};
644
+
645
+
vcc_ddr: DCDC_REG3 {
646
+
regulator-always-on;
647
+
regulator-boot-on;
648
+
regulator-initial-mode = <0x2>;
649
+
regulator-name = "vcc_ddr";
650
+
regulator-state-mem {
651
+
regulator-on-in-suspend;
652
+
};
653
+
};
654
+
655
+
vcc_3v3: DCDC_REG4 {
656
+
regulator-always-on;
657
+
regulator-boot-on;
658
+
regulator-initial-mode = <0x2>;
659
+
regulator-max-microvolt = <3300000>;
660
+
regulator-min-microvolt = <3300000>;
661
+
regulator-name = "vcc_3v3";
662
+
regulator-state-mem {
663
+
regulator-on-in-suspend;
664
+
regulator-suspend-microvolt = <3300000>;
665
+
};
666
+
};
667
+
668
+
vcca1v8_pmu: LDO_REG1 {
669
+
regulator-always-on;
670
+
regulator-boot-on;
671
+
regulator-max-microvolt = <1800000>;
672
+
regulator-min-microvolt = <1800000>;
673
+
regulator-name = "vcca1v8_pmu";
674
+
regulator-state-mem {
675
+
regulator-on-in-suspend;
676
+
regulator-suspend-microvolt = <1800000>;
677
+
};
678
+
};
679
+
680
+
vdda_0v9: LDO_REG2 {
681
+
regulator-always-on;
682
+
regulator-boot-on;
683
+
regulator-max-microvolt = <900000>;
684
+
regulator-min-microvolt = <900000>;
685
+
regulator-name = "vdda_0v9";
686
+
regulator-state-mem {
687
+
regulator-off-in-suspend;
688
+
};
689
+
};
690
+
691
+
vdda0v9_pmu: LDO_REG3 {
692
+
regulator-always-on;
693
+
regulator-boot-on;
694
+
regulator-max-microvolt = <900000>;
695
+
regulator-min-microvolt = <900000>;
696
+
regulator-name = "vdda0v9_pmu";
697
+
regulator-state-mem {
698
+
regulator-on-in-suspend;
699
+
regulator-suspend-microvolt = <900000>;
700
+
};
701
+
};
702
+
703
+
vccio_acodec: LDO_REG4 {
704
+
regulator-always-on;
705
+
regulator-boot-on;
706
+
regulator-max-microvolt = <3300000>;
707
+
regulator-min-microvolt = <3300000>;
708
+
regulator-name = "vccio_acodec";
709
+
regulator-state-mem {
710
+
regulator-off-in-suspend;
711
+
};
712
+
};
713
+
714
+
vccio_sd: LDO_REG5 {
715
+
regulator-always-on;
716
+
regulator-boot-on;
717
+
regulator-max-microvolt = <3300000>;
718
+
regulator-min-microvolt = <1800000>;
719
+
regulator-name = "vccio_sd";
720
+
regulator-state-mem {
721
+
regulator-off-in-suspend;
722
+
};
723
+
};
724
+
725
+
vcc3v3_pmu: LDO_REG6 {
726
+
regulator-always-on;
727
+
regulator-boot-on;
728
+
regulator-max-microvolt = <3300000>;
729
+
regulator-min-microvolt = <3300000>;
730
+
regulator-name = "vcc3v3_pmu";
731
+
regulator-state-mem {
732
+
regulator-on-in-suspend;
733
+
regulator-suspend-microvolt = <3300000>;
734
+
};
735
+
};
736
+
737
+
vcc_1v8: LDO_REG7 {
738
+
regulator-always-on;
739
+
regulator-boot-on;
740
+
regulator-max-microvolt = <1800000>;
741
+
regulator-min-microvolt = <1800000>;
742
+
regulator-name = "vcc_1v8";
743
+
regulator-state-mem {
744
+
regulator-on-in-suspend;
745
+
};
746
+
};
747
+
748
+
vcc1v8_dvp: LDO_REG8 {
749
+
regulator-always-on;
750
+
regulator-boot-on;
751
+
regulator-max-microvolt = <3300000>;
752
+
regulator-min-microvolt = <1800000>;
753
+
regulator-name = "vcc1v8_dvp";
754
+
regulator-state-mem {
755
+
regulator-off-in-suspend;
756
+
};
757
+
};
758
+
759
+
vcc2v8_dvp: LDO_REG9 {
760
+
regulator-always-on;
761
+
regulator-boot-on;
762
+
regulator-max-microvolt = <2800000>;
763
+
regulator-min-microvolt = <2800000>;
764
+
regulator-name = "vcc2v8_dvp";
765
+
regulator-state-mem {
766
+
regulator-off-in-suspend;
767
+
};
768
+
};
769
+
770
+
dcdc_boost: BOOST {
771
+
regulator-always-on;
772
+
regulator-boot-on;
773
+
regulator-max-microvolt = <5400000>;
774
+
regulator-min-microvolt = <4700000>;
775
+
regulator-name = "boost";
776
+
regulator-state-mem {
777
+
regulator-off-in-suspend;
778
+
};
779
+
};
780
+
781
+
otg_switch: OTG_SWITCH {
782
+
regulator-name = "otg_switch";
783
+
regulator-state-mem {
784
+
regulator-off-in-suspend;
785
+
};
786
+
};
787
+
};
788
+
789
+
rk817_charger: charger {
790
+
monitored-battery = <&battery>;
791
+
rockchip,resistor-sense-micro-ohms = <10000>;
792
+
rockchip,sleep-enter-current-microamp = <150000>;
793
+
rockchip,sleep-filter-current-microamp = <100000>;
794
+
};
795
+
};
796
+
797
+
vdd_cpu: regulator@40 {
798
+
compatible = "silergy,syr827";
799
+
reg = <0x40>;
800
+
fcs,suspend-voltage-selector = <1>;
801
+
regulator-always-on;
802
+
regulator-boot-on;
803
+
regulator-max-microvolt = <1390000>;
804
+
regulator-min-microvolt = <712500>;
805
+
regulator-name = "vdd_cpu";
806
+
regulator-ramp-delay = <2300>;
807
+
vin-supply = <&vcc_sys>;
808
+
regulator-state-mem {
809
+
regulator-off-in-suspend;
810
+
};
811
+
};
812
+
813
+
/*
814
+
* Currently the rk817_charger and the cw2015 don't work together.
815
+
* Disable the cw2015 for now because it performs the same function
816
+
* as the rk817_charger for battery monitoring.
817
+
*/
818
+
cw2015: battery@62 {
819
+
compatible = "cellwise,cw2015";
820
+
reg = <0x62>;
821
+
cellwise,battery-profile = /bits/ 8
822
+
< 0x17 0x67 0x81 0x6F 0x69 0x65 0x63 0x54
823
+
0x75 0x50 0x57 0x56 0x4E 0x4F 0x44 0x35
824
+
0x2C 0x24 0x1E 0x1B 0x24 0x32 0x41 0x4D
825
+
0x1C 0x57 0x0B 0x85 0x34 0x54 0x59 0x6D
826
+
0x85 0x81 0x81 0x84 0x3C 0x1B 0x6C 0x6C
827
+
0x0B 0x41 0x1C 0x4D 0x80 0x95 0xA0 0x14
828
+
0x38 0x7E 0x98 0xA3 0x80 0x89 0x97 0xCB
829
+
0x2F 0x00 0x64 0xA5 0xB5 0xC1 0x46 0xAE>;
830
+
cellwise,monitor-interval-ms = <5000>;
831
+
monitored-battery = <&battery>;
832
+
power-supplies = <&rk817_charger>;
833
+
status = "disabled";
834
+
};
835
+
};
836
+
837
+
&i2c2 {
838
+
clock-frequency = <200000>;
839
+
pinctrl-0 = <&i2c2m1_xfer>;
840
+
pinctrl-names = "default";
841
+
status = "okay";
842
+
843
+
/* awinic,aw87391 at 0x58 */
844
+
/* awinic,aw87391 at 0x5b */
845
+
/* invensense,icm42607p at 0x68 */
846
+
};
847
+
848
+
&i2c3 {
849
+
clock-frequency = <400000>;
850
+
pinctrl-0 = <&i2c3m1_xfer>;
851
+
pinctrl-names = "default";
852
+
status = "okay";
853
+
854
+
touch1: touchscreen@14 {
855
+
compatible = "goodix,gt911";
856
+
reg = <0x14>;
857
+
AVDD28-supply = <&vcc2v8_dvp>;
858
+
interrupt-parent = <&gpio0>;
859
+
interrupts = <RK_PC0 IRQ_TYPE_LEVEL_LOW>;
860
+
irq-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
861
+
panel = <&panel1>;
862
+
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
863
+
touchscreen-size-x = <640>;
864
+
touchscreen-size-y = <480>;
865
+
touchscreen-inverted-x;
866
+
touchscreen-inverted-y;
867
+
pinctrl-0 = <&touch1_rst &touch1_irq>;
868
+
pinctrl-names = "default";
869
+
VDDIO-supply = <&vcc3v3_pmu>;
870
+
};
871
+
};
872
+
873
+
&i2c5 {
874
+
clock-frequency = <400000>;
875
+
pinctrl-0 = <&i2c5m0_xfer>;
876
+
pinctrl-names = "default";
877
+
status = "okay";
878
+
879
+
touch0: touchscreen@14 {
880
+
compatible = "goodix,gt911";
881
+
reg = <0x14>;
882
+
AVDD28-supply = <&vcc2v8_dvp>;
883
+
interrupt-parent = <&gpio0>;
884
+
interrupts = <RK_PB6 IRQ_TYPE_LEVEL_LOW>;
885
+
irq-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
886
+
panel = <&panel0>;
887
+
reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
888
+
touchscreen-size-x = <640>;
889
+
touchscreen-size-y = <480>;
890
+
pinctrl-0 = <&touch0_rst &touch0_irq>;
891
+
pinctrl-names = "default";
892
+
VDDIO-supply = <&vcc3v3_pmu>;
893
+
};
894
+
895
+
/* Unused iSmartWare SW2001 encryption device at 0x3c */
896
+
};
897
+
898
+
&i2s1_8ch {
899
+
pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
900
+
pinctrl-names = "default";
901
+
rockchip,trcm-sync-tx-only;
902
+
status = "okay";
903
+
};
904
+
905
+
&pinctrl {
906
+
gpio-keys {
907
+
vol_keys_l: vol-keys_l {
908
+
rockchip,pins =
909
+
<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
910
+
<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
911
+
};
912
+
913
+
gamepad_keys_l: gamepad-keys-l {
914
+
rockchip,pins =
915
+
<2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
916
+
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
917
+
<2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>,
918
+
<2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>,
919
+
<2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
920
+
<2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
921
+
<2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>,
922
+
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
923
+
<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
924
+
<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
925
+
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
926
+
<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
927
+
<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
928
+
<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
929
+
<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
930
+
<3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
931
+
<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
932
+
};
933
+
};
934
+
935
+
gpio-lcd {
936
+
lcd0_rst: lcd0-rst {
937
+
rockchip,pins =
938
+
<0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
939
+
};
940
+
941
+
lcd1_rst: lcd1-rst {
942
+
rockchip,pins =
943
+
<0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
944
+
};
945
+
};
946
+
947
+
hall-sensor {
948
+
hall_int_l: hal-int-l {
949
+
rockchip,pins =
950
+
<0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
951
+
};
952
+
};
953
+
954
+
hp-detect {
955
+
hp_det: hp-det {
956
+
rockchip,pins =
957
+
<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
958
+
};
959
+
};
960
+
961
+
joy-mux {
962
+
joy_mux_en: joy-mux-en {
963
+
rockchip,pins =
964
+
<3 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
965
+
};
966
+
967
+
joy_mux_config: joy-mux-config {
968
+
rockchip,pins =
969
+
<3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
970
+
<3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
971
+
};
972
+
};
973
+
974
+
pmic {
975
+
pmic_int_l: pmic-int-l {
976
+
rockchip,pins =
977
+
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
978
+
};
979
+
};
980
+
981
+
sdio-pwrseq {
982
+
wifi_enable_h: wifi-enable-h {
983
+
rockchip,pins =
984
+
<4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
985
+
};
986
+
};
987
+
988
+
sdmmc {
989
+
sdmmc_pwren_l: sdmmc-pwren-l {
990
+
rockchip,pins =
991
+
<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
992
+
};
993
+
};
994
+
995
+
touch {
996
+
touch0_rst: touch0-rst {
997
+
rockchip,pins =
998
+
<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
999
+
};
1000
+
1001
+
touch0_irq: touch0-irq {
1002
+
rockchip,pins =
1003
+
<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
1004
+
};
1005
+
1006
+
touch1_rst: touch1-rst {
1007
+
rockchip,pins =
1008
+
<0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
1009
+
};
1010
+
1011
+
touch1_irq: touch1-irq {
1012
+
rockchip,pins =
1013
+
<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
1014
+
};
1015
+
};
1016
+
1017
+
vcc-lcd {
1018
+
vdd_lcd0_h: vdd-lcd0-h {
1019
+
rockchip,pins =
1020
+
<0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
1021
+
};
1022
+
1023
+
vccio_lcd0_h: vccio-lcd0-h {
1024
+
rockchip,pins =
1025
+
<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
1026
+
};
1027
+
1028
+
vdd_lcd1_h: vdd-lcd1-h {
1029
+
rockchip,pins =
1030
+
<0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
1031
+
};
1032
+
1033
+
vccio_lcd1_h: vccio-lcd1-h {
1034
+
rockchip,pins =
1035
+
<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
1036
+
};
1037
+
};
1038
+
1039
+
vcc-wifi {
1040
+
vcc_wifi_h: vcc-wifi-h {
1041
+
rockchip,pins =
1042
+
<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
1043
+
};
1044
+
};
1045
+
1046
+
wifi-irq {
1047
+
wifi_host_wake_irq: wifi-host-wake-irq {
1048
+
rockchip,pins =
1049
+
<4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
1050
+
};
1051
+
};
1052
+
};
1053
+
1054
+
&pmu_io_domains {
1055
+
status = "okay";
1056
+
pmuio1-supply = <&vcc3v3_pmu>;
1057
+
pmuio2-supply = <&vcc3v3_pmu>;
1058
+
vccio1-supply = <&vccio_acodec>;
1059
+
vccio3-supply = <&vccio_sd>;
1060
+
vccio4-supply = <&vcc_3v3>;
1061
+
vccio5-supply = <&vcc_3v3>;
1062
+
vccio6-supply = <&vcc_1v8>;
1063
+
vccio7-supply = <&vcc_3v3>;
1064
+
};
1065
+
1066
+
&pwm5 {
1067
+
pinctrl-0 = <&pwm5_pins>;
1068
+
pinctrl-names = "default";
1069
+
status = "okay";
1070
+
};
1071
+
1072
+
&pwm6 {
1073
+
pinctrl-0 = <&pwm6_pins>;
1074
+
pinctrl-names = "default";
1075
+
status = "okay";
1076
+
};
1077
+
1078
+
&pwm7 {
1079
+
pinctrl-0 = <&pwm7_pins>;
1080
+
pinctrl-names = "default";
1081
+
status = "okay";
1082
+
};
1083
+
1084
+
&pwm12 {
1085
+
pinctrl-0 = <&pwm12m1_pins>;
1086
+
pinctrl-names = "default";
1087
+
status = "okay";
1088
+
};
1089
+
1090
+
&pwm13 {
1091
+
pinctrl-0 = <&pwm13m1_pins>;
1092
+
pinctrl-names = "default";
1093
+
status = "okay";
1094
+
};
1095
+
1096
+
&pwm14 {
1097
+
pinctrl-0 = <&pwm14m0_pins>;
1098
+
pinctrl-names = "default";
1099
+
status = "okay";
1100
+
};
1101
+
1102
+
&saradc {
1103
+
vref-supply = <&vcc_1v8>;
1104
+
status = "okay";
1105
+
};
1106
+
1107
+
&sdhci {
1108
+
bus-width = <8>;
1109
+
max-frequency = <200000000>;
1110
+
no-sd;
1111
+
no-sdio;
1112
+
non-removable;
1113
+
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
1114
+
pinctrl-names = "default";
1115
+
status = "okay";
1116
+
};
1117
+
1118
+
&sdmmc0 {
1119
+
bus-width = <4>;
1120
+
cap-sd-highspeed;
1121
+
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
1122
+
disable-wp;
1123
+
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
1124
+
pinctrl-names = "default";
1125
+
sd-uhs-sdr104;
1126
+
vmmc-supply = <&vcc3v3_sd>;
1127
+
vqmmc-supply = <&vccio_sd>;
1128
+
status = "okay";
1129
+
};
1130
+
1131
+
&sdmmc2 {
1132
+
#address-cells = <1>;
1133
+
bus-width = <4>;
1134
+
cap-sd-highspeed;
1135
+
cap-sdio-irq;
1136
+
keep-power-in-suspend;
1137
+
max-frequency = <100000000>;
1138
+
mmc-pwrseq = <&sdio_pwrseq>;
1139
+
non-removable;
1140
+
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
1141
+
pinctrl-names = "default";
1142
+
sd-uhs-sdr104;
1143
+
#size-cells = <0>;
1144
+
vmmc-supply = <&vcc_wifi>;
1145
+
status = "okay";
1146
+
1147
+
sdio_wifi: wifi@1 {
1148
+
reg = <1>;
1149
+
interrupt-parent = <&gpio4>;
1150
+
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
1151
+
interrupt-names = "host-wake";
1152
+
pinctrl-0 = <&wifi_host_wake_irq>;
1153
+
pinctrl-names = "default";
1154
+
};
1155
+
};
1156
+
1157
+
&tsadc {
1158
+
rockchip,hw-tshut-mode = <0>;
1159
+
rockchip,hw-tshut-polarity = <0>;
1160
+
status = "okay";
1161
+
};
1162
+
1163
+
&uart1 {
1164
+
pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
1165
+
pinctrl-names = "default";
1166
+
uart-has-rtscts;
1167
+
status = "okay";
1168
+
1169
+
bluetooth {
1170
+
compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
1171
+
device-wake-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
1172
+
enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
1173
+
host-wake-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
1174
+
};
1175
+
};
1176
+
1177
+
/* No DMA for a debug serial console. */
1178
+
&uart2 {
1179
+
/delete-property/ dmas;
1180
+
status = "okay";
1181
+
};
1182
+
1183
+
&usb_host0_xhci {
1184
+
dr_mode = "peripheral";
1185
+
phy-names = "usb2-phy";
1186
+
phys = <&usb2phy0_otg>;
1187
+
maximum-speed = "high-speed";
1188
+
status = "okay";
1189
+
};
1190
+
1191
+
&usb_host0_ehci {
1192
+
status = "okay";
1193
+
};
1194
+
1195
+
&usb_host0_ohci {
1196
+
status = "okay";
1197
+
};
1198
+
1199
+
&usb2phy0 {
1200
+
status = "okay";
1201
+
};
1202
+
1203
+
&usb2phy0_otg {
1204
+
status = "okay";
1205
+
};
1206
+
1207
+
&usb2phy1 {
1208
+
status = "okay";
1209
+
};
1210
+
1211
+
&usb2phy1_otg {
1212
+
status = "okay";
1213
+
};
1214
+
1215
+
&vop {
1216
+
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
1217
+
assigned-clock-parents = <&cru PLL_VPLL>, <&cru PLL_VPLL>;
1218
+
status = "okay";
1219
+
};
1220
+
1221
+
&vop_mmu {
1222
+
status = "okay";
1223
+
};
1224
+
1225
+
&vp0 {
1226
+
vp0_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
1227
+
reg = <ROCKCHIP_VOP2_EP_MIPI0>;
1228
+
remote-endpoint = <&dsi0_in_vp0>;
1229
+
};
1230
+
};
1231
+
1232
+
&vp1 {
1233
+
vp1_out_dsi1: endpoint@ROCKCHIP_VOP2_EP_MIPI1 {
1234
+
reg = <ROCKCHIP_VOP2_EP_MIPI1>;
1235
+
remote-endpoint = <&dsi1_in_vp1>;
1236
+
};
1237
+
};
+15
-3
arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts
+15
-3
arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts
···
6
6
7
7
/dts-v1/;
8
8
9
+
#include "rk3568.dtsi"
9
10
#include "rk3568-qnap-tsx33.dtsi"
10
11
11
12
/ {
···
18
17
};
19
18
};
20
19
21
-
/* connected to sata2 */
22
-
&combphy2 {
20
+
/* Connected to usb_host0_xhci */
21
+
&combphy0 {
23
22
status = "okay";
24
23
};
25
24
···
49
48
pagesize = <16>;
50
49
read-only;
51
50
};
51
+
};
52
+
53
+
&keys {
54
+
pinctrl-names = "default";
55
+
pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
56
+
57
+
key-copy {
58
+
label = "copy";
59
+
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
60
+
linux,code = <KEY_COPY>;
61
+
};
52
62
};
53
63
54
64
&leds {
···
104
92
};
105
93
};
106
94
107
-
&sata2 {
95
+
&sata1 {
108
96
status = "okay";
109
97
};
110
98
+15
-3
arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
+15
-3
arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
···
6
6
7
7
/dts-v1/;
8
8
9
+
#include "rk3568.dtsi"
9
10
#include "rk3568-qnap-tsx33.dtsi"
10
11
11
12
/ {
···
28
27
};
29
28
};
30
29
31
-
/* connected to sata2 */
32
-
&combphy2 {
30
+
/* Connected to usb_host0_xhci */
31
+
&combphy0 {
33
32
status = "okay";
34
33
};
35
34
···
59
58
pagesize = <16>;
60
59
read-only;
61
60
};
61
+
};
62
+
63
+
&keys {
64
+
pinctrl-names = "default";
65
+
pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
66
+
67
+
key-copy {
68
+
label = "copy";
69
+
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
70
+
linux,code = <KEY_COPY>;
71
+
};
62
72
};
63
73
64
74
&leds {
···
162
150
};
163
151
};
164
152
165
-
&sata2 {
153
+
&sata1 {
166
154
status = "okay";
167
155
};
168
156
+7
-14
arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi
+7
-14
arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi
···
1
1
#include <dt-bindings/input/input.h>
2
2
#include <dt-bindings/leds/common.h>
3
3
#include <dt-bindings/gpio/gpio.h>
4
-
#include "rk3568.dtsi"
5
4
6
5
/ {
7
6
aliases {
···
12
13
stdout-path = "serial2:115200n8";
13
14
};
14
15
15
-
keys {
16
+
keys: keys {
16
17
compatible = "gpio-keys";
17
-
pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
18
+
pinctrl-0 = <&reset_button_pin>;
18
19
pinctrl-names = "default";
19
-
20
-
key-copy {
21
-
label = "copy";
22
-
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
23
-
linux,code = <KEY_COPY>;
24
-
};
25
20
26
21
key-reset {
27
22
label = "reset";
···
106
113
};
107
114
};
108
115
109
-
/* connected to usb_host0_xhci */
110
-
&combphy0 {
116
+
/* Connected USB3 on TS133 / SATA1 on all the others */
117
+
&combphy1 {
111
118
status = "okay";
112
119
};
113
120
114
-
/* connected to sata1 */
115
-
&combphy1 {
121
+
/* Connected to SATA2 */
122
+
&combphy2 {
116
123
status = "okay";
117
124
};
118
125
···
478
485
status = "okay";
479
486
};
480
487
481
-
&sata1 {
488
+
&sata2 {
482
489
status = "okay";
483
490
};
484
491
+204
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts
+204
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include <dt-bindings/leds/common.h>
9
+
#include <dt-bindings/gpio/gpio.h>
10
+
#include <dt-bindings/pinctrl/rockchip.h>
11
+
#include "rk3568-radxa-cm3j.dtsi"
12
+
13
+
/ {
14
+
model = "Radxa CM3J on RPi CM4 IO Board";
15
+
compatible = "radxa,cm3j-rpi-cm4", "radxa,cm3j", "rockchip,rk3568";
16
+
17
+
aliases {
18
+
ethernet0 = &gmac1;
19
+
mmc1 = &sdmmc0;
20
+
rtc0 = &pcf85063;
21
+
};
22
+
23
+
chosen {
24
+
stdout-path = "serial2:1500000n8";
25
+
};
26
+
27
+
hdmi-con {
28
+
compatible = "hdmi-connector";
29
+
type = "a";
30
+
31
+
port {
32
+
hdmi_con_in: endpoint {
33
+
remote-endpoint = <&hdmi_out_con>;
34
+
};
35
+
};
36
+
};
37
+
38
+
leds-1 {
39
+
compatible = "gpio-leds";
40
+
41
+
led-1 {
42
+
color = <LED_COLOR_ID_RED>;
43
+
default-state = "on";
44
+
function = LED_FUNCTION_POWER;
45
+
gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
46
+
pinctrl-names = "default";
47
+
pinctrl-0 = <&npwr_led>;
48
+
};
49
+
50
+
led-2 {
51
+
color = <LED_COLOR_ID_GREEN>;
52
+
default-state = "on";
53
+
function = LED_FUNCTION_STATUS;
54
+
gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
55
+
linux,default-trigger = "heartbeat";
56
+
pinctrl-names = "default";
57
+
pinctrl-0 = <&pi_nled_activity>;
58
+
};
59
+
};
60
+
61
+
dc12v: regulator-12v0 {
62
+
compatible = "regulator-fixed";
63
+
regulator-name = "dc12v";
64
+
regulator-always-on;
65
+
regulator-boot-on;
66
+
regulator-min-microvolt = <12000000>;
67
+
regulator-max-microvolt = <12000000>;
68
+
};
69
+
70
+
dc3v3_pcie: regulator-3v3-2 {
71
+
compatible = "regulator-fixed";
72
+
regulator-name = "dc3v3_pcie";
73
+
regulator-always-on;
74
+
regulator-boot-on;
75
+
regulator-min-microvolt = <3300000>;
76
+
regulator-max-microvolt = <3300000>;
77
+
vin-supply = <&dc12v>;
78
+
};
79
+
80
+
gpio_vref: regulator-3v3-3 {
81
+
compatible = "regulator-fixed";
82
+
regulator-name = "gpio_vref";
83
+
regulator-always-on;
84
+
regulator-boot-on;
85
+
regulator-min-microvolt = <3300000>;
86
+
regulator-max-microvolt = <3300000>;
87
+
vin-supply = <&dc3v3>;
88
+
};
89
+
90
+
dc5v: regulator-5v0 {
91
+
compatible = "regulator-fixed";
92
+
regulator-name = "dc5v";
93
+
regulator-always-on;
94
+
regulator-boot-on;
95
+
regulator-min-microvolt = <5000000>;
96
+
regulator-max-microvolt = <5000000>;
97
+
vin-supply = <&dc12v>;
98
+
};
99
+
};
100
+
101
+
&combphy0 {
102
+
status = "okay";
103
+
};
104
+
105
+
&combphy2 {
106
+
status = "okay";
107
+
};
108
+
109
+
&gmac1 {
110
+
status = "okay";
111
+
};
112
+
113
+
&gpio0 {
114
+
nextrst-hog {
115
+
gpio-hog;
116
+
/*
117
+
* GPIO_ACTIVE_LOW + output-low here means that the pin is set
118
+
* to high, because output-low decides the value pre-inversion.
119
+
*/
120
+
gpios = <RK_PC0 GPIO_ACTIVE_LOW>;
121
+
line-name = "nEXTRST";
122
+
output-low;
123
+
};
124
+
};
125
+
126
+
&hdmi {
127
+
status = "okay";
128
+
};
129
+
130
+
&hdmi_sound {
131
+
status = "okay";
132
+
};
133
+
134
+
&i2c0 {
135
+
emc2301: fan-controller@2f {
136
+
compatible = "microchip,emc2301", "microchip,emc2305";
137
+
reg = <0x2f>;
138
+
#address-cells = <1>;
139
+
#size-cells = <0>;
140
+
#pwm-cells = <3>;
141
+
142
+
fan@0 {
143
+
reg = <0x0>;
144
+
pwms = <&emc2301 26000 0 1>;
145
+
#cooling-cells = <2>;
146
+
};
147
+
};
148
+
149
+
pcf85063: rtc@51 {
150
+
compatible = "nxp,pcf85063a";
151
+
reg = <0x51>;
152
+
wakeup-source;
153
+
};
154
+
};
155
+
156
+
&i2s0_8ch {
157
+
status = "okay";
158
+
};
159
+
160
+
&pinctrl {
161
+
leds {
162
+
npwr_led: npwr-led {
163
+
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
164
+
};
165
+
166
+
pi_nled_activity: pi-nled-activity {
167
+
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
168
+
};
169
+
};
170
+
};
171
+
172
+
&pcie2x1 {
173
+
vpcie3v3-supply = <&dc3v3_pcie>;
174
+
status = "okay";
175
+
};
176
+
177
+
&sdmmc0 {
178
+
bus-width = <4>;
179
+
cap-sd-highspeed;
180
+
broken-cd;
181
+
disable-wp;
182
+
no-mmc;
183
+
no-sdio;
184
+
pinctrl-names = "default";
185
+
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
186
+
vmmc-supply = <&dc3v3>;
187
+
status = "okay";
188
+
};
189
+
190
+
&uart2 {
191
+
status = "okay";
192
+
};
193
+
194
+
&usb2phy0 {
195
+
status = "okay";
196
+
};
197
+
198
+
&usb2phy0_otg {
199
+
status = "okay";
200
+
};
201
+
202
+
&usb_host0_xhci {
203
+
status = "okay";
204
+
};
+558
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi
+558
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd.
4
+
*/
5
+
6
+
#include <dt-bindings/leds/common.h>
7
+
#include <dt-bindings/gpio/gpio.h>
8
+
#include <dt-bindings/pinctrl/rockchip.h>
9
+
#include <dt-bindings/soc/rockchip,vop2.h>
10
+
#include "rk3568.dtsi"
11
+
12
+
/ {
13
+
aliases {
14
+
mmc0 = &sdhci;
15
+
mmc2 = &sdmmc2;
16
+
};
17
+
18
+
gmac1_clkin: clock-125m {
19
+
compatible = "fixed-clock";
20
+
clock-frequency = <125000000>;
21
+
clock-output-names = "gmac1_clkin";
22
+
#clock-cells = <0>;
23
+
};
24
+
25
+
leds-0 {
26
+
compatible = "gpio-leds";
27
+
28
+
led-0 {
29
+
color = <LED_COLOR_ID_GREEN>;
30
+
default-state = "on";
31
+
function = LED_FUNCTION_POWER;
32
+
gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
33
+
pinctrl-names = "default";
34
+
pinctrl-0 = <&gpio0_b4_led>;
35
+
};
36
+
};
37
+
38
+
vcc3v3_sys: regulator-3v3-0 {
39
+
compatible = "regulator-fixed";
40
+
regulator-name = "vcc3v3_sys";
41
+
regulator-always-on;
42
+
regulator-boot-on;
43
+
regulator-min-microvolt = <3300000>;
44
+
regulator-max-microvolt = <3300000>;
45
+
vin-supply = <&dc5v>;
46
+
};
47
+
48
+
vcc_3v3_1: regulator-3v3-1 {
49
+
compatible = "regulator-fixed";
50
+
regulator-name = "vcc_3v3_1";
51
+
regulator-always-on;
52
+
regulator-boot-on;
53
+
regulator-min-microvolt = <3300000>;
54
+
regulator-max-microvolt = <3300000>;
55
+
vin-supply = <&vcc3v3_sys>;
56
+
};
57
+
58
+
sdio_pwrseq: sdio-pwrseq {
59
+
compatible = "mmc-pwrseq-simple";
60
+
clocks = <&rk809 1>;
61
+
clock-names = "ext_clock";
62
+
pinctrl-names = "default";
63
+
pinctrl-0 = <&wifi_reg_on_h_gpio3_d4>;
64
+
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
65
+
};
66
+
};
67
+
68
+
&cpu0 {
69
+
cpu-supply = <&vdd_cpu>;
70
+
};
71
+
72
+
&cpu1 {
73
+
cpu-supply = <&vdd_cpu>;
74
+
};
75
+
76
+
&cpu2 {
77
+
cpu-supply = <&vdd_cpu>;
78
+
};
79
+
80
+
&cpu3 {
81
+
cpu-supply = <&vdd_cpu>;
82
+
};
83
+
84
+
&gmac1 {
85
+
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
86
+
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
87
+
clock_in_out = "input";
88
+
phy-handle = <&rgmii_phy1>;
89
+
phy-mode = "rgmii-id";
90
+
phy-supply = <&vcc_3v3_1>;
91
+
pinctrl-names = "default";
92
+
pinctrl-0 = <&gmac1m1_miim
93
+
&gmac1m1_clkinout
94
+
&gmac1m1_rx_bus2
95
+
&gmac1m1_tx_bus2
96
+
&gmac1m1_rgmii_clk
97
+
&gmac1m1_rgmii_bus>;
98
+
};
99
+
100
+
&gpu {
101
+
mali-supply = <&vdd_gpu>;
102
+
status = "okay";
103
+
};
104
+
105
+
&hdmi {
106
+
avdd-0v9-supply = <&vdda0v9_image>;
107
+
avdd-1v8-supply = <&vcca1v8_image>;
108
+
};
109
+
110
+
&hdmi_in {
111
+
hdmi_in_vp0: endpoint {
112
+
remote-endpoint = <&vp0_out_hdmi>;
113
+
};
114
+
};
115
+
116
+
&hdmi_out {
117
+
hdmi_out_con: endpoint {
118
+
remote-endpoint = <&hdmi_con_in>;
119
+
};
120
+
};
121
+
122
+
&i2c0 {
123
+
status = "okay";
124
+
125
+
rk809: pmic@20 {
126
+
compatible = "rockchip,rk809";
127
+
reg = <0x20>;
128
+
#clock-cells = <1>;
129
+
clock-output-names = "rk809-clkout1", "rk809-clkout2";
130
+
interrupt-parent = <&gpio0>;
131
+
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
132
+
pinctrl-names = "default";
133
+
pinctrl-0 = <&pmic_int_l>;
134
+
system-power-controller;
135
+
vcc1-supply = <&vcc3v3_sys>;
136
+
vcc2-supply = <&vcc3v3_sys>;
137
+
vcc3-supply = <&vcc3v3_sys>;
138
+
vcc4-supply = <&vcc3v3_sys>;
139
+
vcc5-supply = <&vcc3v3_sys>;
140
+
vcc6-supply = <&vcc3v3_sys>;
141
+
vcc7-supply = <&vcc3v3_sys>;
142
+
vcc8-supply = <&vcc3v3_sys>;
143
+
vcc9-supply = <&vcc3v3_sys>;
144
+
wakeup-source;
145
+
146
+
regulators {
147
+
vdd_logic: DCDC_REG1 {
148
+
regulator-name = "vdd_logic";
149
+
regulator-always-on;
150
+
regulator-boot-on;
151
+
regulator-initial-mode = <0x2>;
152
+
regulator-min-microvolt = <500000>;
153
+
regulator-max-microvolt = <1350000>;
154
+
regulator-ramp-delay = <6001>;
155
+
156
+
regulator-state-mem {
157
+
regulator-off-in-suspend;
158
+
};
159
+
};
160
+
161
+
vdd_gpu: DCDC_REG2 {
162
+
regulator-name = "vdd_gpu";
163
+
regulator-initial-mode = <0x2>;
164
+
regulator-min-microvolt = <500000>;
165
+
regulator-max-microvolt = <1350000>;
166
+
regulator-ramp-delay = <6001>;
167
+
168
+
regulator-state-mem {
169
+
regulator-off-in-suspend;
170
+
};
171
+
};
172
+
173
+
vcc_ddr: DCDC_REG3 {
174
+
regulator-name = "vcc_ddr";
175
+
regulator-always-on;
176
+
regulator-boot-on;
177
+
regulator-initial-mode = <0x2>;
178
+
179
+
regulator-state-mem {
180
+
regulator-on-in-suspend;
181
+
};
182
+
};
183
+
184
+
vdd_npu: DCDC_REG4 {
185
+
regulator-name = "vdd_npu";
186
+
regulator-initial-mode = <0x2>;
187
+
regulator-min-microvolt = <500000>;
188
+
regulator-max-microvolt = <1350000>;
189
+
regulator-ramp-delay = <6001>;
190
+
191
+
regulator-state-mem {
192
+
regulator-off-in-suspend;
193
+
};
194
+
};
195
+
196
+
dc1v8: vccio_flash: vcc_1v8: DCDC_REG5 {
197
+
regulator-name = "vcc_1v8";
198
+
regulator-always-on;
199
+
regulator-boot-on;
200
+
regulator-min-microvolt = <1800000>;
201
+
regulator-max-microvolt = <1800000>;
202
+
203
+
regulator-state-mem {
204
+
regulator-off-in-suspend;
205
+
};
206
+
};
207
+
208
+
vdda0v9_image: LDO_REG1 {
209
+
regulator-name = "vdda0v9_image";
210
+
regulator-min-microvolt = <900000>;
211
+
regulator-max-microvolt = <900000>;
212
+
213
+
regulator-state-mem {
214
+
regulator-off-in-suspend;
215
+
};
216
+
};
217
+
218
+
vdda_0v9: LDO_REG2 {
219
+
regulator-name = "vdda_0v9";
220
+
regulator-always-on;
221
+
regulator-boot-on;
222
+
regulator-min-microvolt = <900000>;
223
+
regulator-max-microvolt = <900000>;
224
+
225
+
regulator-state-mem {
226
+
regulator-off-in-suspend;
227
+
};
228
+
};
229
+
230
+
vdda0v9_pmu: LDO_REG3 {
231
+
regulator-name = "vdda0v9_pmu";
232
+
regulator-always-on;
233
+
regulator-boot-on;
234
+
regulator-min-microvolt = <900000>;
235
+
regulator-max-microvolt = <900000>;
236
+
237
+
regulator-state-mem {
238
+
regulator-on-in-suspend;
239
+
regulator-suspend-microvolt = <900000>;
240
+
};
241
+
};
242
+
243
+
vccio_acodec: LDO_REG4 {
244
+
regulator-name = "vccio_acodec";
245
+
regulator-min-microvolt = <3300000>;
246
+
regulator-max-microvolt = <3300000>;
247
+
248
+
regulator-state-mem {
249
+
regulator-off-in-suspend;
250
+
};
251
+
};
252
+
253
+
vccio_sd: LDO_REG5 {
254
+
regulator-name = "vccio_sd";
255
+
regulator-always-on;
256
+
regulator-boot-on;
257
+
regulator-min-microvolt = <1800000>;
258
+
regulator-max-microvolt = <3300000>;
259
+
260
+
regulator-state-mem {
261
+
regulator-off-in-suspend;
262
+
};
263
+
};
264
+
265
+
vcc3v3_pmu: LDO_REG6 {
266
+
regulator-name = "vcc3v3_pmu";
267
+
regulator-always-on;
268
+
regulator-boot-on;
269
+
regulator-min-microvolt = <3300000>;
270
+
regulator-max-microvolt = <3300000>;
271
+
272
+
regulator-state-mem {
273
+
regulator-on-in-suspend;
274
+
regulator-suspend-microvolt = <3300000>;
275
+
};
276
+
};
277
+
278
+
vcca_1v8: LDO_REG7 {
279
+
regulator-name = "vcca_1v8";
280
+
regulator-always-on;
281
+
regulator-boot-on;
282
+
regulator-min-microvolt = <1800000>;
283
+
regulator-max-microvolt = <1800000>;
284
+
285
+
regulator-state-mem {
286
+
regulator-off-in-suspend;
287
+
};
288
+
};
289
+
290
+
vcca1v8_pmu: LDO_REG8 {
291
+
regulator-name = "vcca1v8_pmu";
292
+
regulator-always-on;
293
+
regulator-boot-on;
294
+
regulator-min-microvolt = <1800000>;
295
+
regulator-max-microvolt = <1800000>;
296
+
297
+
regulator-state-mem {
298
+
regulator-on-in-suspend;
299
+
regulator-suspend-microvolt = <1800000>;
300
+
};
301
+
};
302
+
303
+
vcca1v8_image: LDO_REG9 {
304
+
regulator-name = "vcca1v8_image";
305
+
regulator-min-microvolt = <1800000>;
306
+
regulator-max-microvolt = <1800000>;
307
+
308
+
regulator-state-mem {
309
+
regulator-off-in-suspend;
310
+
};
311
+
};
312
+
313
+
dc3v3: vcc_3v3: SWITCH_REG1 {
314
+
regulator-name = "vcc_3v3";
315
+
regulator-always-on;
316
+
regulator-boot-on;
317
+
318
+
regulator-state-mem {
319
+
regulator-off-in-suspend;
320
+
};
321
+
};
322
+
323
+
vcc3v3_sd: SWITCH_REG2 {
324
+
regulator-name = "vcc3v3_sd";
325
+
regulator-always-on;
326
+
regulator-boot-on;
327
+
328
+
regulator-state-mem {
329
+
regulator-off-in-suspend;
330
+
};
331
+
};
332
+
};
333
+
};
334
+
335
+
vdd_cpu: regulator@40 {
336
+
compatible = "silergy,syr827";
337
+
reg = <0x40>;
338
+
fcs,suspend-voltage-selector = <1>;
339
+
regulator-name = "vdd_cpu";
340
+
regulator-always-on;
341
+
regulator-boot-on;
342
+
regulator-min-microvolt = <712500>;
343
+
regulator-max-microvolt = <1390000>;
344
+
regulator-ramp-delay = <2300>;
345
+
vin-supply = <&dc5v>;
346
+
};
347
+
};
348
+
349
+
&i2c2 {
350
+
status = "okay";
351
+
352
+
eeprom@50 {
353
+
compatible = "belling,bl24c16a", "atmel,24c16";
354
+
reg = <0x50>;
355
+
pagesize = <16>;
356
+
read-only;
357
+
vcc-supply = <&gpio_vref>;
358
+
};
359
+
};
360
+
361
+
&mdio1 {
362
+
rgmii_phy1: ethernet-phy@0 {
363
+
compatible = "ethernet-phy-id001c.c916";
364
+
reg = <0x0>;
365
+
pinctrl-names = "default";
366
+
pinctrl-0 = <&gmac1_rstn_gpio3_b0>; // GPIO4_C3
367
+
reset-assert-us = <20000>;
368
+
reset-deassert-us = <100000>;
369
+
reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
370
+
};
371
+
};
372
+
373
+
&pinctrl {
374
+
bluetooth {
375
+
bt_reg_on_h_gpio4_b2: bt-reg-on-h-gpio4-b2 {
376
+
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
377
+
};
378
+
379
+
bt_wake_host_h_gpio4_b4: bt-wake-host-h-gpio4-b4 {
380
+
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
381
+
};
382
+
383
+
host_wake_bt_h_gpio4_b5: host-wake-bt-h-gpio4-b5 {
384
+
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
385
+
};
386
+
};
387
+
388
+
ethernet {
389
+
gmac1_rstn_gpio3_b0: gmac1-rstn-gpio3-b0 {
390
+
rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
391
+
};
392
+
};
393
+
394
+
leds {
395
+
gpio0_b4_led: gpio0-b4-led {
396
+
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
397
+
};
398
+
};
399
+
400
+
pcie {
401
+
pcie20_clkreqnm2: pcie20_clkreqnm2 {
402
+
rockchip,pins = <1 RK_PB0 4 &pcfg_pull_none>;
403
+
};
404
+
405
+
pcie_nrst: pcie-nrst {
406
+
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
407
+
};
408
+
};
409
+
410
+
pmic {
411
+
pmic_int_l: pmic-int-l {
412
+
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
413
+
};
414
+
};
415
+
416
+
wifi {
417
+
wifi_reg_on_h_gpio3_d4: wifi-reg-on-h-gpio3-d4 {
418
+
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
419
+
};
420
+
};
421
+
};
422
+
423
+
&pcie2x1 {
424
+
pinctrl-names = "default";
425
+
pinctrl-0 = <&pcie20_clkreqnm2 &pcie_nrst>;
426
+
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
427
+
supports-clkreq;
428
+
};
429
+
430
+
&pmu_io_domains {
431
+
pmuio1-supply = <&vcc3v3_pmu>;
432
+
pmuio2-supply = <&vcc_3v3>;
433
+
vccio1-supply = <&vccio_acodec>;
434
+
vccio2-supply = <&vccio_flash>;
435
+
vccio3-supply = <&vccio_sd>;
436
+
vccio4-supply = <&vcc_1v8>;
437
+
vccio5-supply = <&vcc_3v3>;
438
+
vccio6-supply = <&vcc_1v8>;
439
+
vccio7-supply = <&vcc_3v3>;
440
+
status = "okay";
441
+
};
442
+
443
+
&saradc {
444
+
vref-supply = <&vcca_1v8>;
445
+
status = "okay";
446
+
};
447
+
448
+
&sdhci {
449
+
bus-width = <8>;
450
+
cap-mmc-highspeed;
451
+
mmc-hs200-1_8v;
452
+
max-frequency = <200000000>;
453
+
no-sd;
454
+
no-sdio;
455
+
non-removable;
456
+
pinctrl-names = "default";
457
+
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
458
+
vmmc-supply = <&vcc_3v3>;
459
+
vqmmc-supply = <&vccio_flash>;
460
+
status = "okay";
461
+
};
462
+
463
+
&sdmmc2 {
464
+
#address-cells = <1>;
465
+
bus-width = <4>;
466
+
cap-sd-highspeed;
467
+
cap-sdio-irq;
468
+
disable-wp;
469
+
keep-power-in-suspend;
470
+
max-frequency = <200000000>;
471
+
mmc-pwrseq = <&sdio_pwrseq>;
472
+
no-mmc;
473
+
no-sd;
474
+
non-removable;
475
+
pinctrl-names = "default";
476
+
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
477
+
sd-uhs-sdr104;
478
+
#size-cells = <0>;
479
+
status = "okay";
480
+
481
+
wifi@1 {
482
+
compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
483
+
reg = <1>;
484
+
};
485
+
};
486
+
487
+
&sfc {
488
+
#address-cells = <1>;
489
+
#size-cells = <0>;
490
+
status = "okay";
491
+
492
+
flash@0 {
493
+
compatible = "jedec,spi-nor";
494
+
reg = <0>;
495
+
spi-max-frequency = <104000000>;
496
+
spi-rx-bus-width = <4>;
497
+
spi-tx-bus-width = <1>;
498
+
vcc-supply = <&vccio_flash>;
499
+
};
500
+
};
501
+
502
+
&tsadc {
503
+
rockchip,hw-tshut-mode = <1>;
504
+
rockchip,hw-tshut-polarity = <0>;
505
+
status = "okay";
506
+
};
507
+
508
+
&uart2 {
509
+
status = "okay";
510
+
};
511
+
512
+
&uart8 {
513
+
dma-names = "tx", "rx";
514
+
pinctrl-names = "default";
515
+
pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
516
+
uart-has-rtscts;
517
+
status = "okay";
518
+
519
+
bluetooth {
520
+
compatible = "brcm,bcm4345c5";
521
+
clocks = <&rk809 1>;
522
+
clock-names = "lpo";
523
+
device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
524
+
host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
525
+
max-speed = <1500000>;
526
+
pinctrl-names = "default";
527
+
pinctrl-0 = <&bt_reg_on_h_gpio4_b2
528
+
&bt_wake_host_h_gpio4_b4
529
+
&host_wake_bt_h_gpio4_b5>;
530
+
shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
531
+
vbat-supply = <&vcc_3v3_1>;
532
+
vddio-supply = <&vcc_1v8>;
533
+
};
534
+
};
535
+
536
+
&usb_host0_xhci {
537
+
extcon = <&usb2phy0>;
538
+
maximum-speed = "high-speed";
539
+
phys = <&usb2phy0_otg>;
540
+
phy-names = "usb2-phy";
541
+
};
542
+
543
+
&vop {
544
+
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
545
+
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
546
+
status = "okay";
547
+
};
548
+
549
+
&vop_mmu {
550
+
status = "okay";
551
+
};
552
+
553
+
&vp0 {
554
+
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
555
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
556
+
remote-endpoint = <&hdmi_in_vp0>;
557
+
};
558
+
};
+2
-2
arch/arm64/boot/dts/rockchip/rk3568.dtsi
+2
-2
arch/arm64/boot/dts/rockchip/rk3568.dtsi
···
185
185
<0x0 0xf2000000 0x0 0x00100000>;
186
186
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
187
187
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
188
-
<0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
188
+
<0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
189
189
reg-names = "dbi", "apb", "config";
190
190
resets = <&cru SRST_PCIE30X1_POWERUP>;
191
191
reset-names = "pipe";
···
238
238
<0x0 0xf0000000 0x0 0x00100000>;
239
239
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
240
240
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
241
-
<0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
241
+
<0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
242
242
reg-names = "dbi", "apb", "config";
243
243
resets = <&cru SRST_PCIE30X2_POWERUP>;
244
244
reset-names = "pipe";
+1
-1
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
···
1022
1022
power-domains = <&power RK3568_PD_PIPE>;
1023
1023
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1024
1024
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
1025
-
<0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
1025
+
<0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
1026
1026
resets = <&cru SRST_PCIE20_POWERUP>;
1027
1027
reset-names = "pipe";
1028
1028
#address-cells = <3>;
+22
arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
+22
arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
···
223
223
vin-supply = <&vcc_3v3_s3>;
224
224
};
225
225
226
+
vcc3v3_sd: regulator-vcc-3v3-sd {
227
+
compatible = "regulator-fixed";
228
+
enable-active-high;
229
+
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
230
+
pinctrl-names = "default";
231
+
pinctrl-0 = <&sdmmc_pwren>;
232
+
regulator-name = "vcc3v3_sd";
233
+
regulator-min-microvolt = <3300000>;
234
+
regulator-max-microvolt = <3300000>;
235
+
vin-supply = <&vcc_3v3_s0>;
236
+
};
237
+
226
238
vcc_ufs_s0: regulator-vcc-ufs-s0 {
227
239
compatible = "regulator-fixed";
228
240
regulator-name = "vcc_ufs_s0";
···
916
904
};
917
905
};
918
906
907
+
sdmmc {
908
+
sdmmc_pwren: sdmmc-pwren {
909
+
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
910
+
};
911
+
};
912
+
919
913
usb {
920
914
usb_host_pwren: usb-host-pwren {
921
915
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
···
976
958
bus-width = <4>;
977
959
cap-mmc-highspeed;
978
960
cap-sd-highspeed;
961
+
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
979
962
disable-wp;
980
963
max-frequency = <200000000>;
981
964
no-sdio;
982
965
no-mmc;
966
+
pinctrl-names = "default";
967
+
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
983
968
sd-uhs-sdr104;
969
+
vmmc-supply = <&vcc3v3_sd>;
984
970
vqmmc-supply = <&vccio_sd_s0>;
985
971
status = "okay";
986
972
};
+22
-1
arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
+22
-1
arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
···
192
192
regulator-name = "vcc_3v3_s0";
193
193
vin-supply = <&vcc_3v3_s3>;
194
194
};
195
+
196
+
vcc3v3_sd: regulator-vcc-3v3-sd {
197
+
compatible = "regulator-fixed";
198
+
enable-active-high;
199
+
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
200
+
pinctrl-names = "default";
201
+
pinctrl-0 = <&sdmmc_pwren>;
202
+
regulator-name = "vcc3v3_sd";
203
+
regulator-min-microvolt = <3300000>;
204
+
regulator-max-microvolt = <3300000>;
205
+
vin-supply = <&vcc_3v3_s0>;
206
+
};
195
207
};
196
208
197
209
&combphy0_ps {
···
738
726
};
739
727
};
740
728
729
+
sdmmc {
730
+
sdmmc_pwren: sdmmc-pwren {
731
+
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
732
+
};
733
+
};
734
+
741
735
usb {
742
736
usb_otg0_pwren_h: usb-otg0-pwren-h {
743
737
rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
···
769
751
bus-width = <4>;
770
752
cap-mmc-highspeed;
771
753
cap-sd-highspeed;
754
+
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
772
755
disable-wp;
773
756
no-mmc;
774
757
no-sdio;
758
+
pinctrl-names = "default";
759
+
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
775
760
sd-uhs-sdr104;
776
-
vmmc-supply = <&vcc_3v3_s3>;
761
+
vmmc-supply = <&vcc3v3_sd>;
777
762
vqmmc-supply = <&vccio_sd_s0>;
778
763
status = "okay";
779
764
};
+7
arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi
+7
arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3576.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3576.dtsi
···
1865
1865
assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
1866
1866
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1867
1867
power-domains = <&power RK3576_PD_USB>;
1868
-
pinctrl-0 = <&ufs_refclk>;
1868
+
pinctrl-0 = <&ufs_refclk &ufs_rstgpio>;
1869
1869
pinctrl-names = "default";
1870
1870
resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
1871
1871
<&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
+2
-2
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+2
-2
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
···
2019
2019
power-domains = <&power RK3588_PD_PCIE>;
2020
2020
ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
2021
2021
<0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
2022
-
<0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
2022
+
<0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
2023
2023
reg = <0xa 0x40c00000 0x0 0x00400000>,
2024
2024
<0x0 0xfe180000 0x0 0x00010000>,
2025
2025
<0x0 0xf3000000 0x0 0x00100000>;
···
2071
2071
power-domains = <&power RK3588_PD_PCIE>;
2072
2072
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
2073
2073
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
2074
-
<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
2074
+
<0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
2075
2075
reg = <0xa 0x41000000 0x0 0x00400000>,
2076
2076
<0x0 0xfe190000 0x0 0x00010000>,
2077
2077
<0x0 0xf4000000 0x0 0x00100000>;
+3
-3
arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+3
-3
arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
···
375
375
power-domains = <&power RK3588_PD_PCIE>;
376
376
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
377
377
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
378
-
<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
378
+
<0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
379
379
reg = <0xa 0x40000000 0x0 0x00400000>,
380
380
<0x0 0xfe150000 0x0 0x00010000>,
381
381
<0x0 0xf0000000 0x0 0x00100000>;
···
462
462
power-domains = <&power RK3588_PD_PCIE>;
463
463
ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
464
464
<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
465
-
<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
465
+
<0x03000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
466
466
reg = <0xa 0x40400000 0x0 0x00400000>,
467
467
<0x0 0xfe160000 0x0 0x00010000>,
468
468
<0x0 0xf1000000 0x0 0x00100000>;
···
512
512
power-domains = <&power RK3588_PD_PCIE>;
513
513
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
514
514
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
515
-
<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
515
+
<0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
516
516
reg = <0xa 0x40800000 0x0 0x00400000>,
517
517
<0x0 0xfe170000 0x0 0x00010000>,
518
518
<0x0 0xf2000000 0x0 0x00100000>;
+1
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+1
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts