Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - relocate CSR access code
As the common hw_data files are growing and the adf_hw_csr_ops is going
to be extended with new operations, move all logic related to ring CSRs
to the newly created adf_gen[2|4]_hw_csr_data.[c|h] files.
This does not introduce any functional change.
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Xin Zeng <xin.zeng@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Giovanni Cabiddu
and committed by
Herbert Xu
680302d1
867e8010
+397
-362
+1
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
+1
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
+1
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+1
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+1
drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
+1
drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
+1
drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
+1
drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
+1
drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
+1
drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
+1
drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
+1
drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
+2
drivers/crypto/intel/qat/qat_common/Makefile
+2
drivers/crypto/intel/qat/qat_common/Makefile
+101
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c
+101
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright(c) 2024 Intel Corporation */
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+
#include <linux/types.h>
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+
#include "adf_gen2_hw_csr_data.h"
5
+
6
+
static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
7
+
{
8
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return BUILD_RING_BASE_ADDR(addr, size);
9
+
}
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+
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static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
12
+
{
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return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
14
+
}
15
+
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static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
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+
u32 value)
18
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{
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WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
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+
}
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+
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+
static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
23
+
{
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return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
25
+
}
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+
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static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
28
+
u32 value)
29
+
{
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WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
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+
}
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+
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static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
34
+
{
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return READ_CSR_E_STAT(csr_base_addr, bank);
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}
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+
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static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
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u32 ring, u32 value)
40
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{
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WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
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}
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+
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static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
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dma_addr_t addr)
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{
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WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
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+
}
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+
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static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)
51
+
{
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WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
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+
}
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+
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static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
56
+
{
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WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
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+
}
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+
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static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,
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+
u32 value)
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{
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WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
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+
}
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+
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static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
67
+
u32 value)
68
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{
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WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
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+
}
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+
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static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
73
+
u32 value)
74
+
{
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WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
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}
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+
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static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
79
+
u32 value)
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+
{
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WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
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}
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+
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void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
85
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{
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csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
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csr_ops->read_csr_ring_head = read_csr_ring_head;
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csr_ops->write_csr_ring_head = write_csr_ring_head;
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csr_ops->read_csr_ring_tail = read_csr_ring_tail;
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csr_ops->write_csr_ring_tail = write_csr_ring_tail;
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csr_ops->read_csr_e_stat = read_csr_e_stat;
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csr_ops->write_csr_ring_config = write_csr_ring_config;
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csr_ops->write_csr_ring_base = write_csr_ring_base;
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csr_ops->write_csr_int_flag = write_csr_int_flag;
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csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
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csr_ops->write_csr_int_col_en = write_csr_int_col_en;
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csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
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csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
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csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
100
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}
101
+
EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops);
+86
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h
+86
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright(c) 2024 Intel Corporation */
3
+
#ifndef ADF_GEN2_HW_CSR_DATA_H_
4
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#define ADF_GEN2_HW_CSR_DATA_H_
5
+
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#include <linux/bitops.h>
7
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#include "adf_accel_devices.h"
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+
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#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
10
+
#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
11
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#define ADF_RING_CSR_RING_CONFIG 0x000
12
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#define ADF_RING_CSR_RING_LBASE 0x040
13
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#define ADF_RING_CSR_RING_UBASE 0x080
14
+
#define ADF_RING_CSR_RING_HEAD 0x0C0
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#define ADF_RING_CSR_RING_TAIL 0x100
16
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#define ADF_RING_CSR_E_STAT 0x14C
17
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#define ADF_RING_CSR_INT_FLAG 0x170
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#define ADF_RING_CSR_INT_SRCSEL 0x174
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#define ADF_RING_CSR_INT_SRCSEL_2 0x178
20
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#define ADF_RING_CSR_INT_COL_EN 0x17C
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#define ADF_RING_CSR_INT_COL_CTL 0x180
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#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
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#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
24
+
#define ADF_RING_BUNDLE_SIZE 0x1000
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+
#define ADF_ARB_REG_SLOT 0x1000
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+
#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
27
+
28
+
#define BUILD_RING_BASE_ADDR(addr, size) \
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(((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
30
+
#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
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+
ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
32
+
ADF_RING_CSR_RING_HEAD + ((ring) << 2))
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+
#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
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ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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+
ADF_RING_CSR_RING_TAIL + ((ring) << 2))
36
+
#define READ_CSR_E_STAT(csr_base_addr, bank) \
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ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
38
+
ADF_RING_CSR_E_STAT)
39
+
#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
41
+
ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
42
+
#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
43
+
do { \
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u32 l_base = 0, u_base = 0; \
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l_base = (u32)((value) & 0xFFFFFFFF); \
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+
u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \
47
+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
48
+
ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \
49
+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
50
+
ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \
51
+
} while (0)
52
+
53
+
#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
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+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
55
+
ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
56
+
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
58
+
ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
59
+
#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
61
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ADF_RING_CSR_INT_FLAG, value)
62
+
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
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+
do { \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
66
+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
67
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ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
68
+
} while (0)
69
+
#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
71
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ADF_RING_CSR_INT_COL_EN, value)
72
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#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
74
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ADF_RING_CSR_INT_COL_CTL, \
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+
ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
76
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#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
78
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ADF_RING_CSR_INT_FLAG_AND_COL, value)
79
+
80
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#define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \
81
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ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
82
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(ADF_ARB_REG_SLOT * (index)), value)
83
+
84
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void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
85
+
86
+
#endif
-97
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
-97
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
···
111
111
}
112
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EXPORT_SYMBOL_GPL(adf_gen2_enable_ints);
113
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114
-
static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
115
-
{
116
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return BUILD_RING_BASE_ADDR(addr, size);
117
-
}
118
-
119
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static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
120
-
{
121
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return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
122
-
}
123
-
124
-
static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
125
-
u32 value)
126
-
{
127
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WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
128
-
}
129
-
130
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static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
131
-
{
132
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return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
133
-
}
134
-
135
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static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
136
-
u32 value)
137
-
{
138
-
WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
139
-
}
140
-
141
-
static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
142
-
{
143
-
return READ_CSR_E_STAT(csr_base_addr, bank);
144
-
}
145
-
146
-
static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
147
-
u32 ring, u32 value)
148
-
{
149
-
WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
150
-
}
151
-
152
-
static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
153
-
dma_addr_t addr)
154
-
{
155
-
WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
156
-
}
157
-
158
-
static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)
159
-
{
160
-
WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
161
-
}
162
-
163
-
static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
164
-
{
165
-
WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
166
-
}
167
-
168
-
static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,
169
-
u32 value)
170
-
{
171
-
WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
172
-
}
173
-
174
-
static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
175
-
u32 value)
176
-
{
177
-
WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
178
-
}
179
-
180
-
static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
181
-
u32 value)
182
-
{
183
-
WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
184
-
}
185
-
186
-
static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
187
-
u32 value)
188
-
{
189
-
WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
190
-
}
191
-
192
-
void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
193
-
{
194
-
csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
195
-
csr_ops->read_csr_ring_head = read_csr_ring_head;
196
-
csr_ops->write_csr_ring_head = write_csr_ring_head;
197
-
csr_ops->read_csr_ring_tail = read_csr_ring_tail;
198
-
csr_ops->write_csr_ring_tail = write_csr_ring_tail;
199
-
csr_ops->read_csr_e_stat = read_csr_e_stat;
200
-
csr_ops->write_csr_ring_config = write_csr_ring_config;
201
-
csr_ops->write_csr_ring_base = write_csr_ring_base;
202
-
csr_ops->write_csr_int_flag = write_csr_int_flag;
203
-
csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
204
-
csr_ops->write_csr_int_col_en = write_csr_int_col_en;
205
-
csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
206
-
csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
207
-
csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
208
-
}
209
-
EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops);
210
-
211
114
u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev)
212
115
{
213
116
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
-76
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
-76
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
···
6
6
#include "adf_accel_devices.h"
7
7
#include "adf_cfg_common.h"
8
8
9
-
/* Transport access */
10
-
#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
11
-
#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
12
-
#define ADF_RING_CSR_RING_CONFIG 0x000
13
-
#define ADF_RING_CSR_RING_LBASE 0x040
14
-
#define ADF_RING_CSR_RING_UBASE 0x080
15
-
#define ADF_RING_CSR_RING_HEAD 0x0C0
16
-
#define ADF_RING_CSR_RING_TAIL 0x100
17
-
#define ADF_RING_CSR_E_STAT 0x14C
18
-
#define ADF_RING_CSR_INT_FLAG 0x170
19
-
#define ADF_RING_CSR_INT_SRCSEL 0x174
20
-
#define ADF_RING_CSR_INT_SRCSEL_2 0x178
21
-
#define ADF_RING_CSR_INT_COL_EN 0x17C
22
-
#define ADF_RING_CSR_INT_COL_CTL 0x180
23
-
#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
24
-
#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
25
-
#define ADF_RING_BUNDLE_SIZE 0x1000
26
9
#define ADF_GEN2_RX_RINGS_OFFSET 8
27
10
#define ADF_GEN2_TX_RINGS_MASK 0xFF
28
-
29
-
#define BUILD_RING_BASE_ADDR(addr, size) \
30
-
(((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
31
-
#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
32
-
ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33
-
ADF_RING_CSR_RING_HEAD + ((ring) << 2))
34
-
#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
35
-
ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36
-
ADF_RING_CSR_RING_TAIL + ((ring) << 2))
37
-
#define READ_CSR_E_STAT(csr_base_addr, bank) \
38
-
ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39
-
ADF_RING_CSR_E_STAT)
40
-
#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
41
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42
-
ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
43
-
#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
44
-
do { \
45
-
u32 l_base = 0, u_base = 0; \
46
-
l_base = (u32)((value) & 0xFFFFFFFF); \
47
-
u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \
48
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
49
-
ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \
50
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
51
-
ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \
52
-
} while (0)
53
-
54
-
#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
55
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
56
-
ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
57
-
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
58
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
59
-
ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
60
-
#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
61
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
62
-
ADF_RING_CSR_INT_FLAG, value)
63
-
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
64
-
do { \
65
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
66
-
ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
67
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
68
-
ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
69
-
} while (0)
70
-
#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
71
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
72
-
ADF_RING_CSR_INT_COL_EN, value)
73
-
#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
74
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
75
-
ADF_RING_CSR_INT_COL_CTL, \
76
-
ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
77
-
#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
78
-
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
79
-
ADF_RING_CSR_INT_FLAG_AND_COL, value)
80
11
81
12
/* AE to function map */
82
13
#define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190)
···
37
106
#define ADF_ARB_OFFSET 0x30000
38
107
#define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
39
108
#define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
40
-
#define ADF_ARB_REG_SLOT 0x1000
41
-
#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
42
-
43
-
#define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \
44
-
ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
45
-
(ADF_ARB_REG_SLOT * (index)), value)
46
109
47
110
/* Power gating */
48
111
#define ADF_POWERGATE_DC BIT(23)
···
83
158
void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev);
84
159
void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
85
160
int num_a_regs, int num_b_regs);
86
-
void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
87
161
void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info);
88
162
void adf_gen2_get_arb_info(struct arb_info *arb_info);
89
163
void adf_gen2_enable_ints(struct adf_accel_dev *accel_dev);
+101
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c
+101
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright(c) 2024 Intel Corporation */
3
+
#include <linux/types.h>
4
+
#include "adf_gen4_hw_csr_data.h"
5
+
6
+
static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
7
+
{
8
+
return BUILD_RING_BASE_ADDR(addr, size);
9
+
}
10
+
11
+
static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
12
+
{
13
+
return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
14
+
}
15
+
16
+
static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
17
+
u32 value)
18
+
{
19
+
WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
20
+
}
21
+
22
+
static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
23
+
{
24
+
return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
25
+
}
26
+
27
+
static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
28
+
u32 value)
29
+
{
30
+
WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
31
+
}
32
+
33
+
static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
34
+
{
35
+
return READ_CSR_E_STAT(csr_base_addr, bank);
36
+
}
37
+
38
+
static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,
39
+
u32 value)
40
+
{
41
+
WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
42
+
}
43
+
44
+
static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
45
+
dma_addr_t addr)
46
+
{
47
+
WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
48
+
}
49
+
50
+
static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank,
51
+
u32 value)
52
+
{
53
+
WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
54
+
}
55
+
56
+
static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
57
+
{
58
+
WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
59
+
}
60
+
61
+
static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value)
62
+
{
63
+
WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
64
+
}
65
+
66
+
static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
67
+
u32 value)
68
+
{
69
+
WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
70
+
}
71
+
72
+
static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
73
+
u32 value)
74
+
{
75
+
WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
76
+
}
77
+
78
+
static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
79
+
u32 value)
80
+
{
81
+
WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
82
+
}
83
+
84
+
void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
85
+
{
86
+
csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
87
+
csr_ops->read_csr_ring_head = read_csr_ring_head;
88
+
csr_ops->write_csr_ring_head = write_csr_ring_head;
89
+
csr_ops->read_csr_ring_tail = read_csr_ring_tail;
90
+
csr_ops->write_csr_ring_tail = write_csr_ring_tail;
91
+
csr_ops->read_csr_e_stat = read_csr_e_stat;
92
+
csr_ops->write_csr_ring_config = write_csr_ring_config;
93
+
csr_ops->write_csr_ring_base = write_csr_ring_base;
94
+
csr_ops->write_csr_int_flag = write_csr_int_flag;
95
+
csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
96
+
csr_ops->write_csr_int_col_en = write_csr_int_col_en;
97
+
csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
98
+
csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
99
+
csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
100
+
}
101
+
EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops);
+97
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h
+97
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright(c) 2024 Intel Corporation */
3
+
#ifndef ADF_GEN4_HW_CSR_DATA_H_
4
+
#define ADF_GEN4_HW_CSR_DATA_H_
5
+
6
+
#include <linux/bitops.h>
7
+
#include "adf_accel_devices.h"
8
+
9
+
#define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
10
+
#define ADF_RING_CSR_RING_CONFIG 0x1000
11
+
#define ADF_RING_CSR_RING_LBASE 0x1040
12
+
#define ADF_RING_CSR_RING_UBASE 0x1080
13
+
#define ADF_RING_CSR_RING_HEAD 0x0C0
14
+
#define ADF_RING_CSR_RING_TAIL 0x100
15
+
#define ADF_RING_CSR_E_STAT 0x14C
16
+
#define ADF_RING_CSR_INT_FLAG 0x170
17
+
#define ADF_RING_CSR_INT_SRCSEL 0x174
18
+
#define ADF_RING_CSR_INT_COL_CTL 0x180
19
+
#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
20
+
#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
21
+
#define ADF_RING_CSR_INT_COL_EN 0x17C
22
+
#define ADF_RING_CSR_ADDR_OFFSET 0x100000
23
+
#define ADF_RING_BUNDLE_SIZE 0x2000
24
+
#define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C
25
+
26
+
#define BUILD_RING_BASE_ADDR(addr, size) \
27
+
((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6)
28
+
#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
29
+
ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
30
+
ADF_RING_BUNDLE_SIZE * (bank) + \
31
+
ADF_RING_CSR_RING_HEAD + ((ring) << 2))
32
+
#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
33
+
ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
34
+
ADF_RING_BUNDLE_SIZE * (bank) + \
35
+
ADF_RING_CSR_RING_TAIL + ((ring) << 2))
36
+
#define READ_CSR_E_STAT(csr_base_addr, bank) \
37
+
ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
38
+
ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
39
+
#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
40
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
41
+
ADF_RING_BUNDLE_SIZE * (bank) + \
42
+
ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
43
+
#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
44
+
do { \
45
+
void __iomem *_csr_base_addr = csr_base_addr; \
46
+
u32 _bank = bank; \
47
+
u32 _ring = ring; \
48
+
dma_addr_t _value = value; \
49
+
u32 l_base = 0, u_base = 0; \
50
+
l_base = lower_32_bits(_value); \
51
+
u_base = upper_32_bits(_value); \
52
+
ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
53
+
ADF_RING_BUNDLE_SIZE * (_bank) + \
54
+
ADF_RING_CSR_RING_LBASE + ((_ring) << 2), l_base); \
55
+
ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
56
+
ADF_RING_BUNDLE_SIZE * (_bank) + \
57
+
ADF_RING_CSR_RING_UBASE + ((_ring) << 2), u_base); \
58
+
} while (0)
59
+
60
+
#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
61
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
62
+
ADF_RING_BUNDLE_SIZE * (bank) + \
63
+
ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
64
+
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
65
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
66
+
ADF_RING_BUNDLE_SIZE * (bank) + \
67
+
ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
68
+
#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
69
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
70
+
ADF_RING_BUNDLE_SIZE * (bank) + \
71
+
ADF_RING_CSR_INT_FLAG, (value))
72
+
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
73
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
74
+
ADF_RING_BUNDLE_SIZE * (bank) + \
75
+
ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK)
76
+
#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
77
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
78
+
ADF_RING_BUNDLE_SIZE * (bank) + \
79
+
ADF_RING_CSR_INT_COL_EN, (value))
80
+
#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
81
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
82
+
ADF_RING_BUNDLE_SIZE * (bank) + \
83
+
ADF_RING_CSR_INT_COL_CTL, \
84
+
ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
85
+
#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
86
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
87
+
ADF_RING_BUNDLE_SIZE * (bank) + \
88
+
ADF_RING_CSR_INT_FLAG_AND_COL, (value))
89
+
90
+
#define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \
91
+
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
92
+
ADF_RING_BUNDLE_SIZE * (bank) + \
93
+
ADF_RING_CSR_RING_SRV_ARB_EN, (value))
94
+
95
+
void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
96
+
97
+
#endif
-97
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
-97
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
···
8
8
#include "adf_gen4_hw_data.h"
9
9
#include "adf_gen4_pm.h"
10
10
11
-
static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
12
-
{
13
-
return BUILD_RING_BASE_ADDR(addr, size);
14
-
}
15
-
16
-
static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
17
-
{
18
-
return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
19
-
}
20
-
21
-
static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
22
-
u32 value)
23
-
{
24
-
WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
25
-
}
26
-
27
-
static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
28
-
{
29
-
return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
30
-
}
31
-
32
-
static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
33
-
u32 value)
34
-
{
35
-
WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
36
-
}
37
-
38
-
static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
39
-
{
40
-
return READ_CSR_E_STAT(csr_base_addr, bank);
41
-
}
42
-
43
-
static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,
44
-
u32 value)
45
-
{
46
-
WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
47
-
}
48
-
49
-
static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
50
-
dma_addr_t addr)
51
-
{
52
-
WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
53
-
}
54
-
55
-
static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank,
56
-
u32 value)
57
-
{
58
-
WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
59
-
}
60
-
61
-
static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
62
-
{
63
-
WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
64
-
}
65
-
66
-
static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value)
67
-
{
68
-
WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
69
-
}
70
-
71
-
static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
72
-
u32 value)
73
-
{
74
-
WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
75
-
}
76
-
77
-
static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
78
-
u32 value)
79
-
{
80
-
WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
81
-
}
82
-
83
-
static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
84
-
u32 value)
85
-
{
86
-
WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
87
-
}
88
-
89
-
void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
90
-
{
91
-
csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
92
-
csr_ops->read_csr_ring_head = read_csr_ring_head;
93
-
csr_ops->write_csr_ring_head = write_csr_ring_head;
94
-
csr_ops->read_csr_ring_tail = read_csr_ring_tail;
95
-
csr_ops->write_csr_ring_tail = write_csr_ring_tail;
96
-
csr_ops->read_csr_e_stat = read_csr_e_stat;
97
-
csr_ops->write_csr_ring_config = write_csr_ring_config;
98
-
csr_ops->write_csr_ring_base = write_csr_ring_base;
99
-
csr_ops->write_csr_int_flag = write_csr_int_flag;
100
-
csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
101
-
csr_ops->write_csr_int_col_en = write_csr_int_col_en;
102
-
csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
103
-
csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
104
-
csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
105
-
}
106
-
EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops);
107
-
108
11
u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self)
109
12
{
110
13
return ADF_GEN4_ACCELERATORS_MASK;
+2
-92
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
+2
-92
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
···
1
1
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2
2
/* Copyright(c) 2020 Intel Corporation */
3
-
#ifndef ADF_GEN4_HW_CSR_DATA_H_
4
-
#define ADF_GEN4_HW_CSR_DATA_H_
3
+
#ifndef ADF_GEN4_HW_DATA_H_
4
+
#define ADF_GEN4_HW_DATA_H_
5
5
6
6
#include <linux/units.h>
7
7
···
53
53
#define ADF_GEN4_ADMINMSGUR_OFFSET 0x500574
54
54
#define ADF_GEN4_ADMINMSGLR_OFFSET 0x500578
55
55
#define ADF_GEN4_MAILBOX_BASE_OFFSET 0x600970
56
-
57
-
/* Transport access */
58
-
#define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
59
-
#define ADF_RING_CSR_RING_CONFIG 0x1000
60
-
#define ADF_RING_CSR_RING_LBASE 0x1040
61
-
#define ADF_RING_CSR_RING_UBASE 0x1080
62
-
#define ADF_RING_CSR_RING_HEAD 0x0C0
63
-
#define ADF_RING_CSR_RING_TAIL 0x100
64
-
#define ADF_RING_CSR_E_STAT 0x14C
65
-
#define ADF_RING_CSR_INT_FLAG 0x170
66
-
#define ADF_RING_CSR_INT_SRCSEL 0x174
67
-
#define ADF_RING_CSR_INT_COL_CTL 0x180
68
-
#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
69
-
#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
70
-
#define ADF_RING_CSR_INT_COL_EN 0x17C
71
-
#define ADF_RING_CSR_ADDR_OFFSET 0x100000
72
-
#define ADF_RING_BUNDLE_SIZE 0x2000
73
-
74
-
#define BUILD_RING_BASE_ADDR(addr, size) \
75
-
((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6)
76
-
#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
77
-
ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
78
-
ADF_RING_BUNDLE_SIZE * (bank) + \
79
-
ADF_RING_CSR_RING_HEAD + ((ring) << 2))
80
-
#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
81
-
ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
82
-
ADF_RING_BUNDLE_SIZE * (bank) + \
83
-
ADF_RING_CSR_RING_TAIL + ((ring) << 2))
84
-
#define READ_CSR_E_STAT(csr_base_addr, bank) \
85
-
ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
86
-
ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
87
-
#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
88
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
89
-
ADF_RING_BUNDLE_SIZE * (bank) + \
90
-
ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
91
-
#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
92
-
do { \
93
-
void __iomem *_csr_base_addr = csr_base_addr; \
94
-
u32 _bank = bank; \
95
-
u32 _ring = ring; \
96
-
dma_addr_t _value = value; \
97
-
u32 l_base = 0, u_base = 0; \
98
-
l_base = lower_32_bits(_value); \
99
-
u_base = upper_32_bits(_value); \
100
-
ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
101
-
ADF_RING_BUNDLE_SIZE * (_bank) + \
102
-
ADF_RING_CSR_RING_LBASE + ((_ring) << 2), l_base); \
103
-
ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
104
-
ADF_RING_BUNDLE_SIZE * (_bank) + \
105
-
ADF_RING_CSR_RING_UBASE + ((_ring) << 2), u_base); \
106
-
} while (0)
107
-
108
-
#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
109
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
110
-
ADF_RING_BUNDLE_SIZE * (bank) + \
111
-
ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
112
-
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
113
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
114
-
ADF_RING_BUNDLE_SIZE * (bank) + \
115
-
ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
116
-
#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
117
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
118
-
ADF_RING_BUNDLE_SIZE * (bank) + \
119
-
ADF_RING_CSR_INT_FLAG, (value))
120
-
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
121
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
122
-
ADF_RING_BUNDLE_SIZE * (bank) + \
123
-
ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK)
124
-
#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
125
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
126
-
ADF_RING_BUNDLE_SIZE * (bank) + \
127
-
ADF_RING_CSR_INT_COL_EN, (value))
128
-
#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
129
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
130
-
ADF_RING_BUNDLE_SIZE * (bank) + \
131
-
ADF_RING_CSR_INT_COL_CTL, \
132
-
ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
133
-
#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
134
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
135
-
ADF_RING_BUNDLE_SIZE * (bank) + \
136
-
ADF_RING_CSR_INT_FLAG_AND_COL, (value))
137
-
138
-
/* Arbiter configuration */
139
-
#define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C
140
-
141
-
#define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \
142
-
ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
143
-
ADF_RING_BUNDLE_SIZE * (bank) + \
144
-
ADF_RING_CSR_RING_SRV_ARB_EN, (value))
145
56
146
57
/* Default ring mapping */
147
58
#define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP \
···
145
234
enum dev_sku_info adf_gen4_get_sku(struct adf_hw_device_data *self);
146
235
u32 adf_gen4_get_sram_bar_id(struct adf_hw_device_data *self);
147
236
int adf_gen4_init_device(struct adf_accel_dev *accel_dev);
148
-
void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
149
237
int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number);
150
238
void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev);
151
239
void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
+1
drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+1
drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+1
drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
+1
drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c