tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'amd-drm-fixes-7.0-2026-03-04' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes

amd-drm-fixes-7.0-2026-03-04:

amdgpu:
- LUT fixes
- VCN5 fix
- Dispclk fix
- SMU 13.x fix
- Fix race in VM acquire
- PSP 15.x fix
- UserQ fix

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260304204837.1937266-1-alexander.deucher@amd.com

Dave Airlie 681d787c 11439c46

+172 -88
+5 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
··· 1439 1439 *process_info = info; 1440 1440 } 1441 1441 1442 - vm->process_info = *process_info; 1442 + if (cmpxchg(&vm->process_info, NULL, *process_info) != NULL) { 1443 + ret = -EINVAL; 1444 + goto already_acquired; 1445 + } 1443 1446 1444 1447 /* Validate page directory and attach eviction fence */ 1445 1448 ret = amdgpu_bo_reserve(vm->root.bo, true); ··· 1482 1479 amdgpu_bo_unreserve(vm->root.bo); 1483 1480 reserve_pd_fail: 1484 1481 vm->process_info = NULL; 1482 + already_acquired: 1485 1483 if (info) { 1486 1484 dma_fence_put(&info->eviction_fence->base); 1487 1485 *process_info = NULL;
+81 -35
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
··· 446 446 return ret; 447 447 } 448 448 449 - static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue, 450 - int queue_id) 449 + static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue) 451 450 { 452 451 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 453 452 struct amdgpu_device *adev = uq_mgr->adev; ··· 460 461 uq_funcs->mqd_destroy(queue); 461 462 amdgpu_userq_fence_driver_free(queue); 462 463 /* Use interrupt-safe locking since IRQ handlers may access these XArrays */ 463 - xa_erase_irq(&uq_mgr->userq_xa, (unsigned long)queue_id); 464 464 xa_erase_irq(&adev->userq_doorbell_xa, queue->doorbell_index); 465 465 queue->userq_mgr = NULL; 466 466 list_del(&queue->userq_va_list); 467 467 kfree(queue); 468 468 469 469 up_read(&adev->reset_domain->sem); 470 - } 471 - 472 - static struct amdgpu_usermode_queue * 473 - amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid) 474 - { 475 - return xa_load(&uq_mgr->userq_xa, qid); 476 470 } 477 471 478 472 void ··· 617 625 } 618 626 619 627 static int 620 - amdgpu_userq_destroy(struct drm_file *filp, int queue_id) 628 + amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) 621 629 { 622 - struct amdgpu_fpriv *fpriv = filp->driver_priv; 623 - struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; 624 630 struct amdgpu_device *adev = uq_mgr->adev; 625 - struct amdgpu_usermode_queue *queue; 626 631 int r = 0; 627 632 628 633 cancel_delayed_work_sync(&uq_mgr->resume_work); 629 634 mutex_lock(&uq_mgr->userq_mutex); 630 - queue = amdgpu_userq_find(uq_mgr, queue_id); 631 - if (!queue) { 632 - drm_dbg_driver(adev_to_drm(uq_mgr->adev), "Invalid queue id to destroy\n"); 633 - mutex_unlock(&uq_mgr->userq_mutex); 634 - return -EINVAL; 635 - } 636 635 amdgpu_userq_wait_for_last_fence(queue); 637 636 /* Cancel any pending hang detection work and cleanup */ 638 637 if (queue->hang_detect_fence) { ··· 655 672 drm_warn(adev_to_drm(uq_mgr->adev), "trying to destroy a HW mapping userq\n"); 656 673 queue->state = AMDGPU_USERQ_STATE_HUNG; 657 674 } 658 - amdgpu_userq_cleanup(queue, queue_id); 675 + amdgpu_userq_cleanup(queue); 659 676 mutex_unlock(&uq_mgr->userq_mutex); 660 677 661 678 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 662 679 663 680 return r; 681 + } 682 + 683 + static void amdgpu_userq_kref_destroy(struct kref *kref) 684 + { 685 + int r; 686 + struct amdgpu_usermode_queue *queue = 687 + container_of(kref, struct amdgpu_usermode_queue, refcount); 688 + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 689 + 690 + r = amdgpu_userq_destroy(uq_mgr, queue); 691 + if (r) 692 + drm_file_err(uq_mgr->file, "Failed to destroy usermode queue %d\n", r); 693 + } 694 + 695 + struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid) 696 + { 697 + struct amdgpu_usermode_queue *queue; 698 + 699 + xa_lock(&uq_mgr->userq_xa); 700 + queue = xa_load(&uq_mgr->userq_xa, qid); 701 + if (queue) 702 + kref_get(&queue->refcount); 703 + xa_unlock(&uq_mgr->userq_xa); 704 + 705 + return queue; 706 + } 707 + 708 + void amdgpu_userq_put(struct amdgpu_usermode_queue *queue) 709 + { 710 + if (queue) 711 + kref_put(&queue->refcount, amdgpu_userq_kref_destroy); 664 712 } 665 713 666 714 static int amdgpu_userq_priority_permit(struct drm_file *filp, ··· 848 834 goto unlock; 849 835 } 850 836 837 + /* drop this refcount during queue destroy */ 838 + kref_init(&queue->refcount); 839 + 851 840 /* Wait for mode-1 reset to complete */ 852 841 down_read(&adev->reset_domain->sem); 853 842 r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); ··· 1002 985 struct drm_file *filp) 1003 986 { 1004 987 union drm_amdgpu_userq *args = data; 1005 - int r; 988 + struct amdgpu_fpriv *fpriv = filp->driver_priv; 989 + struct amdgpu_usermode_queue *queue; 990 + int r = 0; 1006 991 1007 992 if (!amdgpu_userq_enabled(dev)) 1008 993 return -ENOTSUPP; ··· 1019 1000 drm_file_err(filp, "Failed to create usermode queue\n"); 1020 1001 break; 1021 1002 1022 - case AMDGPU_USERQ_OP_FREE: 1023 - r = amdgpu_userq_destroy(filp, args->in.queue_id); 1024 - if (r) 1025 - drm_file_err(filp, "Failed to destroy usermode queue\n"); 1003 + case AMDGPU_USERQ_OP_FREE: { 1004 + xa_lock(&fpriv->userq_mgr.userq_xa); 1005 + queue = __xa_erase(&fpriv->userq_mgr.userq_xa, args->in.queue_id); 1006 + xa_unlock(&fpriv->userq_mgr.userq_xa); 1007 + if (!queue) 1008 + return -ENOENT; 1009 + 1010 + amdgpu_userq_put(queue); 1026 1011 break; 1012 + } 1027 1013 1028 1014 default: 1029 1015 drm_dbg_driver(dev, "Invalid user queue op specified: %d\n", args->in.op); ··· 1047 1023 1048 1024 /* Resume all the queues for this process */ 1049 1025 xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { 1026 + queue = amdgpu_userq_get(uq_mgr, queue_id); 1027 + if (!queue) 1028 + continue; 1029 + 1050 1030 if (!amdgpu_userq_buffer_vas_mapped(queue)) { 1051 1031 drm_file_err(uq_mgr->file, 1052 1032 "trying restore queue without va mapping\n"); 1053 1033 queue->state = AMDGPU_USERQ_STATE_INVALID_VA; 1034 + amdgpu_userq_put(queue); 1054 1035 continue; 1055 1036 } 1056 1037 1057 1038 r = amdgpu_userq_restore_helper(queue); 1058 1039 if (r) 1059 1040 ret = r; 1041 + 1042 + amdgpu_userq_put(queue); 1060 1043 } 1061 1044 1062 1045 if (ret) ··· 1297 1266 amdgpu_userq_detect_and_reset_queues(uq_mgr); 1298 1267 /* Try to unmap all the queues in this process ctx */ 1299 1268 xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { 1269 + queue = amdgpu_userq_get(uq_mgr, queue_id); 1270 + if (!queue) 1271 + continue; 1300 1272 r = amdgpu_userq_preempt_helper(queue); 1301 1273 if (r) 1302 1274 ret = r; 1275 + amdgpu_userq_put(queue); 1303 1276 } 1304 1277 1305 1278 if (ret) ··· 1336 1301 int ret; 1337 1302 1338 1303 xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { 1304 + queue = amdgpu_userq_get(uq_mgr, queue_id); 1305 + if (!queue) 1306 + continue; 1307 + 1339 1308 struct dma_fence *f = queue->last_fence; 1340 1309 1341 - if (!f || dma_fence_is_signaled(f)) 1310 + if (!f || dma_fence_is_signaled(f)) { 1311 + amdgpu_userq_put(queue); 1342 1312 continue; 1313 + } 1343 1314 ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100)); 1344 1315 if (ret <= 0) { 1345 1316 drm_file_err(uq_mgr->file, "Timed out waiting for fence=%llu:%llu\n", 1346 1317 f->context, f->seqno); 1318 + amdgpu_userq_put(queue); 1347 1319 return -ETIMEDOUT; 1348 1320 } 1321 + amdgpu_userq_put(queue); 1349 1322 } 1350 1323 1351 1324 return 0; ··· 1404 1361 void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) 1405 1362 { 1406 1363 struct amdgpu_usermode_queue *queue; 1407 - unsigned long queue_id; 1364 + unsigned long queue_id = 0; 1408 1365 1409 - cancel_delayed_work_sync(&userq_mgr->resume_work); 1366 + for (;;) { 1367 + xa_lock(&userq_mgr->userq_xa); 1368 + queue = xa_find(&userq_mgr->userq_xa, &queue_id, ULONG_MAX, 1369 + XA_PRESENT); 1370 + if (queue) 1371 + __xa_erase(&userq_mgr->userq_xa, queue_id); 1372 + xa_unlock(&userq_mgr->userq_xa); 1410 1373 1411 - mutex_lock(&userq_mgr->userq_mutex); 1412 - amdgpu_userq_detect_and_reset_queues(userq_mgr); 1413 - xa_for_each(&userq_mgr->userq_xa, queue_id, queue) { 1414 - amdgpu_userq_wait_for_last_fence(queue); 1415 - amdgpu_userq_unmap_helper(queue); 1416 - amdgpu_userq_cleanup(queue, queue_id); 1374 + if (!queue) 1375 + break; 1376 + 1377 + amdgpu_userq_put(queue); 1417 1378 } 1418 1379 1419 1380 xa_destroy(&userq_mgr->userq_xa); 1420 - mutex_unlock(&userq_mgr->userq_mutex); 1421 1381 mutex_destroy(&userq_mgr->userq_mutex); 1422 1382 } 1423 1383
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
··· 74 74 struct dentry *debugfs_queue; 75 75 struct delayed_work hang_detect_work; 76 76 struct dma_fence *hang_detect_fence; 77 + struct kref refcount; 77 78 78 79 struct list_head userq_va_list; 79 80 }; ··· 112 111 uint32_t doorbell_offset; 113 112 struct amdgpu_userq_obj *db_obj; 114 113 }; 114 + 115 + struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid); 116 + void amdgpu_userq_put(struct amdgpu_usermode_queue *queue); 115 117 116 118 int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 117 119
+15 -27
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
··· 466 466 struct drm_amdgpu_userq_signal *args = data; 467 467 struct drm_gem_object **gobj_write = NULL; 468 468 struct drm_gem_object **gobj_read = NULL; 469 - struct amdgpu_usermode_queue *queue; 469 + struct amdgpu_usermode_queue *queue = NULL; 470 470 struct amdgpu_userq_fence *userq_fence; 471 471 struct drm_syncobj **syncobj = NULL; 472 472 u32 *bo_handles_write, num_write_bo_handles; ··· 553 553 } 554 554 555 555 /* Retrieve the user queue */ 556 - queue = xa_load(&userq_mgr->userq_xa, args->queue_id); 556 + queue = amdgpu_userq_get(userq_mgr, args->queue_id); 557 557 if (!queue) { 558 558 r = -ENOENT; 559 559 goto put_gobj_write; ··· 648 648 free_syncobj_handles: 649 649 kfree(syncobj_handles); 650 650 651 + if (queue) 652 + amdgpu_userq_put(queue); 653 + 651 654 return r; 652 655 } 653 656 ··· 663 660 struct drm_amdgpu_userq_wait *wait_info = data; 664 661 struct amdgpu_fpriv *fpriv = filp->driver_priv; 665 662 struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; 666 - struct amdgpu_usermode_queue *waitq; 663 + struct amdgpu_usermode_queue *waitq = NULL; 667 664 struct drm_gem_object **gobj_write; 668 665 struct drm_gem_object **gobj_read; 669 666 struct dma_fence **fences = NULL; ··· 929 926 */ 930 927 num_fences = dma_fence_dedup_array(fences, num_fences); 931 928 932 - waitq = xa_load(&userq_mgr->userq_xa, wait_info->waitq_id); 929 + waitq = amdgpu_userq_get(userq_mgr, wait_info->waitq_id); 933 930 if (!waitq) { 934 931 r = -EINVAL; 935 932 goto free_fences; ··· 986 983 r = -EFAULT; 987 984 goto free_fences; 988 985 } 989 - 990 - kfree(fences); 991 - kfree(fence_info); 992 986 } 993 987 994 - drm_exec_fini(&exec); 995 - for (i = 0; i < num_read_bo_handles; i++) 996 - drm_gem_object_put(gobj_read[i]); 997 - kfree(gobj_read); 998 - 999 - for (i = 0; i < num_write_bo_handles; i++) 1000 - drm_gem_object_put(gobj_write[i]); 1001 - kfree(gobj_write); 1002 - 1003 - kfree(timeline_points); 1004 - kfree(timeline_handles); 1005 - kfree(syncobj_handles); 1006 - kfree(bo_handles_write); 1007 - kfree(bo_handles_read); 1008 - 1009 - return 0; 1010 - 1011 988 free_fences: 1012 - while (num_fences-- > 0) 1013 - dma_fence_put(fences[num_fences]); 1014 - kfree(fences); 989 + if (fences) { 990 + while (num_fences-- > 0) 991 + dma_fence_put(fences[num_fences]); 992 + kfree(fences); 993 + } 1015 994 free_fence_info: 1016 995 kfree(fence_info); 1017 996 exec_fini: ··· 1016 1031 kfree(bo_handles_write); 1017 1032 free_bo_handles_read: 1018 1033 kfree(bo_handles_read); 1034 + 1035 + if (waitq) 1036 + amdgpu_userq_put(waitq); 1019 1037 1020 1038 return r; 1021 1039 }
+10 -10
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
··· 69 69 0x80000000, 0x80000000, false); 70 70 } else { 71 71 /* Write the ring destroy command*/ 72 - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, 72 + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, 73 73 GFX_CTRL_CMD_ID_DESTROY_RINGS); 74 74 /* there might be handshake issue with hardware which needs delay */ 75 75 mdelay(20); 76 76 /* Wait for response flag (bit 31) */ 77 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 77 + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 78 78 0x80000000, 0x80000000, false); 79 79 } 80 80 ··· 116 116 117 117 } else { 118 118 /* Wait for sOS ready for ring creation */ 119 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 119 + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 120 120 0x80000000, 0x80000000, false); 121 121 if (ret) { 122 122 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); ··· 125 125 126 126 /* Write low address of the ring to C2PMSG_69 */ 127 127 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 128 - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); 128 + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg); 129 129 /* Write high address of the ring to C2PMSG_70 */ 130 130 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 131 - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg); 131 + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg); 132 132 /* Write size of ring to C2PMSG_71 */ 133 133 psp_ring_reg = ring->ring_size; 134 - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg); 134 + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg); 135 135 /* Write the ring initialization command to C2PMSG_64 */ 136 136 psp_ring_reg = ring_type; 137 137 psp_ring_reg = psp_ring_reg << 16; 138 - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg); 138 + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg); 139 139 140 140 /* there might be handshake issue with hardware which needs delay */ 141 141 mdelay(20); 142 142 143 143 /* Wait for response flag (bit 31) in C2PMSG_64 */ 144 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 144 + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 145 145 0x80000000, 0x8000FFFF, false); 146 146 } 147 147 ··· 174 174 if (amdgpu_sriov_vf(adev)) 175 175 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); 176 176 else 177 - data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67); 177 + data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67); 178 178 179 179 return data; 180 180 } ··· 188 188 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 189 189 GFX_CTRL_CMD_ID_CONSUME_CMD); 190 190 } else 191 - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); 191 + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value); 192 192 } 193 193 194 194 static const struct psp_funcs psp_v15_0_0_funcs = {
+3 -1
drivers/gpu/drm/amd/amdgpu/soc21.c
··· 858 858 AMD_CG_SUPPORT_IH_CG | 859 859 AMD_CG_SUPPORT_BIF_MGCG | 860 860 AMD_CG_SUPPORT_BIF_LS; 861 - adev->pg_flags = AMD_PG_SUPPORT_VCN | 861 + adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 862 + AMD_PG_SUPPORT_VCN | 863 + AMD_PG_SUPPORT_JPEG_DPG | 862 864 AMD_PG_SUPPORT_JPEG | 863 865 AMD_PG_SUPPORT_GFX_PG; 864 866 adev->external_rev_id = adev->rev_id + 0x1;
+4 -2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
··· 1706 1706 struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func; 1707 1707 struct drm_atomic_state *state = plane_state->state; 1708 1708 const struct amdgpu_device *adev = drm_to_adev(colorop->dev); 1709 + bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend; 1709 1710 const struct drm_device *dev = colorop->dev; 1710 1711 const struct drm_color_lut32 *lut3d; 1711 1712 uint32_t lut3d_size; ··· 1723 1722 } 1724 1723 1725 1724 if (colorop_state && !colorop_state->bypass && colorop->type == DRM_COLOROP_3D_LUT) { 1726 - if (!adev->dm.dc->caps.color.dpp.hw_3d_lut) { 1725 + if (!has_3dlut) { 1727 1726 drm_dbg(dev, "3D LUT is not supported by hardware\n"); 1728 1727 return -EINVAL; 1729 1728 } ··· 1876 1875 struct drm_colorop *colorop = plane_state->color_pipeline; 1877 1876 struct drm_device *dev = plane_state->plane->dev; 1878 1877 struct amdgpu_device *adev = drm_to_adev(dev); 1878 + bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend; 1879 1879 int ret; 1880 1880 1881 1881 /* 1D Curve - DEGAM TF */ ··· 1909 1907 if (ret) 1910 1908 return ret; 1911 1909 1912 - if (adev->dm.dc->caps.color.dpp.hw_3d_lut) { 1910 + if (has_3dlut) { 1913 1911 /* 1D Curve & LUT - SHAPER TF & LUT */ 1914 1912 colorop = colorop->next; 1915 1913 if (!colorop) {
+2 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
··· 60 60 struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; 61 61 struct drm_device *dev = plane->dev; 62 62 struct amdgpu_device *adev = drm_to_adev(dev); 63 + bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend; 63 64 int ret; 64 65 int i = 0; 65 66 ··· 113 112 114 113 i++; 115 114 116 - if (adev->dm.dc->caps.color.dpp.hw_3d_lut) { 115 + if (has_3dlut) { 117 116 /* 1D curve - SHAPER TF */ 118 117 ops[i] = kzalloc_obj(*ops[0]); 119 118 if (!ops[i]) {
+8 -8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
··· 765 765 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 766 766 767 767 /* Don't enable DRM CRTC degamma property for 768 - * 1. Degamma is replaced by color pipeline. 769 - * 2. DCE since it doesn't support programmable degamma anywhere. 770 - * 3. DCN401 since pre-blending degamma LUT doesn't apply to cursor. 768 + * 1. DCE since it doesn't support programmable degamma anywhere. 769 + * 2. DCN401 since pre-blending degamma LUT doesn't apply to cursor. 770 + * Note: DEGAMMA properties are created even if the primary plane has the 771 + * COLOR_PIPELINE property. User space can use either the DEGAMMA properties 772 + * or the COLOR_PIPELINE property. An atomic commit which attempts to enable 773 + * both is rejected. 771 774 */ 772 - if (plane->color_pipeline_property) 773 - has_degamma = false; 774 - else 775 - has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch && 776 - dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01; 775 + has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch && 776 + dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01; 777 777 778 778 drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0, 779 779 true, MAX_COLOR_LUT_ENTRIES);
+8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
··· 1256 1256 if (ret) 1257 1257 return ret; 1258 1258 1259 + /* Reject commits that attempt to use both COLOR_PIPELINE and CRTC DEGAMMA_LUT */ 1260 + if (new_plane_state->color_pipeline && new_crtc_state->degamma_lut) { 1261 + drm_dbg_atomic(plane->dev, 1262 + "[PLANE:%d:%s] COLOR_PIPELINE and CRTC DEGAMMA_LUT cannot be enabled simultaneously\n", 1263 + plane->base.id, plane->name); 1264 + return -EINVAL; 1265 + } 1266 + 1259 1267 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); 1260 1268 if (ret) 1261 1269 return ret;
+5 -1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
··· 72 72 * audio corruption. Read current DISPCLK from DENTIST and request the same 73 73 * freq to ensure that the timing is valid and unchanged. 74 74 */ 75 - clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); 75 + if (dc->clk_mgr->funcs->get_dispclk_from_dentist) { 76 + clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); 77 + } else { 78 + clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000; 79 + } 76 80 } 77 81 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; 78 82 clocks->fclk_p_state_change_support = true;
+18
drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
··· 82 82 #define regMPASP_SMN_IH_SW_INT_CTRL 0x0142 83 83 #define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0 84 84 85 + // addressBlock: mp_SmuMpASPPub_PcruDec 86 + // base address: 0x3800000 87 + #define regMPASP_PCRU1_MPASP_C2PMSG_64 0x4280 88 + #define regMPASP_PCRU1_MPASP_C2PMSG_64_BASE_IDX 3 89 + #define regMPASP_PCRU1_MPASP_C2PMSG_65 0x4281 90 + #define regMPASP_PCRU1_MPASP_C2PMSG_65_BASE_IDX 3 91 + #define regMPASP_PCRU1_MPASP_C2PMSG_66 0x4282 92 + #define regMPASP_PCRU1_MPASP_C2PMSG_66_BASE_IDX 3 93 + #define regMPASP_PCRU1_MPASP_C2PMSG_67 0x4283 94 + #define regMPASP_PCRU1_MPASP_C2PMSG_67_BASE_IDX 3 95 + #define regMPASP_PCRU1_MPASP_C2PMSG_68 0x4284 96 + #define regMPASP_PCRU1_MPASP_C2PMSG_68_BASE_IDX 3 97 + #define regMPASP_PCRU1_MPASP_C2PMSG_69 0x4285 98 + #define regMPASP_PCRU1_MPASP_C2PMSG_69_BASE_IDX 3 99 + #define regMPASP_PCRU1_MPASP_C2PMSG_70 0x4286 100 + #define regMPASP_PCRU1_MPASP_C2PMSG_70_BASE_IDX 3 101 + #define regMPASP_PCRU1_MPASP_C2PMSG_71 0x4287 102 + #define regMPASP_PCRU1_MPASP_C2PMSG_71_BASE_IDX 3 85 103 86 104 // addressBlock: mp_SmuMp1_SmnDec 87 105 // base address: 0x0
+7 -1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
··· 2034 2034 smu, SMU_DRIVER_TABLE_GPU_METRICS); 2035 2035 SmuMetricsExternal_t metrics_ext; 2036 2036 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 2037 + uint32_t mp1_ver = amdgpu_ip_version(smu->adev, MP1_HWIP, 0); 2037 2038 int ret = 0; 2038 2039 2039 2040 ret = smu_cmn_get_metrics_table(smu, ··· 2059 2058 metrics->Vcn1ActivityPercentage); 2060 2059 2061 2060 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 2062 - gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 2061 + 2062 + if ((mp1_ver == IP_VERSION(13, 0, 0) && smu->smc_fw_version <= 0x004e1e00) || 2063 + (mp1_ver == IP_VERSION(13, 0, 10) && smu->smc_fw_version <= 0x00500800)) 2064 + gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 2065 + else 2066 + gpu_metrics->energy_accumulator = UINT_MAX; 2063 2067 2064 2068 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 2065 2069 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
+2 -1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
··· 2065 2065 metrics->Vcn1ActivityPercentage); 2066 2066 2067 2067 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 2068 - gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 2068 + gpu_metrics->energy_accumulator = smu->smc_fw_version <= 0x00521400 ? 2069 + metrics->EnergyAccumulator : UINT_MAX; 2069 2070 2070 2071 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD) 2071 2072 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;