Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Our first real batch of fixes this release cycle. Nothing really
concerning, and diffstat is a bit inflated due to some DT contents
moving around on STi platforms.
There's a collection of them here:
- A fixup for a build breakage that hits on arm64 allmodconfig in
QCOM SCM firmware drivers
- MMC fixes for OMAP that had quite a bit of breakage this merge
window.
- Misc build/warning fixes on PXA and OMAP
- A couple of minor fixes for Beagleboard X15 which is now starting
to see a few more users in the wild"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits)
ARM: sti: dt: adapt DT to fix probe/bind issues in DRM driver
ARM: dts: fix omap2+ address translation for pbias
firmware: qcom: scm: Add function stubs for ARM64
ARM: dts: am57xx-beagle-x15: use palmas-usb for USB2
ARM: omap2plus_defconfig: enable GPIO_PCA953X
ARM: dts: omap5-uevm.dts: fix i2c5 pinctrl offsets
ARM: OMAP2+: AM43XX: Enable autoidle for clks in am43xx_init_late
ARM: dts: am57xx-beagle-x15: Update Phy supplies
ARM: pxa: balloon3: Fix build error
ARM: dts: Fixup model name for HP t410 dts
ARM: dts: DRA7: fix a typo in ethernet
ARM: omap2plus_defconfig: make PCF857x built-in
ARM: dts: Use ti,pbias compatible string for pbias
ARM: OMAP5: Cleanup options for SoC only build
ARM: DRA7: Select missing options for SoC only build
ARM: OMAP2+: board-generic: Remove stale of_irq macros
ARM: OMAP4+: PM: erratum is used by OMAP5 and DRA7 as well
ARM: dts: omap3-igep: Move eth IRQ pinmux to IGEPv2 common dtsi
ARM: dts: am57xx-beagle-x15: Add wakeup irq for mcp79410
ARM: dts: am335x-phycore-som: Fix mpu voltage
...
+270
-154
+2
-2
arch/arm/boot/dts/am335x-phycore-som.dtsi
+2
-2
arch/arm/boot/dts/am335x-phycore-som.dtsi
···
252
252
};
253
253
254
254
vdd1_reg: regulator@2 {
255
-
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
255
+
/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
256
256
regulator-name = "vdd_mpu";
257
257
regulator-min-microvolt = <912500>;
258
-
regulator-max-microvolt = <1312500>;
258
+
regulator-max-microvolt = <1378000>;
259
259
regulator-boot-on;
260
260
regulator-always-on;
261
261
};
+29
-17
arch/arm/boot/dts/am57xx-beagle-x15.dts
+29
-17
arch/arm/boot/dts/am57xx-beagle-x15.dts
···
98
98
pinctrl-0 = <&extcon_usb1_pins>;
99
99
};
100
100
101
-
extcon_usb2: extcon_usb2 {
102
-
compatible = "linux,extcon-usb-gpio";
103
-
id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
104
-
pinctrl-names = "default";
105
-
pinctrl-0 = <&extcon_usb2_pins>;
106
-
};
107
-
108
101
hdmi0: connector {
109
102
compatible = "hdmi-connector";
110
103
label = "hdmi";
···
319
326
>;
320
327
};
321
328
322
-
extcon_usb2_pins: extcon_usb2_pins {
323
-
pinctrl-single,pins = <
324
-
0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */
325
-
>;
326
-
};
327
-
328
329
tpd12s015_pins: pinmux_tpd12s015_pins {
329
330
pinctrl-single,pins = <
330
331
0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
···
419
432
};
420
433
421
434
ldo3_reg: ldo3 {
422
-
/* VDDA_1V8_PHY */
435
+
/* VDDA_1V8_PHYA */
423
436
regulator-name = "ldo3";
437
+
regulator-min-microvolt = <1800000>;
438
+
regulator-max-microvolt = <1800000>;
439
+
regulator-always-on;
440
+
regulator-boot-on;
441
+
};
442
+
443
+
ldo4_reg: ldo4 {
444
+
/* VDDA_1V8_PHYB */
445
+
regulator-name = "ldo4";
424
446
regulator-min-microvolt = <1800000>;
425
447
regulator-max-microvolt = <1800000>;
426
448
regulator-always-on;
···
491
495
gpio-controller;
492
496
#gpio-cells = <2>;
493
497
};
498
+
499
+
extcon_usb2: tps659038_usb {
500
+
compatible = "ti,palmas-usb-vid";
501
+
ti,enable-vbus-detection;
502
+
ti,enable-id-detection;
503
+
id-gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>;
504
+
};
505
+
494
506
};
495
507
496
508
tmp102: tmp102@48 {
···
521
517
mcp_rtc: rtc@6f {
522
518
compatible = "microchip,mcp7941x";
523
519
reg = <0x6f>;
524
-
interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
520
+
interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
521
+
<&dra7_pmx_core 0x424>;
525
522
526
523
pinctrl-names = "default";
527
524
pinctrl-0 = <&mcp79410_pins_default>;
···
584
579
pinctrl-0 = <&mmc1_pins_default>;
585
580
586
581
vmmc-supply = <&ldo1_reg>;
587
-
vmmc_aux-supply = <&vdd_3v3>;
588
582
bus-width = <4>;
589
583
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
590
584
};
···
627
623
};
628
624
629
625
&usb2 {
626
+
/*
627
+
* Stand alone usage is peripheral only.
628
+
* However, with some resistor modifications
629
+
* this port can be used via expansion connectors
630
+
* as "host" or "dual-role". If so, provide
631
+
* the necessary dr_mode override in the expansion
632
+
* board's DT.
633
+
*/
630
634
dr_mode = "peripheral";
631
635
};
632
636
···
693
681
694
682
&hdmi {
695
683
status = "ok";
696
-
vdda-supply = <&ldo3_reg>;
684
+
vdda-supply = <&ldo4_reg>;
697
685
698
686
pinctrl-names = "default";
699
687
pinctrl-0 = <&hdmi_pins>;
+2
-2
arch/arm/boot/dts/dm8148-evm.dts
+2
-2
arch/arm/boot/dts/dm8148-evm.dts
+3
-3
arch/arm/boot/dts/dm8148-t410.dts
+3
-3
arch/arm/boot/dts/dm8148-t410.dts
···
8
8
#include "dm814x.dtsi"
9
9
10
10
/ {
11
-
model = "DM8148 EVM";
11
+
model = "HP t410 Smart Zero Client";
12
12
compatible = "hp,t410", "ti,dm8148";
13
13
14
14
memory {
···
19
19
20
20
&cpsw_emac0 {
21
21
phy_id = <&davinci_mdio>, <0>;
22
-
phy-mode = "mii";
22
+
phy-mode = "rgmii";
23
23
};
24
24
25
25
&cpsw_emac1 {
26
26
phy_id = <&davinci_mdio>, <1>;
27
-
phy-mode = "mii";
27
+
phy-mode = "rgmii";
28
28
};
+4
-4
arch/arm/boot/dts/dm814x.dtsi
+4
-4
arch/arm/boot/dts/dm814x.dtsi
···
181
181
ti,hwmods = "timer3";
182
182
};
183
183
184
-
control: control@160000 {
184
+
control: control@140000 {
185
185
compatible = "ti,dm814-scm", "simple-bus";
186
-
reg = <0x160000 0x16d000>;
186
+
reg = <0x140000 0x16d000>;
187
187
#address-cells = <1>;
188
188
#size-cells = <1>;
189
189
ranges = <0 0x160000 0x16d000>;
···
321
321
mac-address = [ 00 00 00 00 00 00 ];
322
322
};
323
323
324
-
phy_sel: cpsw-phy-sel@0x48160650 {
324
+
phy_sel: cpsw-phy-sel@48140650 {
325
325
compatible = "ti,am3352-cpsw-phy-sel";
326
-
reg= <0x48160650 0x4>;
326
+
reg= <0x48140650 0x4>;
327
327
reg-names = "gmii-sel";
328
328
};
329
329
};
+3
-2
arch/arm/boot/dts/dra7.dtsi
+3
-2
arch/arm/boot/dts/dra7.dtsi
···
120
120
reg = <0x0 0x1400>;
121
121
#address-cells = <1>;
122
122
#size-cells = <1>;
123
+
ranges = <0 0x0 0x1400>;
123
124
124
125
pbias_regulator: pbias_regulator {
125
-
compatible = "ti,pbias-omap";
126
+
compatible = "ti,pbias-dra7", "ti,pbias-omap";
126
127
reg = <0xe00 0x4>;
127
128
syscon = <&scm_conf>;
128
129
pbias_mmc_reg: pbias_mmc_omap5 {
···
1418
1417
ti,irqs-safe-map = <0>;
1419
1418
};
1420
1419
1421
-
mac: ethernet@4a100000 {
1420
+
mac: ethernet@48484000 {
1422
1421
compatible = "ti,dra7-cpsw","ti,cpsw";
1423
1422
ti,hwmods = "gmac";
1424
1423
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
+2
-1
arch/arm/boot/dts/omap2430.dtsi
+2
-1
arch/arm/boot/dts/omap2430.dtsi
···
56
56
reg = <0x270 0x240>;
57
57
#address-cells = <1>;
58
58
#size-cells = <1>;
59
+
ranges = <0 0x270 0x240>;
59
60
60
61
scm_clocks: clocks {
61
62
#address-cells = <1>;
···
64
63
};
65
64
66
65
pbias_regulator: pbias_regulator {
67
-
compatible = "ti,pbias-omap";
66
+
compatible = "ti,pbias-omap2", "ti,pbias-omap";
68
67
reg = <0x230 0x4>;
69
68
syscon = <&scm_conf>;
70
69
pbias_mmc_reg: pbias_mmc_omap2430 {
+1
-1
arch/arm/boot/dts/omap3-beagle.dts
+1
-1
arch/arm/boot/dts/omap3-beagle.dts
-6
arch/arm/boot/dts/omap3-igep.dtsi
-6
arch/arm/boot/dts/omap3-igep.dtsi
···
78
78
>;
79
79
};
80
80
81
-
smsc9221_pins: pinmux_smsc9221_pins {
82
-
pinctrl-single,pins = <
83
-
0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
84
-
>;
85
-
};
86
-
87
81
i2c1_pins: pinmux_i2c1_pins {
88
82
pinctrl-single,pins = <
89
83
0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+6
arch/arm/boot/dts/omap3-igep0020-common.dtsi
+6
arch/arm/boot/dts/omap3-igep0020-common.dtsi
···
156
156
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
157
157
>;
158
158
};
159
+
160
+
smsc9221_pins: pinmux_smsc9221_pins {
161
+
pinctrl-single,pins = <
162
+
OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
163
+
>;
164
+
};
159
165
};
160
166
161
167
&omap3_pmx_core2 {
+13
-12
arch/arm/boot/dts/omap3.dtsi
+13
-12
arch/arm/boot/dts/omap3.dtsi
···
113
113
};
114
114
115
115
scm_conf: scm_conf@270 {
116
-
compatible = "syscon";
116
+
compatible = "syscon", "simple-bus";
117
117
reg = <0x270 0x330>;
118
118
#address-cells = <1>;
119
119
#size-cells = <1>;
120
+
ranges = <0 0x270 0x330>;
121
+
122
+
pbias_regulator: pbias_regulator {
123
+
compatible = "ti,pbias-omap3", "ti,pbias-omap";
124
+
reg = <0x2b0 0x4>;
125
+
syscon = <&scm_conf>;
126
+
pbias_mmc_reg: pbias_mmc_omap2430 {
127
+
regulator-name = "pbias_mmc_omap2430";
128
+
regulator-min-microvolt = <1800000>;
129
+
regulator-max-microvolt = <3000000>;
130
+
};
131
+
};
120
132
121
133
scm_clocks: clocks {
122
134
#address-cells = <1>;
···
212
200
#dma-cells = <1>;
213
201
dma-channels = <32>;
214
202
dma-requests = <96>;
215
-
};
216
-
217
-
pbias_regulator: pbias_regulator {
218
-
compatible = "ti,pbias-omap";
219
-
reg = <0x2b0 0x4>;
220
-
syscon = <&scm_conf>;
221
-
pbias_mmc_reg: pbias_mmc_omap2430 {
222
-
regulator-name = "pbias_mmc_omap2430";
223
-
regulator-min-microvolt = <1800000>;
224
-
regulator-max-microvolt = <3000000>;
225
-
};
226
203
};
227
204
228
205
gpio1: gpio@48310000 {
+2
-1
arch/arm/boot/dts/omap4.dtsi
+2
-1
arch/arm/boot/dts/omap4.dtsi
···
196
196
reg = <0x5a0 0x170>;
197
197
#address-cells = <1>;
198
198
#size-cells = <1>;
199
+
ranges = <0 0x5a0 0x170>;
199
200
200
201
pbias_regulator: pbias_regulator {
201
-
compatible = "ti,pbias-omap";
202
+
compatible = "ti,pbias-omap4", "ti,pbias-omap";
202
203
reg = <0x60 0x4>;
203
204
syscon = <&omap4_padconf_global>;
204
205
pbias_mmc_reg: pbias_mmc_omap4 {
+2
-2
arch/arm/boot/dts/omap5-uevm.dts
+2
-2
arch/arm/boot/dts/omap5-uevm.dts
···
174
174
175
175
i2c5_pins: pinmux_i2c5_pins {
176
176
pinctrl-single,pins = <
177
-
0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
178
-
0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */
177
+
0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
178
+
0x188 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */
179
179
>;
180
180
};
181
181
+2
-1
arch/arm/boot/dts/omap5.dtsi
+2
-1
arch/arm/boot/dts/omap5.dtsi
···
185
185
reg = <0x5a0 0xec>;
186
186
#address-cells = <1>;
187
187
#size-cells = <1>;
188
+
ranges = <0 0x5a0 0xec>;
188
189
189
190
pbias_regulator: pbias_regulator {
190
-
compatible = "ti,pbias-omap";
191
+
compatible = "ti,pbias-omap5", "ti,pbias-omap";
191
192
reg = <0x60 0x4>;
192
193
syscon = <&omap5_padconf_global>;
193
194
pbias_mmc_reg: pbias_mmc_omap5 {
+1
arch/arm/boot/dts/rk3288-veyron.dtsi
+1
arch/arm/boot/dts/rk3288-veyron.dtsi
+36
-38
arch/arm/boot/dts/stih407.dtsi
+36
-38
arch/arm/boot/dts/stih407.dtsi
···
103
103
<&clk_s_d0_quadfs 0>,
104
104
<&clk_s_d2_quadfs 0>,
105
105
<&clk_s_d2_quadfs 0>;
106
-
ranges;
106
+
};
107
107
108
-
sti-hdmi@8d04000 {
109
-
compatible = "st,stih407-hdmi";
110
-
reg = <0x8d04000 0x1000>;
111
-
reg-names = "hdmi-reg";
112
-
interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
113
-
interrupt-names = "irq";
114
-
clock-names = "pix",
115
-
"tmds",
116
-
"phy",
117
-
"audio",
118
-
"main_parent",
119
-
"aux_parent";
108
+
sti-hdmi@8d04000 {
109
+
compatible = "st,stih407-hdmi";
110
+
reg = <0x8d04000 0x1000>;
111
+
reg-names = "hdmi-reg";
112
+
interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
113
+
interrupt-names = "irq";
114
+
clock-names = "pix",
115
+
"tmds",
116
+
"phy",
117
+
"audio",
118
+
"main_parent",
119
+
"aux_parent";
120
120
121
-
clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
122
-
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
123
-
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
124
-
<&clk_s_d0_flexgen CLK_PCM_0>,
125
-
<&clk_s_d2_quadfs 0>,
126
-
<&clk_s_d2_quadfs 1>;
121
+
clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
122
+
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
123
+
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
124
+
<&clk_s_d0_flexgen CLK_PCM_0>,
125
+
<&clk_s_d2_quadfs 0>,
126
+
<&clk_s_d2_quadfs 1>;
127
127
128
-
hdmi,hpd-gpio = <&pio5 3>;
129
-
reset-names = "hdmi";
130
-
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
131
-
ddc = <&hdmiddc>;
128
+
hdmi,hpd-gpio = <&pio5 3>;
129
+
reset-names = "hdmi";
130
+
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
131
+
ddc = <&hdmiddc>;
132
+
};
132
133
133
-
};
134
-
135
-
sti-hda@8d02000 {
136
-
compatible = "st,stih407-hda";
137
-
reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
138
-
reg-names = "hda-reg", "video-dacs-ctrl";
139
-
clock-names = "pix",
140
-
"hddac",
141
-
"main_parent",
142
-
"aux_parent";
143
-
clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
144
-
<&clk_s_d2_flexgen CLK_HDDAC>,
145
-
<&clk_s_d2_quadfs 0>,
146
-
<&clk_s_d2_quadfs 1>;
147
-
};
134
+
sti-hda@8d02000 {
135
+
compatible = "st,stih407-hda";
136
+
reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
137
+
reg-names = "hda-reg", "video-dacs-ctrl";
138
+
clock-names = "pix",
139
+
"hddac",
140
+
"main_parent",
141
+
"aux_parent";
142
+
clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
143
+
<&clk_s_d2_flexgen CLK_HDDAC>,
144
+
<&clk_s_d2_quadfs 0>,
145
+
<&clk_s_d2_quadfs 1>;
148
146
};
149
147
};
150
148
};
+36
-38
arch/arm/boot/dts/stih410.dtsi
+36
-38
arch/arm/boot/dts/stih410.dtsi
···
178
178
<&clk_s_d0_quadfs 0>,
179
179
<&clk_s_d2_quadfs 0>,
180
180
<&clk_s_d2_quadfs 0>;
181
-
ranges;
181
+
};
182
182
183
-
sti-hdmi@8d04000 {
184
-
compatible = "st,stih407-hdmi";
185
-
reg = <0x8d04000 0x1000>;
186
-
reg-names = "hdmi-reg";
187
-
interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
188
-
interrupt-names = "irq";
189
-
clock-names = "pix",
190
-
"tmds",
191
-
"phy",
192
-
"audio",
193
-
"main_parent",
194
-
"aux_parent";
183
+
sti-hdmi@8d04000 {
184
+
compatible = "st,stih407-hdmi";
185
+
reg = <0x8d04000 0x1000>;
186
+
reg-names = "hdmi-reg";
187
+
interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
188
+
interrupt-names = "irq";
189
+
clock-names = "pix",
190
+
"tmds",
191
+
"phy",
192
+
"audio",
193
+
"main_parent",
194
+
"aux_parent";
195
195
196
-
clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
197
-
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
198
-
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
199
-
<&clk_s_d0_flexgen CLK_PCM_0>,
200
-
<&clk_s_d2_quadfs 0>,
201
-
<&clk_s_d2_quadfs 1>;
196
+
clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
197
+
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
198
+
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
199
+
<&clk_s_d0_flexgen CLK_PCM_0>,
200
+
<&clk_s_d2_quadfs 0>,
201
+
<&clk_s_d2_quadfs 1>;
202
202
203
-
hdmi,hpd-gpio = <&pio5 3>;
204
-
reset-names = "hdmi";
205
-
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
206
-
ddc = <&hdmiddc>;
203
+
hdmi,hpd-gpio = <&pio5 3>;
204
+
reset-names = "hdmi";
205
+
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
206
+
ddc = <&hdmiddc>;
207
+
};
207
208
208
-
};
209
-
210
-
sti-hda@8d02000 {
211
-
compatible = "st,stih407-hda";
212
-
reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
213
-
reg-names = "hda-reg", "video-dacs-ctrl";
214
-
clock-names = "pix",
215
-
"hddac",
216
-
"main_parent",
217
-
"aux_parent";
218
-
clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
219
-
<&clk_s_d2_flexgen CLK_HDDAC>,
220
-
<&clk_s_d2_quadfs 0>,
221
-
<&clk_s_d2_quadfs 1>;
222
-
};
209
+
sti-hda@8d02000 {
210
+
compatible = "st,stih407-hda";
211
+
reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
212
+
reg-names = "hda-reg", "video-dacs-ctrl";
213
+
clock-names = "pix",
214
+
"hddac",
215
+
"main_parent",
216
+
"aux_parent";
217
+
clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
218
+
<&clk_s_d2_flexgen CLK_HDDAC>,
219
+
<&clk_s_d2_quadfs 0>,
220
+
<&clk_s_d2_quadfs 1>;
223
221
};
224
222
};
225
223
+4
-1
arch/arm/configs/omap2plus_defconfig
+4
-1
arch/arm/configs/omap2plus_defconfig
···
240
240
CONFIG_PINCTRL_SINGLE=y
241
241
CONFIG_DEBUG_GPIO=y
242
242
CONFIG_GPIO_SYSFS=y
243
-
CONFIG_GPIO_PCF857X=m
243
+
CONFIG_GPIO_PCA953X=m
244
+
CONFIG_GPIO_PCF857X=y
244
245
CONFIG_GPIO_TWL4030=y
245
246
CONFIG_GPIO_PALMAS=y
246
247
CONFIG_W1=m
···
351
350
CONFIG_USB_MUSB_OMAP2PLUS=m
352
351
CONFIG_USB_MUSB_AM35X=m
353
352
CONFIG_USB_MUSB_DSPS=m
353
+
CONFIG_USB_INVENTRA_DMA=y
354
+
CONFIG_USB_TI_CPPI41_DMA=y
354
355
CONFIG_USB_DWC3=m
355
356
CONFIG_USB_TEST=m
356
357
CONFIG_AM335X_PHY_USB=y
+5
-1
arch/arm/mach-omap2/Kconfig
+5
-1
arch/arm/mach-omap2/Kconfig
···
44
44
select ARM_CPU_SUSPEND if PM
45
45
select ARM_GIC
46
46
select HAVE_ARM_SCU if SMP
47
-
select HAVE_ARM_TWD if SMP
48
47
select HAVE_ARM_ARCH_TIMER
49
48
select ARM_ERRATA_798181 if SMP
49
+
select OMAP_INTERCONNECT
50
50
select OMAP_INTERCONNECT_BARRIER
51
+
select PM_OPP if PM
51
52
52
53
config SOC_AM33XX
53
54
bool "TI AM33XX"
···
71
70
select ARCH_OMAP2PLUS
72
71
select ARM_CPU_SUSPEND if PM
73
72
select ARM_GIC
73
+
select HAVE_ARM_SCU if SMP
74
74
select HAVE_ARM_ARCH_TIMER
75
75
select IRQ_CROSSBAR
76
76
select ARM_ERRATA_798181 if SMP
77
+
select OMAP_INTERCONNECT
77
78
select OMAP_INTERCONNECT_BARRIER
79
+
select PM_OPP if PM
78
80
79
81
config ARCH_OMAP2PLUS
80
82
bool
-7
arch/arm/mach-omap2/board-generic.c
-7
arch/arm/mach-omap2/board-generic.c
···
20
20
21
21
#include "common.h"
22
22
23
-
#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
24
-
#define intc_of_init NULL
25
-
#endif
26
-
#ifndef CONFIG_ARCH_OMAP4
27
-
#define gic_of_init NULL
28
-
#endif
29
-
30
23
static const struct of_device_id omap_dt_match_table[] __initconst = {
31
24
{ .compatible = "simple-bus", },
32
25
{ .compatible = "ti,omap-infra", },
+6
-2
arch/arm/mach-omap2/id.c
+6
-2
arch/arm/mach-omap2/id.c
···
653
653
omap_revision = DRA752_REV_ES1_0;
654
654
break;
655
655
case 1:
656
-
default:
657
656
omap_revision = DRA752_REV_ES1_1;
657
+
break;
658
+
case 2:
659
+
default:
660
+
omap_revision = DRA752_REV_ES2_0;
661
+
break;
658
662
}
659
663
break;
660
664
···
678
674
/* Unknown default to latest silicon rev as default*/
679
675
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
680
676
__func__, idcode, hawkeye, rev);
681
-
omap_revision = DRA752_REV_ES1_1;
677
+
omap_revision = DRA752_REV_ES2_0;
682
678
}
683
679
684
680
sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
+1
arch/arm/mach-omap2/io.c
+1
arch/arm/mach-omap2/io.c
+2
-1
arch/arm/mach-omap2/omap_device.c
+2
-1
arch/arm/mach-omap2/omap_device.c
···
901
901
if (od->hwmods[i]->flags & HWMOD_INIT_NO_IDLE)
902
902
return 0;
903
903
904
-
if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
904
+
if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER &&
905
+
od->_driver_status != BUS_NOTIFY_BIND_DRIVER) {
905
906
if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
906
907
dev_warn(dev, "%s: enabled but no driver. Idling\n",
907
908
__func__);
+2
-1
arch/arm/mach-omap2/pm.h
+2
-1
arch/arm/mach-omap2/pm.h
···
103
103
#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0)
104
104
#define PM_OMAP4_CPU_OSWR_DISABLE (1 << 1)
105
105
106
-
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
106
+
#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) ||\
107
+
defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
107
108
extern u16 pm44xx_errata;
108
109
#define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id))
109
110
#else
+2
arch/arm/mach-omap2/soc.h
+2
arch/arm/mach-omap2/soc.h
···
469
469
#define DRA7XX_CLASS 0x07000000
470
470
#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
471
471
#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
472
+
#define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8))
473
+
#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
472
474
#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
473
475
474
476
void omap2xxx_check_revision(void);
+2
-6
arch/arm/mach-omap2/timer.c
+2
-6
arch/arm/mach-omap2/timer.c
···
297
297
if (IS_ERR(src))
298
298
return PTR_ERR(src);
299
299
300
-
r = clk_set_parent(timer->fclk, src);
301
-
if (r < 0) {
302
-
pr_warn("%s: %s cannot set source\n", __func__, oh->name);
303
-
clk_put(src);
304
-
return r;
305
-
}
300
+
WARN(clk_set_parent(timer->fclk, src) < 0,
301
+
"Cannot set timer parent clock, no PLL clock driver?");
306
302
307
303
clk_put(src);
308
304
+1
-1
arch/arm/mach-omap2/vc.c
+1
-1
arch/arm/mach-omap2/vc.c
···
300
300
301
301
val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
302
302
if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
303
-
(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) {
303
+
(val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) {
304
304
val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
305
305
val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
306
306
pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
+1
-1
arch/arm/mach-pxa/balloon3.c
+1
-1
arch/arm/mach-pxa/balloon3.c
+7
arch/arm/mach-pxa/include/mach/addr-map.h
+7
arch/arm/mach-pxa/include/mach/addr-map.h
+20
-1
arch/arm/mach-pxa/pxa3xx.c
+20
-1
arch/arm/mach-pxa/pxa3xx.c
···
47
47
#define ISRAM_START 0x5c000000
48
48
#define ISRAM_SIZE SZ_256K
49
49
50
+
/*
51
+
* NAND NFC: DFI bus arbitration subset
52
+
*/
53
+
#define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0))
54
+
#define NDCR_ND_ARB_EN (1 << 12)
55
+
#define NDCR_ND_ARB_CNTL (1 << 19)
56
+
50
57
static void __iomem *sram;
51
58
static unsigned long wakeup_src;
52
59
···
369
362
.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
370
363
.length = SMEMC_SIZE,
371
364
.type = MT_DEVICE
372
-
}
365
+
}, {
366
+
.virtual = (unsigned long)NAND_VIRT,
367
+
.pfn = __phys_to_pfn(NAND_PHYS),
368
+
.length = NAND_SIZE,
369
+
.type = MT_DEVICE
370
+
},
373
371
};
374
372
375
373
void __init pxa3xx_map_io(void)
···
430
418
* preserve them here in case they will be referenced later
431
419
*/
432
420
ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
421
+
422
+
/*
423
+
* Disable DFI bus arbitration, to prevent a system bus lock if
424
+
* somebody disables the NAND clock (unused clock) while this
425
+
* bit remains set.
426
+
*/
427
+
NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
433
428
434
429
if ((ret = pxa_init_dma(IRQ_DMA, 32)))
435
430
return ret;
-1
arch/arm/plat-pxa/ssp.c
-1
arch/arm/plat-pxa/ssp.c
···
107
107
{ .compatible = "mvrl,pxa168-ssp", .data = (void *) PXA168_SSP },
108
108
{ .compatible = "mrvl,pxa910-ssp", .data = (void *) PXA910_SSP },
109
109
{ .compatible = "mrvl,ce4100-ssp", .data = (void *) CE4100_SSP },
110
-
{ .compatible = "mrvl,lpss-ssp", .data = (void *) LPSS_SSP },
111
110
{ },
112
111
};
113
112
MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
+8
drivers/firmware/Kconfig
+8
drivers/firmware/Kconfig
···
139
139
bool
140
140
depends on ARM || ARM64
141
141
142
+
config QCOM_SCM_32
143
+
def_bool y
144
+
depends on QCOM_SCM && ARM
145
+
146
+
config QCOM_SCM_64
147
+
def_bool y
148
+
depends on QCOM_SCM && ARM64
149
+
142
150
source "drivers/firmware/broadcom/Kconfig"
143
151
source "drivers/firmware/google/Kconfig"
144
152
source "drivers/firmware/efi/Kconfig"
+2
-1
drivers/firmware/Makefile
+2
-1
drivers/firmware/Makefile
···
13
13
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
14
14
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
15
15
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
16
-
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
16
+
obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o
17
+
obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o
17
18
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
18
19
19
20
obj-y += broadcom/
+63
drivers/firmware/qcom_scm-64.c
+63
drivers/firmware/qcom_scm-64.c
···
1
+
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2
+
*
3
+
* This program is free software; you can redistribute it and/or modify
4
+
* it under the terms of the GNU General Public License version 2 and
5
+
* only version 2 as published by the Free Software Foundation.
6
+
*
7
+
* This program is distributed in the hope that it will be useful,
8
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
9
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10
+
* GNU General Public License for more details.
11
+
*/
12
+
13
+
#include <linux/io.h>
14
+
#include <linux/errno.h>
15
+
#include <linux/qcom_scm.h>
16
+
17
+
/**
18
+
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
19
+
* @entry: Entry point function for the cpus
20
+
* @cpus: The cpumask of cpus that will use the entry point
21
+
*
22
+
* Set the cold boot address of the cpus. Any cpu outside the supported
23
+
* range would be removed from the cpu present mask.
24
+
*/
25
+
int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
26
+
{
27
+
return -ENOTSUPP;
28
+
}
29
+
30
+
/**
31
+
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
32
+
* @entry: Entry point function for the cpus
33
+
* @cpus: The cpumask of cpus that will use the entry point
34
+
*
35
+
* Set the Linux entry point for the SCM to transfer control to when coming
36
+
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
37
+
*/
38
+
int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
39
+
{
40
+
return -ENOTSUPP;
41
+
}
42
+
43
+
/**
44
+
* qcom_scm_cpu_power_down() - Power down the cpu
45
+
* @flags - Flags to flush cache
46
+
*
47
+
* This is an end point to power down cpu. If there was a pending interrupt,
48
+
* the control would return from this function, otherwise, the cpu jumps to the
49
+
* warm boot entry point set for this cpu upon reset.
50
+
*/
51
+
void __qcom_scm_cpu_power_down(u32 flags)
52
+
{
53
+
}
54
+
55
+
int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id)
56
+
{
57
+
return -ENOTSUPP;
58
+
}
59
+
60
+
int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
61
+
{
62
+
return -ENOTSUPP;
63
+
}