tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/msm/dpu: dpu_hw_ctl.h: fix all kernel-doc warnings

Correct and add kernel-doc comments to eliminate all warnings:

Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:18 cannot understand
function prototype: 'enum dpu_ctl_mode_sel'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:58 struct member 'wb'
not described in 'dpu_hw_intf_cfg'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:66 Incorrect use of
kernel-doc format: * kickoff hw operation for Sw controlled interfaces
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:73 Incorrect use of
kernel-doc format: * check if the ctl is started
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:80 Incorrect use of
kernel-doc format: * kickoff prepare is in progress hw operation for sw
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:88 Incorrect use of
kernel-doc format: * Clear the value of the cached pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:96 Incorrect use of
kernel-doc format: * Query the value of the cached pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:103 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:112 Incorrect use of
kernel-doc format: * OR in the given flushbits to the
cached pending_(wb_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:121 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(cwb_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:130 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(intf_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:139 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(periph_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:148 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(merge_3d_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:157 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:166 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:175 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:185 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(dsc_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:194 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(cdm_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:202 Incorrect use of
kernel-doc format: * Write the value of the pending_flush_mask to hardware
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:208 Incorrect use of
kernel-doc format: * Read the value of the flush register
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:215 Incorrect use of
kernel-doc format: * Setup ctl_path interface config
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:223 Incorrect use of
kernel-doc format: * reset ctl_path interface config
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:244 Incorrect use of
kernel-doc format: * Set all blend stages to disabled
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:250 Incorrect use of
kernel-doc format: * Configure layer mixer to pipe configuration
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:262 Incorrect use of
kernel-doc format: * Set active pipes attached to this CTL
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:270 Incorrect use of
kernel-doc format: * Set active layer mixers attached to this CTL
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member
'trigger_start' not described in 'dpu_hw_ctl_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member
'is_started' not described in 'dpu_hw_ctl_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member
'trigger_pending' not described in 'dpu_hw_ctl_ops'
[many here]
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member
'pending_periph_flush_mask' not described in 'dpu_hw_ctl'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member
'pending_merge_3d_flush_mask' not described in 'dpu_hw_ctl'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member
'pending_dspp_flush_mask' not described in 'dpu_hw_ctl'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:327 expecting
prototype for dpu_hw_ctl(). Prototype was for to_dpu_hw_ctl() instead

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/695649/
Link: https://lore.kernel.org/r/20251219184638.1813181-5-rdunlap@infradead.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Randy Dunlap and committed by
Dmitry Baryshkov 686f6aaf ce269538

+53 -31
+53 -31
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
··· 12 12 #include "dpu_hw_sspp.h" 13 13 14 14 /** 15 - * dpu_ctl_mode_sel: Interface mode selection 16 - * DPU_CTL_MODE_SEL_VID: Video mode interface 17 - * DPU_CTL_MODE_SEL_CMD: Command mode interface 15 + * enum dpu_ctl_mode_sel: Interface mode selection 16 + * @DPU_CTL_MODE_SEL_VID: Video mode interface 17 + * @DPU_CTL_MODE_SEL_CMD: Command mode interface 18 18 */ 19 19 enum dpu_ctl_mode_sel { 20 20 DPU_CTL_MODE_SEL_VID = 0, ··· 37 37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 38 38 * @intf : Interface id 39 39 * @intf_master: Master interface id in the dual pipe topology 40 + * @wb: Writeback mode 40 41 * @mode_3d: 3d mux configuration 41 42 * @merge_3d: 3d merge block used 42 43 * @intf_mode_sel: Interface mode, cmd / vid ··· 65 64 */ 66 65 struct dpu_hw_ctl_ops { 67 66 /** 68 - * kickoff hw operation for Sw controlled interfaces 67 + * @trigger_start: kickoff hw operation for Sw controlled interfaces 69 68 * DSI cmd mode and WB interface are SW controlled 70 69 * @ctx : ctl path ctx pointer 71 70 */ 72 71 void (*trigger_start)(struct dpu_hw_ctl *ctx); 73 72 74 73 /** 75 - * check if the ctl is started 74 + * @is_started: check if the ctl is started 76 75 * @ctx : ctl path ctx pointer 77 76 * @Return: true if started, false if stopped 78 77 */ 79 78 bool (*is_started)(struct dpu_hw_ctl *ctx); 80 79 81 80 /** 82 - * kickoff prepare is in progress hw operation for sw 81 + * @trigger_pending: kickoff prepare is in progress hw operation for sw 83 82 * controlled interfaces: DSI cmd mode and WB interface 84 83 * are SW controlled 85 84 * @ctx : ctl path ctx pointer ··· 87 86 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 88 87 89 88 /** 90 - * Clear the value of the cached pending_flush_mask 89 + * @clear_pending_flush: Clear the value of the cached pending_flush_mask 91 90 * No effect on hardware. 92 91 * Required to be implemented. 93 92 * @ctx : ctl path ctx pointer ··· 95 94 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 96 95 97 96 /** 98 - * Query the value of the cached pending_flush_mask 97 + * @get_pending_flush: Query the value of the cached pending_flush_mask 99 98 * No effect on hardware 100 99 * @ctx : ctl path ctx pointer 101 100 */ 102 101 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 103 102 104 103 /** 105 - * OR in the given flushbits to the cached pending_flush_mask 104 + * @update_pending_flush: OR in the given flushbits to the cached 105 + * pending_flush_mask. 106 106 * No effect on hardware 107 107 * @ctx : ctl path ctx pointer 108 108 * @flushbits : module flushmask ··· 112 110 u32 flushbits); 113 111 114 112 /** 115 - * OR in the given flushbits to the cached pending_(wb_)flush_mask 113 + * @update_pending_flush_wb: OR in the given flushbits to the 114 + * cached pending_(wb_)flush_mask. 116 115 * No effect on hardware 117 116 * @ctx : ctl path ctx pointer 118 117 * @blk : writeback block index ··· 122 119 enum dpu_wb blk); 123 120 124 121 /** 125 - * OR in the given flushbits to the cached pending_(cwb_)flush_mask 122 + * @update_pending_flush_cwb: OR in the given flushbits to the 123 + * cached pending_(cwb_)flush_mask. 126 124 * No effect on hardware 127 125 * @ctx : ctl path ctx pointer 128 126 * @blk : concurrent writeback block index ··· 132 128 enum dpu_cwb blk); 133 129 134 130 /** 135 - * OR in the given flushbits to the cached pending_(intf_)flush_mask 131 + * @update_pending_flush_intf: OR in the given flushbits to the 132 + * cached pending_(intf_)flush_mask. 136 133 * No effect on hardware 137 134 * @ctx : ctl path ctx pointer 138 135 * @blk : interface block index ··· 142 137 enum dpu_intf blk); 143 138 144 139 /** 145 - * OR in the given flushbits to the cached pending_(periph_)flush_mask 140 + * @update_pending_flush_periph: OR in the given flushbits to the 141 + * cached pending_(periph_)flush_mask. 146 142 * No effect on hardware 147 143 * @ctx : ctl path ctx pointer 148 144 * @blk : interface block index ··· 152 146 enum dpu_intf blk); 153 147 154 148 /** 155 - * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask 149 + * @update_pending_flush_merge_3d: OR in the given flushbits to the 150 + * cached pending_(merge_3d_)flush_mask. 156 151 * No effect on hardware 157 152 * @ctx : ctl path ctx pointer 158 153 * @blk : interface block index ··· 162 155 enum dpu_merge_3d blk); 163 156 164 157 /** 165 - * OR in the given flushbits to the cached pending_flush_mask 158 + * @update_pending_flush_sspp: OR in the given flushbits to the 159 + * cached pending_flush_mask. 166 160 * No effect on hardware 167 161 * @ctx : ctl path ctx pointer 168 162 * @blk : SSPP block index ··· 172 164 enum dpu_sspp blk); 173 165 174 166 /** 175 - * OR in the given flushbits to the cached pending_flush_mask 167 + * @update_pending_flush_mixer: OR in the given flushbits to the 168 + * cached pending_flush_mask. 176 169 * No effect on hardware 177 170 * @ctx : ctl path ctx pointer 178 171 * @blk : LM block index ··· 182 173 enum dpu_lm blk); 183 174 184 175 /** 185 - * OR in the given flushbits to the cached pending_flush_mask 176 + * @update_pending_flush_dspp: OR in the given flushbits to the 177 + * cached pending_flush_mask. 186 178 * No effect on hardware 187 179 * @ctx : ctl path ctx pointer 188 180 * @blk : DSPP block index ··· 193 183 enum dpu_dspp blk, u32 dspp_sub_blk); 194 184 195 185 /** 196 - * OR in the given flushbits to the cached pending_(dsc_)flush_mask 186 + * @update_pending_flush_dsc: OR in the given flushbits to the 187 + * cached pending_(dsc_)flush_mask. 197 188 * No effect on hardware 198 189 * @ctx: ctl path ctx pointer 199 190 * @blk: interface block index ··· 203 192 enum dpu_dsc blk); 204 193 205 194 /** 206 - * OR in the given flushbits to the cached pending_(cdm_)flush_mask 195 + * @update_pending_flush_cdm: OR in the given flushbits to the 196 + * cached pending_(cdm_)flush_mask. 207 197 * No effect on hardware 208 198 * @ctx: ctl path ctx pointer 209 199 * @cdm_num: idx of cdm to be flushed ··· 212 200 void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num); 213 201 214 202 /** 215 - * Write the value of the pending_flush_mask to hardware 203 + * @trigger_flush: Write the value of the pending_flush_mask to hardware 216 204 * @ctx : ctl path ctx pointer 217 205 */ 218 206 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 219 207 220 208 /** 221 - * Read the value of the flush register 209 + * @get_flush_register: Read the value of the flush register 222 210 * @ctx : ctl path ctx pointer 223 211 * @Return: value of the ctl flush register. 224 212 */ 225 213 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 226 214 227 215 /** 228 - * Setup ctl_path interface config 216 + * @setup_intf_cfg: Setup ctl_path interface config 229 217 * @ctx 230 218 * @cfg : interface config structure pointer 231 219 */ ··· 233 221 struct dpu_hw_intf_cfg *cfg); 234 222 235 223 /** 236 - * reset ctl_path interface config 224 + * @reset_intf_cfg: reset ctl_path interface config 237 225 * @ctx : ctl path ctx pointer 238 226 * @cfg : interface config structure pointer 239 227 */ 240 228 void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx, 241 229 struct dpu_hw_intf_cfg *cfg); 242 230 231 + /** 232 + * @reset: reset function for this ctl type 233 + */ 243 234 int (*reset)(struct dpu_hw_ctl *c); 244 235 245 - /* 246 - * wait_reset_status - checks ctl reset status 236 + /** 237 + * @wait_reset_status: checks ctl reset status 247 238 * @ctx : ctl path ctx pointer 248 239 * 249 240 * This function checks the ctl reset status bit. ··· 257 242 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 258 243 259 244 /** 260 - * Set all blend stages to disabled 245 + * @clear_all_blendstages: Set all blend stages to disabled 261 246 * @ctx : ctl path ctx pointer 262 247 */ 263 248 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 264 249 265 250 /** 266 - * Configure layer mixer to pipe configuration 251 + * @setup_blendstage: Configure layer mixer to pipe configuration 267 252 * @ctx : ctl path ctx pointer 268 253 * @lm : layer mixer enumeration 269 254 * @cfg : blend stage configuration ··· 271 256 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 272 257 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 273 258 259 + /** 260 + * @set_active_fetch_pipes: Set active pipes attached to this CTL 261 + * @ctx: ctl path ctx pointer 262 + * @active_pipes: bitmap of enum dpu_sspp 263 + */ 274 264 void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx, 275 265 unsigned long *fetch_active); 276 266 277 267 /** 278 - * Set active pipes attached to this CTL 268 + * @set_active_pipes: Set active pipes attached to this CTL 279 269 * @ctx: ctl path ctx pointer 280 270 * @active_pipes: bitmap of enum dpu_sspp 281 271 */ ··· 288 268 unsigned long *active_pipes); 289 269 290 270 /** 291 - * Set active layer mixers attached to this CTL 271 + * @set_active_lms: Set active layer mixers attached to this CTL 292 272 * @ctx: ctl path ctx pointer 293 273 * @active_lms: bitmap of enum dpu_lm 294 274 */ 295 275 void (*set_active_lms)(struct dpu_hw_ctl *ctx, 296 276 unsigned long *active_lms); 297 - 298 277 }; 299 278 300 279 /** ··· 308 289 * @pending_intf_flush_mask: pending INTF flush 309 290 * @pending_wb_flush_mask: pending WB flush 310 291 * @pending_cwb_flush_mask: pending CWB flush 292 + * @pending_periph_flush_mask: pending PERIPH flush 293 + * @pending_merge_3d_flush_mask: pending MERGE 3D flush 294 + * @pending_dspp_flush_mask: pending DSPP flush 311 295 * @pending_dsc_flush_mask: pending DSC flush 312 296 * @pending_cdm_flush_mask: pending CDM flush 313 297 * @mdss_ver: MDSS revision information ··· 342 320 }; 343 321 344 322 /** 345 - * dpu_hw_ctl - convert base object dpu_hw_base to container 323 + * to_dpu_hw_ctl - convert base object dpu_hw_base to container 346 324 * @hw: Pointer to base hardware block 347 325 * return: Pointer to hardware block container 348 326 */