Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/ras: add pmfw eeprom smu interfaces
add smu interfaces and its data structures for
pmfw eeprom in uniras
v2: add 'const' to smu messages array, and specify
index for each member when initializing.
Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Gangliang Xie
and committed by
Alex Deucher
689b03a0
45c692a1
+64
+46
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
+46
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
···
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#define RAS_MP1_MSG_QueryValidMcaCeCount 0x3A
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#define RAS_MP1_MSG_McaBankCeDumpDW 0x3B
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static const enum smu_message_type pmfw_eeprom_msgs[] = {
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[RAS_SMU_GetRASTableVersion] = SMU_MSG_GetRASTableVersion,
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[RAS_SMU_GetBadPageCount] = SMU_MSG_GetBadPageCount,
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[RAS_SMU_SetTimestamp] = SMU_MSG_SetTimestamp,
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[RAS_SMU_GetTimestamp] = SMU_MSG_GetTimestamp,
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[RAS_SMU_GetBadPageIpid] = SMU_MSG_GetBadPageIpid,
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[RAS_SMU_EraseRasTable] = SMU_MSG_EraseRasTable,
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[RAS_SMU_GetBadPageMcaAddr] = SMU_MSG_GetBadPageMcaAddr,
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};
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static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core,
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u32 msg, u32 *count)
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{
···
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return ret;
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}
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static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core,
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enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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int ret = 0;
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if (down_read_trylock(&adev->reset_domain->sem)) {
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ret = amdgpu_smu_ras_send_msg(adev,
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pmfw_eeprom_msgs[index], param, read_arg);
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up_read(&adev->reset_domain->sem);
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} else {
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ret = -RAS_CORE_GPU_IN_MODE1_RESET;
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}
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return ret;
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}
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static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core,
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uint64_t *enabled_mask)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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int ret = 0;
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if (down_read_trylock(&adev->reset_domain->sem)) {
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if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT))
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*enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM;
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up_read(&adev->reset_domain->sem);
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} else {
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ret = -RAS_CORE_GPU_IN_MODE1_RESET;
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}
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return ret;
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}
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const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = {
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.mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count,
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.mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank,
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.mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg,
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.mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask,
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};
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+18
drivers/gpu/drm/amd/ras/rascore/ras.h
+18
drivers/gpu/drm/amd/ras/rascore/ras.h
···
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#define GPU_RESET_CAUSE_FATAL (RAS_CORE_RESET_GPU | 0x0002)
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#define GPU_RESET_CAUSE_RMA (RAS_CORE_RESET_GPU | 0x0004)
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enum ras_core_fw_feature_flags {
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RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0),
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};
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enum ras_block_id {
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RAS_BLOCK_ID__UMC = 0,
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RAS_BLOCK_ID__SDMA,
···
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RAS_GPU_STATUS__IS_VF = 0x8,
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};
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enum ras_fw_eeprom_cmd {
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RAS_SMU_GetRASTableVersion = 0,
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RAS_SMU_GetBadPageCount,
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RAS_SMU_SetTimestamp,
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RAS_SMU_GetTimestamp,
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RAS_SMU_GetBadPageIpid,
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RAS_SMU_EraseRasTable,
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RAS_SMU_GetBadPageMcaAddr,
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};
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struct ras_core_context;
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struct ras_bank_ecc;
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struct ras_umc;
···
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u32 msg, u32 *count);
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int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
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u32 msg, u32 idx, u32 reg_idx, u64 *val);
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int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
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enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg);
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int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
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uint64_t *enabled_mask);
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};
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struct ras_eeprom_sys_func {