tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915/gvt: use proper macros for DP AUX CH CTL registers

Use the proper helpers for DP AUX CH CTL registers, instead of
reinventing the wheels.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f30d35f28ef106d6fb2faf100fe1c5e3a42dfa20.1716894909.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Jani Nikula 68cc33f6 d3e80f2d

+20 -23
+16 -19
drivers/gpu/drm/i915/gvt/handlers.c
··· 1083 1083 1084 1084 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1085 1085 event = AUX_CHANNEL_A; 1086 - else if (reg == _PCH_DPB_AUX_CH_CTL || 1086 + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) || 1087 1087 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1088 1088 event = AUX_CHANNEL_B; 1089 - else if (reg == _PCH_DPC_AUX_CH_CTL || 1089 + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) || 1090 1090 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1091 1091 event = AUX_CHANNEL_C; 1092 - else if (reg == _PCH_DPD_AUX_CH_CTL || 1092 + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) || 1093 1093 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1094 1094 event = AUX_CHANNEL_D; 1095 1095 else { ··· 1153 1153 } 1154 1154 } 1155 1155 1156 - #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 1157 - ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 1158 - 1159 - #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 1160 - 1161 1156 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1162 1157 1163 1158 #define dpy_is_valid_port(port) \ ··· 1176 1181 write_vreg(vgpu, offset, p_data, bytes); 1177 1182 data = vgpu_vreg(vgpu, offset); 1178 1183 1179 - if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) 1180 - && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 1184 + if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 && 1185 + offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) { 1181 1186 /* SKL DPB/C/D aux ctl register changed */ 1182 1187 return 0; 1183 1188 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1184 - offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 1189 + offset != i915_mmio_reg_offset(port_index ? 1190 + PCH_DP_AUX_CH_CTL(port_index) : 1191 + DP_AUX_CH_CTL(port_index))) { 1185 1192 /* write to the data registers */ 1186 1193 return 0; 1187 1194 } ··· 2296 2299 gmbus_mmio_write); 2297 2300 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2298 2301 2299 - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2300 - dp_aux_ch_ctl_mmio_write); 2301 - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2302 - dp_aux_ch_ctl_mmio_write); 2303 - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2304 - dp_aux_ch_ctl_mmio_write); 2302 + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2303 + dp_aux_ch_ctl_mmio_write); 2304 + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2305 + dp_aux_ch_ctl_mmio_write); 2306 + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2307 + dp_aux_ch_ctl_mmio_write); 2305 2308 2306 2309 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2307 2310 ··· 2338 2341 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2339 2342 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2340 2343 2341 - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2342 - dp_aux_ch_ctl_mmio_write); 2344 + MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL, 2345 + dp_aux_ch_ctl_mmio_write); 2343 2346 2344 2347 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2345 2348 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+4 -4
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
··· 517 517 MMIO_D(SBI_DATA); 518 518 MMIO_D(SBI_CTL_STAT); 519 519 MMIO_D(PIXCLK_GATE); 520 - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4); 520 + MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4); 521 521 MMIO_D(DDI_BUF_CTL(PORT_A)); 522 522 MMIO_D(DDI_BUF_CTL(PORT_B)); 523 523 MMIO_D(DDI_BUF_CTL(PORT_C)); ··· 888 888 MMIO_D(FORCEWAKE_MT); 889 889 890 890 MMIO_D(PCH_ADPA); 891 - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4); 892 - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4); 893 - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4); 891 + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4); 892 + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4); 893 + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4); 894 894 895 895 MMIO_F(_MMIO(0x70440), 0xc); 896 896 MMIO_F(_MMIO(0x71440), 0xc);