tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pinctrl-v6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

- Fix register naming in the Mediatek mt8189 driver

- Select REGMAP_MMIO for the Realtek RTD driver

- Fix the number of items in groups in the Toshiba Visconti driver

- Fix a memory leak in the Cirrus CS42L43 driver

- Fix a deadlock (!) in Qualcomm pinmux configuration

- Fix use of uninitialized memory and list initialization in the S32CC
pin controller

* tag 'pinctrl-v6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
dt-bindings: pinctrl: xlnx,versal-pinctrl: Add missing unevaluatedProperties on '^conf' nodes
pinctrl: s32cc: initialize gpio_pin_config::list after kmalloc()
pinctrl: s32cc: fix uninitialized memory in s32_pinctrl_desc
pinctrl: qcom: msm: Fix deadlock in pinmux configuration
pinctrl: cirrus: Fix fwnode leak in cs42l43_pin_probe()
dt-bindings: pinctrl: toshiba,visconti: Fix number of items in groups
pinctrl: realtek: Select REGMAP_MMIO for RTD driver
pinctrl: mediatek: mt8189: align register base names to dt-bindings ones
pinctrl: mediatek: mt8196: align register base names to dt-bindings ones

Linus Torvalds 68d804c6 2c26574c

+40 -24
+14 -12
Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
··· 50 50 groups: 51 51 description: 52 52 Name of the pin group to use for the functions. 53 - $ref: /schemas/types.yaml#/definitions/string 54 - enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, 55 - i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp, 56 - spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp, 57 - spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp, 58 - uart0_grp, uart1_grp, uart2_grp, uart3_grp, 59 - pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp, 60 - pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp, 61 - pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp, 62 - pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp, 63 - pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp, 64 - pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp] 53 + items: 54 + enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, 55 + i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp, 56 + spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp, 57 + spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp, 58 + uart0_grp, uart1_grp, uart2_grp, uart3_grp, 59 + pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp, 60 + pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp, 61 + pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp, 62 + pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp, 63 + pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp, 64 + pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp] 65 + minItems: 1 66 + maxItems: 8 65 67 66 68 drive-strength: 67 69 enum: [2, 4, 6, 8, 16, 24, 32]
+1
Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml
··· 74 74 75 75 '^conf': 76 76 type: object 77 + unevaluatedProperties: false 77 78 description: 78 79 Pinctrl node's client devices use subnodes for pin configurations, 79 80 which in turn use the standard properties below.
+18 -3
drivers/pinctrl/cirrus/pinctrl-cs42l43.c
··· 532 532 return ret; 533 533 } 534 534 535 + static void cs42l43_fwnode_put(void *data) 536 + { 537 + fwnode_handle_put(data); 538 + } 539 + 535 540 static int cs42l43_pin_probe(struct platform_device *pdev) 536 541 { 537 542 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); ··· 568 563 priv->gpio_chip.ngpio = CS42L43_NUM_GPIOS; 569 564 570 565 if (is_of_node(fwnode)) { 571 - fwnode = fwnode_get_named_child_node(fwnode, "pinctrl"); 566 + struct fwnode_handle *child; 572 567 573 - if (fwnode && !fwnode->dev) 574 - fwnode->dev = priv->dev; 568 + child = fwnode_get_named_child_node(fwnode, "pinctrl"); 569 + if (child) { 570 + ret = devm_add_action_or_reset(&pdev->dev, 571 + cs42l43_fwnode_put, child); 572 + if (ret) { 573 + fwnode_handle_put(child); 574 + return ret; 575 + } 576 + if (!child->dev) 577 + child->dev = priv->dev; 578 + fwnode = child; 579 + } 575 580 } 576 581 577 582 priv->gpio_chip.fwnode = fwnode;
+1 -3
drivers/pinctrl/mediatek/pinctrl-mt8189.c
··· 1642 1642 }; 1643 1643 1644 1644 static const char * const mt8189_pinctrl_register_base_names[] = { 1645 - "gpio_base", "iocfg_bm0_base", "iocfg_bm1_base", "iocfg_bm2_base", "iocfg_lm_base", 1646 - "iocfg_lt0_base", "iocfg_lt1_base", "iocfg_rb0_base", "iocfg_rb1_base", 1647 - "iocfg_rt_base" 1645 + "base", "lm", "rb0", "rb1", "bm0", "bm1", "bm2", "lt0", "lt1", "rt", 1648 1646 }; 1649 1647 1650 1648 static const struct mtk_eint_hw mt8189_eint_hw = {
+2 -4
drivers/pinctrl/mediatek/pinctrl-mt8196.c
··· 1801 1801 }; 1802 1802 1803 1803 static const char * const mt8196_pinctrl_register_base_names[] = { 1804 - "iocfg0", "iocfg_rt", "iocfg_rm1", "iocfg_rm2", 1805 - "iocfg_rb", "iocfg_bm1", "iocfg_bm2", "iocfg_bm3", 1806 - "iocfg_lt", "iocfg_lm1", "iocfg_lm2", "iocfg_lb1", 1807 - "iocfg_lb2", "iocfg_tm1", "iocfg_tm2", "iocfg_tm3", 1804 + "base", "rt", "rm1", "rm2", "rb", "bm1", "bm2", "bm3", 1805 + "lt", "lm1", "lm2", "lb1", "lb2", "tm1", "tm2", "tm3", 1808 1806 }; 1809 1807 1810 1808 static const struct mtk_eint_hw mt8196_eint_hw = {
+2 -1
drivers/pinctrl/nxp/pinctrl-s32cc.c
··· 392 392 393 393 gpio_pin->pin_id = offset; 394 394 gpio_pin->config = config; 395 + INIT_LIST_HEAD(&gpio_pin->list); 395 396 396 397 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); 397 398 list_add(&gpio_pin->list, &ipctl->gpio_configs); ··· 952 951 spin_lock_init(&ipctl->gpio_configs_lock); 953 952 954 953 s32_pinctrl_desc = 955 - devm_kmalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); 954 + devm_kzalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); 956 955 if (!s32_pinctrl_desc) 957 956 return -ENOMEM; 958 957
+1 -1
drivers/pinctrl/qcom/pinctrl-msm.c
··· 189 189 */ 190 190 if (d && i != gpio_func && 191 191 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) 192 - disable_irq(irq); 192 + disable_irq_nosync(irq); 193 193 194 194 raw_spin_lock_irqsave(&pctrl->lock, flags); 195 195
+1
drivers/pinctrl/realtek/Kconfig
··· 6 6 default y 7 7 select PINMUX 8 8 select GENERIC_PINCONF 9 + select REGMAP_MMIO 9 10 10 11 config PINCTRL_RTD1619B 11 12 tristate "Realtek DHC 1619B pin controller driver"