Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
RDMA/hns: Clean the hardware related code for HEM
Move the HIP06 related code to the hw v1 source file for HEM.
Link: https://lore.kernel.org/r/1621589395-2435-6-git-send-email-liweihang@huawei.com
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
authored by
Xi Wang
and committed by
Jason Gunthorpe
68e11a60
82eb481d
+85
-90
-2
drivers/infiniband/hw/hns/hns_roce_device.h
-2
drivers/infiniband/hw/hns/hns_roce_device.h
+2
-80
drivers/infiniband/hw/hns/hns_roce_hem.c
+2
-80
drivers/infiniband/hw/hns/hns_roce_hem.c
···
36
36
#include "hns_roce_hem.h"
37
37
#include "hns_roce_common.h"
38
38
39
-
#define DMA_ADDR_T_SHIFT 12
40
-
#define BT_BA_SHIFT 32
41
-
42
39
#define HEM_INDEX_BUF BIT(0)
43
40
#define HEM_INDEX_L0 BIT(1)
44
41
#define HEM_INDEX_L1 BIT(2)
···
334
337
kfree(hem);
335
338
}
336
339
337
-
static int hns_roce_set_hem(struct hns_roce_dev *hr_dev,
338
-
struct hns_roce_hem_table *table, unsigned long obj)
339
-
{
340
-
spinlock_t *lock = &hr_dev->bt_cmd_lock;
341
-
struct device *dev = hr_dev->dev;
342
-
struct hns_roce_hem_iter iter;
343
-
void __iomem *bt_cmd;
344
-
__le32 bt_cmd_val[2];
345
-
__le32 bt_cmd_h = 0;
346
-
unsigned long flags;
347
-
__le32 bt_cmd_l;
348
-
int ret = 0;
349
-
u64 bt_ba;
350
-
long end;
351
-
352
-
/* Find the HEM(Hardware Entry Memory) entry */
353
-
unsigned long i = (obj & (table->num_obj - 1)) /
354
-
(table->table_chunk_size / table->obj_size);
355
-
356
-
switch (table->type) {
357
-
case HEM_TYPE_QPC:
358
-
case HEM_TYPE_MTPT:
359
-
case HEM_TYPE_CQC:
360
-
case HEM_TYPE_SRQC:
361
-
roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
362
-
ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
363
-
break;
364
-
default:
365
-
return ret;
366
-
}
367
-
368
-
roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
369
-
ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
370
-
roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
371
-
roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
372
-
373
-
/* Currently iter only a chunk */
374
-
for (hns_roce_hem_first(table->hem[i], &iter);
375
-
!hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
376
-
bt_ba = hns_roce_hem_addr(&iter) >> DMA_ADDR_T_SHIFT;
377
-
378
-
spin_lock_irqsave(lock, flags);
379
-
380
-
bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
381
-
382
-
end = HW_SYNC_TIMEOUT_MSECS;
383
-
while (end > 0) {
384
-
if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
385
-
break;
386
-
387
-
mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
388
-
end -= HW_SYNC_SLEEP_TIME_INTERVAL;
389
-
}
390
-
391
-
if (end <= 0) {
392
-
dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
393
-
spin_unlock_irqrestore(lock, flags);
394
-
return -EBUSY;
395
-
}
396
-
397
-
bt_cmd_l = cpu_to_le32(bt_ba);
398
-
roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
399
-
ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
400
-
bt_ba >> BT_BA_SHIFT);
401
-
402
-
bt_cmd_val[0] = bt_cmd_l;
403
-
bt_cmd_val[1] = bt_cmd_h;
404
-
hns_roce_write64_k(bt_cmd_val,
405
-
hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
406
-
spin_unlock_irqrestore(lock, flags);
407
-
}
408
-
409
-
return ret;
410
-
}
411
-
412
340
static int calc_hem_config(struct hns_roce_dev *hr_dev,
413
341
struct hns_roce_hem_table *table, unsigned long obj,
414
342
struct hns_roce_hem_mhop *mhop,
···
599
677
}
600
678
601
679
/* Set HEM base address(128K/page, pa) to Hardware */
602
-
if (hns_roce_set_hem(hr_dev, table, obj)) {
680
+
if (hr_dev->hw->set_hem(hr_dev, table, obj, HEM_HOP_STEP_DIRECT)) {
603
681
hns_roce_free_hem(hr_dev, table->hem[i]);
604
682
table->hem[i] = NULL;
605
683
ret = -ENODEV;
···
704
782
&table->mutex))
705
783
return;
706
784
707
-
if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
785
+
if (hr_dev->hw->clear_hem(hr_dev, table, obj, HEM_HOP_STEP_DIRECT))
708
786
dev_warn(dev, "failed to clear HEM base address.\n");
709
787
710
788
hns_roce_free_hem(hr_dev, table->hem[i]);
+1
-8
drivers/infiniband/hw/hns/hns_roce_hem.h
+1
-8
drivers/infiniband/hw/hns/hns_roce_hem.h
···
34
34
#ifndef _HNS_ROCE_HEM_H
35
35
#define _HNS_ROCE_HEM_H
36
36
37
-
#define HW_SYNC_SLEEP_TIME_INTERVAL 20
38
-
#define HW_SYNC_TIMEOUT_MSECS (25 * HW_SYNC_SLEEP_TIME_INTERVAL)
39
-
#define BT_CMD_SYNC_SHIFT 31
37
+
#define HEM_HOP_STEP_DIRECT 0xff
40
38
41
39
enum {
42
40
/* MAP HEM(Hardware Entry Memory) */
···
71
73
((type < HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0) || \
72
74
(type >= HEM_TYPE_MTT && hop_num == 1) || \
73
75
(type >= HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0))
74
-
75
-
enum {
76
-
HNS_ROCE_HEM_PAGE_SHIFT = 12,
77
-
HNS_ROCE_HEM_PAGE_SIZE = 1 << HNS_ROCE_HEM_PAGE_SHIFT,
78
-
};
79
76
80
77
struct hns_roce_hem_chunk {
81
78
struct list_head list;
+77
drivers/infiniband/hw/hns/hns_roce_hw_v1.c
+77
drivers/infiniband/hw/hns/hns_roce_hw_v1.c
···
462
462
roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
463
463
}
464
464
465
+
static int hns_roce_v1_set_hem(struct hns_roce_dev *hr_dev,
466
+
struct hns_roce_hem_table *table, int obj,
467
+
int step_idx)
468
+
{
469
+
spinlock_t *lock = &hr_dev->bt_cmd_lock;
470
+
struct device *dev = hr_dev->dev;
471
+
struct hns_roce_hem_iter iter;
472
+
void __iomem *bt_cmd;
473
+
__le32 bt_cmd_val[2];
474
+
__le32 bt_cmd_h = 0;
475
+
unsigned long flags;
476
+
__le32 bt_cmd_l;
477
+
int ret = 0;
478
+
u64 bt_ba;
479
+
long end;
480
+
481
+
/* Find the HEM(Hardware Entry Memory) entry */
482
+
unsigned long i = (obj & (table->num_obj - 1)) /
483
+
(table->table_chunk_size / table->obj_size);
484
+
485
+
switch (table->type) {
486
+
case HEM_TYPE_QPC:
487
+
case HEM_TYPE_MTPT:
488
+
case HEM_TYPE_CQC:
489
+
case HEM_TYPE_SRQC:
490
+
roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
491
+
ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
492
+
break;
493
+
default:
494
+
return ret;
495
+
}
496
+
497
+
roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
498
+
ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
499
+
roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
500
+
roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
501
+
502
+
/* Currently iter only a chunk */
503
+
for (hns_roce_hem_first(table->hem[i], &iter);
504
+
!hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
505
+
bt_ba = hns_roce_hem_addr(&iter) >> HNS_HW_PAGE_SHIFT;
506
+
507
+
spin_lock_irqsave(lock, flags);
508
+
509
+
bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
510
+
511
+
end = HW_SYNC_TIMEOUT_MSECS;
512
+
while (end > 0) {
513
+
if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
514
+
break;
515
+
516
+
mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
517
+
end -= HW_SYNC_SLEEP_TIME_INTERVAL;
518
+
}
519
+
520
+
if (end <= 0) {
521
+
dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
522
+
spin_unlock_irqrestore(lock, flags);
523
+
return -EBUSY;
524
+
}
525
+
526
+
bt_cmd_l = cpu_to_le32(bt_ba);
527
+
roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
528
+
ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
529
+
upper_32_bits(bt_ba));
530
+
531
+
bt_cmd_val[0] = bt_cmd_l;
532
+
bt_cmd_val[1] = bt_cmd_h;
533
+
hns_roce_write64_k(bt_cmd_val,
534
+
hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
535
+
spin_unlock_irqrestore(lock, flags);
536
+
}
537
+
538
+
return ret;
539
+
}
540
+
465
541
static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
466
542
u32 odb_mode)
467
543
{
···
4428
4352
.set_mtu = hns_roce_v1_set_mtu,
4429
4353
.write_mtpt = hns_roce_v1_write_mtpt,
4430
4354
.write_cqc = hns_roce_v1_write_cqc,
4355
+
.set_hem = hns_roce_v1_set_hem,
4431
4356
.clear_hem = hns_roce_v1_clear_hem,
4432
4357
.modify_qp = hns_roce_v1_modify_qp,
4433
4358
.dereg_mr = hns_roce_v1_dereg_mr,
+5
drivers/infiniband/hw/hns/hns_roce_hw_v1.h
+5
drivers/infiniband/hw/hns/hns_roce_hw_v1.h
···
1085
1085
struct hns_roce_ext_db *ext_db;
1086
1086
};
1087
1087
1088
+
#define HW_SYNC_SLEEP_TIME_INTERVAL 20
1089
+
#define HW_SYNC_TIMEOUT_MSECS (25 * HW_SYNC_SLEEP_TIME_INTERVAL)
1090
+
#define BT_CMD_SYNC_SHIFT 31
1091
+
#define HNS_ROCE_BA_SIZE (32 * 4096)
1092
+
1088
1093
struct hns_roce_bt_table {
1089
1094
struct hns_roce_buf_list qpc_buf;
1090
1095
struct hns_roce_buf_list mtpt_buf;