+9

Documentation/devicetree/bindings/clock/qcom,gpucc.yaml

reviewed

··· 53 53 power-domains: 54 54 maxItems: 1 55 55 56 56 + vdd-gfx-supply: 57 57 + description: Regulator supply for the VDD_GFX pads 58 58 + 56 59 '#clock-cells': 57 60 const: 1 58 61 ··· 76 73 - '#clock-cells' 77 74 - '#reset-cells' 78 75 - '#power-domain-cells' 76 76 + 77 77 + # Require that power-domains and vdd-gfx-supply are not both present 78 78 + not: 79 79 + required: 80 80 + - power-domains 81 81 + - vdd-gfx-supply 79 82 80 83 additionalProperties: false 81 84

+1 -1

Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml

reviewed

··· 7 7 title: Q6SSTOP clock Controller 8 8 9 9 maintainers: 10 10 - - Govind Singh <govinds@codeaurora.org> 10 10 + - Bjorn Andersson <andersson@kernel.org> 11 11 12 12 properties: 13 13 compatible:

-61

Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 - %YAML 1.2 3 3 - --- 4 4 - $id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml# 5 5 - $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 - 7 7 - title: Qualcomm Modem Clock Controller on SC7180 8 8 - 9 9 - maintainers: 10 10 - - Taniya Das <quic_tdas@quicinc.com> 11 11 - 12 12 - description: | 13 13 - Qualcomm modem clock control module provides the clocks on SC7180. 14 14 - 15 15 - See also:: include/dt-bindings/clock/qcom,mss-sc7180.h 16 16 - 17 17 - properties: 18 18 - compatible: 19 19 - const: qcom,sc7180-mss 20 20 - 21 21 - clocks: 22 22 - items: 23 23 - - description: gcc_mss_mfab_axi clock from GCC 24 24 - - description: gcc_mss_nav_axi clock from GCC 25 25 - - description: gcc_mss_cfg_ahb clock from GCC 26 26 - 27 27 - clock-names: 28 28 - items: 29 29 - - const: gcc_mss_mfab_axis 30 30 - - const: gcc_mss_nav_axi 31 31 - - const: cfg_ahb 32 32 - 33 33 - '#clock-cells': 34 34 - const: 1 35 35 - 36 36 - reg: 37 37 - maxItems: 1 38 38 - 39 39 - required: 40 40 - - compatible 41 41 - - reg 42 42 - - clocks 43 43 - - '#clock-cells' 44 44 - 45 45 - additionalProperties: false 46 46 - 47 47 - examples: 48 48 - - | 49 49 - #include <dt-bindings/clock/qcom,gcc-sc7180.h> 50 50 - clock-controller@41a8000 { 51 51 - compatible = "qcom,sc7180-mss"; 52 52 - reg = <0x041a8000 0x8000>; 53 53 - clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>, 54 54 - <&gcc GCC_MSS_NAV_AXI_CLK>, 55 55 - <&gcc GCC_MSS_CFG_AHB_CLK>; 56 56 - clock-names = "gcc_mss_mfab_axis", 57 57 - "gcc_mss_nav_axi", 58 58 - "cfg_ahb"; 59 59 - #clock-cells = <1>; 60 60 - }; 61 61 - ...

+2

Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

reviewed

··· 17 17 include/dt-bindings/clock/qcom,sm8450-camcc.h 18 18 include/dt-bindings/clock/qcom,sm8550-camcc.h 19 19 include/dt-bindings/clock/qcom,sc8280xp-camcc.h 20 20 + include/dt-bindings/clock/qcom,x1e80100-camcc.h 20 21 21 22 allOf: 22 23 - $ref: qcom,gcc.yaml# ··· 28 27 - qcom,sc8280xp-camcc 29 28 - qcom,sm8450-camcc 30 29 - qcom,sm8550-camcc 30 30 + - qcom,x1e80100-camcc 31 31 32 32 clocks: 33 33 items:

+2

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

reviewed

··· 18 18 include/dt-bindings/clock/qcom,sm8550-gpucc.h 19 19 include/dt-bindings/reset/qcom,sm8450-gpucc.h 20 20 include/dt-bindings/reset/qcom,sm8650-gpucc.h 21 21 + include/dt-bindings/reset/qcom,x1e80100-gpucc.h 21 22 22 23 properties: 23 24 compatible: ··· 26 25 - qcom,sm8450-gpucc 27 26 - qcom,sm8550-gpucc 28 27 - qcom,sm8650-gpucc 28 28 + - qcom,x1e80100-gpucc 29 29 30 30 clocks: 31 31 items:

+6 -1

Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml

reviewed

··· 14 14 Qualcomm display clock control module provides the clocks, resets and power 15 15 domains on SM8550. 16 16 17 17 - See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h 17 17 + See also: 18 18 + - include/dt-bindings/clock/qcom,sm8550-dispcc.h 19 19 + - include/dt-bindings/clock/qcom,sm8650-dispcc.h 20 20 + - include/dt-bindings/clock/qcom,x1e80100-dispcc.h 18 21 19 22 properties: 20 23 compatible: 21 24 enum: 22 25 - qcom,sm8550-dispcc 26 26 + - qcom,sm8650-dispcc 27 27 + - qcom,x1e80100-dispcc 23 28 24 29 clocks: 25 30 items:

+1

Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml

reviewed

··· 23 23 - enum: 24 24 - qcom,sm8550-tcsr 25 25 - qcom,sm8650-tcsr 26 26 + - qcom,x1e80100-tcsr 26 27 - const: syscon 27 28 28 29 clocks:

-106

Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 - %YAML 1.2 3 3 - --- 4 4 - $id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml# 5 5 - $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 - 7 7 - title: Qualcomm Display Clock & Reset Controller for SM8650 8 8 - 9 9 - maintainers: 10 10 - - Bjorn Andersson <andersson@kernel.org> 11 11 - - Neil Armstrong <neil.armstrong@linaro.org> 12 12 - 13 13 - description: | 14 14 - Qualcomm display clock control module provides the clocks, resets and power 15 15 - domains on SM8650. 16 16 - 17 17 - See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h 18 18 - 19 19 - properties: 20 20 - compatible: 21 21 - enum: 22 22 - - qcom,sm8650-dispcc 23 23 - 24 24 - clocks: 25 25 - items: 26 26 - - description: Board XO source 27 27 - - description: Board Always On XO source 28 28 - - description: Display's AHB clock 29 29 - - description: sleep clock 30 30 - - description: Byte clock from DSI PHY0 31 31 - - description: Pixel clock from DSI PHY0 32 32 - - description: Byte clock from DSI PHY1 33 33 - - description: Pixel clock from DSI PHY1 34 34 - - description: Link clock from DP PHY0 35 35 - - description: VCO DIV clock from DP PHY0 36 36 - - description: Link clock from DP PHY1 37 37 - - description: VCO DIV clock from DP PHY1 38 38 - - description: Link clock from DP PHY2 39 39 - - description: VCO DIV clock from DP PHY2 40 40 - - description: Link clock from DP PHY3 41 41 - - description: VCO DIV clock from DP PHY3 42 42 - 43 43 - '#clock-cells': 44 44 - const: 1 45 45 - 46 46 - '#reset-cells': 47 47 - const: 1 48 48 - 49 49 - '#power-domain-cells': 50 50 - const: 1 51 51 - 52 52 - reg: 53 53 - maxItems: 1 54 54 - 55 55 - power-domains: 56 56 - description: 57 57 - A phandle and PM domain specifier for the MMCX power domain. 58 58 - maxItems: 1 59 59 - 60 60 - required-opps: 61 61 - description: 62 62 - A phandle to an OPP node describing required MMCX performance point. 63 63 - maxItems: 1 64 64 - 65 65 - required: 66 66 - - compatible 67 67 - - reg 68 68 - - clocks 69 69 - - '#clock-cells' 70 70 - - '#reset-cells' 71 71 - - '#power-domain-cells' 72 72 - 73 73 - additionalProperties: false 74 74 - 75 75 - examples: 76 76 - - | 77 77 - #include <dt-bindings/clock/qcom,sm8650-gcc.h> 78 78 - #include <dt-bindings/clock/qcom,rpmh.h> 79 79 - #include <dt-bindings/power/qcom-rpmpd.h> 80 80 - #include <dt-bindings/power/qcom,rpmhpd.h> 81 81 - clock-controller@af00000 { 82 82 - compatible = "qcom,sm8650-dispcc"; 83 83 - reg = <0x0af00000 0x10000>; 84 84 - clocks = <&rpmhcc RPMH_CXO_CLK>, 85 85 - <&rpmhcc RPMH_CXO_CLK_A>, 86 86 - <&gcc GCC_DISP_AHB_CLK>, 87 87 - <&sleep_clk>, 88 88 - <&dsi0_phy 0>, 89 89 - <&dsi0_phy 1>, 90 90 - <&dsi1_phy 0>, 91 91 - <&dsi1_phy 1>, 92 92 - <&dp0_phy 0>, 93 93 - <&dp0_phy 1>, 94 94 - <&dp1_phy 0>, 95 95 - <&dp1_phy 1>, 96 96 - <&dp2_phy 0>, 97 97 - <&dp2_phy 1>, 98 98 - <&dp3_phy 0>, 99 99 - <&dp3_phy 1>; 100 100 - #clock-cells = <1>; 101 101 - #reset-cells = <1>; 102 102 - #power-domain-cells = <1>; 103 103 - power-domains = <&rpmhpd RPMHPD_MMCX>; 104 104 - required-opps = <&rpmhpd_opp_low_svs>; 105 105 - }; 106 106 - ...

+4 -2

Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml

reviewed

··· 24 24 maxItems: 1 25 25 26 26 clocks: 27 27 - maxItems: 1 27 27 + items: 28 28 + - description: AHB peripheral clock 29 29 + - description: CAN bus clock 28 30 29 31 required: 30 32 - compatible ··· 41 39 can@2010c000 { 42 40 compatible = "microchip,mpfs-can"; 43 41 reg = <0x2010c000 0x1000>; 44 44 - clocks = <&clkcfg 17>; 42 42 + clocks = <&clkcfg 17>, <&clkcfg 37>; 45 43 interrupt-parent = <&plic>; 46 44 interrupts = <56>; 47 45 };

+3

drivers/clk/clk.c

reviewed

··· 418 418 if (IS_ERR(hw)) 419 419 return ERR_CAST(hw); 420 420 421 421 + if (!hw) 422 422 + return NULL; 423 423 + 421 424 return hw->core; 422 425 } 423 426

+2 -4

drivers/clk/imx/clk-imx8-acm.c

reviewed

··· 394 394 return ret; 395 395 } 396 396 397 397 - static int imx8_acm_clk_remove(struct platform_device *pdev) 397 397 + static void imx8_acm_clk_remove(struct platform_device *pdev) 398 398 { 399 399 struct imx8_acm_priv *priv = dev_get_drvdata(&pdev->dev); 400 400 401 401 pm_runtime_disable(&pdev->dev); 402 402 403 403 clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); 404 404 - 405 405 - return 0; 406 404 } 407 405 408 406 static const struct imx8_acm_soc_data imx8qm_acm_data = { ··· 468 470 .pm = &imx8_acm_pm_ops, 469 471 }, 470 472 .probe = imx8_acm_clk_probe, 471 471 - .remove = imx8_acm_clk_remove, 473 473 + .remove_new = imx8_acm_clk_remove, 472 474 }; 473 475 module_platform_driver(imx8_acm_clk_driver); 474 476

+2

drivers/clk/meson/axg.c

reviewed

··· 2142 2142 &axg_vclk_input, 2143 2143 &axg_vclk2_input, 2144 2144 &axg_vclk_div, 2145 2145 + &axg_vclk_div1, 2145 2146 &axg_vclk2_div, 2147 2147 + &axg_vclk2_div1, 2146 2148 &axg_vclk_div2_en, 2147 2149 &axg_vclk_div4_en, 2148 2150 &axg_vclk_div6_en,

+87 -67

drivers/clk/microchip/clk-mpfs.c

reviewed

··· 15 15 16 16 /* address offset of control registers */ 17 17 #define REG_MSSPLL_REF_CR 0x08u 18 18 - #define REG_MSSPLL_POSTDIV_CR 0x10u 18 18 + #define REG_MSSPLL_POSTDIV01_CR 0x10u 19 19 + #define REG_MSSPLL_POSTDIV23_CR 0x14u 19 20 #define REG_MSSPLL_SSCG_2_CR 0x2Cu 20 21 #define REG_CLOCK_CONFIG_CR 0x08u 21 22 #define REG_RTC_CLOCK_CR 0x0Cu ··· 27 26 #define MSSPLL_FBDIV_WIDTH 0x0Cu 28 27 #define MSSPLL_REFDIV_SHIFT 0x08u 29 28 #define MSSPLL_REFDIV_WIDTH 0x06u 30 30 - #define MSSPLL_POSTDIV_SHIFT 0x08u 29 29 + #define MSSPLL_POSTDIV02_SHIFT 0x08u 30 30 + #define MSSPLL_POSTDIV13_SHIFT 0x18u 31 31 #define MSSPLL_POSTDIV_WIDTH 0x07u 32 32 #define MSSPLL_FIXED_DIV 4u 33 33 + 34 34 + /* 35 35 + * This clock ID is defined here, rather than the binding headers, as it is an 36 36 + * internal clock only, and therefore has no consumers in other peripheral 37 37 + * blocks. 38 38 + */ 39 39 + #define CLK_MSSPLL_INTERNAL 38u 33 40 34 41 struct mpfs_clock_data { 35 42 struct device *dev; ··· 48 39 49 40 struct mpfs_msspll_hw_clock { 50 41 void __iomem *base; 42 42 + struct clk_hw hw; 43 43 + struct clk_init_data init; 51 44 unsigned int id; 52 45 u32 reg_offset; 53 46 u32 shift; 54 47 u32 width; 55 48 u32 flags; 56 56 - struct clk_hw hw; 57 57 - struct clk_init_data init; 58 49 }; 59 50 60 51 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 52 52 + 53 53 + struct mpfs_msspll_out_hw_clock { 54 54 + void __iomem *base; 55 55 + struct clk_divider output; 56 56 + struct clk_init_data init; 57 57 + unsigned int id; 58 58 + u32 reg_offset; 59 59 + }; 60 60 + 61 61 + #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw) 61 62 62 63 struct mpfs_cfg_hw_clock { 63 64 struct clk_divider cfg; ··· 112 93 { 0, 0 } 113 94 }; 114 95 96 96 + /* 97 97 + * MSS PLL internal clock 98 98 + */ 99 99 + 115 100 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 116 101 { 117 102 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 118 103 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 119 104 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 120 120 - void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 121 121 - u32 mult, ref_div, postdiv; 122 122 - 123 123 - mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 124 124 - mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 125 125 - ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 126 126 - ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 127 127 - postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 128 128 - postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 129 129 - 130 130 - return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 131 131 - } 132 132 - 133 133 - static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 134 134 - { 135 135 - struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 136 136 - void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 137 137 - void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 138 105 u32 mult, ref_div; 139 139 - unsigned long rate_before_ctrl; 140 106 141 107 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 142 108 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 143 109 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 144 110 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 145 111 146 146 - rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 147 147 - 148 148 - return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 149 149 - msspll_hw->flags); 150 150 - } 151 151 - 152 152 - static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 153 153 - { 154 154 - struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 155 155 - void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 156 156 - void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 157 157 - void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 158 158 - u32 mult, ref_div, postdiv; 159 159 - int divider_setting; 160 160 - unsigned long rate_before_ctrl, flags; 161 161 - 162 162 - mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 163 163 - mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 164 164 - ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 165 165 - ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 166 166 - 167 167 - rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 168 168 - divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 169 169 - msspll_hw->flags); 170 170 - 171 171 - if (divider_setting < 0) 172 172 - return divider_setting; 173 173 - 174 174 - spin_lock_irqsave(&mpfs_clk_lock, flags); 175 175 - 176 176 - postdiv = readl_relaxed(postdiv_addr); 177 177 - postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 178 178 - writel_relaxed(postdiv, postdiv_addr); 179 179 - 180 180 - spin_unlock_irqrestore(&mpfs_clk_lock, flags); 181 181 - 182 182 - return 0; 112 112 + return prate * mult / (ref_div * MSSPLL_FIXED_DIV); 183 113 } 184 114 185 115 static const struct clk_ops mpfs_clk_msspll_ops = { 186 116 .recalc_rate = mpfs_clk_msspll_recalc_rate, 187 187 - .round_rate = mpfs_clk_msspll_round_rate, 188 188 - .set_rate = mpfs_clk_msspll_set_rate, 189 117 }; 190 118 191 119 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 192 120 .id = _id, \ 121 121 + .flags = _flags, \ 193 122 .shift = _shift, \ 194 123 .width = _width, \ 195 124 .reg_offset = _offset, \ 196 196 - .flags = _flags, \ 197 125 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 198 126 } 199 127 200 128 static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 201 201 - CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 129 129 + CLK_PLL(CLK_MSSPLL_INTERNAL, "clk_msspll_internal", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 202 130 MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 203 131 }; 204 132 ··· 162 196 ret = devm_clk_hw_register(dev, &msspll_hw->hw); 163 197 if (ret) 164 198 return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 165 165 - CLK_MSSPLL); 199 199 + CLK_MSSPLL_INTERNAL); 166 200 167 201 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 202 202 + } 203 203 + 204 204 + return 0; 205 205 + } 206 206 + 207 207 + /* 208 208 + * MSS PLL output clocks 209 209 + */ 210 210 + 211 211 + #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ 212 212 + .id = _id, \ 213 213 + .output.shift = _shift, \ 214 214 + .output.width = _width, \ 215 215 + .output.table = NULL, \ 216 216 + .reg_offset = _offset, \ 217 217 + .output.flags = _flags, \ 218 218 + .output.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ 219 219 + .output.lock = &mpfs_clk_lock, \ 220 220 + } 221 221 + 222 222 + static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { 223 223 + CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, 224 224 + MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), 225 225 + CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, 226 226 + MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), 227 227 + CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, 228 228 + MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), 229 229 + CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, 230 230 + MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), 231 231 + }; 232 232 + 233 233 + static int mpfs_clk_register_msspll_outs(struct device *dev, 234 234 + struct mpfs_msspll_out_hw_clock *msspll_out_hws, 235 235 + unsigned int num_clks, struct mpfs_clock_data *data) 236 236 + { 237 237 + unsigned int i; 238 238 + int ret; 239 239 + 240 240 + for (i = 0; i < num_clks; i++) { 241 241 + struct mpfs_msspll_out_hw_clock *msspll_out_hw = &msspll_out_hws[i]; 242 242 + 243 243 + msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset; 244 244 + ret = devm_clk_hw_register(dev, &msspll_out_hw->output.hw); 245 245 + if (ret) 246 246 + return dev_err_probe(dev, ret, "failed to register msspll out id: %d\n", 247 247 + msspll_out_hw->id); 248 248 + 249 249 + data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw; 168 250 } 169 251 170 252 return 0; ··· 456 442 int ret; 457 443 458 444 /* CLK_RESERVED is not part of clock arrays, so add 1 */ 459 459 - num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 460 460 - + ARRAY_SIZE(mpfs_periph_clks) + 1; 445 445 + num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_msspll_out_clks) 446 446 + + ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1; 461 447 462 448 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 463 449 if (!clk_data) ··· 477 463 478 464 ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 479 465 clk_data); 466 466 + if (ret) 467 467 + return ret; 468 468 + 469 469 + ret = mpfs_clk_register_msspll_outs(dev, mpfs_msspll_out_clks, 470 470 + ARRAY_SIZE(mpfs_msspll_out_clks), 471 471 + clk_data); 480 472 if (ret) 481 473 return ret; 482 474

+35 -10

drivers/clk/qcom/Kconfig

reviewed

··· 20 20 21 21 if COMMON_CLK_QCOM 22 22 23 23 + config CLK_X1E80100_CAMCC 24 24 + tristate "X1E80100 Camera Clock Controller" 25 25 + depends on ARM64 || COMPILE_TEST 26 26 + select CLK_X1E80100_GCC 27 27 + help 28 28 + Support for the camera clock controller on X1E80100 devices. 29 29 + Say Y if you want to support camera devices and camera functionality. 30 30 + 31 31 + config CLK_X1E80100_DISPCC 32 32 + tristate "X1E80100 Display Clock Controller" 33 33 + depends on ARM64 || COMPILE_TEST 34 34 + select CLK_X1E80100_GCC 35 35 + help 36 36 + Support for the two display clock controllers on Qualcomm 37 37 + Technologies, Inc. X1E80100 devices. 38 38 + Say Y if you want to support display devices and functionality such as 39 39 + splash screen. 40 40 + 23 41 config CLK_X1E80100_GCC 24 42 tristate "X1E80100 Global Clock Controller" 25 43 depends on ARM64 || COMPILE_TEST ··· 47 29 X1E80100 devices. 48 30 Say Y if you want to use peripheral devices such as UART, SPI, I2C, 49 31 USB, UFS, SD/eMMC, PCIe, etc. 32 32 + 33 33 + config CLK_X1E80100_GPUCC 34 34 + tristate "X1E80100 Graphics Clock Controller" 35 35 + depends on ARM64 || COMPILE_TEST 36 36 + select CLK_X1E80100_GCC 37 37 + help 38 38 + Support for the graphics clock controller on X1E80100 devices. 39 39 + Say Y if you want to support graphics controller devices and 40 40 + functionality such as 3D graphics. 41 41 + 42 42 + config CLK_X1E80100_TCSRCC 43 43 + tristate "X1E80100 TCSR Clock Controller" 44 44 + depends on ARM64 || COMPILE_TEST 45 45 + select QCOM_GDSC 46 46 + help 47 47 + Support for the TCSR clock controller on X1E80100 devices. 48 48 + Say Y if you want to use peripheral devices such as SD/UFS. 50 49 51 50 config QCOM_A53PLL 52 51 tristate "MSM8916 A53 PLL" ··· 634 599 controller on SC7280 devices. 635 600 Say Y if you want to use LPASS clocks and power domains of the LPASS 636 601 core clock controller. 637 637 - 638 638 - config SC_MSS_7180 639 639 - tristate "SC7180 Modem Clock Controller" 640 640 - depends on ARM64 || COMPILE_TEST 641 641 - select SC_GCC_7180 642 642 - help 643 643 - Support for the Modem Subsystem clock controller on Qualcomm 644 644 - Technologies, Inc on SC7180 devices. 645 645 - Say Y if you want to use the Modem branch clocks of the Modem 646 646 - subsystem clock controller to reset the MSS subsystem. 647 602 648 603 config SC_VIDEOCC_7180 649 604 tristate "SC7180 Video Clock Controller"

+4 -1

drivers/clk/qcom/Makefile

reviewed

··· 21 21 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o 22 22 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o 23 23 obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o 24 24 + obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o 25 25 + obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o 24 26 obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o 27 27 + obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o 28 28 + obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o 25 29 obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o 26 30 obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o 27 31 obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o ··· 91 87 obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o 92 88 obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o 93 89 obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o 94 94 - obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o 95 90 obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o 96 91 obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o 97 92 obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o

+1 -11

drivers/clk/qcom/camcc-sc7180.c

reviewed

··· 1703 1703 }, 1704 1704 }; 1705 1705 1706 1706 - static int __init cam_cc_sc7180_init(void) 1707 1707 - { 1708 1708 - return platform_driver_register(&cam_cc_sc7180_driver); 1709 1709 - } 1710 1710 - subsys_initcall(cam_cc_sc7180_init); 1711 1711 - 1712 1712 - static void __exit cam_cc_sc7180_exit(void) 1713 1713 - { 1714 1714 - platform_driver_unregister(&cam_cc_sc7180_driver); 1715 1715 - } 1716 1716 - module_exit(cam_cc_sc7180_exit); 1706 1706 + module_platform_driver(cam_cc_sc7180_driver); 1717 1707 1718 1708 MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver"); 1719 1709 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/camcc-sc7280.c

reviewed

··· 2468 2468 }, 2469 2469 }; 2470 2470 2471 2471 - static int __init cam_cc_sc7280_init(void) 2472 2472 - { 2473 2473 - return platform_driver_register(&cam_cc_sc7280_driver); 2474 2474 - } 2475 2475 - subsys_initcall(cam_cc_sc7280_init); 2476 2476 - 2477 2477 - static void __exit cam_cc_sc7280_exit(void) 2478 2478 - { 2479 2479 - platform_driver_unregister(&cam_cc_sc7280_driver); 2480 2480 - } 2481 2481 - module_exit(cam_cc_sc7280_exit); 2471 2471 + module_platform_driver(cam_cc_sc7280_driver); 2482 2472 2483 2473 MODULE_DESCRIPTION("QTI CAM_CC SC7280 Driver"); 2484 2474 MODULE_LICENSE("GPL v2");

+23 -4

drivers/clk/qcom/camcc-sc8280xp.c

reviewed

··· 630 630 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 631 631 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 632 632 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 633 633 + { } 633 634 }; 634 635 635 636 static struct clk_rcg2 camcc_bps_clk_src = { ··· 655 654 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0), 656 655 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 657 656 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 657 657 + { } 658 658 }; 659 659 660 660 static struct clk_rcg2 camcc_camnoc_axi_clk_src = { ··· 675 673 static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = { 676 674 F(19200000, P_BI_TCXO, 1, 0, 0), 677 675 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0), 676 676 + { } 678 677 }; 679 678 680 679 static struct clk_rcg2 camcc_cci_0_clk_src = { ··· 738 735 F(19200000, P_BI_TCXO, 1, 0, 0), 739 736 F(240000000, P_CAMCC_PLL0_OUT_EVEN, 2.5, 0, 0), 740 737 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 738 738 + { } 741 739 }; 742 740 743 741 static struct clk_rcg2 camcc_cphy_rx_clk_src = { ··· 758 754 static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = { 759 755 F(19200000, P_BI_TCXO, 1, 0, 0), 760 756 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 757 757 + { } 761 758 }; 762 759 763 760 static struct clk_rcg2 camcc_csi0phytimer_clk_src = { ··· 823 818 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0), 824 819 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0), 825 820 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 821 821 + { } 826 822 }; 827 823 828 824 static struct clk_rcg2 camcc_fast_ahb_clk_src = { ··· 844 838 F(19200000, P_BI_TCXO, 1, 0, 0), 845 839 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 846 840 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 841 841 + { } 847 842 }; 848 843 849 844 static struct clk_rcg2 camcc_icp_clk_src = { ··· 867 860 F(558000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 868 861 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 869 862 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 863 863 + { } 870 864 }; 871 865 872 866 static struct clk_rcg2 camcc_ife_0_clk_src = { ··· 891 883 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 892 884 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 893 885 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 886 886 + { } 894 887 }; 895 888 896 889 static struct clk_rcg2 camcc_ife_0_csid_clk_src = { ··· 914 905 F(558000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 915 906 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 916 907 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 908 908 + { } 917 909 }; 918 910 919 911 static struct clk_rcg2 camcc_ife_1_clk_src = { ··· 951 941 F(558000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 952 942 F(637000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 953 943 F(760000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 944 944 + { } 954 945 }; 955 946 956 947 static struct clk_rcg2 camcc_ife_2_clk_src = { ··· 973 962 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 974 963 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 975 964 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 965 965 + { } 976 966 }; 977 967 978 968 static struct clk_rcg2 camcc_ife_2_csid_clk_src = { ··· 996 984 F(558000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 997 985 F(637000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 998 986 F(760000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 987 987 + { } 999 988 }; 1000 989 1001 990 static struct clk_rcg2 camcc_ife_3_clk_src = { ··· 1033 1020 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 1034 1021 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 1035 1022 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 1023 1023 + { } 1036 1024 }; 1037 1025 1038 1026 static struct clk_rcg2 camcc_ife_lite_0_clk_src = { ··· 1154 1140 F(475000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1155 1141 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1156 1142 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1143 1143 + { } 1157 1144 }; 1158 1145 1159 1146 static struct clk_rcg2 camcc_ipe_0_clk_src = { ··· 1178 1163 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 1179 1164 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 1180 1165 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 1166 1166 + { } 1181 1167 }; 1182 1168 1183 1169 static struct clk_rcg2 camcc_jpeg_clk_src = { ··· 1200 1184 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 1201 1185 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0), 1202 1186 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 1187 1187 + { } 1203 1188 }; 1204 1189 1205 1190 static struct clk_rcg2 camcc_lrme_clk_src = { ··· 1221 1204 F(19200000, P_BI_TCXO, 1, 0, 0), 1222 1205 F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4), 1223 1206 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0), 1207 1207 + { } 1224 1208 }; 1225 1209 1226 1210 static struct clk_rcg2 camcc_mclk0_clk_src = { ··· 1338 1320 1339 1321 static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = { 1340 1322 F(32000, P_SLEEP_CLK, 1, 0, 0), 1323 1323 + { } 1341 1324 }; 1342 1325 1343 1326 static struct clk_rcg2 camcc_sleep_clk_src = { ··· 1358 1339 static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = { 1359 1340 F(19200000, P_BI_TCXO, 1, 0, 0), 1360 1341 F(80000000, P_CAMCC_PLL7_OUT_EVEN, 6, 0, 0), 1342 1342 + { } 1361 1343 }; 1362 1344 1363 1345 static struct clk_rcg2 camcc_slow_ahb_clk_src = { ··· 1377 1357 1378 1358 static const struct freq_tbl ftbl_camcc_xo_clk_src[] = { 1379 1359 F(19200000, P_BI_TCXO, 1, 0, 0), 1360 1360 + { } 1380 1361 }; 1381 1362 1382 1363 static struct clk_rcg2 camcc_xo_clk_src = { ··· 3031 3010 clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config); 3032 3011 clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config); 3033 3012 3034 3034 - /* 3035 3035 - * Keep camcc_gdsc_clk always enabled: 3036 3036 - */ 3037 3037 - regmap_update_bits(regmap, 0xc1e4, BIT(0), 1); 3013 3013 + /* Keep some clocks always-on */ 3014 3014 + qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */ 3038 3015 3039 3016 ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap); 3040 3017 if (ret)

+1 -11

drivers/clk/qcom/camcc-sdm845.c

reviewed

··· 1746 1746 }, 1747 1747 }; 1748 1748 1749 1749 - static int __init cam_cc_sdm845_init(void) 1750 1750 - { 1751 1751 - return platform_driver_register(&cam_cc_sdm845_driver); 1752 1752 - } 1753 1753 - subsys_initcall(cam_cc_sdm845_init); 1754 1754 - 1755 1755 - static void __exit cam_cc_sdm845_exit(void) 1756 1756 - { 1757 1757 - platform_driver_unregister(&cam_cc_sdm845_driver); 1758 1758 - } 1759 1759 - module_exit(cam_cc_sdm845_exit); 1749 1749 + module_platform_driver(cam_cc_sdm845_driver); 1760 1750 1761 1751 MODULE_DESCRIPTION("QTI CAM_CC SDM845 Driver"); 1762 1752 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/camcc-sm6350.c

reviewed

··· 1890 1890 }, 1891 1891 }; 1892 1892 1893 1893 - static int __init camcc_sm6350_init(void) 1894 1894 - { 1895 1895 - return platform_driver_register(&camcc_sm6350_driver); 1896 1896 - } 1897 1897 - subsys_initcall(camcc_sm6350_init); 1898 1898 - 1899 1899 - static void __exit camcc_sm6350_exit(void) 1900 1900 - { 1901 1901 - platform_driver_unregister(&camcc_sm6350_driver); 1902 1902 - } 1903 1903 - module_exit(camcc_sm6350_exit); 1893 1893 + module_platform_driver(camcc_sm6350_driver); 1904 1894 1905 1895 MODULE_DESCRIPTION("QTI CAMCC SM6350 Driver"); 1906 1896 MODULE_LICENSE("GPL");

+3 -7

drivers/clk/qcom/camcc-sm8550.c

reviewed

··· 3536 3536 clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config); 3537 3537 clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config); 3538 3538 3539 3539 - /* 3540 3540 - * Keep clocks always enabled: 3541 3541 - * cam_cc_gdsc_clk 3542 3542 - * cam_cc_sleep_clk 3543 3543 - */ 3544 3544 - regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0)); 3545 3545 - regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0)); 3539 3539 + /* Keep some clocks always-on */ 3540 3540 + qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */ 3541 3541 + qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */ 3546 3542 3547 3543 ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap); 3548 3544

+2487

drivers/clk/qcom/camcc-x1e80100.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 + */ 5 5 + 6 6 + #include <linux/clk-provider.h> 7 7 + #include <linux/mod_devicetable.h> 8 8 + #include <linux/module.h> 9 9 + #include <linux/platform_device.h> 10 10 + #include <linux/pm_runtime.h> 11 11 + #include <linux/regmap.h> 12 12 + 13 13 + #include <dt-bindings/clock/qcom,x1e80100-camcc.h> 14 14 + 15 15 + #include "clk-alpha-pll.h" 16 16 + #include "clk-branch.h" 17 17 + #include "clk-rcg.h" 18 18 + #include "clk-regmap.h" 19 19 + #include "common.h" 20 20 + #include "gdsc.h" 21 21 + #include "reset.h" 22 22 + 23 23 + enum { 24 24 + DT_IFACE, 25 25 + DT_BI_TCXO, 26 26 + DT_BI_TCXO_AO, 27 27 + DT_SLEEP_CLK, 28 28 + }; 29 29 + 30 30 + enum { 31 31 + P_BI_TCXO, 32 32 + P_BI_TCXO_AO, 33 33 + P_CAM_CC_PLL0_OUT_EVEN, 34 34 + P_CAM_CC_PLL0_OUT_MAIN, 35 35 + P_CAM_CC_PLL0_OUT_ODD, 36 36 + P_CAM_CC_PLL1_OUT_EVEN, 37 37 + P_CAM_CC_PLL2_OUT_EVEN, 38 38 + P_CAM_CC_PLL2_OUT_MAIN, 39 39 + P_CAM_CC_PLL3_OUT_EVEN, 40 40 + P_CAM_CC_PLL4_OUT_EVEN, 41 41 + P_CAM_CC_PLL6_OUT_EVEN, 42 42 + P_CAM_CC_PLL8_OUT_EVEN, 43 43 + P_SLEEP_CLK, 44 44 + }; 45 45 + 46 46 + static const struct pll_vco lucid_ole_vco[] = { 47 47 + { 249600000, 2300000000, 0 }, 48 48 + }; 49 49 + 50 50 + static const struct pll_vco rivian_ole_vco[] = { 51 51 + { 777000000, 1285000000, 0 }, 52 52 + }; 53 53 + 54 54 + static const struct alpha_pll_config cam_cc_pll0_config = { 55 55 + .l = 0x3e, 56 56 + .alpha = 0x8000, 57 57 + .config_ctl_val = 0x20485699, 58 58 + .config_ctl_hi_val = 0x00182261, 59 59 + .config_ctl_hi1_val = 0x82aa299c, 60 60 + .test_ctl_val = 0x00000000, 61 61 + .test_ctl_hi_val = 0x00000003, 62 62 + .test_ctl_hi1_val = 0x00009000, 63 63 + .test_ctl_hi2_val = 0x00000034, 64 64 + .user_ctl_val = 0x00008400, 65 65 + .user_ctl_hi_val = 0x00000005, 66 66 + }; 67 67 + 68 68 + static struct clk_alpha_pll cam_cc_pll0 = { 69 69 + .offset = 0x0, 70 70 + .vco_table = lucid_ole_vco, 71 71 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 72 72 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 73 73 + .clkr = { 74 74 + .hw.init = &(const struct clk_init_data) { 75 75 + .name = "cam_cc_pll0", 76 76 + .parent_data = &(const struct clk_parent_data) { 77 77 + .index = DT_BI_TCXO, 78 78 + }, 79 79 + .num_parents = 1, 80 80 + .ops = &clk_alpha_pll_lucid_evo_ops, 81 81 + }, 82 82 + }, 83 83 + }; 84 84 + 85 85 + static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 86 86 + { 0x1, 2 }, 87 87 + { } 88 88 + }; 89 89 + 90 90 + static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 91 91 + .offset = 0x0, 92 92 + .post_div_shift = 10, 93 93 + .post_div_table = post_div_table_cam_cc_pll0_out_even, 94 94 + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 95 95 + .width = 4, 96 96 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 97 97 + .clkr.hw.init = &(const struct clk_init_data) { 98 98 + .name = "cam_cc_pll0_out_even", 99 99 + .parent_hws = (const struct clk_hw*[]) { 100 100 + &cam_cc_pll0.clkr.hw, 101 101 + }, 102 102 + .num_parents = 1, 103 103 + .flags = CLK_SET_RATE_PARENT, 104 104 + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 105 105 + }, 106 106 + }; 107 107 + 108 108 + static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 109 109 + { 0x2, 3 }, 110 110 + { } 111 111 + }; 112 112 + 113 113 + static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 114 114 + .offset = 0x0, 115 115 + .post_div_shift = 14, 116 116 + .post_div_table = post_div_table_cam_cc_pll0_out_odd, 117 117 + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 118 118 + .width = 4, 119 119 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 120 120 + .clkr.hw.init = &(const struct clk_init_data) { 121 121 + .name = "cam_cc_pll0_out_odd", 122 122 + .parent_hws = (const struct clk_hw*[]) { 123 123 + &cam_cc_pll0.clkr.hw, 124 124 + }, 125 125 + .num_parents = 1, 126 126 + .flags = CLK_SET_RATE_PARENT, 127 127 + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 128 128 + }, 129 129 + }; 130 130 + 131 131 + static const struct alpha_pll_config cam_cc_pll1_config = { 132 132 + .l = 0x1f, 133 133 + .alpha = 0xaaaa, 134 134 + .config_ctl_val = 0x20485699, 135 135 + .config_ctl_hi_val = 0x00182261, 136 136 + .config_ctl_hi1_val = 0x82aa299c, 137 137 + .test_ctl_val = 0x00000000, 138 138 + .test_ctl_hi_val = 0x00000003, 139 139 + .test_ctl_hi1_val = 0x00009000, 140 140 + .test_ctl_hi2_val = 0x00000034, 141 141 + .user_ctl_val = 0x00000400, 142 142 + .user_ctl_hi_val = 0x00000005, 143 143 + }; 144 144 + 145 145 + static struct clk_alpha_pll cam_cc_pll1 = { 146 146 + .offset = 0x1000, 147 147 + .vco_table = lucid_ole_vco, 148 148 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 149 149 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 150 150 + .clkr = { 151 151 + .hw.init = &(const struct clk_init_data) { 152 152 + .name = "cam_cc_pll1", 153 153 + .parent_data = &(const struct clk_parent_data) { 154 154 + .index = DT_BI_TCXO, 155 155 + }, 156 156 + .num_parents = 1, 157 157 + .ops = &clk_alpha_pll_lucid_evo_ops, 158 158 + }, 159 159 + }, 160 160 + }; 161 161 + 162 162 + static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 163 163 + { 0x1, 2 }, 164 164 + { } 165 165 + }; 166 166 + 167 167 + static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 168 168 + .offset = 0x1000, 169 169 + .post_div_shift = 10, 170 170 + .post_div_table = post_div_table_cam_cc_pll1_out_even, 171 171 + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 172 172 + .width = 4, 173 173 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 174 174 + .clkr.hw.init = &(const struct clk_init_data) { 175 175 + .name = "cam_cc_pll1_out_even", 176 176 + .parent_hws = (const struct clk_hw*[]) { 177 177 + &cam_cc_pll1.clkr.hw, 178 178 + }, 179 179 + .num_parents = 1, 180 180 + .flags = CLK_SET_RATE_PARENT, 181 181 + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 182 182 + }, 183 183 + }; 184 184 + 185 185 + static const struct alpha_pll_config cam_cc_pll2_config = { 186 186 + .l = 0x32, 187 187 + .alpha = 0x0, 188 188 + .config_ctl_val = 0x10000030, 189 189 + .config_ctl_hi_val = 0x80890263, 190 190 + .config_ctl_hi1_val = 0x00000217, 191 191 + .user_ctl_val = 0x00000001, 192 192 + .user_ctl_hi_val = 0x00000000, 193 193 + }; 194 194 + 195 195 + static struct clk_alpha_pll cam_cc_pll2 = { 196 196 + .offset = 0x2000, 197 197 + .vco_table = rivian_ole_vco, 198 198 + .num_vco = ARRAY_SIZE(rivian_ole_vco), 199 199 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 200 200 + .clkr = { 201 201 + .hw.init = &(const struct clk_init_data) { 202 202 + .name = "cam_cc_pll2", 203 203 + .parent_data = &(const struct clk_parent_data) { 204 204 + .index = DT_BI_TCXO, 205 205 + }, 206 206 + .num_parents = 1, 207 207 + .ops = &clk_alpha_pll_rivian_evo_ops, 208 208 + }, 209 209 + }, 210 210 + }; 211 211 + 212 212 + static const struct alpha_pll_config cam_cc_pll3_config = { 213 213 + .l = 0x24, 214 214 + .alpha = 0x0, 215 215 + .config_ctl_val = 0x20485699, 216 216 + .config_ctl_hi_val = 0x00182261, 217 217 + .config_ctl_hi1_val = 0x82aa299c, 218 218 + .test_ctl_val = 0x00000000, 219 219 + .test_ctl_hi_val = 0x00000003, 220 220 + .test_ctl_hi1_val = 0x00009000, 221 221 + .test_ctl_hi2_val = 0x00000034, 222 222 + .user_ctl_val = 0x00000400, 223 223 + .user_ctl_hi_val = 0x00000005, 224 224 + }; 225 225 + 226 226 + static struct clk_alpha_pll cam_cc_pll3 = { 227 227 + .offset = 0x3000, 228 228 + .vco_table = lucid_ole_vco, 229 229 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 230 230 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 231 231 + .clkr = { 232 232 + .hw.init = &(const struct clk_init_data) { 233 233 + .name = "cam_cc_pll3", 234 234 + .parent_data = &(const struct clk_parent_data) { 235 235 + .index = DT_BI_TCXO, 236 236 + }, 237 237 + .num_parents = 1, 238 238 + .ops = &clk_alpha_pll_lucid_evo_ops, 239 239 + }, 240 240 + }, 241 241 + }; 242 242 + 243 243 + static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 244 244 + { 0x1, 2 }, 245 245 + { } 246 246 + }; 247 247 + 248 248 + static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 249 249 + .offset = 0x3000, 250 250 + .post_div_shift = 10, 251 251 + .post_div_table = post_div_table_cam_cc_pll3_out_even, 252 252 + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 253 253 + .width = 4, 254 254 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 255 255 + .clkr.hw.init = &(const struct clk_init_data) { 256 256 + .name = "cam_cc_pll3_out_even", 257 257 + .parent_hws = (const struct clk_hw*[]) { 258 258 + &cam_cc_pll3.clkr.hw, 259 259 + }, 260 260 + .num_parents = 1, 261 261 + .flags = CLK_SET_RATE_PARENT, 262 262 + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 263 263 + }, 264 264 + }; 265 265 + 266 266 + static const struct alpha_pll_config cam_cc_pll4_config = { 267 267 + .l = 0x24, 268 268 + .alpha = 0x0, 269 269 + .config_ctl_val = 0x20485699, 270 270 + .config_ctl_hi_val = 0x00182261, 271 271 + .config_ctl_hi1_val = 0x82aa299c, 272 272 + .test_ctl_val = 0x00000000, 273 273 + .test_ctl_hi_val = 0x00000003, 274 274 + .test_ctl_hi1_val = 0x00009000, 275 275 + .test_ctl_hi2_val = 0x00000034, 276 276 + .user_ctl_val = 0x00000400, 277 277 + .user_ctl_hi_val = 0x00000005, 278 278 + }; 279 279 + 280 280 + static struct clk_alpha_pll cam_cc_pll4 = { 281 281 + .offset = 0x4000, 282 282 + .vco_table = lucid_ole_vco, 283 283 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 284 284 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 285 285 + .clkr = { 286 286 + .hw.init = &(const struct clk_init_data) { 287 287 + .name = "cam_cc_pll4", 288 288 + .parent_data = &(const struct clk_parent_data) { 289 289 + .index = DT_BI_TCXO, 290 290 + }, 291 291 + .num_parents = 1, 292 292 + .ops = &clk_alpha_pll_lucid_evo_ops, 293 293 + }, 294 294 + }, 295 295 + }; 296 296 + 297 297 + static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 298 298 + { 0x1, 2 }, 299 299 + { } 300 300 + }; 301 301 + 302 302 + static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 303 303 + .offset = 0x4000, 304 304 + .post_div_shift = 10, 305 305 + .post_div_table = post_div_table_cam_cc_pll4_out_even, 306 306 + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 307 307 + .width = 4, 308 308 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 309 309 + .clkr.hw.init = &(const struct clk_init_data) { 310 310 + .name = "cam_cc_pll4_out_even", 311 311 + .parent_hws = (const struct clk_hw*[]) { 312 312 + &cam_cc_pll4.clkr.hw, 313 313 + }, 314 314 + .num_parents = 1, 315 315 + .flags = CLK_SET_RATE_PARENT, 316 316 + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 317 317 + }, 318 318 + }; 319 319 + 320 320 + static const struct alpha_pll_config cam_cc_pll6_config = { 321 321 + .l = 0x24, 322 322 + .alpha = 0x0, 323 323 + .config_ctl_val = 0x20485699, 324 324 + .config_ctl_hi_val = 0x00182261, 325 325 + .config_ctl_hi1_val = 0x82aa299c, 326 326 + .test_ctl_val = 0x00000000, 327 327 + .test_ctl_hi_val = 0x00000003, 328 328 + .test_ctl_hi1_val = 0x00009000, 329 329 + .test_ctl_hi2_val = 0x00000034, 330 330 + .user_ctl_val = 0x00000400, 331 331 + .user_ctl_hi_val = 0x00000005, 332 332 + }; 333 333 + 334 334 + static struct clk_alpha_pll cam_cc_pll6 = { 335 335 + .offset = 0x6000, 336 336 + .vco_table = lucid_ole_vco, 337 337 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 338 338 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 339 339 + .clkr = { 340 340 + .hw.init = &(const struct clk_init_data) { 341 341 + .name = "cam_cc_pll6", 342 342 + .parent_data = &(const struct clk_parent_data) { 343 343 + .index = DT_BI_TCXO, 344 344 + }, 345 345 + .num_parents = 1, 346 346 + .ops = &clk_alpha_pll_lucid_evo_ops, 347 347 + }, 348 348 + }, 349 349 + }; 350 350 + 351 351 + static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 352 352 + { 0x1, 2 }, 353 353 + { } 354 354 + }; 355 355 + 356 356 + static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 357 357 + .offset = 0x6000, 358 358 + .post_div_shift = 10, 359 359 + .post_div_table = post_div_table_cam_cc_pll6_out_even, 360 360 + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 361 361 + .width = 4, 362 362 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 363 363 + .clkr.hw.init = &(const struct clk_init_data) { 364 364 + .name = "cam_cc_pll6_out_even", 365 365 + .parent_hws = (const struct clk_hw*[]) { 366 366 + &cam_cc_pll6.clkr.hw, 367 367 + }, 368 368 + .num_parents = 1, 369 369 + .flags = CLK_SET_RATE_PARENT, 370 370 + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 371 371 + }, 372 372 + }; 373 373 + 374 374 + static const struct alpha_pll_config cam_cc_pll8_config = { 375 375 + .l = 0x32, 376 376 + .alpha = 0x0, 377 377 + .config_ctl_val = 0x20485699, 378 378 + .config_ctl_hi_val = 0x00182261, 379 379 + .config_ctl_hi1_val = 0x82aa299c, 380 380 + .test_ctl_val = 0x00000000, 381 381 + .test_ctl_hi_val = 0x00000003, 382 382 + .test_ctl_hi1_val = 0x00009000, 383 383 + .test_ctl_hi2_val = 0x00000034, 384 384 + .user_ctl_val = 0x00000400, 385 385 + .user_ctl_hi_val = 0x00000005, 386 386 + }; 387 387 + 388 388 + static struct clk_alpha_pll cam_cc_pll8 = { 389 389 + .offset = 0x8000, 390 390 + .vco_table = lucid_ole_vco, 391 391 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 392 392 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 393 393 + .clkr = { 394 394 + .hw.init = &(const struct clk_init_data) { 395 395 + .name = "cam_cc_pll8", 396 396 + .parent_data = &(const struct clk_parent_data) { 397 397 + .index = DT_BI_TCXO, 398 398 + }, 399 399 + .num_parents = 1, 400 400 + .ops = &clk_alpha_pll_lucid_evo_ops, 401 401 + }, 402 402 + }, 403 403 + }; 404 404 + 405 405 + static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { 406 406 + { 0x1, 2 }, 407 407 + { } 408 408 + }; 409 409 + 410 410 + static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { 411 411 + .offset = 0x8000, 412 412 + .post_div_shift = 10, 413 413 + .post_div_table = post_div_table_cam_cc_pll8_out_even, 414 414 + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), 415 415 + .width = 4, 416 416 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 417 417 + .clkr.hw.init = &(const struct clk_init_data) { 418 418 + .name = "cam_cc_pll8_out_even", 419 419 + .parent_hws = (const struct clk_hw*[]) { 420 420 + &cam_cc_pll8.clkr.hw, 421 421 + }, 422 422 + .num_parents = 1, 423 423 + .flags = CLK_SET_RATE_PARENT, 424 424 + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 425 425 + }, 426 426 + }; 427 427 + 428 428 + static const struct parent_map cam_cc_parent_map_0[] = { 429 429 + { P_BI_TCXO, 0 }, 430 430 + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 431 431 + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 432 432 + { P_CAM_CC_PLL0_OUT_ODD, 3 }, 433 433 + { P_CAM_CC_PLL8_OUT_EVEN, 5 }, 434 434 + }; 435 435 + 436 436 + static const struct clk_parent_data cam_cc_parent_data_0[] = { 437 437 + { .index = DT_BI_TCXO }, 438 438 + { .hw = &cam_cc_pll0.clkr.hw }, 439 439 + { .hw = &cam_cc_pll0_out_even.clkr.hw }, 440 440 + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 441 441 + { .hw = &cam_cc_pll8_out_even.clkr.hw }, 442 442 + }; 443 443 + 444 444 + static const struct parent_map cam_cc_parent_map_1[] = { 445 445 + { P_BI_TCXO, 0 }, 446 446 + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 447 447 + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 448 448 + }; 449 449 + 450 450 + static const struct clk_parent_data cam_cc_parent_data_1[] = { 451 451 + { .index = DT_BI_TCXO }, 452 452 + { .hw = &cam_cc_pll2.clkr.hw }, 453 453 + { .hw = &cam_cc_pll2.clkr.hw }, 454 454 + }; 455 455 + 456 456 + static const struct parent_map cam_cc_parent_map_2[] = { 457 457 + { P_BI_TCXO, 0 }, 458 458 + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 459 459 + }; 460 460 + 461 461 + static const struct clk_parent_data cam_cc_parent_data_2[] = { 462 462 + { .index = DT_BI_TCXO }, 463 463 + { .hw = &cam_cc_pll3_out_even.clkr.hw }, 464 464 + }; 465 465 + 466 466 + static const struct parent_map cam_cc_parent_map_3[] = { 467 467 + { P_BI_TCXO, 0 }, 468 468 + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 469 469 + }; 470 470 + 471 471 + static const struct clk_parent_data cam_cc_parent_data_3[] = { 472 472 + { .index = DT_BI_TCXO }, 473 473 + { .hw = &cam_cc_pll4_out_even.clkr.hw }, 474 474 + }; 475 475 + 476 476 + static const struct parent_map cam_cc_parent_map_4[] = { 477 477 + { P_BI_TCXO, 0 }, 478 478 + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 479 479 + }; 480 480 + 481 481 + static const struct clk_parent_data cam_cc_parent_data_4[] = { 482 482 + { .index = DT_BI_TCXO }, 483 483 + { .hw = &cam_cc_pll1_out_even.clkr.hw }, 484 484 + }; 485 485 + 486 486 + static const struct parent_map cam_cc_parent_map_5[] = { 487 487 + { P_BI_TCXO, 0 }, 488 488 + { P_CAM_CC_PLL6_OUT_EVEN, 6 }, 489 489 + }; 490 490 + 491 491 + static const struct clk_parent_data cam_cc_parent_data_5[] = { 492 492 + { .index = DT_BI_TCXO }, 493 493 + { .hw = &cam_cc_pll6_out_even.clkr.hw }, 494 494 + }; 495 495 + 496 496 + static const struct parent_map cam_cc_parent_map_6[] = { 497 497 + { P_SLEEP_CLK, 0 }, 498 498 + }; 499 499 + 500 500 + static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 501 501 + { .index = DT_SLEEP_CLK }, 502 502 + }; 503 503 + 504 504 + static const struct parent_map cam_cc_parent_map_7[] = { 505 505 + { P_BI_TCXO, 0 }, 506 506 + }; 507 507 + 508 508 + static const struct clk_parent_data cam_cc_parent_data_7_ao[] = { 509 509 + { .index = DT_BI_TCXO_AO }, 510 510 + }; 511 511 + 512 512 + static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 513 513 + F(19200000, P_BI_TCXO, 1, 0, 0), 514 514 + F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 515 515 + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 516 516 + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 517 517 + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 518 518 + { } 519 519 + }; 520 520 + 521 521 + static struct clk_rcg2 cam_cc_bps_clk_src = { 522 522 + .cmd_rcgr = 0x10278, 523 523 + .mnd_width = 0, 524 524 + .hid_width = 5, 525 525 + .parent_map = cam_cc_parent_map_0, 526 526 + .freq_tbl = ftbl_cam_cc_bps_clk_src, 527 527 + .clkr.hw.init = &(const struct clk_init_data) { 528 528 + .name = "cam_cc_bps_clk_src", 529 529 + .parent_data = cam_cc_parent_data_0, 530 530 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 531 531 + .flags = CLK_SET_RATE_PARENT, 532 532 + .ops = &clk_rcg2_shared_ops, 533 533 + }, 534 534 + }; 535 535 + 536 536 + static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { 537 537 + F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 538 538 + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 539 539 + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 540 540 + { } 541 541 + }; 542 542 + 543 543 + static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { 544 544 + .cmd_rcgr = 0x138f8, 545 545 + .mnd_width = 0, 546 546 + .hid_width = 5, 547 547 + .parent_map = cam_cc_parent_map_0, 548 548 + .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, 549 549 + .clkr.hw.init = &(const struct clk_init_data) { 550 550 + .name = "cam_cc_camnoc_axi_rt_clk_src", 551 551 + .parent_data = cam_cc_parent_data_0, 552 552 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 553 553 + .flags = CLK_SET_RATE_PARENT, 554 554 + .ops = &clk_rcg2_shared_ops, 555 555 + }, 556 556 + }; 557 557 + 558 558 + static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 559 559 + F(19200000, P_BI_TCXO, 1, 0, 0), 560 560 + F(30000000, P_CAM_CC_PLL8_OUT_EVEN, 16, 0, 0), 561 561 + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 562 562 + { } 563 563 + }; 564 564 + 565 565 + static struct clk_rcg2 cam_cc_cci_0_clk_src = { 566 566 + .cmd_rcgr = 0x1365c, 567 567 + .mnd_width = 8, 568 568 + .hid_width = 5, 569 569 + .parent_map = cam_cc_parent_map_0, 570 570 + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 571 571 + .clkr.hw.init = &(const struct clk_init_data) { 572 572 + .name = "cam_cc_cci_0_clk_src", 573 573 + .parent_data = cam_cc_parent_data_0, 574 574 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 575 575 + .flags = CLK_SET_RATE_PARENT, 576 576 + .ops = &clk_rcg2_ops, 577 577 + }, 578 578 + }; 579 579 + 580 580 + static struct clk_rcg2 cam_cc_cci_1_clk_src = { 581 581 + .cmd_rcgr = 0x1378c, 582 582 + .mnd_width = 8, 583 583 + .hid_width = 5, 584 584 + .parent_map = cam_cc_parent_map_0, 585 585 + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 586 586 + .clkr.hw.init = &(const struct clk_init_data) { 587 587 + .name = "cam_cc_cci_1_clk_src", 588 588 + .parent_data = cam_cc_parent_data_0, 589 589 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 590 590 + .flags = CLK_SET_RATE_PARENT, 591 591 + .ops = &clk_rcg2_ops, 592 592 + }, 593 593 + }; 594 594 + 595 595 + static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 596 596 + F(19200000, P_BI_TCXO, 1, 0, 0), 597 597 + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 598 598 + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 599 599 + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 600 600 + { } 601 601 + }; 602 602 + 603 603 + static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 604 604 + .cmd_rcgr = 0x11164, 605 605 + .mnd_width = 0, 606 606 + .hid_width = 5, 607 607 + .parent_map = cam_cc_parent_map_0, 608 608 + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 609 609 + .clkr.hw.init = &(const struct clk_init_data) { 610 610 + .name = "cam_cc_cphy_rx_clk_src", 611 611 + .parent_data = cam_cc_parent_data_0, 612 612 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 613 613 + .flags = CLK_SET_RATE_PARENT, 614 614 + .ops = &clk_rcg2_ops, 615 615 + }, 616 616 + }; 617 617 + 618 618 + static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 619 619 + F(19200000, P_BI_TCXO, 1, 0, 0), 620 620 + F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 621 621 + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 622 622 + { } 623 623 + }; 624 624 + 625 625 + static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 626 626 + .cmd_rcgr = 0x150e0, 627 627 + .mnd_width = 0, 628 628 + .hid_width = 5, 629 629 + .parent_map = cam_cc_parent_map_0, 630 630 + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 631 631 + .clkr.hw.init = &(const struct clk_init_data) { 632 632 + .name = "cam_cc_csi0phytimer_clk_src", 633 633 + .parent_data = cam_cc_parent_data_0, 634 634 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 635 635 + .flags = CLK_SET_RATE_PARENT, 636 636 + .ops = &clk_rcg2_ops, 637 637 + }, 638 638 + }; 639 639 + 640 640 + static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 641 641 + .cmd_rcgr = 0x15104, 642 642 + .mnd_width = 0, 643 643 + .hid_width = 5, 644 644 + .parent_map = cam_cc_parent_map_0, 645 645 + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 646 646 + .clkr.hw.init = &(const struct clk_init_data) { 647 647 + .name = "cam_cc_csi1phytimer_clk_src", 648 648 + .parent_data = cam_cc_parent_data_0, 649 649 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 650 650 + .flags = CLK_SET_RATE_PARENT, 651 651 + .ops = &clk_rcg2_ops, 652 652 + }, 653 653 + }; 654 654 + 655 655 + static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 656 656 + .cmd_rcgr = 0x15124, 657 657 + .mnd_width = 0, 658 658 + .hid_width = 5, 659 659 + .parent_map = cam_cc_parent_map_0, 660 660 + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 661 661 + .clkr.hw.init = &(const struct clk_init_data) { 662 662 + .name = "cam_cc_csi2phytimer_clk_src", 663 663 + .parent_data = cam_cc_parent_data_0, 664 664 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 665 665 + .flags = CLK_SET_RATE_PARENT, 666 666 + .ops = &clk_rcg2_ops, 667 667 + }, 668 668 + }; 669 669 + 670 670 + static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 671 671 + .cmd_rcgr = 0x15258, 672 672 + .mnd_width = 0, 673 673 + .hid_width = 5, 674 674 + .parent_map = cam_cc_parent_map_0, 675 675 + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 676 676 + .clkr.hw.init = &(const struct clk_init_data) { 677 677 + .name = "cam_cc_csi3phytimer_clk_src", 678 678 + .parent_data = cam_cc_parent_data_0, 679 679 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 680 680 + .flags = CLK_SET_RATE_PARENT, 681 681 + .ops = &clk_rcg2_ops, 682 682 + }, 683 683 + }; 684 684 + 685 685 + static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 686 686 + .cmd_rcgr = 0x1538c, 687 687 + .mnd_width = 0, 688 688 + .hid_width = 5, 689 689 + .parent_map = cam_cc_parent_map_0, 690 690 + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 691 691 + .clkr.hw.init = &(const struct clk_init_data) { 692 692 + .name = "cam_cc_csi4phytimer_clk_src", 693 693 + .parent_data = cam_cc_parent_data_0, 694 694 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 695 695 + .flags = CLK_SET_RATE_PARENT, 696 696 + .ops = &clk_rcg2_ops, 697 697 + }, 698 698 + }; 699 699 + 700 700 + static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 701 701 + .cmd_rcgr = 0x154c0, 702 702 + .mnd_width = 0, 703 703 + .hid_width = 5, 704 704 + .parent_map = cam_cc_parent_map_0, 705 705 + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 706 706 + .clkr.hw.init = &(const struct clk_init_data) { 707 707 + .name = "cam_cc_csi5phytimer_clk_src", 708 708 + .parent_data = cam_cc_parent_data_0, 709 709 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 710 710 + .flags = CLK_SET_RATE_PARENT, 711 711 + .ops = &clk_rcg2_ops, 712 712 + }, 713 713 + }; 714 714 + 715 715 + static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { 716 716 + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 717 717 + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 718 718 + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 719 719 + { } 720 720 + }; 721 721 + 722 722 + static struct clk_rcg2 cam_cc_csid_clk_src = { 723 723 + .cmd_rcgr = 0x138d4, 724 724 + .mnd_width = 0, 725 725 + .hid_width = 5, 726 726 + .parent_map = cam_cc_parent_map_0, 727 727 + .freq_tbl = ftbl_cam_cc_csid_clk_src, 728 728 + .clkr.hw.init = &(const struct clk_init_data) { 729 729 + .name = "cam_cc_csid_clk_src", 730 730 + .parent_data = cam_cc_parent_data_0, 731 731 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 732 732 + .flags = CLK_SET_RATE_PARENT, 733 733 + .ops = &clk_rcg2_shared_ops, 734 734 + }, 735 735 + }; 736 736 + 737 737 + static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 738 738 + F(19200000, P_BI_TCXO, 1, 0, 0), 739 739 + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 740 740 + F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 741 741 + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 742 742 + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 743 743 + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 744 744 + { } 745 745 + }; 746 746 + 747 747 + static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 748 748 + .cmd_rcgr = 0x10018, 749 749 + .mnd_width = 0, 750 750 + .hid_width = 5, 751 751 + .parent_map = cam_cc_parent_map_0, 752 752 + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 753 753 + .clkr.hw.init = &(const struct clk_init_data) { 754 754 + .name = "cam_cc_fast_ahb_clk_src", 755 755 + .parent_data = cam_cc_parent_data_0, 756 756 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 757 757 + .flags = CLK_SET_RATE_PARENT, 758 758 + .ops = &clk_rcg2_shared_ops, 759 759 + }, 760 760 + }; 761 761 + 762 762 + static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 763 763 + F(19200000, P_BI_TCXO, 1, 0, 0), 764 764 + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 765 765 + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 766 766 + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 767 767 + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 768 768 + { } 769 769 + }; 770 770 + 771 771 + static struct clk_rcg2 cam_cc_icp_clk_src = { 772 772 + .cmd_rcgr = 0x13520, 773 773 + .mnd_width = 0, 774 774 + .hid_width = 5, 775 775 + .parent_map = cam_cc_parent_map_0, 776 776 + .freq_tbl = ftbl_cam_cc_icp_clk_src, 777 777 + .clkr.hw.init = &(const struct clk_init_data) { 778 778 + .name = "cam_cc_icp_clk_src", 779 779 + .parent_data = cam_cc_parent_data_0, 780 780 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 781 781 + .flags = CLK_SET_RATE_PARENT, 782 782 + .ops = &clk_rcg2_shared_ops, 783 783 + }, 784 784 + }; 785 785 + 786 786 + static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 787 787 + F(19200000, P_BI_TCXO, 1, 0, 0), 788 788 + F(345600000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 789 789 + F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 790 790 + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 791 791 + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 792 792 + F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 793 793 + { } 794 794 + }; 795 795 + 796 796 + static struct clk_rcg2 cam_cc_ife_0_clk_src = { 797 797 + .cmd_rcgr = 0x11018, 798 798 + .mnd_width = 0, 799 799 + .hid_width = 5, 800 800 + .parent_map = cam_cc_parent_map_2, 801 801 + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 802 802 + .clkr.hw.init = &(const struct clk_init_data) { 803 803 + .name = "cam_cc_ife_0_clk_src", 804 804 + .parent_data = cam_cc_parent_data_2, 805 805 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 806 806 + .flags = CLK_SET_RATE_PARENT, 807 807 + .ops = &clk_rcg2_shared_ops, 808 808 + }, 809 809 + }; 810 810 + 811 811 + static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 812 812 + F(19200000, P_BI_TCXO, 1, 0, 0), 813 813 + F(345600000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 814 814 + F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 815 815 + F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 816 816 + F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 817 817 + F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 818 818 + { } 819 819 + }; 820 820 + 821 821 + static struct clk_rcg2 cam_cc_ife_1_clk_src = { 822 822 + .cmd_rcgr = 0x12018, 823 823 + .mnd_width = 0, 824 824 + .hid_width = 5, 825 825 + .parent_map = cam_cc_parent_map_3, 826 826 + .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 827 827 + .clkr.hw.init = &(const struct clk_init_data) { 828 828 + .name = "cam_cc_ife_1_clk_src", 829 829 + .parent_data = cam_cc_parent_data_3, 830 830 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 831 831 + .flags = CLK_SET_RATE_PARENT, 832 832 + .ops = &clk_rcg2_shared_ops, 833 833 + }, 834 834 + }; 835 835 + 836 836 + static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 837 837 + F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 838 838 + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 839 839 + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 840 840 + { } 841 841 + }; 842 842 + 843 843 + static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 844 844 + .cmd_rcgr = 0x13000, 845 845 + .mnd_width = 0, 846 846 + .hid_width = 5, 847 847 + .parent_map = cam_cc_parent_map_0, 848 848 + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 849 849 + .clkr.hw.init = &(const struct clk_init_data) { 850 850 + .name = "cam_cc_ife_lite_clk_src", 851 851 + .parent_data = cam_cc_parent_data_0, 852 852 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 853 853 + .flags = CLK_SET_RATE_PARENT, 854 854 + .ops = &clk_rcg2_shared_ops, 855 855 + }, 856 856 + }; 857 857 + 858 858 + static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 859 859 + .cmd_rcgr = 0x1313c, 860 860 + .mnd_width = 0, 861 861 + .hid_width = 5, 862 862 + .parent_map = cam_cc_parent_map_0, 863 863 + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 864 864 + .clkr.hw.init = &(const struct clk_init_data) { 865 865 + .name = "cam_cc_ife_lite_csid_clk_src", 866 866 + .parent_data = cam_cc_parent_data_0, 867 867 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 868 868 + .flags = CLK_SET_RATE_PARENT, 869 869 + .ops = &clk_rcg2_shared_ops, 870 870 + }, 871 871 + }; 872 872 + 873 873 + static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 874 874 + F(304000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 875 875 + F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 876 876 + F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 877 877 + F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 878 878 + F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 879 879 + { } 880 880 + }; 881 881 + 882 882 + static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 883 883 + .cmd_rcgr = 0x103cc, 884 884 + .mnd_width = 0, 885 885 + .hid_width = 5, 886 886 + .parent_map = cam_cc_parent_map_4, 887 887 + .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 888 888 + .clkr.hw.init = &(const struct clk_init_data) { 889 889 + .name = "cam_cc_ipe_nps_clk_src", 890 890 + .parent_data = cam_cc_parent_data_4, 891 891 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 892 892 + .flags = CLK_SET_RATE_PARENT, 893 893 + .ops = &clk_rcg2_shared_ops, 894 894 + }, 895 895 + }; 896 896 + 897 897 + static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 898 898 + F(19200000, P_BI_TCXO, 1, 0, 0), 899 899 + F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 900 900 + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 901 901 + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 902 902 + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 903 903 + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 904 904 + { } 905 905 + }; 906 906 + 907 907 + static struct clk_rcg2 cam_cc_jpeg_clk_src = { 908 908 + .cmd_rcgr = 0x133dc, 909 909 + .mnd_width = 0, 910 910 + .hid_width = 5, 911 911 + .parent_map = cam_cc_parent_map_0, 912 912 + .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 913 913 + .clkr.hw.init = &(const struct clk_init_data) { 914 914 + .name = "cam_cc_jpeg_clk_src", 915 915 + .parent_data = cam_cc_parent_data_0, 916 916 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 917 917 + .flags = CLK_SET_RATE_PARENT, 918 918 + .ops = &clk_rcg2_shared_ops, 919 919 + }, 920 920 + }; 921 921 + 922 922 + static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 923 923 + F(19200000, P_BI_TCXO, 1, 0, 0), 924 924 + F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 925 925 + F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), 926 926 + { } 927 927 + }; 928 928 + 929 929 + static struct clk_rcg2 cam_cc_mclk0_clk_src = { 930 930 + .cmd_rcgr = 0x15000, 931 931 + .mnd_width = 8, 932 932 + .hid_width = 5, 933 933 + .parent_map = cam_cc_parent_map_1, 934 934 + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 935 935 + .clkr.hw.init = &(const struct clk_init_data) { 936 936 + .name = "cam_cc_mclk0_clk_src", 937 937 + .parent_data = cam_cc_parent_data_1, 938 938 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 939 939 + .flags = CLK_SET_RATE_PARENT, 940 940 + .ops = &clk_rcg2_ops, 941 941 + }, 942 942 + }; 943 943 + 944 944 + static struct clk_rcg2 cam_cc_mclk1_clk_src = { 945 945 + .cmd_rcgr = 0x1501c, 946 946 + .mnd_width = 8, 947 947 + .hid_width = 5, 948 948 + .parent_map = cam_cc_parent_map_1, 949 949 + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 950 950 + .clkr.hw.init = &(const struct clk_init_data) { 951 951 + .name = "cam_cc_mclk1_clk_src", 952 952 + .parent_data = cam_cc_parent_data_1, 953 953 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 954 954 + .flags = CLK_SET_RATE_PARENT, 955 955 + .ops = &clk_rcg2_ops, 956 956 + }, 957 957 + }; 958 958 + 959 959 + static struct clk_rcg2 cam_cc_mclk2_clk_src = { 960 960 + .cmd_rcgr = 0x15038, 961 961 + .mnd_width = 8, 962 962 + .hid_width = 5, 963 963 + .parent_map = cam_cc_parent_map_1, 964 964 + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 965 965 + .clkr.hw.init = &(const struct clk_init_data) { 966 966 + .name = "cam_cc_mclk2_clk_src", 967 967 + .parent_data = cam_cc_parent_data_1, 968 968 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 969 969 + .flags = CLK_SET_RATE_PARENT, 970 970 + .ops = &clk_rcg2_ops, 971 971 + }, 972 972 + }; 973 973 + 974 974 + static struct clk_rcg2 cam_cc_mclk3_clk_src = { 975 975 + .cmd_rcgr = 0x15054, 976 976 + .mnd_width = 8, 977 977 + .hid_width = 5, 978 978 + .parent_map = cam_cc_parent_map_1, 979 979 + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 980 980 + .clkr.hw.init = &(const struct clk_init_data) { 981 981 + .name = "cam_cc_mclk3_clk_src", 982 982 + .parent_data = cam_cc_parent_data_1, 983 983 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 984 984 + .flags = CLK_SET_RATE_PARENT, 985 985 + .ops = &clk_rcg2_ops, 986 986 + }, 987 987 + }; 988 988 + 989 989 + static struct clk_rcg2 cam_cc_mclk4_clk_src = { 990 990 + .cmd_rcgr = 0x15070, 991 991 + .mnd_width = 8, 992 992 + .hid_width = 5, 993 993 + .parent_map = cam_cc_parent_map_1, 994 994 + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 995 995 + .clkr.hw.init = &(const struct clk_init_data) { 996 996 + .name = "cam_cc_mclk4_clk_src", 997 997 + .parent_data = cam_cc_parent_data_1, 998 998 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 999 999 + .flags = CLK_SET_RATE_PARENT, 1000 1000 + .ops = &clk_rcg2_ops, 1001 1001 + }, 1002 1002 + }; 1003 1003 + 1004 1004 + static struct clk_rcg2 cam_cc_mclk5_clk_src = { 1005 1005 + .cmd_rcgr = 0x1508c, 1006 1006 + .mnd_width = 8, 1007 1007 + .hid_width = 5, 1008 1008 + .parent_map = cam_cc_parent_map_1, 1009 1009 + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1010 1010 + .clkr.hw.init = &(const struct clk_init_data) { 1011 1011 + .name = "cam_cc_mclk5_clk_src", 1012 1012 + .parent_data = cam_cc_parent_data_1, 1013 1013 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1014 1014 + .flags = CLK_SET_RATE_PARENT, 1015 1015 + .ops = &clk_rcg2_ops, 1016 1016 + }, 1017 1017 + }; 1018 1018 + 1019 1019 + static struct clk_rcg2 cam_cc_mclk6_clk_src = { 1020 1020 + .cmd_rcgr = 0x150a8, 1021 1021 + .mnd_width = 8, 1022 1022 + .hid_width = 5, 1023 1023 + .parent_map = cam_cc_parent_map_1, 1024 1024 + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1025 1025 + .clkr.hw.init = &(const struct clk_init_data) { 1026 1026 + .name = "cam_cc_mclk6_clk_src", 1027 1027 + .parent_data = cam_cc_parent_data_1, 1028 1028 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1029 1029 + .flags = CLK_SET_RATE_PARENT, 1030 1030 + .ops = &clk_rcg2_ops, 1031 1031 + }, 1032 1032 + }; 1033 1033 + 1034 1034 + static struct clk_rcg2 cam_cc_mclk7_clk_src = { 1035 1035 + .cmd_rcgr = 0x150c4, 1036 1036 + .mnd_width = 8, 1037 1037 + .hid_width = 5, 1038 1038 + .parent_map = cam_cc_parent_map_1, 1039 1039 + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1040 1040 + .clkr.hw.init = &(const struct clk_init_data) { 1041 1041 + .name = "cam_cc_mclk7_clk_src", 1042 1042 + .parent_data = cam_cc_parent_data_1, 1043 1043 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1044 1044 + .flags = CLK_SET_RATE_PARENT, 1045 1045 + .ops = &clk_rcg2_ops, 1046 1046 + }, 1047 1047 + }; 1048 1048 + 1049 1049 + static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { 1050 1050 + F(345600000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1051 1051 + F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1052 1052 + F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1053 1053 + F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1054 1054 + F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1055 1055 + { } 1056 1056 + }; 1057 1057 + 1058 1058 + static struct clk_rcg2 cam_cc_sfe_0_clk_src = { 1059 1059 + .cmd_rcgr = 0x13294, 1060 1060 + .mnd_width = 0, 1061 1061 + .hid_width = 5, 1062 1062 + .parent_map = cam_cc_parent_map_5, 1063 1063 + .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, 1064 1064 + .clkr.hw.init = &(const struct clk_init_data) { 1065 1065 + .name = "cam_cc_sfe_0_clk_src", 1066 1066 + .parent_data = cam_cc_parent_data_5, 1067 1067 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1068 1068 + .flags = CLK_SET_RATE_PARENT, 1069 1069 + .ops = &clk_rcg2_shared_ops, 1070 1070 + }, 1071 1071 + }; 1072 1072 + 1073 1073 + static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 1074 1074 + F(32000, P_SLEEP_CLK, 1, 0, 0), 1075 1075 + { } 1076 1076 + }; 1077 1077 + 1078 1078 + static struct clk_rcg2 cam_cc_sleep_clk_src = { 1079 1079 + .cmd_rcgr = 0x13aa0, 1080 1080 + .mnd_width = 0, 1081 1081 + .hid_width = 5, 1082 1082 + .parent_map = cam_cc_parent_map_6, 1083 1083 + .freq_tbl = ftbl_cam_cc_sleep_clk_src, 1084 1084 + .clkr.hw.init = &(const struct clk_init_data) { 1085 1085 + .name = "cam_cc_sleep_clk_src", 1086 1086 + .parent_data = cam_cc_parent_data_6_ao, 1087 1087 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 1088 1088 + .flags = CLK_SET_RATE_PARENT, 1089 1089 + .ops = &clk_rcg2_ops, 1090 1090 + }, 1091 1091 + }; 1092 1092 + 1093 1093 + static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1094 1094 + F(19200000, P_BI_TCXO, 1, 0, 0), 1095 1095 + F(64000000, P_CAM_CC_PLL8_OUT_EVEN, 7.5, 0, 0), 1096 1096 + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1097 1097 + { } 1098 1098 + }; 1099 1099 + 1100 1100 + static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1101 1101 + .cmd_rcgr = 0x10148, 1102 1102 + .mnd_width = 8, 1103 1103 + .hid_width = 5, 1104 1104 + .parent_map = cam_cc_parent_map_0, 1105 1105 + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1106 1106 + .clkr.hw.init = &(const struct clk_init_data) { 1107 1107 + .name = "cam_cc_slow_ahb_clk_src", 1108 1108 + .parent_data = cam_cc_parent_data_0, 1109 1109 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1110 1110 + .flags = CLK_SET_RATE_PARENT, 1111 1111 + .ops = &clk_rcg2_shared_ops, 1112 1112 + }, 1113 1113 + }; 1114 1114 + 1115 1115 + static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1116 1116 + F(19200000, P_BI_TCXO, 1, 0, 0), 1117 1117 + { } 1118 1118 + }; 1119 1119 + 1120 1120 + static struct clk_rcg2 cam_cc_xo_clk_src = { 1121 1121 + .cmd_rcgr = 0x13a84, 1122 1122 + .mnd_width = 0, 1123 1123 + .hid_width = 5, 1124 1124 + .parent_map = cam_cc_parent_map_7, 1125 1125 + .freq_tbl = ftbl_cam_cc_xo_clk_src, 1126 1126 + .clkr.hw.init = &(const struct clk_init_data) { 1127 1127 + .name = "cam_cc_xo_clk_src", 1128 1128 + .parent_data = cam_cc_parent_data_7_ao, 1129 1129 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_7_ao), 1130 1130 + .flags = CLK_SET_RATE_PARENT, 1131 1131 + .ops = &clk_rcg2_ops, 1132 1132 + }, 1133 1133 + }; 1134 1134 + 1135 1135 + static struct clk_branch cam_cc_bps_ahb_clk = { 1136 1136 + .halt_reg = 0x10274, 1137 1137 + .halt_check = BRANCH_HALT, 1138 1138 + .clkr = { 1139 1139 + .enable_reg = 0x10274, 1140 1140 + .enable_mask = BIT(0), 1141 1141 + .hw.init = &(const struct clk_init_data) { 1142 1142 + .name = "cam_cc_bps_ahb_clk", 1143 1143 + .parent_hws = (const struct clk_hw*[]) { 1144 1144 + &cam_cc_slow_ahb_clk_src.clkr.hw, 1145 1145 + }, 1146 1146 + .num_parents = 1, 1147 1147 + .flags = CLK_SET_RATE_PARENT, 1148 1148 + .ops = &clk_branch2_ops, 1149 1149 + }, 1150 1150 + }, 1151 1151 + }; 1152 1152 + 1153 1153 + static struct clk_branch cam_cc_bps_clk = { 1154 1154 + .halt_reg = 0x103a4, 1155 1155 + .halt_check = BRANCH_HALT, 1156 1156 + .clkr = { 1157 1157 + .enable_reg = 0x103a4, 1158 1158 + .enable_mask = BIT(0), 1159 1159 + .hw.init = &(const struct clk_init_data) { 1160 1160 + .name = "cam_cc_bps_clk", 1161 1161 + .parent_hws = (const struct clk_hw*[]) { 1162 1162 + &cam_cc_bps_clk_src.clkr.hw, 1163 1163 + }, 1164 1164 + .num_parents = 1, 1165 1165 + .flags = CLK_SET_RATE_PARENT, 1166 1166 + .ops = &clk_branch2_ops, 1167 1167 + }, 1168 1168 + }, 1169 1169 + }; 1170 1170 + 1171 1171 + static struct clk_branch cam_cc_bps_fast_ahb_clk = { 1172 1172 + .halt_reg = 0x10144, 1173 1173 + .halt_check = BRANCH_HALT, 1174 1174 + .clkr = { 1175 1175 + .enable_reg = 0x10144, 1176 1176 + .enable_mask = BIT(0), 1177 1177 + .hw.init = &(const struct clk_init_data) { 1178 1178 + .name = "cam_cc_bps_fast_ahb_clk", 1179 1179 + .parent_hws = (const struct clk_hw*[]) { 1180 1180 + &cam_cc_fast_ahb_clk_src.clkr.hw, 1181 1181 + }, 1182 1182 + .num_parents = 1, 1183 1183 + .flags = CLK_SET_RATE_PARENT, 1184 1184 + .ops = &clk_branch2_ops, 1185 1185 + }, 1186 1186 + }, 1187 1187 + }; 1188 1188 + 1189 1189 + static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { 1190 1190 + .halt_reg = 0x13920, 1191 1191 + .halt_check = BRANCH_HALT, 1192 1192 + .clkr = { 1193 1193 + .enable_reg = 0x13920, 1194 1194 + .enable_mask = BIT(0), 1195 1195 + .hw.init = &(const struct clk_init_data) { 1196 1196 + .name = "cam_cc_camnoc_axi_nrt_clk", 1197 1197 + .parent_hws = (const struct clk_hw*[]) { 1198 1198 + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1199 1199 + }, 1200 1200 + .num_parents = 1, 1201 1201 + .flags = CLK_SET_RATE_PARENT, 1202 1202 + .ops = &clk_branch2_ops, 1203 1203 + }, 1204 1204 + }, 1205 1205 + }; 1206 1206 + 1207 1207 + static struct clk_branch cam_cc_camnoc_axi_rt_clk = { 1208 1208 + .halt_reg = 0x13910, 1209 1209 + .halt_check = BRANCH_HALT, 1210 1210 + .clkr = { 1211 1211 + .enable_reg = 0x13910, 1212 1212 + .enable_mask = BIT(0), 1213 1213 + .hw.init = &(const struct clk_init_data) { 1214 1214 + .name = "cam_cc_camnoc_axi_rt_clk", 1215 1215 + .parent_hws = (const struct clk_hw*[]) { 1216 1216 + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1217 1217 + }, 1218 1218 + .num_parents = 1, 1219 1219 + .flags = CLK_SET_RATE_PARENT, 1220 1220 + .ops = &clk_branch2_ops, 1221 1221 + }, 1222 1222 + }, 1223 1223 + }; 1224 1224 + 1225 1225 + static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1226 1226 + .halt_reg = 0x1392c, 1227 1227 + .halt_check = BRANCH_HALT, 1228 1228 + .clkr = { 1229 1229 + .enable_reg = 0x1392c, 1230 1230 + .enable_mask = BIT(0), 1231 1231 + .hw.init = &(const struct clk_init_data) { 1232 1232 + .name = "cam_cc_camnoc_dcd_xo_clk", 1233 1233 + .parent_hws = (const struct clk_hw*[]) { 1234 1234 + &cam_cc_xo_clk_src.clkr.hw, 1235 1235 + }, 1236 1236 + .num_parents = 1, 1237 1237 + .flags = CLK_SET_RATE_PARENT, 1238 1238 + .ops = &clk_branch2_ops, 1239 1239 + }, 1240 1240 + }, 1241 1241 + }; 1242 1242 + 1243 1243 + static struct clk_branch cam_cc_camnoc_xo_clk = { 1244 1244 + .halt_reg = 0x13930, 1245 1245 + .halt_check = BRANCH_HALT, 1246 1246 + .clkr = { 1247 1247 + .enable_reg = 0x13930, 1248 1248 + .enable_mask = BIT(0), 1249 1249 + .hw.init = &(const struct clk_init_data) { 1250 1250 + .name = "cam_cc_camnoc_xo_clk", 1251 1251 + .parent_hws = (const struct clk_hw*[]) { 1252 1252 + &cam_cc_xo_clk_src.clkr.hw, 1253 1253 + }, 1254 1254 + .num_parents = 1, 1255 1255 + .flags = CLK_SET_RATE_PARENT, 1256 1256 + .ops = &clk_branch2_ops, 1257 1257 + }, 1258 1258 + }, 1259 1259 + }; 1260 1260 + 1261 1261 + static struct clk_branch cam_cc_cci_0_clk = { 1262 1262 + .halt_reg = 0x13788, 1263 1263 + .halt_check = BRANCH_HALT, 1264 1264 + .clkr = { 1265 1265 + .enable_reg = 0x13788, 1266 1266 + .enable_mask = BIT(0), 1267 1267 + .hw.init = &(const struct clk_init_data) { 1268 1268 + .name = "cam_cc_cci_0_clk", 1269 1269 + .parent_hws = (const struct clk_hw*[]) { 1270 1270 + &cam_cc_cci_0_clk_src.clkr.hw, 1271 1271 + }, 1272 1272 + .num_parents = 1, 1273 1273 + .flags = CLK_SET_RATE_PARENT, 1274 1274 + .ops = &clk_branch2_ops, 1275 1275 + }, 1276 1276 + }, 1277 1277 + }; 1278 1278 + 1279 1279 + static struct clk_branch cam_cc_cci_1_clk = { 1280 1280 + .halt_reg = 0x138b8, 1281 1281 + .halt_check = BRANCH_HALT, 1282 1282 + .clkr = { 1283 1283 + .enable_reg = 0x138b8, 1284 1284 + .enable_mask = BIT(0), 1285 1285 + .hw.init = &(const struct clk_init_data) { 1286 1286 + .name = "cam_cc_cci_1_clk", 1287 1287 + .parent_hws = (const struct clk_hw*[]) { 1288 1288 + &cam_cc_cci_1_clk_src.clkr.hw, 1289 1289 + }, 1290 1290 + .num_parents = 1, 1291 1291 + .flags = CLK_SET_RATE_PARENT, 1292 1292 + .ops = &clk_branch2_ops, 1293 1293 + }, 1294 1294 + }, 1295 1295 + }; 1296 1296 + 1297 1297 + static struct clk_branch cam_cc_core_ahb_clk = { 1298 1298 + .halt_reg = 0x13a80, 1299 1299 + .halt_check = BRANCH_HALT_VOTED, 1300 1300 + .clkr = { 1301 1301 + .enable_reg = 0x13a80, 1302 1302 + .enable_mask = BIT(0), 1303 1303 + .hw.init = &(const struct clk_init_data) { 1304 1304 + .name = "cam_cc_core_ahb_clk", 1305 1305 + .parent_hws = (const struct clk_hw*[]) { 1306 1306 + &cam_cc_slow_ahb_clk_src.clkr.hw, 1307 1307 + }, 1308 1308 + .num_parents = 1, 1309 1309 + .flags = CLK_SET_RATE_PARENT, 1310 1310 + .ops = &clk_branch2_ops, 1311 1311 + }, 1312 1312 + }, 1313 1313 + }; 1314 1314 + 1315 1315 + static struct clk_branch cam_cc_cpas_ahb_clk = { 1316 1316 + .halt_reg = 0x138bc, 1317 1317 + .halt_check = BRANCH_HALT, 1318 1318 + .clkr = { 1319 1319 + .enable_reg = 0x138bc, 1320 1320 + .enable_mask = BIT(0), 1321 1321 + .hw.init = &(const struct clk_init_data) { 1322 1322 + .name = "cam_cc_cpas_ahb_clk", 1323 1323 + .parent_hws = (const struct clk_hw*[]) { 1324 1324 + &cam_cc_slow_ahb_clk_src.clkr.hw, 1325 1325 + }, 1326 1326 + .num_parents = 1, 1327 1327 + .flags = CLK_SET_RATE_PARENT, 1328 1328 + .ops = &clk_branch2_ops, 1329 1329 + }, 1330 1330 + }, 1331 1331 + }; 1332 1332 + 1333 1333 + static struct clk_branch cam_cc_cpas_bps_clk = { 1334 1334 + .halt_reg = 0x103b0, 1335 1335 + .halt_check = BRANCH_HALT, 1336 1336 + .clkr = { 1337 1337 + .enable_reg = 0x103b0, 1338 1338 + .enable_mask = BIT(0), 1339 1339 + .hw.init = &(const struct clk_init_data) { 1340 1340 + .name = "cam_cc_cpas_bps_clk", 1341 1341 + .parent_hws = (const struct clk_hw*[]) { 1342 1342 + &cam_cc_bps_clk_src.clkr.hw, 1343 1343 + }, 1344 1344 + .num_parents = 1, 1345 1345 + .flags = CLK_SET_RATE_PARENT, 1346 1346 + .ops = &clk_branch2_ops, 1347 1347 + }, 1348 1348 + }, 1349 1349 + }; 1350 1350 + 1351 1351 + static struct clk_branch cam_cc_cpas_fast_ahb_clk = { 1352 1352 + .halt_reg = 0x138c8, 1353 1353 + .halt_check = BRANCH_HALT, 1354 1354 + .clkr = { 1355 1355 + .enable_reg = 0x138c8, 1356 1356 + .enable_mask = BIT(0), 1357 1357 + .hw.init = &(const struct clk_init_data) { 1358 1358 + .name = "cam_cc_cpas_fast_ahb_clk", 1359 1359 + .parent_hws = (const struct clk_hw*[]) { 1360 1360 + &cam_cc_fast_ahb_clk_src.clkr.hw, 1361 1361 + }, 1362 1362 + .num_parents = 1, 1363 1363 + .flags = CLK_SET_RATE_PARENT, 1364 1364 + .ops = &clk_branch2_ops, 1365 1365 + }, 1366 1366 + }, 1367 1367 + }; 1368 1368 + 1369 1369 + static struct clk_branch cam_cc_cpas_ife_0_clk = { 1370 1370 + .halt_reg = 0x11150, 1371 1371 + .halt_check = BRANCH_HALT, 1372 1372 + .clkr = { 1373 1373 + .enable_reg = 0x11150, 1374 1374 + .enable_mask = BIT(0), 1375 1375 + .hw.init = &(const struct clk_init_data) { 1376 1376 + .name = "cam_cc_cpas_ife_0_clk", 1377 1377 + .parent_hws = (const struct clk_hw*[]) { 1378 1378 + &cam_cc_ife_0_clk_src.clkr.hw, 1379 1379 + }, 1380 1380 + .num_parents = 1, 1381 1381 + .flags = CLK_SET_RATE_PARENT, 1382 1382 + .ops = &clk_branch2_ops, 1383 1383 + }, 1384 1384 + }, 1385 1385 + }; 1386 1386 + 1387 1387 + static struct clk_branch cam_cc_cpas_ife_1_clk = { 1388 1388 + .halt_reg = 0x1203c, 1389 1389 + .halt_check = BRANCH_HALT, 1390 1390 + .clkr = { 1391 1391 + .enable_reg = 0x1203c, 1392 1392 + .enable_mask = BIT(0), 1393 1393 + .hw.init = &(const struct clk_init_data) { 1394 1394 + .name = "cam_cc_cpas_ife_1_clk", 1395 1395 + .parent_hws = (const struct clk_hw*[]) { 1396 1396 + &cam_cc_ife_1_clk_src.clkr.hw, 1397 1397 + }, 1398 1398 + .num_parents = 1, 1399 1399 + .flags = CLK_SET_RATE_PARENT, 1400 1400 + .ops = &clk_branch2_ops, 1401 1401 + }, 1402 1402 + }, 1403 1403 + }; 1404 1404 + 1405 1405 + static struct clk_branch cam_cc_cpas_ife_lite_clk = { 1406 1406 + .halt_reg = 0x13138, 1407 1407 + .halt_check = BRANCH_HALT, 1408 1408 + .clkr = { 1409 1409 + .enable_reg = 0x13138, 1410 1410 + .enable_mask = BIT(0), 1411 1411 + .hw.init = &(const struct clk_init_data) { 1412 1412 + .name = "cam_cc_cpas_ife_lite_clk", 1413 1413 + .parent_hws = (const struct clk_hw*[]) { 1414 1414 + &cam_cc_ife_lite_clk_src.clkr.hw, 1415 1415 + }, 1416 1416 + .num_parents = 1, 1417 1417 + .flags = CLK_SET_RATE_PARENT, 1418 1418 + .ops = &clk_branch2_ops, 1419 1419 + }, 1420 1420 + }, 1421 1421 + }; 1422 1422 + 1423 1423 + static struct clk_branch cam_cc_cpas_ipe_nps_clk = { 1424 1424 + .halt_reg = 0x10504, 1425 1425 + .halt_check = BRANCH_HALT, 1426 1426 + .clkr = { 1427 1427 + .enable_reg = 0x10504, 1428 1428 + .enable_mask = BIT(0), 1429 1429 + .hw.init = &(const struct clk_init_data) { 1430 1430 + .name = "cam_cc_cpas_ipe_nps_clk", 1431 1431 + .parent_hws = (const struct clk_hw*[]) { 1432 1432 + &cam_cc_ipe_nps_clk_src.clkr.hw, 1433 1433 + }, 1434 1434 + .num_parents = 1, 1435 1435 + .flags = CLK_SET_RATE_PARENT, 1436 1436 + .ops = &clk_branch2_ops, 1437 1437 + }, 1438 1438 + }, 1439 1439 + }; 1440 1440 + 1441 1441 + static struct clk_branch cam_cc_cpas_sfe_0_clk = { 1442 1442 + .halt_reg = 0x133cc, 1443 1443 + .halt_check = BRANCH_HALT, 1444 1444 + .clkr = { 1445 1445 + .enable_reg = 0x133cc, 1446 1446 + .enable_mask = BIT(0), 1447 1447 + .hw.init = &(const struct clk_init_data) { 1448 1448 + .name = "cam_cc_cpas_sfe_0_clk", 1449 1449 + .parent_hws = (const struct clk_hw*[]) { 1450 1450 + &cam_cc_sfe_0_clk_src.clkr.hw, 1451 1451 + }, 1452 1452 + .num_parents = 1, 1453 1453 + .flags = CLK_SET_RATE_PARENT, 1454 1454 + .ops = &clk_branch2_ops, 1455 1455 + }, 1456 1456 + }, 1457 1457 + }; 1458 1458 + 1459 1459 + static struct clk_branch cam_cc_csi0phytimer_clk = { 1460 1460 + .halt_reg = 0x150f8, 1461 1461 + .halt_check = BRANCH_HALT, 1462 1462 + .clkr = { 1463 1463 + .enable_reg = 0x150f8, 1464 1464 + .enable_mask = BIT(0), 1465 1465 + .hw.init = &(const struct clk_init_data) { 1466 1466 + .name = "cam_cc_csi0phytimer_clk", 1467 1467 + .parent_hws = (const struct clk_hw*[]) { 1468 1468 + &cam_cc_csi0phytimer_clk_src.clkr.hw, 1469 1469 + }, 1470 1470 + .num_parents = 1, 1471 1471 + .flags = CLK_SET_RATE_PARENT, 1472 1472 + .ops = &clk_branch2_ops, 1473 1473 + }, 1474 1474 + }, 1475 1475 + }; 1476 1476 + 1477 1477 + static struct clk_branch cam_cc_csi1phytimer_clk = { 1478 1478 + .halt_reg = 0x1511c, 1479 1479 + .halt_check = BRANCH_HALT, 1480 1480 + .clkr = { 1481 1481 + .enable_reg = 0x1511c, 1482 1482 + .enable_mask = BIT(0), 1483 1483 + .hw.init = &(const struct clk_init_data) { 1484 1484 + .name = "cam_cc_csi1phytimer_clk", 1485 1485 + .parent_hws = (const struct clk_hw*[]) { 1486 1486 + &cam_cc_csi1phytimer_clk_src.clkr.hw, 1487 1487 + }, 1488 1488 + .num_parents = 1, 1489 1489 + .flags = CLK_SET_RATE_PARENT, 1490 1490 + .ops = &clk_branch2_ops, 1491 1491 + }, 1492 1492 + }, 1493 1493 + }; 1494 1494 + 1495 1495 + static struct clk_branch cam_cc_csi2phytimer_clk = { 1496 1496 + .halt_reg = 0x15250, 1497 1497 + .halt_check = BRANCH_HALT, 1498 1498 + .clkr = { 1499 1499 + .enable_reg = 0x15250, 1500 1500 + .enable_mask = BIT(0), 1501 1501 + .hw.init = &(const struct clk_init_data) { 1502 1502 + .name = "cam_cc_csi2phytimer_clk", 1503 1503 + .parent_hws = (const struct clk_hw*[]) { 1504 1504 + &cam_cc_csi2phytimer_clk_src.clkr.hw, 1505 1505 + }, 1506 1506 + .num_parents = 1, 1507 1507 + .flags = CLK_SET_RATE_PARENT, 1508 1508 + .ops = &clk_branch2_ops, 1509 1509 + }, 1510 1510 + }, 1511 1511 + }; 1512 1512 + 1513 1513 + static struct clk_branch cam_cc_csi3phytimer_clk = { 1514 1514 + .halt_reg = 0x15384, 1515 1515 + .halt_check = BRANCH_HALT, 1516 1516 + .clkr = { 1517 1517 + .enable_reg = 0x15384, 1518 1518 + .enable_mask = BIT(0), 1519 1519 + .hw.init = &(const struct clk_init_data) { 1520 1520 + .name = "cam_cc_csi3phytimer_clk", 1521 1521 + .parent_hws = (const struct clk_hw*[]) { 1522 1522 + &cam_cc_csi3phytimer_clk_src.clkr.hw, 1523 1523 + }, 1524 1524 + .num_parents = 1, 1525 1525 + .flags = CLK_SET_RATE_PARENT, 1526 1526 + .ops = &clk_branch2_ops, 1527 1527 + }, 1528 1528 + }, 1529 1529 + }; 1530 1530 + 1531 1531 + static struct clk_branch cam_cc_csi4phytimer_clk = { 1532 1532 + .halt_reg = 0x154b8, 1533 1533 + .halt_check = BRANCH_HALT, 1534 1534 + .clkr = { 1535 1535 + .enable_reg = 0x154b8, 1536 1536 + .enable_mask = BIT(0), 1537 1537 + .hw.init = &(const struct clk_init_data) { 1538 1538 + .name = "cam_cc_csi4phytimer_clk", 1539 1539 + .parent_hws = (const struct clk_hw*[]) { 1540 1540 + &cam_cc_csi4phytimer_clk_src.clkr.hw, 1541 1541 + }, 1542 1542 + .num_parents = 1, 1543 1543 + .flags = CLK_SET_RATE_PARENT, 1544 1544 + .ops = &clk_branch2_ops, 1545 1545 + }, 1546 1546 + }, 1547 1547 + }; 1548 1548 + 1549 1549 + static struct clk_branch cam_cc_csi5phytimer_clk = { 1550 1550 + .halt_reg = 0x155ec, 1551 1551 + .halt_check = BRANCH_HALT, 1552 1552 + .clkr = { 1553 1553 + .enable_reg = 0x155ec, 1554 1554 + .enable_mask = BIT(0), 1555 1555 + .hw.init = &(const struct clk_init_data) { 1556 1556 + .name = "cam_cc_csi5phytimer_clk", 1557 1557 + .parent_hws = (const struct clk_hw*[]) { 1558 1558 + &cam_cc_csi5phytimer_clk_src.clkr.hw, 1559 1559 + }, 1560 1560 + .num_parents = 1, 1561 1561 + .flags = CLK_SET_RATE_PARENT, 1562 1562 + .ops = &clk_branch2_ops, 1563 1563 + }, 1564 1564 + }, 1565 1565 + }; 1566 1566 + 1567 1567 + static struct clk_branch cam_cc_csid_clk = { 1568 1568 + .halt_reg = 0x138ec, 1569 1569 + .halt_check = BRANCH_HALT, 1570 1570 + .clkr = { 1571 1571 + .enable_reg = 0x138ec, 1572 1572 + .enable_mask = BIT(0), 1573 1573 + .hw.init = &(const struct clk_init_data) { 1574 1574 + .name = "cam_cc_csid_clk", 1575 1575 + .parent_hws = (const struct clk_hw*[]) { 1576 1576 + &cam_cc_csid_clk_src.clkr.hw, 1577 1577 + }, 1578 1578 + .num_parents = 1, 1579 1579 + .flags = CLK_SET_RATE_PARENT, 1580 1580 + .ops = &clk_branch2_ops, 1581 1581 + }, 1582 1582 + }, 1583 1583 + }; 1584 1584 + 1585 1585 + static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1586 1586 + .halt_reg = 0x15100, 1587 1587 + .halt_check = BRANCH_HALT, 1588 1588 + .clkr = { 1589 1589 + .enable_reg = 0x15100, 1590 1590 + .enable_mask = BIT(0), 1591 1591 + .hw.init = &(const struct clk_init_data) { 1592 1592 + .name = "cam_cc_csid_csiphy_rx_clk", 1593 1593 + .parent_hws = (const struct clk_hw*[]) { 1594 1594 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1595 1595 + }, 1596 1596 + .num_parents = 1, 1597 1597 + .flags = CLK_SET_RATE_PARENT, 1598 1598 + .ops = &clk_branch2_ops, 1599 1599 + }, 1600 1600 + }, 1601 1601 + }; 1602 1602 + 1603 1603 + static struct clk_branch cam_cc_csiphy0_clk = { 1604 1604 + .halt_reg = 0x150fc, 1605 1605 + .halt_check = BRANCH_HALT, 1606 1606 + .clkr = { 1607 1607 + .enable_reg = 0x150fc, 1608 1608 + .enable_mask = BIT(0), 1609 1609 + .hw.init = &(const struct clk_init_data) { 1610 1610 + .name = "cam_cc_csiphy0_clk", 1611 1611 + .parent_hws = (const struct clk_hw*[]) { 1612 1612 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1613 1613 + }, 1614 1614 + .num_parents = 1, 1615 1615 + .flags = CLK_SET_RATE_PARENT, 1616 1616 + .ops = &clk_branch2_ops, 1617 1617 + }, 1618 1618 + }, 1619 1619 + }; 1620 1620 + 1621 1621 + static struct clk_branch cam_cc_csiphy1_clk = { 1622 1622 + .halt_reg = 0x15120, 1623 1623 + .halt_check = BRANCH_HALT, 1624 1624 + .clkr = { 1625 1625 + .enable_reg = 0x15120, 1626 1626 + .enable_mask = BIT(0), 1627 1627 + .hw.init = &(const struct clk_init_data) { 1628 1628 + .name = "cam_cc_csiphy1_clk", 1629 1629 + .parent_hws = (const struct clk_hw*[]) { 1630 1630 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1631 1631 + }, 1632 1632 + .num_parents = 1, 1633 1633 + .flags = CLK_SET_RATE_PARENT, 1634 1634 + .ops = &clk_branch2_ops, 1635 1635 + }, 1636 1636 + }, 1637 1637 + }; 1638 1638 + 1639 1639 + static struct clk_branch cam_cc_csiphy2_clk = { 1640 1640 + .halt_reg = 0x15254, 1641 1641 + .halt_check = BRANCH_HALT, 1642 1642 + .clkr = { 1643 1643 + .enable_reg = 0x15254, 1644 1644 + .enable_mask = BIT(0), 1645 1645 + .hw.init = &(const struct clk_init_data) { 1646 1646 + .name = "cam_cc_csiphy2_clk", 1647 1647 + .parent_hws = (const struct clk_hw*[]) { 1648 1648 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1649 1649 + }, 1650 1650 + .num_parents = 1, 1651 1651 + .flags = CLK_SET_RATE_PARENT, 1652 1652 + .ops = &clk_branch2_ops, 1653 1653 + }, 1654 1654 + }, 1655 1655 + }; 1656 1656 + 1657 1657 + static struct clk_branch cam_cc_csiphy3_clk = { 1658 1658 + .halt_reg = 0x15388, 1659 1659 + .halt_check = BRANCH_HALT, 1660 1660 + .clkr = { 1661 1661 + .enable_reg = 0x15388, 1662 1662 + .enable_mask = BIT(0), 1663 1663 + .hw.init = &(const struct clk_init_data) { 1664 1664 + .name = "cam_cc_csiphy3_clk", 1665 1665 + .parent_hws = (const struct clk_hw*[]) { 1666 1666 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1667 1667 + }, 1668 1668 + .num_parents = 1, 1669 1669 + .flags = CLK_SET_RATE_PARENT, 1670 1670 + .ops = &clk_branch2_ops, 1671 1671 + }, 1672 1672 + }, 1673 1673 + }; 1674 1674 + 1675 1675 + static struct clk_branch cam_cc_csiphy4_clk = { 1676 1676 + .halt_reg = 0x154bc, 1677 1677 + .halt_check = BRANCH_HALT, 1678 1678 + .clkr = { 1679 1679 + .enable_reg = 0x154bc, 1680 1680 + .enable_mask = BIT(0), 1681 1681 + .hw.init = &(const struct clk_init_data) { 1682 1682 + .name = "cam_cc_csiphy4_clk", 1683 1683 + .parent_hws = (const struct clk_hw*[]) { 1684 1684 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1685 1685 + }, 1686 1686 + .num_parents = 1, 1687 1687 + .flags = CLK_SET_RATE_PARENT, 1688 1688 + .ops = &clk_branch2_ops, 1689 1689 + }, 1690 1690 + }, 1691 1691 + }; 1692 1692 + 1693 1693 + static struct clk_branch cam_cc_csiphy5_clk = { 1694 1694 + .halt_reg = 0x155f0, 1695 1695 + .halt_check = BRANCH_HALT, 1696 1696 + .clkr = { 1697 1697 + .enable_reg = 0x155f0, 1698 1698 + .enable_mask = BIT(0), 1699 1699 + .hw.init = &(const struct clk_init_data) { 1700 1700 + .name = "cam_cc_csiphy5_clk", 1701 1701 + .parent_hws = (const struct clk_hw*[]) { 1702 1702 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1703 1703 + }, 1704 1704 + .num_parents = 1, 1705 1705 + .flags = CLK_SET_RATE_PARENT, 1706 1706 + .ops = &clk_branch2_ops, 1707 1707 + }, 1708 1708 + }, 1709 1709 + }; 1710 1710 + 1711 1711 + static struct clk_branch cam_cc_icp_ahb_clk = { 1712 1712 + .halt_reg = 0x13658, 1713 1713 + .halt_check = BRANCH_HALT, 1714 1714 + .clkr = { 1715 1715 + .enable_reg = 0x13658, 1716 1716 + .enable_mask = BIT(0), 1717 1717 + .hw.init = &(const struct clk_init_data) { 1718 1718 + .name = "cam_cc_icp_ahb_clk", 1719 1719 + .parent_hws = (const struct clk_hw*[]) { 1720 1720 + &cam_cc_slow_ahb_clk_src.clkr.hw, 1721 1721 + }, 1722 1722 + .num_parents = 1, 1723 1723 + .flags = CLK_SET_RATE_PARENT, 1724 1724 + .ops = &clk_branch2_ops, 1725 1725 + }, 1726 1726 + }, 1727 1727 + }; 1728 1728 + 1729 1729 + static struct clk_branch cam_cc_icp_clk = { 1730 1730 + .halt_reg = 0x1364c, 1731 1731 + .halt_check = BRANCH_HALT, 1732 1732 + .clkr = { 1733 1733 + .enable_reg = 0x1364c, 1734 1734 + .enable_mask = BIT(0), 1735 1735 + .hw.init = &(const struct clk_init_data) { 1736 1736 + .name = "cam_cc_icp_clk", 1737 1737 + .parent_hws = (const struct clk_hw*[]) { 1738 1738 + &cam_cc_icp_clk_src.clkr.hw, 1739 1739 + }, 1740 1740 + .num_parents = 1, 1741 1741 + .flags = CLK_SET_RATE_PARENT, 1742 1742 + .ops = &clk_branch2_ops, 1743 1743 + }, 1744 1744 + }, 1745 1745 + }; 1746 1746 + 1747 1747 + static struct clk_branch cam_cc_ife_0_clk = { 1748 1748 + .halt_reg = 0x11144, 1749 1749 + .halt_check = BRANCH_HALT, 1750 1750 + .clkr = { 1751 1751 + .enable_reg = 0x11144, 1752 1752 + .enable_mask = BIT(0), 1753 1753 + .hw.init = &(const struct clk_init_data) { 1754 1754 + .name = "cam_cc_ife_0_clk", 1755 1755 + .parent_hws = (const struct clk_hw*[]) { 1756 1756 + &cam_cc_ife_0_clk_src.clkr.hw, 1757 1757 + }, 1758 1758 + .num_parents = 1, 1759 1759 + .flags = CLK_SET_RATE_PARENT, 1760 1760 + .ops = &clk_branch2_ops, 1761 1761 + }, 1762 1762 + }, 1763 1763 + }; 1764 1764 + 1765 1765 + static struct clk_branch cam_cc_ife_0_dsp_clk = { 1766 1766 + .halt_reg = 0x11154, 1767 1767 + .halt_check = BRANCH_HALT, 1768 1768 + .clkr = { 1769 1769 + .enable_reg = 0x11154, 1770 1770 + .enable_mask = BIT(0), 1771 1771 + .hw.init = &(const struct clk_init_data) { 1772 1772 + .name = "cam_cc_ife_0_dsp_clk", 1773 1773 + .parent_hws = (const struct clk_hw*[]) { 1774 1774 + &cam_cc_ife_0_clk_src.clkr.hw, 1775 1775 + }, 1776 1776 + .num_parents = 1, 1777 1777 + .flags = CLK_SET_RATE_PARENT, 1778 1778 + .ops = &clk_branch2_ops, 1779 1779 + }, 1780 1780 + }, 1781 1781 + }; 1782 1782 + 1783 1783 + static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { 1784 1784 + .halt_reg = 0x11160, 1785 1785 + .halt_check = BRANCH_HALT, 1786 1786 + .clkr = { 1787 1787 + .enable_reg = 0x11160, 1788 1788 + .enable_mask = BIT(0), 1789 1789 + .hw.init = &(const struct clk_init_data) { 1790 1790 + .name = "cam_cc_ife_0_fast_ahb_clk", 1791 1791 + .parent_hws = (const struct clk_hw*[]) { 1792 1792 + &cam_cc_fast_ahb_clk_src.clkr.hw, 1793 1793 + }, 1794 1794 + .num_parents = 1, 1795 1795 + .flags = CLK_SET_RATE_PARENT, 1796 1796 + .ops = &clk_branch2_ops, 1797 1797 + }, 1798 1798 + }, 1799 1799 + }; 1800 1800 + 1801 1801 + static struct clk_branch cam_cc_ife_1_clk = { 1802 1802 + .halt_reg = 0x12030, 1803 1803 + .halt_check = BRANCH_HALT, 1804 1804 + .clkr = { 1805 1805 + .enable_reg = 0x12030, 1806 1806 + .enable_mask = BIT(0), 1807 1807 + .hw.init = &(const struct clk_init_data) { 1808 1808 + .name = "cam_cc_ife_1_clk", 1809 1809 + .parent_hws = (const struct clk_hw*[]) { 1810 1810 + &cam_cc_ife_1_clk_src.clkr.hw, 1811 1811 + }, 1812 1812 + .num_parents = 1, 1813 1813 + .flags = CLK_SET_RATE_PARENT, 1814 1814 + .ops = &clk_branch2_ops, 1815 1815 + }, 1816 1816 + }, 1817 1817 + }; 1818 1818 + 1819 1819 + static struct clk_branch cam_cc_ife_1_dsp_clk = { 1820 1820 + .halt_reg = 0x12040, 1821 1821 + .halt_check = BRANCH_HALT, 1822 1822 + .clkr = { 1823 1823 + .enable_reg = 0x12040, 1824 1824 + .enable_mask = BIT(0), 1825 1825 + .hw.init = &(const struct clk_init_data) { 1826 1826 + .name = "cam_cc_ife_1_dsp_clk", 1827 1827 + .parent_hws = (const struct clk_hw*[]) { 1828 1828 + &cam_cc_ife_1_clk_src.clkr.hw, 1829 1829 + }, 1830 1830 + .num_parents = 1, 1831 1831 + .flags = CLK_SET_RATE_PARENT, 1832 1832 + .ops = &clk_branch2_ops, 1833 1833 + }, 1834 1834 + }, 1835 1835 + }; 1836 1836 + 1837 1837 + static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { 1838 1838 + .halt_reg = 0x1204c, 1839 1839 + .halt_check = BRANCH_HALT, 1840 1840 + .clkr = { 1841 1841 + .enable_reg = 0x1204c, 1842 1842 + .enable_mask = BIT(0), 1843 1843 + .hw.init = &(const struct clk_init_data) { 1844 1844 + .name = "cam_cc_ife_1_fast_ahb_clk", 1845 1845 + .parent_hws = (const struct clk_hw*[]) { 1846 1846 + &cam_cc_fast_ahb_clk_src.clkr.hw, 1847 1847 + }, 1848 1848 + .num_parents = 1, 1849 1849 + .flags = CLK_SET_RATE_PARENT, 1850 1850 + .ops = &clk_branch2_ops, 1851 1851 + }, 1852 1852 + }, 1853 1853 + }; 1854 1854 + 1855 1855 + static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1856 1856 + .halt_reg = 0x13278, 1857 1857 + .halt_check = BRANCH_HALT, 1858 1858 + .clkr = { 1859 1859 + .enable_reg = 0x13278, 1860 1860 + .enable_mask = BIT(0), 1861 1861 + .hw.init = &(const struct clk_init_data) { 1862 1862 + .name = "cam_cc_ife_lite_ahb_clk", 1863 1863 + .parent_hws = (const struct clk_hw*[]) { 1864 1864 + &cam_cc_slow_ahb_clk_src.clkr.hw, 1865 1865 + }, 1866 1866 + .num_parents = 1, 1867 1867 + .flags = CLK_SET_RATE_PARENT, 1868 1868 + .ops = &clk_branch2_ops, 1869 1869 + }, 1870 1870 + }, 1871 1871 + }; 1872 1872 + 1873 1873 + static struct clk_branch cam_cc_ife_lite_clk = { 1874 1874 + .halt_reg = 0x1312c, 1875 1875 + .halt_check = BRANCH_HALT, 1876 1876 + .clkr = { 1877 1877 + .enable_reg = 0x1312c, 1878 1878 + .enable_mask = BIT(0), 1879 1879 + .hw.init = &(const struct clk_init_data) { 1880 1880 + .name = "cam_cc_ife_lite_clk", 1881 1881 + .parent_hws = (const struct clk_hw*[]) { 1882 1882 + &cam_cc_ife_lite_clk_src.clkr.hw, 1883 1883 + }, 1884 1884 + .num_parents = 1, 1885 1885 + .flags = CLK_SET_RATE_PARENT, 1886 1886 + .ops = &clk_branch2_ops, 1887 1887 + }, 1888 1888 + }, 1889 1889 + }; 1890 1890 + 1891 1891 + static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1892 1892 + .halt_reg = 0x13274, 1893 1893 + .halt_check = BRANCH_HALT, 1894 1894 + .clkr = { 1895 1895 + .enable_reg = 0x13274, 1896 1896 + .enable_mask = BIT(0), 1897 1897 + .hw.init = &(const struct clk_init_data) { 1898 1898 + .name = "cam_cc_ife_lite_cphy_rx_clk", 1899 1899 + .parent_hws = (const struct clk_hw*[]) { 1900 1900 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1901 1901 + }, 1902 1902 + .num_parents = 1, 1903 1903 + .flags = CLK_SET_RATE_PARENT, 1904 1904 + .ops = &clk_branch2_ops, 1905 1905 + }, 1906 1906 + }, 1907 1907 + }; 1908 1908 + 1909 1909 + static struct clk_branch cam_cc_ife_lite_csid_clk = { 1910 1910 + .halt_reg = 0x13268, 1911 1911 + .halt_check = BRANCH_HALT, 1912 1912 + .clkr = { 1913 1913 + .enable_reg = 0x13268, 1914 1914 + .enable_mask = BIT(0), 1915 1915 + .hw.init = &(const struct clk_init_data) { 1916 1916 + .name = "cam_cc_ife_lite_csid_clk", 1917 1917 + .parent_hws = (const struct clk_hw*[]) { 1918 1918 + &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1919 1919 + }, 1920 1920 + .num_parents = 1, 1921 1921 + .flags = CLK_SET_RATE_PARENT, 1922 1922 + .ops = &clk_branch2_ops, 1923 1923 + }, 1924 1924 + }, 1925 1925 + }; 1926 1926 + 1927 1927 + static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1928 1928 + .halt_reg = 0x1051c, 1929 1929 + .halt_check = BRANCH_HALT, 1930 1930 + .clkr = { 1931 1931 + .enable_reg = 0x1051c, 1932 1932 + .enable_mask = BIT(0), 1933 1933 + .hw.init = &(const struct clk_init_data) { 1934 1934 + .name = "cam_cc_ipe_nps_ahb_clk", 1935 1935 + .parent_hws = (const struct clk_hw*[]) { 1936 1936 + &cam_cc_slow_ahb_clk_src.clkr.hw, 1937 1937 + }, 1938 1938 + .num_parents = 1, 1939 1939 + .flags = CLK_SET_RATE_PARENT, 1940 1940 + .ops = &clk_branch2_ops, 1941 1941 + }, 1942 1942 + }, 1943 1943 + }; 1944 1944 + 1945 1945 + static struct clk_branch cam_cc_ipe_nps_clk = { 1946 1946 + .halt_reg = 0x104f8, 1947 1947 + .halt_check = BRANCH_HALT, 1948 1948 + .clkr = { 1949 1949 + .enable_reg = 0x104f8, 1950 1950 + .enable_mask = BIT(0), 1951 1951 + .hw.init = &(const struct clk_init_data) { 1952 1952 + .name = "cam_cc_ipe_nps_clk", 1953 1953 + .parent_hws = (const struct clk_hw*[]) { 1954 1954 + &cam_cc_ipe_nps_clk_src.clkr.hw, 1955 1955 + }, 1956 1956 + .num_parents = 1, 1957 1957 + .flags = CLK_SET_RATE_PARENT, 1958 1958 + .ops = &clk_branch2_ops, 1959 1959 + }, 1960 1960 + }, 1961 1961 + }; 1962 1962 + 1963 1963 + static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1964 1964 + .halt_reg = 0x10520, 1965 1965 + .halt_check = BRANCH_HALT, 1966 1966 + .clkr = { 1967 1967 + .enable_reg = 0x10520, 1968 1968 + .enable_mask = BIT(0), 1969 1969 + .hw.init = &(const struct clk_init_data) { 1970 1970 + .name = "cam_cc_ipe_nps_fast_ahb_clk", 1971 1971 + .parent_hws = (const struct clk_hw*[]) { 1972 1972 + &cam_cc_fast_ahb_clk_src.clkr.hw, 1973 1973 + }, 1974 1974 + .num_parents = 1, 1975 1975 + .flags = CLK_SET_RATE_PARENT, 1976 1976 + .ops = &clk_branch2_ops, 1977 1977 + }, 1978 1978 + }, 1979 1979 + }; 1980 1980 + 1981 1981 + static struct clk_branch cam_cc_ipe_pps_clk = { 1982 1982 + .halt_reg = 0x10508, 1983 1983 + .halt_check = BRANCH_HALT, 1984 1984 + .clkr = { 1985 1985 + .enable_reg = 0x10508, 1986 1986 + .enable_mask = BIT(0), 1987 1987 + .hw.init = &(const struct clk_init_data) { 1988 1988 + .name = "cam_cc_ipe_pps_clk", 1989 1989 + .parent_hws = (const struct clk_hw*[]) { 1990 1990 + &cam_cc_ipe_nps_clk_src.clkr.hw, 1991 1991 + }, 1992 1992 + .num_parents = 1, 1993 1993 + .flags = CLK_SET_RATE_PARENT, 1994 1994 + .ops = &clk_branch2_ops, 1995 1995 + }, 1996 1996 + }, 1997 1997 + }; 1998 1998 + 1999 1999 + static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 2000 2000 + .halt_reg = 0x10524, 2001 2001 + .halt_check = BRANCH_HALT, 2002 2002 + .clkr = { 2003 2003 + .enable_reg = 0x10524, 2004 2004 + .enable_mask = BIT(0), 2005 2005 + .hw.init = &(const struct clk_init_data) { 2006 2006 + .name = "cam_cc_ipe_pps_fast_ahb_clk", 2007 2007 + .parent_hws = (const struct clk_hw*[]) { 2008 2008 + &cam_cc_fast_ahb_clk_src.clkr.hw, 2009 2009 + }, 2010 2010 + .num_parents = 1, 2011 2011 + .flags = CLK_SET_RATE_PARENT, 2012 2012 + .ops = &clk_branch2_ops, 2013 2013 + }, 2014 2014 + }, 2015 2015 + }; 2016 2016 + 2017 2017 + static struct clk_branch cam_cc_jpeg_clk = { 2018 2018 + .halt_reg = 0x13508, 2019 2019 + .halt_check = BRANCH_HALT, 2020 2020 + .clkr = { 2021 2021 + .enable_reg = 0x13508, 2022 2022 + .enable_mask = BIT(0), 2023 2023 + .hw.init = &(const struct clk_init_data) { 2024 2024 + .name = "cam_cc_jpeg_clk", 2025 2025 + .parent_hws = (const struct clk_hw*[]) { 2026 2026 + &cam_cc_jpeg_clk_src.clkr.hw, 2027 2027 + }, 2028 2028 + .num_parents = 1, 2029 2029 + .flags = CLK_SET_RATE_PARENT, 2030 2030 + .ops = &clk_branch2_ops, 2031 2031 + }, 2032 2032 + }, 2033 2033 + }; 2034 2034 + 2035 2035 + static struct clk_branch cam_cc_mclk0_clk = { 2036 2036 + .halt_reg = 0x15018, 2037 2037 + .halt_check = BRANCH_HALT, 2038 2038 + .clkr = { 2039 2039 + .enable_reg = 0x15018, 2040 2040 + .enable_mask = BIT(0), 2041 2041 + .hw.init = &(const struct clk_init_data) { 2042 2042 + .name = "cam_cc_mclk0_clk", 2043 2043 + .parent_hws = (const struct clk_hw*[]) { 2044 2044 + &cam_cc_mclk0_clk_src.clkr.hw, 2045 2045 + }, 2046 2046 + .num_parents = 1, 2047 2047 + .flags = CLK_SET_RATE_PARENT, 2048 2048 + .ops = &clk_branch2_ops, 2049 2049 + }, 2050 2050 + }, 2051 2051 + }; 2052 2052 + 2053 2053 + static struct clk_branch cam_cc_mclk1_clk = { 2054 2054 + .halt_reg = 0x15034, 2055 2055 + .halt_check = BRANCH_HALT, 2056 2056 + .clkr = { 2057 2057 + .enable_reg = 0x15034, 2058 2058 + .enable_mask = BIT(0), 2059 2059 + .hw.init = &(const struct clk_init_data) { 2060 2060 + .name = "cam_cc_mclk1_clk", 2061 2061 + .parent_hws = (const struct clk_hw*[]) { 2062 2062 + &cam_cc_mclk1_clk_src.clkr.hw, 2063 2063 + }, 2064 2064 + .num_parents = 1, 2065 2065 + .flags = CLK_SET_RATE_PARENT, 2066 2066 + .ops = &clk_branch2_ops, 2067 2067 + }, 2068 2068 + }, 2069 2069 + }; 2070 2070 + 2071 2071 + static struct clk_branch cam_cc_mclk2_clk = { 2072 2072 + .halt_reg = 0x15050, 2073 2073 + .halt_check = BRANCH_HALT, 2074 2074 + .clkr = { 2075 2075 + .enable_reg = 0x15050, 2076 2076 + .enable_mask = BIT(0), 2077 2077 + .hw.init = &(const struct clk_init_data) { 2078 2078 + .name = "cam_cc_mclk2_clk", 2079 2079 + .parent_hws = (const struct clk_hw*[]) { 2080 2080 + &cam_cc_mclk2_clk_src.clkr.hw, 2081 2081 + }, 2082 2082 + .num_parents = 1, 2083 2083 + .flags = CLK_SET_RATE_PARENT, 2084 2084 + .ops = &clk_branch2_ops, 2085 2085 + }, 2086 2086 + }, 2087 2087 + }; 2088 2088 + 2089 2089 + static struct clk_branch cam_cc_mclk3_clk = { 2090 2090 + .halt_reg = 0x1506c, 2091 2091 + .halt_check = BRANCH_HALT, 2092 2092 + .clkr = { 2093 2093 + .enable_reg = 0x1506c, 2094 2094 + .enable_mask = BIT(0), 2095 2095 + .hw.init = &(const struct clk_init_data) { 2096 2096 + .name = "cam_cc_mclk3_clk", 2097 2097 + .parent_hws = (const struct clk_hw*[]) { 2098 2098 + &cam_cc_mclk3_clk_src.clkr.hw, 2099 2099 + }, 2100 2100 + .num_parents = 1, 2101 2101 + .flags = CLK_SET_RATE_PARENT, 2102 2102 + .ops = &clk_branch2_ops, 2103 2103 + }, 2104 2104 + }, 2105 2105 + }; 2106 2106 + 2107 2107 + static struct clk_branch cam_cc_mclk4_clk = { 2108 2108 + .halt_reg = 0x15088, 2109 2109 + .halt_check = BRANCH_HALT, 2110 2110 + .clkr = { 2111 2111 + .enable_reg = 0x15088, 2112 2112 + .enable_mask = BIT(0), 2113 2113 + .hw.init = &(const struct clk_init_data) { 2114 2114 + .name = "cam_cc_mclk4_clk", 2115 2115 + .parent_hws = (const struct clk_hw*[]) { 2116 2116 + &cam_cc_mclk4_clk_src.clkr.hw, 2117 2117 + }, 2118 2118 + .num_parents = 1, 2119 2119 + .flags = CLK_SET_RATE_PARENT, 2120 2120 + .ops = &clk_branch2_ops, 2121 2121 + }, 2122 2122 + }, 2123 2123 + }; 2124 2124 + 2125 2125 + static struct clk_branch cam_cc_mclk5_clk = { 2126 2126 + .halt_reg = 0x150a4, 2127 2127 + .halt_check = BRANCH_HALT, 2128 2128 + .clkr = { 2129 2129 + .enable_reg = 0x150a4, 2130 2130 + .enable_mask = BIT(0), 2131 2131 + .hw.init = &(const struct clk_init_data) { 2132 2132 + .name = "cam_cc_mclk5_clk", 2133 2133 + .parent_hws = (const struct clk_hw*[]) { 2134 2134 + &cam_cc_mclk5_clk_src.clkr.hw, 2135 2135 + }, 2136 2136 + .num_parents = 1, 2137 2137 + .flags = CLK_SET_RATE_PARENT, 2138 2138 + .ops = &clk_branch2_ops, 2139 2139 + }, 2140 2140 + }, 2141 2141 + }; 2142 2142 + 2143 2143 + static struct clk_branch cam_cc_mclk6_clk = { 2144 2144 + .halt_reg = 0x150c0, 2145 2145 + .halt_check = BRANCH_HALT, 2146 2146 + .clkr = { 2147 2147 + .enable_reg = 0x150c0, 2148 2148 + .enable_mask = BIT(0), 2149 2149 + .hw.init = &(const struct clk_init_data) { 2150 2150 + .name = "cam_cc_mclk6_clk", 2151 2151 + .parent_hws = (const struct clk_hw*[]) { 2152 2152 + &cam_cc_mclk6_clk_src.clkr.hw, 2153 2153 + }, 2154 2154 + .num_parents = 1, 2155 2155 + .flags = CLK_SET_RATE_PARENT, 2156 2156 + .ops = &clk_branch2_ops, 2157 2157 + }, 2158 2158 + }, 2159 2159 + }; 2160 2160 + 2161 2161 + static struct clk_branch cam_cc_mclk7_clk = { 2162 2162 + .halt_reg = 0x150dc, 2163 2163 + .halt_check = BRANCH_HALT, 2164 2164 + .clkr = { 2165 2165 + .enable_reg = 0x150dc, 2166 2166 + .enable_mask = BIT(0), 2167 2167 + .hw.init = &(const struct clk_init_data) { 2168 2168 + .name = "cam_cc_mclk7_clk", 2169 2169 + .parent_hws = (const struct clk_hw*[]) { 2170 2170 + &cam_cc_mclk7_clk_src.clkr.hw, 2171 2171 + }, 2172 2172 + .num_parents = 1, 2173 2173 + .flags = CLK_SET_RATE_PARENT, 2174 2174 + .ops = &clk_branch2_ops, 2175 2175 + }, 2176 2176 + }, 2177 2177 + }; 2178 2178 + 2179 2179 + static struct clk_branch cam_cc_sfe_0_clk = { 2180 2180 + .halt_reg = 0x133c0, 2181 2181 + .halt_check = BRANCH_HALT, 2182 2182 + .clkr = { 2183 2183 + .enable_reg = 0x133c0, 2184 2184 + .enable_mask = BIT(0), 2185 2185 + .hw.init = &(const struct clk_init_data) { 2186 2186 + .name = "cam_cc_sfe_0_clk", 2187 2187 + .parent_hws = (const struct clk_hw*[]) { 2188 2188 + &cam_cc_sfe_0_clk_src.clkr.hw, 2189 2189 + }, 2190 2190 + .num_parents = 1, 2191 2191 + .flags = CLK_SET_RATE_PARENT, 2192 2192 + .ops = &clk_branch2_ops, 2193 2193 + }, 2194 2194 + }, 2195 2195 + }; 2196 2196 + 2197 2197 + static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { 2198 2198 + .halt_reg = 0x133d8, 2199 2199 + .halt_check = BRANCH_HALT, 2200 2200 + .clkr = { 2201 2201 + .enable_reg = 0x133d8, 2202 2202 + .enable_mask = BIT(0), 2203 2203 + .hw.init = &(const struct clk_init_data) { 2204 2204 + .name = "cam_cc_sfe_0_fast_ahb_clk", 2205 2205 + .parent_hws = (const struct clk_hw*[]) { 2206 2206 + &cam_cc_fast_ahb_clk_src.clkr.hw, 2207 2207 + }, 2208 2208 + .num_parents = 1, 2209 2209 + .flags = CLK_SET_RATE_PARENT, 2210 2210 + .ops = &clk_branch2_ops, 2211 2211 + }, 2212 2212 + }, 2213 2213 + }; 2214 2214 + 2215 2215 + static struct gdsc cam_cc_bps_gdsc = { 2216 2216 + .gdscr = 0x10004, 2217 2217 + .en_rest_wait_val = 0x2, 2218 2218 + .en_few_wait_val = 0x2, 2219 2219 + .clk_dis_wait_val = 0xf, 2220 2220 + .pd = { 2221 2221 + .name = "cam_cc_bps_gdsc", 2222 2222 + }, 2223 2223 + .pwrsts = PWRSTS_OFF_ON, 2224 2224 + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2225 2225 + }; 2226 2226 + 2227 2227 + static struct gdsc cam_cc_ife_0_gdsc = { 2228 2228 + .gdscr = 0x11004, 2229 2229 + .en_rest_wait_val = 0x2, 2230 2230 + .en_few_wait_val = 0x2, 2231 2231 + .clk_dis_wait_val = 0xf, 2232 2232 + .pd = { 2233 2233 + .name = "cam_cc_ife_0_gdsc", 2234 2234 + }, 2235 2235 + .pwrsts = PWRSTS_OFF_ON, 2236 2236 + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2237 2237 + }; 2238 2238 + 2239 2239 + static struct gdsc cam_cc_ife_1_gdsc = { 2240 2240 + .gdscr = 0x12004, 2241 2241 + .en_rest_wait_val = 0x2, 2242 2242 + .en_few_wait_val = 0x2, 2243 2243 + .clk_dis_wait_val = 0xf, 2244 2244 + .pd = { 2245 2245 + .name = "cam_cc_ife_1_gdsc", 2246 2246 + }, 2247 2247 + .pwrsts = PWRSTS_OFF_ON, 2248 2248 + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2249 2249 + }; 2250 2250 + 2251 2251 + static struct gdsc cam_cc_ipe_0_gdsc = { 2252 2252 + .gdscr = 0x103b8, 2253 2253 + .en_rest_wait_val = 0x2, 2254 2254 + .en_few_wait_val = 0x2, 2255 2255 + .clk_dis_wait_val = 0xf, 2256 2256 + .pd = { 2257 2257 + .name = "cam_cc_ipe_0_gdsc", 2258 2258 + }, 2259 2259 + .pwrsts = PWRSTS_OFF_ON, 2260 2260 + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2261 2261 + }; 2262 2262 + 2263 2263 + static struct gdsc cam_cc_sfe_0_gdsc = { 2264 2264 + .gdscr = 0x13280, 2265 2265 + .en_rest_wait_val = 0x2, 2266 2266 + .en_few_wait_val = 0x2, 2267 2267 + .clk_dis_wait_val = 0xf, 2268 2268 + .pd = { 2269 2269 + .name = "cam_cc_sfe_0_gdsc", 2270 2270 + }, 2271 2271 + .pwrsts = PWRSTS_OFF_ON, 2272 2272 + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2273 2273 + }; 2274 2274 + 2275 2275 + static struct gdsc cam_cc_titan_top_gdsc = { 2276 2276 + .gdscr = 0x13a6c, 2277 2277 + .en_rest_wait_val = 0x2, 2278 2278 + .en_few_wait_val = 0x2, 2279 2279 + .clk_dis_wait_val = 0xf, 2280 2280 + .pd = { 2281 2281 + .name = "cam_cc_titan_top_gdsc", 2282 2282 + }, 2283 2283 + .pwrsts = PWRSTS_OFF_ON, 2284 2284 + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2285 2285 + }; 2286 2286 + 2287 2287 + static struct clk_regmap *cam_cc_x1e80100_clocks[] = { 2288 2288 + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2289 2289 + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2290 2290 + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2291 2291 + [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, 2292 2292 + [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, 2293 2293 + [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, 2294 2294 + [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, 2295 2295 + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2296 2296 + [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2297 2297 + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2298 2298 + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2299 2299 + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2300 2300 + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2301 2301 + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2302 2302 + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2303 2303 + [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, 2304 2304 + [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, 2305 2305 + [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, 2306 2306 + [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, 2307 2307 + [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, 2308 2308 + [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, 2309 2309 + [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, 2310 2310 + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2311 2311 + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2312 2312 + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2313 2313 + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2314 2314 + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2315 2315 + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2316 2316 + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2317 2317 + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2318 2318 + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2319 2319 + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2320 2320 + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2321 2321 + [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2322 2322 + [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2323 2323 + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2324 2324 + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2325 2325 + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2326 2326 + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2327 2327 + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2328 2328 + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2329 2329 + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2330 2330 + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2331 2331 + [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2332 2332 + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2333 2333 + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2334 2334 + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2335 2335 + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2336 2336 + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2337 2337 + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2338 2338 + [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2339 2339 + [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, 2340 2340 + [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2341 2341 + [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2342 2342 + [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2343 2343 + [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, 2344 2344 + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2345 2345 + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2346 2346 + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2347 2347 + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2348 2348 + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2349 2349 + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2350 2350 + [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2351 2351 + [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2352 2352 + [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2353 2353 + [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2354 2354 + [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2355 2355 + [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2356 2356 + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2357 2357 + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2358 2358 + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2359 2359 + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2360 2360 + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2361 2361 + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2362 2362 + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2363 2363 + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2364 2364 + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2365 2365 + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2366 2366 + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2367 2367 + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2368 2368 + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2369 2369 + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2370 2370 + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, 2371 2371 + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, 2372 2372 + [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, 2373 2373 + [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, 2374 2374 + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2375 2375 + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2376 2376 + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2377 2377 + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2378 2378 + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2379 2379 + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2380 2380 + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2381 2381 + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2382 2382 + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2383 2383 + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2384 2384 + [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2385 2385 + [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2386 2386 + [CAM_CC_PLL8] = &cam_cc_pll8.clkr, 2387 2387 + [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, 2388 2388 + [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, 2389 2389 + [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, 2390 2390 + [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, 2391 2391 + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2392 2392 + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2393 2393 + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2394 2394 + }; 2395 2395 + 2396 2396 + static struct gdsc *cam_cc_x1e80100_gdscs[] = { 2397 2397 + [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, 2398 2398 + [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, 2399 2399 + [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, 2400 2400 + [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2401 2401 + [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc, 2402 2402 + [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2403 2403 + }; 2404 2404 + 2405 2405 + static const struct qcom_reset_map cam_cc_x1e80100_resets[] = { 2406 2406 + [CAM_CC_BPS_BCR] = { 0x10000 }, 2407 2407 + [CAM_CC_ICP_BCR] = { 0x1351c }, 2408 2408 + [CAM_CC_IFE_0_BCR] = { 0x11000 }, 2409 2409 + [CAM_CC_IFE_1_BCR] = { 0x12000 }, 2410 2410 + [CAM_CC_IPE_0_BCR] = { 0x103b4 }, 2411 2411 + [CAM_CC_SFE_0_BCR] = { 0x1327c }, 2412 2412 + }; 2413 2413 + 2414 2414 + static const struct regmap_config cam_cc_x1e80100_regmap_config = { 2415 2415 + .reg_bits = 32, 2416 2416 + .reg_stride = 4, 2417 2417 + .val_bits = 32, 2418 2418 + .max_register = 0x1603c, 2419 2419 + .fast_io = true, 2420 2420 + }; 2421 2421 + 2422 2422 + static const struct qcom_cc_desc cam_cc_x1e80100_desc = { 2423 2423 + .config = &cam_cc_x1e80100_regmap_config, 2424 2424 + .clks = cam_cc_x1e80100_clocks, 2425 2425 + .num_clks = ARRAY_SIZE(cam_cc_x1e80100_clocks), 2426 2426 + .resets = cam_cc_x1e80100_resets, 2427 2427 + .num_resets = ARRAY_SIZE(cam_cc_x1e80100_resets), 2428 2428 + .gdscs = cam_cc_x1e80100_gdscs, 2429 2429 + .num_gdscs = ARRAY_SIZE(cam_cc_x1e80100_gdscs), 2430 2430 + }; 2431 2431 + 2432 2432 + static const struct of_device_id cam_cc_x1e80100_match_table[] = { 2433 2433 + { .compatible = "qcom,x1e80100-camcc" }, 2434 2434 + { } 2435 2435 + }; 2436 2436 + MODULE_DEVICE_TABLE(of, cam_cc_x1e80100_match_table); 2437 2437 + 2438 2438 + static int cam_cc_x1e80100_probe(struct platform_device *pdev) 2439 2439 + { 2440 2440 + struct regmap *regmap; 2441 2441 + int ret; 2442 2442 + 2443 2443 + ret = devm_pm_runtime_enable(&pdev->dev); 2444 2444 + if (ret) 2445 2445 + return ret; 2446 2446 + 2447 2447 + ret = pm_runtime_resume_and_get(&pdev->dev); 2448 2448 + if (ret) 2449 2449 + return ret; 2450 2450 + 2451 2451 + regmap = qcom_cc_map(pdev, &cam_cc_x1e80100_desc); 2452 2452 + if (IS_ERR(regmap)) { 2453 2453 + pm_runtime_put(&pdev->dev); 2454 2454 + return PTR_ERR(regmap); 2455 2455 + } 2456 2456 + 2457 2457 + clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 2458 2458 + clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 2459 2459 + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 2460 2460 + clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 2461 2461 + clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 2462 2462 + clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); 2463 2463 + clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); 2464 2464 + 2465 2465 + /* Keep clocks always enabled */ 2466 2466 + qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */ 2467 2467 + qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */ 2468 2468 + 2469 2469 + ret = qcom_cc_really_probe(pdev, &cam_cc_x1e80100_desc, regmap); 2470 2470 + 2471 2471 + pm_runtime_put(&pdev->dev); 2472 2472 + 2473 2473 + return ret; 2474 2474 + } 2475 2475 + 2476 2476 + static struct platform_driver cam_cc_x1e80100_driver = { 2477 2477 + .probe = cam_cc_x1e80100_probe, 2478 2478 + .driver = { 2479 2479 + .name = "camcc-x1e80100", 2480 2480 + .of_match_table = cam_cc_x1e80100_match_table, 2481 2481 + }, 2482 2482 + }; 2483 2483 + 2484 2484 + module_platform_driver(cam_cc_x1e80100_driver); 2485 2485 + 2486 2486 + MODULE_DESCRIPTION("QTI Camera Clock Controller X1E80100 Driver"); 2487 2487 + MODULE_LICENSE("GPL");

+16

drivers/clk/qcom/clk-alpha-pll.c

reviewed

··· 52 52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 53 53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 54 54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 55 55 + #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) 55 56 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 56 57 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 57 58 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) ··· 228 227 [PLL_OFF_STATUS] = 0x1c, 229 228 [PLL_OFF_ALPHA_VAL] = 0x24, 230 229 [PLL_OFF_ALPHA_VAL_U] = 0x28, 230 230 + }, 231 231 + [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { 232 232 + [PLL_OFF_L_VAL] = 0x04, 233 233 + [PLL_OFF_ALPHA_VAL] = 0x08, 234 234 + [PLL_OFF_USER_CTL] = 0x0c, 235 235 + [PLL_OFF_USER_CTL_U] = 0x10, 236 236 + [PLL_OFF_CONFIG_CTL] = 0x14, 237 237 + [PLL_OFF_CONFIG_CTL_U] = 0x18, 238 238 + [PLL_OFF_CONFIG_CTL_U1] = 0x1c, 239 239 + [PLL_OFF_CONFIG_CTL_U2] = 0x20, 240 240 + [PLL_OFF_TEST_CTL] = 0x24, 241 241 + [PLL_OFF_TEST_CTL_U] = 0x28, 242 242 + [PLL_OFF_TEST_CTL_U1] = 0x2c, 243 243 + [PLL_OFF_OPMODE] = 0x30, 244 244 + [PLL_OFF_STATUS] = 0x3c, 231 245 }, 232 246 }; 233 247 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);

+4

drivers/clk/qcom/clk-alpha-pll.h

reviewed

··· 21 21 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 22 22 CLK_ALPHA_PLL_TYPE_AGERA, 23 23 CLK_ALPHA_PLL_TYPE_ZONDA, 24 24 + CLK_ALPHA_PLL_TYPE_ZONDA_OLE, 24 25 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 25 26 CLK_ALPHA_PLL_TYPE_LUCID_OLE, 26 27 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, ··· 43 42 PLL_OFF_CONFIG_CTL, 44 43 PLL_OFF_CONFIG_CTL_U, 45 44 PLL_OFF_CONFIG_CTL_U1, 45 45 + PLL_OFF_CONFIG_CTL_U2, 46 46 PLL_OFF_TEST_CTL, 47 47 PLL_OFF_TEST_CTL_U, 48 48 PLL_OFF_TEST_CTL_U1, ··· 121 119 u32 config_ctl_val; 122 120 u32 config_ctl_hi_val; 123 121 u32 config_ctl_hi1_val; 122 122 + u32 config_ctl_hi2_val; 124 123 u32 user_ctl_val; 125 124 u32 user_ctl_hi_val; 126 125 u32 user_ctl_hi1_val; ··· 176 173 177 174 extern const struct clk_ops clk_alpha_pll_zonda_ops; 178 175 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops 176 176 + #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops 179 177 180 178 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 181 179 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;

+6

drivers/clk/qcom/clk-branch.h

reviewed

··· 64 64 #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) 65 65 #define CBCR_WAKEUP GENMASK(11, 8) 66 66 #define CBCR_SLEEP GENMASK(7, 4) 67 67 + #define CBCR_CLOCK_ENABLE BIT(0) 67 68 68 69 static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, 69 70 struct clk_branch clk, bool on) ··· 97 96 { 98 97 regmap_update_bits(regmap, clk.halt_reg, CBCR_SLEEP, 99 98 FIELD_PREP(CBCR_SLEEP, val)); 99 99 + } 100 100 + 101 101 + static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) 102 102 + { 103 103 + regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, CBCR_CLOCK_ENABLE); 100 104 } 101 105 102 106 extern const struct clk_ops clk_branch_ops;

+3 -13

drivers/clk/qcom/dispcc-qcm2290.c

reviewed

··· 519 519 520 520 clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 521 521 522 522 - /* Keep DISP_CC_XO_CLK always-ON */ 523 523 - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); 522 522 + /* Keep some clocks always-on */ 523 523 + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ 524 524 525 525 ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap); 526 526 if (ret) { ··· 539 539 }, 540 540 }; 541 541 542 542 - static int __init disp_cc_qcm2290_init(void) 543 543 - { 544 544 - return platform_driver_register(&disp_cc_qcm2290_driver); 545 545 - } 546 546 - subsys_initcall(disp_cc_qcm2290_init); 547 547 - 548 548 - static void __exit disp_cc_qcm2290_exit(void) 549 549 - { 550 550 - platform_driver_unregister(&disp_cc_qcm2290_driver); 551 551 - } 552 552 - module_exit(disp_cc_qcm2290_exit); 542 542 + module_platform_driver(disp_cc_qcm2290_driver); 553 543 554 544 MODULE_DESCRIPTION("QTI DISP_CC qcm2290 Driver"); 555 545 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/dispcc-sc7180.c

reviewed

··· 724 724 }, 725 725 }; 726 726 727 727 - static int __init disp_cc_sc7180_init(void) 728 728 - { 729 729 - return platform_driver_register(&disp_cc_sc7180_driver); 730 730 - } 731 731 - subsys_initcall(disp_cc_sc7180_init); 732 732 - 733 733 - static void __exit disp_cc_sc7180_exit(void) 734 734 - { 735 735 - platform_driver_unregister(&disp_cc_sc7180_driver); 736 736 - } 737 737 - module_exit(disp_cc_sc7180_exit); 727 727 + module_platform_driver(disp_cc_sc7180_driver); 738 728 739 729 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver"); 740 730 MODULE_LICENSE("GPL v2");

+3 -16

drivers/clk/qcom/dispcc-sc7280.c

reviewed

··· 878 878 879 879 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 880 880 881 881 - /* 882 882 - * Keep the clocks always-ON 883 883 - * DISP_CC_XO_CLK 884 884 - */ 885 885 - regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); 881 881 + /* Keep some clocks always-on */ 882 882 + qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */ 886 883 887 884 return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap); 888 885 } ··· 892 895 }, 893 896 }; 894 897 895 895 - static int __init disp_cc_sc7280_init(void) 896 896 - { 897 897 - return platform_driver_register(&disp_cc_sc7280_driver); 898 898 - } 899 899 - subsys_initcall(disp_cc_sc7280_init); 900 900 - 901 901 - static void __exit disp_cc_sc7280_exit(void) 902 902 - { 903 903 - platform_driver_unregister(&disp_cc_sc7280_driver); 904 904 - } 905 905 - module_exit(disp_cc_sc7280_exit); 898 898 + module_platform_driver(disp_cc_sc7280_driver); 906 899 907 900 MODULE_DESCRIPTION("QTI DISP_CC sc7280 Driver"); 908 901 MODULE_LICENSE("GPL v2");

+3 -13

drivers/clk/qcom/dispcc-sc8280xp.c

reviewed

··· 3178 3178 goto out_pm_runtime_put; 3179 3179 } 3180 3180 3181 3181 - /* DISP_CC_XO_CLK always-on */ 3182 3182 - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); 3181 3181 + /* Keep some clocks always-on */ 3182 3182 + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ 3183 3183 3184 3184 out_pm_runtime_put: 3185 3185 pm_runtime_put_sync(&pdev->dev); ··· 3202 3202 }, 3203 3203 }; 3204 3204 3205 3205 - static int __init disp_cc_sc8280xp_init(void) 3206 3206 - { 3207 3207 - return platform_driver_register(&disp_cc_sc8280xp_driver); 3208 3208 - } 3209 3209 - subsys_initcall(disp_cc_sc8280xp_init); 3210 3210 - 3211 3211 - static void __exit disp_cc_sc8280xp_exit(void) 3212 3212 - { 3213 3213 - platform_driver_unregister(&disp_cc_sc8280xp_driver); 3214 3214 - } 3215 3215 - module_exit(disp_cc_sc8280xp_exit); 3205 3205 + module_platform_driver(disp_cc_sc8280xp_driver); 3216 3206 3217 3207 MODULE_DESCRIPTION("Qualcomm SC8280XP dispcc driver"); 3218 3208 MODULE_LICENSE("GPL");

+3 -11

drivers/clk/qcom/dispcc-sdm845.c

reviewed

··· 759 759 760 760 static struct gdsc mdss_gdsc = { 761 761 .gdscr = 0x3000, 762 762 + .en_few_wait_val = 0x6, 763 763 + .en_rest_wait_val = 0x5, 762 764 .pd = { 763 765 .name = "mdss_gdsc", 764 766 }, ··· 874 872 }, 875 873 }; 876 874 877 877 - static int __init disp_cc_sdm845_init(void) 878 878 - { 879 879 - return platform_driver_register(&disp_cc_sdm845_driver); 880 880 - } 881 881 - subsys_initcall(disp_cc_sdm845_init); 882 882 - 883 883 - static void __exit disp_cc_sdm845_exit(void) 884 884 - { 885 885 - platform_driver_unregister(&disp_cc_sdm845_driver); 886 886 - } 887 887 - module_exit(disp_cc_sdm845_exit); 875 875 + module_platform_driver(disp_cc_sdm845_driver); 888 876 889 877 MODULE_LICENSE("GPL v2"); 890 878 MODULE_DESCRIPTION("QTI DISPCC SDM845 Driver");

+2 -2

drivers/clk/qcom/dispcc-sm6115.c

reviewed

··· 583 583 584 584 clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 585 585 586 586 - /* Keep DISP_CC_XO_CLK always-ON */ 587 587 - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); 586 586 + /* Keep some clocks always-on */ 587 587 + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ 588 588 589 589 ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap); 590 590 if (ret) {

+1 -11

drivers/clk/qcom/dispcc-sm6125.c

reviewed

··· 693 693 }, 694 694 }; 695 695 696 696 - static int __init disp_cc_sm6125_init(void) 697 697 - { 698 698 - return platform_driver_register(&disp_cc_sm6125_driver); 699 699 - } 700 700 - subsys_initcall(disp_cc_sm6125_init); 701 701 - 702 702 - static void __exit disp_cc_sm6125_exit(void) 703 703 - { 704 704 - platform_driver_unregister(&disp_cc_sm6125_driver); 705 705 - } 706 706 - module_exit(disp_cc_sm6125_exit); 696 696 + module_platform_driver(disp_cc_sm6125_driver); 707 697 708 698 MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver"); 709 699 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/dispcc-sm6350.c

reviewed

··· 781 781 }, 782 782 }; 783 783 784 784 - static int __init disp_cc_sm6350_init(void) 785 785 - { 786 786 - return platform_driver_register(&disp_cc_sm6350_driver); 787 787 - } 788 788 - subsys_initcall(disp_cc_sm6350_init); 789 789 - 790 790 - static void __exit disp_cc_sm6350_exit(void) 791 791 - { 792 792 - platform_driver_unregister(&disp_cc_sm6350_driver); 793 793 - } 794 794 - module_exit(disp_cc_sm6350_exit); 784 784 + module_platform_driver(disp_cc_sm6350_driver); 795 785 796 786 MODULE_DESCRIPTION("QTI DISP_CC SM6350 Driver"); 797 787 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/dispcc-sm6375.c

reviewed

··· 594 594 }, 595 595 }; 596 596 597 597 - static int __init disp_cc_sm6375_init(void) 598 598 - { 599 599 - return platform_driver_register(&disp_cc_sm6375_driver); 600 600 - } 601 601 - subsys_initcall(disp_cc_sm6375_init); 602 602 - 603 603 - static void __exit disp_cc_sm6375_exit(void) 604 604 - { 605 605 - platform_driver_unregister(&disp_cc_sm6375_driver); 606 606 - } 607 607 - module_exit(disp_cc_sm6375_exit); 597 597 + module_platform_driver(disp_cc_sm6375_driver); 608 598 609 599 MODULE_DESCRIPTION("QTI DISPCC SM6375 Driver"); 610 600 MODULE_LICENSE("GPL");

+61 -73

drivers/clk/qcom/dispcc-sm8250.c

reviewed

··· 39 39 P_DSI1_PHY_PLL_OUT_DSICLK, 40 40 }; 41 41 42 42 - static struct pll_vco vco_table[] = { 42 42 + static const struct pll_vco vco_table[] = { 43 43 { 249600000, 2000000000, 0 }, 44 44 }; 45 45 46 46 - static struct pll_vco lucid_5lpe_vco[] = { 46 46 + static const struct pll_vco lucid_5lpe_vco[] = { 47 47 { 249600000, 1750000000, 0 }, 48 48 }; 49 49 ··· 214 214 .hid_width = 5, 215 215 .parent_map = disp_cc_parent_map_3, 216 216 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 217 217 - .clkr.hw.init = &(struct clk_init_data){ 217 217 + .clkr.hw.init = &(const struct clk_init_data) { 218 218 .name = "disp_cc_mdss_ahb_clk_src", 219 219 .parent_data = disp_cc_parent_data_3, 220 220 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), ··· 233 233 .mnd_width = 0, 234 234 .hid_width = 5, 235 235 .parent_map = disp_cc_parent_map_2, 236 236 - .clkr.hw.init = &(struct clk_init_data){ 236 236 + .clkr.hw.init = &(const struct clk_init_data) { 237 237 .name = "disp_cc_mdss_byte0_clk_src", 238 238 .parent_data = disp_cc_parent_data_2, 239 239 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), ··· 247 247 .mnd_width = 0, 248 248 .hid_width = 5, 249 249 .parent_map = disp_cc_parent_map_2, 250 250 - .clkr.hw.init = &(struct clk_init_data){ 250 250 + .clkr.hw.init = &(const struct clk_init_data) { 251 251 .name = "disp_cc_mdss_byte1_clk_src", 252 252 .parent_data = disp_cc_parent_data_2, 253 253 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), ··· 262 262 .hid_width = 5, 263 263 .parent_map = disp_cc_parent_map_1, 264 264 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 265 265 - .clkr.hw.init = &(struct clk_init_data){ 265 265 + .clkr.hw.init = &(const struct clk_init_data) { 266 266 .name = "disp_cc_mdss_dp_aux1_clk_src", 267 267 .parent_data = disp_cc_parent_data_1, 268 268 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 277 277 .hid_width = 5, 278 278 .parent_map = disp_cc_parent_map_1, 279 279 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 280 280 - .clkr.hw.init = &(struct clk_init_data){ 280 280 + .clkr.hw.init = &(const struct clk_init_data) { 281 281 .name = "disp_cc_mdss_dp_aux_clk_src", 282 282 .parent_data = disp_cc_parent_data_1, 283 283 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 291 291 .mnd_width = 0, 292 292 .hid_width = 5, 293 293 .parent_map = disp_cc_parent_map_0, 294 294 - .clkr.hw.init = &(struct clk_init_data){ 294 294 + .clkr.hw.init = &(const struct clk_init_data) { 295 295 .name = "disp_cc_mdss_dp_link1_clk_src", 296 296 .parent_data = disp_cc_parent_data_0, 297 297 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 304 304 .mnd_width = 0, 305 305 .hid_width = 5, 306 306 .parent_map = disp_cc_parent_map_0, 307 307 - .clkr.hw.init = &(struct clk_init_data){ 307 307 + .clkr.hw.init = &(const struct clk_init_data) { 308 308 .name = "disp_cc_mdss_dp_link_clk_src", 309 309 .parent_data = disp_cc_parent_data_0, 310 310 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 317 317 .mnd_width = 16, 318 318 .hid_width = 5, 319 319 .parent_map = disp_cc_parent_map_0, 320 320 - .clkr.hw.init = &(struct clk_init_data){ 320 320 + .clkr.hw.init = &(const struct clk_init_data) { 321 321 .name = "disp_cc_mdss_dp_pixel1_clk_src", 322 322 .parent_data = disp_cc_parent_data_0, 323 323 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 330 330 .mnd_width = 16, 331 331 .hid_width = 5, 332 332 .parent_map = disp_cc_parent_map_0, 333 333 - .clkr.hw.init = &(struct clk_init_data){ 333 333 + .clkr.hw.init = &(const struct clk_init_data) { 334 334 .name = "disp_cc_mdss_dp_pixel2_clk_src", 335 335 .parent_data = disp_cc_parent_data_0, 336 336 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 343 343 .mnd_width = 16, 344 344 .hid_width = 5, 345 345 .parent_map = disp_cc_parent_map_0, 346 346 - .clkr.hw.init = &(struct clk_init_data){ 346 346 + .clkr.hw.init = &(const struct clk_init_data) { 347 347 .name = "disp_cc_mdss_dp_pixel_clk_src", 348 348 .parent_data = disp_cc_parent_data_0, 349 349 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 357 357 .hid_width = 5, 358 358 .parent_map = disp_cc_parent_map_1, 359 359 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 360 360 - .clkr.hw.init = &(struct clk_init_data){ 360 360 + .clkr.hw.init = &(const struct clk_init_data) { 361 361 .name = "disp_cc_mdss_edp_aux_clk_src", 362 362 .parent_data = disp_cc_parent_data_1, 363 363 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 372 372 .hid_width = 5, 373 373 .parent_map = disp_cc_parent_map_7, 374 374 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 375 375 - .clkr.hw.init = &(struct clk_init_data){ 375 375 + .clkr.hw.init = &(const struct clk_init_data) { 376 376 .name = "disp_cc_mdss_edp_gtc_clk_src", 377 377 .parent_data = disp_cc_parent_data_7, 378 378 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), ··· 386 386 .mnd_width = 0, 387 387 .hid_width = 5, 388 388 .parent_map = disp_cc_parent_map_4, 389 389 - .clkr.hw.init = &(struct clk_init_data){ 389 389 + .clkr.hw.init = &(const struct clk_init_data) { 390 390 .name = "disp_cc_mdss_edp_link_clk_src", 391 391 .parent_data = disp_cc_parent_data_4, 392 392 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), ··· 400 400 .mnd_width = 16, 401 401 .hid_width = 5, 402 402 .parent_map = disp_cc_parent_map_4, 403 403 - .clkr.hw.init = &(struct clk_init_data){ 403 403 + .clkr.hw.init = &(const struct clk_init_data) { 404 404 .name = "disp_cc_mdss_edp_pixel_clk_src", 405 405 .parent_data = disp_cc_parent_data_4, 406 406 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), ··· 414 414 .clkr = { 415 415 .enable_reg = 0x2078, 416 416 .enable_mask = BIT(0), 417 417 - .hw.init = &(struct clk_init_data){ 417 417 + .hw.init = &(const struct clk_init_data) { 418 418 .name = "disp_cc_mdss_edp_aux_clk", 419 419 .parent_hws = (const struct clk_hw*[]){ 420 420 &disp_cc_mdss_edp_aux_clk_src.clkr.hw, ··· 432 432 .clkr = { 433 433 .enable_reg = 0x207c, 434 434 .enable_mask = BIT(0), 435 435 - .hw.init = &(struct clk_init_data){ 435 435 + .hw.init = &(const struct clk_init_data) { 436 436 .name = "disp_cc_mdss_edp_gtc_clk", 437 437 .parent_hws = (const struct clk_hw*[]){ 438 438 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, ··· 450 450 .clkr = { 451 451 .enable_reg = 0x2070, 452 452 .enable_mask = BIT(0), 453 453 - .hw.init = &(struct clk_init_data){ 453 453 + .hw.init = &(const struct clk_init_data) { 454 454 .name = "disp_cc_mdss_edp_link_clk", 455 455 .parent_hws = (const struct clk_hw*[]){ 456 456 &disp_cc_mdss_edp_link_clk_src.clkr.hw, ··· 466 466 .reg = 0x2288, 467 467 .shift = 0, 468 468 .width = 2, 469 469 - .clkr.hw.init = &(struct clk_init_data) { 469 469 + .clkr.hw.init = &(const struct clk_init_data) { 470 470 .name = "disp_cc_mdss_edp_link_div_clk_src", 471 471 .parent_hws = (const struct clk_hw*[]){ 472 472 &disp_cc_mdss_edp_link_clk_src.clkr.hw, ··· 482 482 .clkr = { 483 483 .enable_reg = 0x2074, 484 484 .enable_mask = BIT(0), 485 485 - .hw.init = &(struct clk_init_data){ 485 485 + .hw.init = &(const struct clk_init_data) { 486 486 .name = "disp_cc_mdss_edp_link_intf_clk", 487 487 .parent_hws = (const struct clk_hw*[]){ 488 488 &disp_cc_mdss_edp_link_div_clk_src.clkr.hw, ··· 500 500 .clkr = { 501 501 .enable_reg = 0x206c, 502 502 .enable_mask = BIT(0), 503 503 - .hw.init = &(struct clk_init_data){ 503 503 + .hw.init = &(const struct clk_init_data) { 504 504 .name = "disp_cc_mdss_edp_pixel_clk", 505 505 .parent_hws = (const struct clk_hw*[]){ 506 506 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, ··· 518 518 .hid_width = 5, 519 519 .parent_map = disp_cc_parent_map_2, 520 520 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 521 521 - .clkr.hw.init = &(struct clk_init_data){ 521 521 + .clkr.hw.init = &(const struct clk_init_data) { 522 522 .name = "disp_cc_mdss_esc0_clk_src", 523 523 .parent_data = disp_cc_parent_data_2, 524 524 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), ··· 533 533 .hid_width = 5, 534 534 .parent_map = disp_cc_parent_map_2, 535 535 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 536 536 - .clkr.hw.init = &(struct clk_init_data){ 536 536 + .clkr.hw.init = &(const struct clk_init_data) { 537 537 .name = "disp_cc_mdss_esc1_clk_src", 538 538 .parent_data = disp_cc_parent_data_2, 539 539 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), ··· 560 560 .hid_width = 5, 561 561 .parent_map = disp_cc_parent_map_5, 562 562 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 563 563 - .clkr.hw.init = &(struct clk_init_data){ 563 563 + .clkr.hw.init = &(const struct clk_init_data) { 564 564 .name = "disp_cc_mdss_mdp_clk_src", 565 565 .parent_data = disp_cc_parent_data_5, 566 566 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), ··· 574 574 .mnd_width = 8, 575 575 .hid_width = 5, 576 576 .parent_map = disp_cc_parent_map_6, 577 577 - .clkr.hw.init = &(struct clk_init_data){ 577 577 + .clkr.hw.init = &(const struct clk_init_data) { 578 578 .name = "disp_cc_mdss_pclk0_clk_src", 579 579 .parent_data = disp_cc_parent_data_6, 580 580 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), ··· 588 588 .mnd_width = 8, 589 589 .hid_width = 5, 590 590 .parent_map = disp_cc_parent_map_6, 591 591 - .clkr.hw.init = &(struct clk_init_data){ 591 591 + .clkr.hw.init = &(const struct clk_init_data) { 592 592 .name = "disp_cc_mdss_pclk1_clk_src", 593 593 .parent_data = disp_cc_parent_data_6, 594 594 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), ··· 612 612 .hid_width = 5, 613 613 .parent_map = disp_cc_parent_map_5, 614 614 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 615 615 - .clkr.hw.init = &(struct clk_init_data){ 615 615 + .clkr.hw.init = &(const struct clk_init_data) { 616 616 .name = "disp_cc_mdss_rot_clk_src", 617 617 .parent_data = disp_cc_parent_data_5, 618 618 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), ··· 627 627 .hid_width = 5, 628 628 .parent_map = disp_cc_parent_map_1, 629 629 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 630 630 - .clkr.hw.init = &(struct clk_init_data){ 630 630 + .clkr.hw.init = &(const struct clk_init_data) { 631 631 .name = "disp_cc_mdss_vsync_clk_src", 632 632 .parent_data = disp_cc_parent_data_1, 633 633 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 640 640 .reg = 0x2128, 641 641 .shift = 0, 642 642 .width = 2, 643 643 - .clkr.hw.init = &(struct clk_init_data) { 643 643 + .clkr.hw.init = &(const struct clk_init_data) { 644 644 .name = "disp_cc_mdss_byte0_div_clk_src", 645 645 .parent_hws = (const struct clk_hw*[]){ 646 646 &disp_cc_mdss_byte0_clk_src.clkr.hw, ··· 655 655 .reg = 0x2144, 656 656 .shift = 0, 657 657 .width = 2, 658 658 - .clkr.hw.init = &(struct clk_init_data) { 658 658 + .clkr.hw.init = &(const struct clk_init_data) { 659 659 .name = "disp_cc_mdss_byte1_div_clk_src", 660 660 .parent_hws = (const struct clk_hw*[]){ 661 661 &disp_cc_mdss_byte1_clk_src.clkr.hw, ··· 665 665 }, 666 666 }; 667 667 668 668 - 669 668 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { 670 669 .reg = 0x2224, 671 670 .shift = 0, 672 671 .width = 2, 673 673 - .clkr.hw.init = &(struct clk_init_data) { 672 672 + .clkr.hw.init = &(const struct clk_init_data) { 674 673 .name = "disp_cc_mdss_dp_link1_div_clk_src", 675 674 .parent_hws = (const struct clk_hw*[]){ 676 675 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, ··· 679 680 }, 680 681 }; 681 682 682 682 - 683 683 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { 684 684 .reg = 0x2190, 685 685 .shift = 0, 686 686 .width = 2, 687 687 - .clkr.hw.init = &(struct clk_init_data) { 687 687 + .clkr.hw.init = &(const struct clk_init_data) { 688 688 .name = "disp_cc_mdss_dp_link_div_clk_src", 689 689 .parent_hws = (const struct clk_hw*[]){ 690 690 &disp_cc_mdss_dp_link_clk_src.clkr.hw, ··· 699 701 .clkr = { 700 702 .enable_reg = 0x2080, 701 703 .enable_mask = BIT(0), 702 702 - .hw.init = &(struct clk_init_data){ 704 704 + .hw.init = &(const struct clk_init_data) { 703 705 .name = "disp_cc_mdss_ahb_clk", 704 706 .parent_hws = (const struct clk_hw*[]){ 705 707 &disp_cc_mdss_ahb_clk_src.clkr.hw, ··· 717 719 .clkr = { 718 720 .enable_reg = 0x2028, 719 721 .enable_mask = BIT(0), 720 720 - .hw.init = &(struct clk_init_data){ 722 722 + .hw.init = &(const struct clk_init_data) { 721 723 .name = "disp_cc_mdss_byte0_clk", 722 724 .parent_hws = (const struct clk_hw*[]){ 723 725 &disp_cc_mdss_byte0_clk_src.clkr.hw, ··· 735 737 .clkr = { 736 738 .enable_reg = 0x202c, 737 739 .enable_mask = BIT(0), 738 738 - .hw.init = &(struct clk_init_data){ 740 740 + .hw.init = &(const struct clk_init_data) { 739 741 .name = "disp_cc_mdss_byte0_intf_clk", 740 742 .parent_hws = (const struct clk_hw*[]){ 741 743 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, ··· 753 755 .clkr = { 754 756 .enable_reg = 0x2030, 755 757 .enable_mask = BIT(0), 756 756 - .hw.init = &(struct clk_init_data){ 758 758 + .hw.init = &(const struct clk_init_data) { 757 759 .name = "disp_cc_mdss_byte1_clk", 758 760 .parent_hws = (const struct clk_hw*[]){ 759 761 &disp_cc_mdss_byte1_clk_src.clkr.hw, ··· 771 773 .clkr = { 772 774 .enable_reg = 0x2034, 773 775 .enable_mask = BIT(0), 774 774 - .hw.init = &(struct clk_init_data){ 776 776 + .hw.init = &(const struct clk_init_data) { 775 777 .name = "disp_cc_mdss_byte1_intf_clk", 776 778 .parent_hws = (const struct clk_hw*[]){ 777 779 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, ··· 789 791 .clkr = { 790 792 .enable_reg = 0x2068, 791 793 .enable_mask = BIT(0), 792 792 - .hw.init = &(struct clk_init_data){ 794 794 + .hw.init = &(const struct clk_init_data) { 793 795 .name = "disp_cc_mdss_dp_aux1_clk", 794 796 .parent_hws = (const struct clk_hw*[]){ 795 797 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, ··· 807 809 .clkr = { 808 810 .enable_reg = 0x2054, 809 811 .enable_mask = BIT(0), 810 810 - .hw.init = &(struct clk_init_data){ 812 812 + .hw.init = &(const struct clk_init_data) { 811 813 .name = "disp_cc_mdss_dp_aux_clk", 812 814 .parent_hws = (const struct clk_hw*[]){ 813 815 &disp_cc_mdss_dp_aux_clk_src.clkr.hw, ··· 825 827 .clkr = { 826 828 .enable_reg = 0x205c, 827 829 .enable_mask = BIT(0), 828 828 - .hw.init = &(struct clk_init_data){ 830 830 + .hw.init = &(const struct clk_init_data) { 829 831 .name = "disp_cc_mdss_dp_link1_clk", 830 832 .parent_hws = (const struct clk_hw*[]){ 831 833 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, ··· 843 845 .clkr = { 844 846 .enable_reg = 0x2060, 845 847 .enable_mask = BIT(0), 846 846 - .hw.init = &(struct clk_init_data){ 848 848 + .hw.init = &(const struct clk_init_data) { 847 849 .name = "disp_cc_mdss_dp_link1_intf_clk", 848 850 .parent_hws = (const struct clk_hw*[]){ 849 851 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, ··· 860 862 .clkr = { 861 863 .enable_reg = 0x2040, 862 864 .enable_mask = BIT(0), 863 863 - .hw.init = &(struct clk_init_data){ 865 865 + .hw.init = &(const struct clk_init_data) { 864 866 .name = "disp_cc_mdss_dp_link_clk", 865 867 .parent_hws = (const struct clk_hw*[]){ 866 868 &disp_cc_mdss_dp_link_clk_src.clkr.hw, ··· 878 880 .clkr = { 879 881 .enable_reg = 0x2044, 880 882 .enable_mask = BIT(0), 881 881 - .hw.init = &(struct clk_init_data){ 883 883 + .hw.init = &(const struct clk_init_data) { 882 884 .name = "disp_cc_mdss_dp_link_intf_clk", 883 885 .parent_hws = (const struct clk_hw*[]){ 884 886 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, ··· 895 897 .clkr = { 896 898 .enable_reg = 0x2050, 897 899 .enable_mask = BIT(0), 898 898 - .hw.init = &(struct clk_init_data){ 900 900 + .hw.init = &(const struct clk_init_data) { 899 901 .name = "disp_cc_mdss_dp_pixel1_clk", 900 902 .parent_hws = (const struct clk_hw*[]){ 901 903 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, ··· 913 915 .clkr = { 914 916 .enable_reg = 0x2058, 915 917 .enable_mask = BIT(0), 916 916 - .hw.init = &(struct clk_init_data){ 918 918 + .hw.init = &(const struct clk_init_data) { 917 919 .name = "disp_cc_mdss_dp_pixel2_clk", 918 920 .parent_hws = (const struct clk_hw*[]){ 919 921 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, ··· 931 933 .clkr = { 932 934 .enable_reg = 0x204c, 933 935 .enable_mask = BIT(0), 934 934 - .hw.init = &(struct clk_init_data){ 936 936 + .hw.init = &(const struct clk_init_data) { 935 937 .name = "disp_cc_mdss_dp_pixel_clk", 936 938 .parent_hws = (const struct clk_hw*[]){ 937 939 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, ··· 949 951 .clkr = { 950 952 .enable_reg = 0x2038, 951 953 .enable_mask = BIT(0), 952 952 - .hw.init = &(struct clk_init_data){ 954 954 + .hw.init = &(const struct clk_init_data) { 953 955 .name = "disp_cc_mdss_esc0_clk", 954 956 .parent_hws = (const struct clk_hw*[]){ 955 957 &disp_cc_mdss_esc0_clk_src.clkr.hw, ··· 967 969 .clkr = { 968 970 .enable_reg = 0x203c, 969 971 .enable_mask = BIT(0), 970 970 - .hw.init = &(struct clk_init_data){ 972 972 + .hw.init = &(const struct clk_init_data) { 971 973 .name = "disp_cc_mdss_esc1_clk", 972 974 .parent_hws = (const struct clk_hw*[]){ 973 975 &disp_cc_mdss_esc1_clk_src.clkr.hw, ··· 985 987 .clkr = { 986 988 .enable_reg = 0x200c, 987 989 .enable_mask = BIT(0), 988 988 - .hw.init = &(struct clk_init_data){ 990 990 + .hw.init = &(const struct clk_init_data) { 989 991 .name = "disp_cc_mdss_mdp_clk", 990 992 .parent_hws = (const struct clk_hw*[]){ 991 993 &disp_cc_mdss_mdp_clk_src.clkr.hw, ··· 1003 1005 .clkr = { 1004 1006 .enable_reg = 0x201c, 1005 1007 .enable_mask = BIT(0), 1006 1006 - .hw.init = &(struct clk_init_data){ 1008 1008 + .hw.init = &(const struct clk_init_data) { 1007 1009 .name = "disp_cc_mdss_mdp_lut_clk", 1008 1010 .parent_hws = (const struct clk_hw*[]){ 1009 1011 &disp_cc_mdss_mdp_clk_src.clkr.hw, ··· 1020 1022 .clkr = { 1021 1023 .enable_reg = 0x4004, 1022 1024 .enable_mask = BIT(0), 1023 1023 - .hw.init = &(struct clk_init_data){ 1025 1025 + .hw.init = &(const struct clk_init_data) { 1024 1026 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1025 1027 .parent_hws = (const struct clk_hw*[]){ 1026 1028 &disp_cc_mdss_ahb_clk_src.clkr.hw, ··· 1038 1040 .clkr = { 1039 1041 .enable_reg = 0x2004, 1040 1042 .enable_mask = BIT(0), 1041 1041 - .hw.init = &(struct clk_init_data){ 1043 1043 + .hw.init = &(const struct clk_init_data) { 1042 1044 .name = "disp_cc_mdss_pclk0_clk", 1043 1045 .parent_hws = (const struct clk_hw*[]){ 1044 1046 &disp_cc_mdss_pclk0_clk_src.clkr.hw, ··· 1056 1058 .clkr = { 1057 1059 .enable_reg = 0x2008, 1058 1060 .enable_mask = BIT(0), 1059 1059 - .hw.init = &(struct clk_init_data){ 1061 1061 + .hw.init = &(const struct clk_init_data) { 1060 1062 .name = "disp_cc_mdss_pclk1_clk", 1061 1063 .parent_hws = (const struct clk_hw*[]){ 1062 1064 &disp_cc_mdss_pclk1_clk_src.clkr.hw, ··· 1074 1076 .clkr = { 1075 1077 .enable_reg = 0x2014, 1076 1078 .enable_mask = BIT(0), 1077 1077 - .hw.init = &(struct clk_init_data){ 1079 1079 + .hw.init = &(const struct clk_init_data) { 1078 1080 .name = "disp_cc_mdss_rot_clk", 1079 1081 .parent_hws = (const struct clk_hw*[]){ 1080 1082 &disp_cc_mdss_rot_clk_src.clkr.hw, ··· 1092 1094 .clkr = { 1093 1095 .enable_reg = 0x400c, 1094 1096 .enable_mask = BIT(0), 1095 1095 - .hw.init = &(struct clk_init_data){ 1097 1097 + .hw.init = &(const struct clk_init_data) { 1096 1098 .name = "disp_cc_mdss_rscc_ahb_clk", 1097 1099 .parent_hws = (const struct clk_hw*[]){ 1098 1100 &disp_cc_mdss_ahb_clk_src.clkr.hw, ··· 1110 1112 .clkr = { 1111 1113 .enable_reg = 0x4008, 1112 1114 .enable_mask = BIT(0), 1113 1113 - .hw.init = &(struct clk_init_data){ 1115 1115 + .hw.init = &(const struct clk_init_data) { 1114 1116 .name = "disp_cc_mdss_rscc_vsync_clk", 1115 1117 .parent_hws = (const struct clk_hw*[]){ 1116 1118 &disp_cc_mdss_vsync_clk_src.clkr.hw, ··· 1128 1130 .clkr = { 1129 1131 .enable_reg = 0x2024, 1130 1132 .enable_mask = BIT(0), 1131 1131 - .hw.init = &(struct clk_init_data){ 1133 1133 + .hw.init = &(const struct clk_init_data) { 1132 1134 .name = "disp_cc_mdss_vsync_clk", 1133 1135 .parent_hws = (const struct clk_hw*[]){ 1134 1136 &disp_cc_mdss_vsync_clk_src.clkr.hw, ··· 1363 1365 /* Enable clock gating for MDP clocks */ 1364 1366 regmap_update_bits(regmap, 0x8000, 0x10, 0x10); 1365 1367 1366 1366 - /* DISP_CC_XO_CLK always-on */ 1367 1367 - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); 1368 1368 + /* Keep some clocks always-on */ 1369 1369 + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ 1368 1370 1369 1371 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); 1370 1372 ··· 1381 1383 }, 1382 1384 }; 1383 1385 1384 1384 - static int __init disp_cc_sm8250_init(void) 1385 1385 - { 1386 1386 - return platform_driver_register(&disp_cc_sm8250_driver); 1387 1387 - } 1388 1388 - subsys_initcall(disp_cc_sm8250_init); 1389 1389 - 1390 1390 - static void __exit disp_cc_sm8250_exit(void) 1391 1391 - { 1392 1392 - platform_driver_unregister(&disp_cc_sm8250_driver); 1393 1393 - } 1394 1394 - module_exit(disp_cc_sm8250_exit); 1386 1386 + module_platform_driver(disp_cc_sm8250_driver); 1395 1387 1396 1388 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); 1397 1389 MODULE_LICENSE("GPL v2");

+3 -16

drivers/clk/qcom/dispcc-sm8450.c

reviewed

··· 1787 1787 /* Enable clock gating for MDP clocks */ 1788 1788 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1789 1789 1790 1790 - /* 1791 1791 - * Keep clocks always enabled: 1792 1792 - * disp_cc_xo_clk 1793 1793 - */ 1794 1794 - regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0)); 1790 1790 + /* Keep some clocks always-on */ 1791 1791 + qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ 1795 1792 1796 1793 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap); 1797 1794 if (ret) ··· 1812 1815 }, 1813 1816 }; 1814 1817 1815 1815 - static int __init disp_cc_sm8450_init(void) 1816 1816 - { 1817 1817 - return platform_driver_register(&disp_cc_sm8450_driver); 1818 1818 - } 1819 1819 - subsys_initcall(disp_cc_sm8450_init); 1820 1820 - 1821 1821 - static void __exit disp_cc_sm8450_exit(void) 1822 1822 - { 1823 1823 - platform_driver_unregister(&disp_cc_sm8450_driver); 1824 1824 - } 1825 1825 - module_exit(disp_cc_sm8450_exit); 1818 1818 + module_platform_driver(disp_cc_sm8450_driver); 1826 1819 1827 1820 MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver"); 1828 1821 MODULE_LICENSE("GPL");

+3 -16

drivers/clk/qcom/dispcc-sm8550.c

reviewed

··· 1780 1780 /* Enable clock gating for MDP clocks */ 1781 1781 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1782 1782 1783 1783 - /* 1784 1784 - * Keep clocks always enabled: 1785 1785 - * disp_cc_xo_clk 1786 1786 - */ 1787 1787 - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); 1783 1783 + /* Keep some clocks always-on */ 1784 1784 + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ 1788 1785 1789 1786 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); 1790 1787 if (ret) ··· 1805 1808 }, 1806 1809 }; 1807 1810 1808 1808 - static int __init disp_cc_sm8550_init(void) 1809 1809 - { 1810 1810 - return platform_driver_register(&disp_cc_sm8550_driver); 1811 1811 - } 1812 1812 - subsys_initcall(disp_cc_sm8550_init); 1813 1813 - 1814 1814 - static void __exit disp_cc_sm8550_exit(void) 1815 1815 - { 1816 1816 - platform_driver_unregister(&disp_cc_sm8550_driver); 1817 1817 - } 1818 1818 - module_exit(disp_cc_sm8550_exit); 1811 1811 + module_platform_driver(disp_cc_sm8550_driver); 1819 1812 1820 1813 MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver"); 1821 1814 MODULE_LICENSE("GPL");

+3 -13

drivers/clk/qcom/dispcc-sm8650.c

reviewed

··· 1777 1777 /* Enable clock gating for MDP clocks */ 1778 1778 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1779 1779 1780 1780 - /* Keep clocks always enabled */ 1781 1781 - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */ 1780 1780 + /* Keep some clocks always-on */ 1781 1781 + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ 1782 1782 1783 1783 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap); 1784 1784 if (ret) ··· 1802 1802 }, 1803 1803 }; 1804 1804 1805 1805 - static int __init disp_cc_sm8650_init(void) 1806 1806 - { 1807 1807 - return platform_driver_register(&disp_cc_sm8650_driver); 1808 1808 - } 1809 1809 - subsys_initcall(disp_cc_sm8650_init); 1810 1810 - 1811 1811 - static void __exit disp_cc_sm8650_exit(void) 1812 1812 - { 1813 1813 - platform_driver_unregister(&disp_cc_sm8650_driver); 1814 1814 - } 1815 1815 - module_exit(disp_cc_sm8650_exit); 1805 1805 + module_platform_driver(disp_cc_sm8650_driver); 1816 1806 1817 1807 MODULE_DESCRIPTION("QTI DISPCC SM8650 Driver"); 1818 1808 MODULE_LICENSE("GPL");

+1718

drivers/clk/qcom/dispcc-x1e80100.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 + */ 5 5 + 6 6 + #include <linux/clk-provider.h> 7 7 + #include <linux/err.h> 8 8 + #include <linux/kernel.h> 9 9 + #include <linux/mod_devicetable.h> 10 10 + #include <linux/module.h> 11 11 + #include <linux/platform_device.h> 12 12 + #include <linux/pm_runtime.h> 13 13 + #include <linux/regmap.h> 14 14 + 15 15 + #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 16 16 + 17 17 + #include "common.h" 18 18 + #include "clk-alpha-pll.h" 19 19 + #include "clk-branch.h" 20 20 + #include "clk-pll.h" 21 21 + #include "clk-rcg.h" 22 22 + #include "clk-regmap.h" 23 23 + #include "clk-regmap-divider.h" 24 24 + #include "reset.h" 25 25 + #include "gdsc.h" 26 26 + 27 27 + /* Need to match the order of clocks in DT binding */ 28 28 + enum { 29 29 + DT_BI_TCXO, 30 30 + DT_BI_TCXO_AO, 31 31 + DT_AHB_CLK, 32 32 + DT_SLEEP_CLK, 33 33 + 34 34 + DT_DSI0_PHY_PLL_OUT_BYTECLK, 35 35 + DT_DSI0_PHY_PLL_OUT_DSICLK, 36 36 + DT_DSI1_PHY_PLL_OUT_BYTECLK, 37 37 + DT_DSI1_PHY_PLL_OUT_DSICLK, 38 38 + 39 39 + DT_DP0_PHY_PLL_LINK_CLK, 40 40 + DT_DP0_PHY_PLL_VCO_DIV_CLK, 41 41 + DT_DP1_PHY_PLL_LINK_CLK, 42 42 + DT_DP1_PHY_PLL_VCO_DIV_CLK, 43 43 + DT_DP2_PHY_PLL_LINK_CLK, 44 44 + DT_DP2_PHY_PLL_VCO_DIV_CLK, 45 45 + DT_DP3_PHY_PLL_LINK_CLK, 46 46 + DT_DP3_PHY_PLL_VCO_DIV_CLK, 47 47 + }; 48 48 + 49 49 + #define DISP_CC_MISC_CMD 0xF000 50 50 + 51 51 + enum { 52 52 + P_BI_TCXO, 53 53 + P_BI_TCXO_AO, 54 54 + P_DISP_CC_PLL0_OUT_MAIN, 55 55 + P_DISP_CC_PLL1_OUT_EVEN, 56 56 + P_DISP_CC_PLL1_OUT_MAIN, 57 57 + P_DP0_PHY_PLL_LINK_CLK, 58 58 + P_DP0_PHY_PLL_VCO_DIV_CLK, 59 59 + P_DP1_PHY_PLL_LINK_CLK, 60 60 + P_DP1_PHY_PLL_VCO_DIV_CLK, 61 61 + P_DP2_PHY_PLL_LINK_CLK, 62 62 + P_DP2_PHY_PLL_VCO_DIV_CLK, 63 63 + P_DP3_PHY_PLL_LINK_CLK, 64 64 + P_DP3_PHY_PLL_VCO_DIV_CLK, 65 65 + P_DSI0_PHY_PLL_OUT_BYTECLK, 66 66 + P_DSI0_PHY_PLL_OUT_DSICLK, 67 67 + P_DSI1_PHY_PLL_OUT_BYTECLK, 68 68 + P_DSI1_PHY_PLL_OUT_DSICLK, 69 69 + P_SLEEP_CLK, 70 70 + }; 71 71 + 72 72 + static const struct pll_vco lucid_ole_vco[] = { 73 73 + { 249600000, 2300000000, 0 }, 74 74 + }; 75 75 + 76 76 + static const struct alpha_pll_config disp_cc_pll0_config = { 77 77 + .l = 0xd, 78 78 + .alpha = 0x6492, 79 79 + .config_ctl_val = 0x20485699, 80 80 + .config_ctl_hi_val = 0x00182261, 81 81 + .config_ctl_hi1_val = 0x82aa299c, 82 82 + .test_ctl_val = 0x00000000, 83 83 + .test_ctl_hi_val = 0x00000003, 84 84 + .test_ctl_hi1_val = 0x00009000, 85 85 + .test_ctl_hi2_val = 0x00000034, 86 86 + .user_ctl_val = 0x00000000, 87 87 + .user_ctl_hi_val = 0x00000005, 88 88 + }; 89 89 + 90 90 + static struct clk_alpha_pll disp_cc_pll0 = { 91 91 + .offset = 0x0, 92 92 + .vco_table = lucid_ole_vco, 93 93 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 94 94 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 95 95 + .clkr = { 96 96 + .hw.init = &(const struct clk_init_data) { 97 97 + .name = "disp_cc_pll0", 98 98 + .parent_data = &(const struct clk_parent_data) { 99 99 + .index = DT_BI_TCXO, 100 100 + }, 101 101 + .num_parents = 1, 102 102 + .ops = &clk_alpha_pll_reset_lucid_ole_ops, 103 103 + }, 104 104 + }, 105 105 + }; 106 106 + 107 107 + static const struct alpha_pll_config disp_cc_pll1_config = { 108 108 + .l = 0x1f, 109 109 + .alpha = 0x4000, 110 110 + .config_ctl_val = 0x20485699, 111 111 + .config_ctl_hi_val = 0x00182261, 112 112 + .config_ctl_hi1_val = 0x82aa299c, 113 113 + .test_ctl_val = 0x00000000, 114 114 + .test_ctl_hi_val = 0x00000003, 115 115 + .test_ctl_hi1_val = 0x00009000, 116 116 + .test_ctl_hi2_val = 0x00000034, 117 117 + .user_ctl_val = 0x00000000, 118 118 + .user_ctl_hi_val = 0x00000005, 119 119 + }; 120 120 + 121 121 + static struct clk_alpha_pll disp_cc_pll1 = { 122 122 + .offset = 0x1000, 123 123 + .vco_table = lucid_ole_vco, 124 124 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 125 125 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 126 126 + .clkr = { 127 127 + .hw.init = &(const struct clk_init_data) { 128 128 + .name = "disp_cc_pll1", 129 129 + .parent_data = &(const struct clk_parent_data) { 130 130 + .index = DT_BI_TCXO, 131 131 + }, 132 132 + .num_parents = 1, 133 133 + .ops = &clk_alpha_pll_reset_lucid_ole_ops, 134 134 + }, 135 135 + }, 136 136 + }; 137 137 + 138 138 + static const struct parent_map disp_cc_parent_map_0[] = { 139 139 + { P_BI_TCXO, 0 }, 140 140 + { P_DP0_PHY_PLL_LINK_CLK, 1 }, 141 141 + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 142 142 + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 143 143 + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 144 144 + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 145 145 + }; 146 146 + 147 147 + static const struct clk_parent_data disp_cc_parent_data_0[] = { 148 148 + { .index = DT_BI_TCXO }, 149 149 + { .index = DT_DP0_PHY_PLL_LINK_CLK }, 150 150 + { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 151 151 + { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 152 152 + { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 153 153 + { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 154 154 + }; 155 155 + 156 156 + static const struct parent_map disp_cc_parent_map_1[] = { 157 157 + { P_BI_TCXO, 0 }, 158 158 + }; 159 159 + 160 160 + static const struct clk_parent_data disp_cc_parent_data_1[] = { 161 161 + { .index = DT_BI_TCXO }, 162 162 + }; 163 163 + 164 164 + static const struct clk_parent_data disp_cc_parent_data_1_ao[] = { 165 165 + { .index = DT_BI_TCXO_AO }, 166 166 + }; 167 167 + 168 168 + static const struct parent_map disp_cc_parent_map_2[] = { 169 169 + { P_BI_TCXO, 0 }, 170 170 + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 171 171 + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 172 172 + { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 173 173 + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 174 174 + }; 175 175 + 176 176 + static const struct clk_parent_data disp_cc_parent_data_2[] = { 177 177 + { .index = DT_BI_TCXO }, 178 178 + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 179 179 + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 180 180 + { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 181 181 + { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 182 182 + }; 183 183 + 184 184 + static const struct parent_map disp_cc_parent_map_3[] = { 185 185 + { P_BI_TCXO, 0 }, 186 186 + { P_DP0_PHY_PLL_LINK_CLK, 1 }, 187 187 + { P_DP1_PHY_PLL_LINK_CLK, 2 }, 188 188 + { P_DP2_PHY_PLL_LINK_CLK, 3 }, 189 189 + { P_DP3_PHY_PLL_LINK_CLK, 4 }, 190 190 + }; 191 191 + 192 192 + static const struct clk_parent_data disp_cc_parent_data_3[] = { 193 193 + { .index = DT_BI_TCXO }, 194 194 + { .index = DT_DP0_PHY_PLL_LINK_CLK }, 195 195 + { .index = DT_DP1_PHY_PLL_LINK_CLK }, 196 196 + { .index = DT_DP2_PHY_PLL_LINK_CLK }, 197 197 + { .index = DT_DP3_PHY_PLL_LINK_CLK }, 198 198 + }; 199 199 + 200 200 + static const struct parent_map disp_cc_parent_map_4[] = { 201 201 + { P_BI_TCXO, 0 }, 202 202 + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 203 203 + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 204 204 + }; 205 205 + 206 206 + static const struct clk_parent_data disp_cc_parent_data_4[] = { 207 207 + { .index = DT_BI_TCXO }, 208 208 + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 209 209 + { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 210 210 + }; 211 211 + 212 212 + static const struct parent_map disp_cc_parent_map_5[] = { 213 213 + { P_BI_TCXO, 0 }, 214 214 + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 215 215 + { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 216 216 + }; 217 217 + 218 218 + static const struct clk_parent_data disp_cc_parent_data_5[] = { 219 219 + { .index = DT_BI_TCXO }, 220 220 + { .hw = &disp_cc_pll1.clkr.hw }, 221 221 + { .hw = &disp_cc_pll1.clkr.hw }, 222 222 + }; 223 223 + 224 224 + static const struct parent_map disp_cc_parent_map_6[] = { 225 225 + { P_BI_TCXO, 0 }, 226 226 + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 227 227 + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 228 228 + { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 229 229 + }; 230 230 + 231 231 + static const struct clk_parent_data disp_cc_parent_data_6[] = { 232 232 + { .index = DT_BI_TCXO }, 233 233 + { .hw = &disp_cc_pll0.clkr.hw }, 234 234 + { .hw = &disp_cc_pll1.clkr.hw }, 235 235 + { .hw = &disp_cc_pll1.clkr.hw }, 236 236 + }; 237 237 + 238 238 + static const struct parent_map disp_cc_parent_map_7[] = { 239 239 + { P_SLEEP_CLK, 0 }, 240 240 + }; 241 241 + 242 242 + static const struct clk_parent_data disp_cc_parent_data_7[] = { 243 243 + { .index = DT_SLEEP_CLK }, 244 244 + }; 245 245 + 246 246 + static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 247 247 + F(19200000, P_BI_TCXO, 1, 0, 0), 248 248 + F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 249 249 + F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 250 250 + { } 251 251 + }; 252 252 + 253 253 + static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 254 254 + .cmd_rcgr = 0x82ec, 255 255 + .mnd_width = 0, 256 256 + .hid_width = 5, 257 257 + .parent_map = disp_cc_parent_map_5, 258 258 + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 259 259 + .clkr.hw.init = &(const struct clk_init_data) { 260 260 + .name = "disp_cc_mdss_ahb_clk_src", 261 261 + .parent_data = disp_cc_parent_data_5, 262 262 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 263 263 + .flags = CLK_SET_RATE_PARENT, 264 264 + .ops = &clk_rcg2_ops, 265 265 + }, 266 266 + }; 267 267 + 268 268 + static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 269 269 + F(19200000, P_BI_TCXO, 1, 0, 0), 270 270 + { } 271 271 + }; 272 272 + 273 273 + static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 274 274 + .cmd_rcgr = 0x810c, 275 275 + .mnd_width = 0, 276 276 + .hid_width = 5, 277 277 + .parent_map = disp_cc_parent_map_2, 278 278 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 279 279 + .clkr.hw.init = &(const struct clk_init_data) { 280 280 + .name = "disp_cc_mdss_byte0_clk_src", 281 281 + .parent_data = disp_cc_parent_data_2, 282 282 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 283 283 + .flags = CLK_SET_RATE_PARENT, 284 284 + .ops = &clk_byte2_ops, 285 285 + }, 286 286 + }; 287 287 + 288 288 + static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 289 289 + .cmd_rcgr = 0x8128, 290 290 + .mnd_width = 0, 291 291 + .hid_width = 5, 292 292 + .parent_map = disp_cc_parent_map_2, 293 293 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 294 294 + .clkr.hw.init = &(const struct clk_init_data) { 295 295 + .name = "disp_cc_mdss_byte1_clk_src", 296 296 + .parent_data = disp_cc_parent_data_2, 297 297 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 298 298 + .flags = CLK_SET_RATE_PARENT, 299 299 + .ops = &clk_byte2_ops, 300 300 + }, 301 301 + }; 302 302 + 303 303 + static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 304 304 + .cmd_rcgr = 0x81c0, 305 305 + .mnd_width = 0, 306 306 + .hid_width = 5, 307 307 + .parent_map = disp_cc_parent_map_1, 308 308 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 309 309 + .clkr.hw.init = &(const struct clk_init_data) { 310 310 + .name = "disp_cc_mdss_dptx0_aux_clk_src", 311 311 + .parent_data = disp_cc_parent_data_1, 312 312 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 313 313 + .flags = CLK_SET_RATE_PARENT, 314 314 + .ops = &clk_rcg2_ops, 315 315 + }, 316 316 + }; 317 317 + 318 318 + static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 319 319 + .cmd_rcgr = 0x8174, 320 320 + .mnd_width = 0, 321 321 + .hid_width = 5, 322 322 + .parent_map = disp_cc_parent_map_3, 323 323 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 324 324 + .clkr.hw.init = &(const struct clk_init_data) { 325 325 + .name = "disp_cc_mdss_dptx0_link_clk_src", 326 326 + .parent_data = disp_cc_parent_data_3, 327 327 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 328 328 + .flags = CLK_SET_RATE_PARENT, 329 329 + .ops = &clk_byte2_ops, 330 330 + }, 331 331 + }; 332 332 + 333 333 + static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 334 334 + .cmd_rcgr = 0x8190, 335 335 + .mnd_width = 16, 336 336 + .hid_width = 5, 337 337 + .parent_map = disp_cc_parent_map_0, 338 338 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 339 339 + .clkr.hw.init = &(const struct clk_init_data) { 340 340 + .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 341 341 + .parent_data = disp_cc_parent_data_0, 342 342 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 343 343 + .flags = CLK_SET_RATE_PARENT, 344 344 + .ops = &clk_dp_ops, 345 345 + }, 346 346 + }; 347 347 + 348 348 + static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 349 349 + .cmd_rcgr = 0x81a8, 350 350 + .mnd_width = 16, 351 351 + .hid_width = 5, 352 352 + .parent_map = disp_cc_parent_map_0, 353 353 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 354 354 + .clkr.hw.init = &(const struct clk_init_data) { 355 355 + .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 356 356 + .parent_data = disp_cc_parent_data_0, 357 357 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 358 358 + .flags = CLK_SET_RATE_PARENT, 359 359 + .ops = &clk_dp_ops, 360 360 + }, 361 361 + }; 362 362 + 363 363 + static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 364 364 + .cmd_rcgr = 0x8224, 365 365 + .mnd_width = 0, 366 366 + .hid_width = 5, 367 367 + .parent_map = disp_cc_parent_map_1, 368 368 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 369 369 + .clkr.hw.init = &(const struct clk_init_data) { 370 370 + .name = "disp_cc_mdss_dptx1_aux_clk_src", 371 371 + .parent_data = disp_cc_parent_data_1, 372 372 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 373 373 + .flags = CLK_SET_RATE_PARENT, 374 374 + .ops = &clk_rcg2_ops, 375 375 + }, 376 376 + }; 377 377 + 378 378 + static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 379 379 + .cmd_rcgr = 0x8208, 380 380 + .mnd_width = 0, 381 381 + .hid_width = 5, 382 382 + .parent_map = disp_cc_parent_map_3, 383 383 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 384 384 + .clkr.hw.init = &(const struct clk_init_data) { 385 385 + .name = "disp_cc_mdss_dptx1_link_clk_src", 386 386 + .parent_data = disp_cc_parent_data_3, 387 387 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 388 388 + .flags = CLK_SET_RATE_PARENT, 389 389 + .ops = &clk_byte2_ops, 390 390 + }, 391 391 + }; 392 392 + 393 393 + static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 394 394 + .cmd_rcgr = 0x81d8, 395 395 + .mnd_width = 16, 396 396 + .hid_width = 5, 397 397 + .parent_map = disp_cc_parent_map_0, 398 398 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 399 399 + .clkr.hw.init = &(const struct clk_init_data) { 400 400 + .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 401 401 + .parent_data = disp_cc_parent_data_0, 402 402 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 403 403 + .flags = CLK_SET_RATE_PARENT, 404 404 + .ops = &clk_dp_ops, 405 405 + }, 406 406 + }; 407 407 + 408 408 + static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 409 409 + .cmd_rcgr = 0x81f0, 410 410 + .mnd_width = 16, 411 411 + .hid_width = 5, 412 412 + .parent_map = disp_cc_parent_map_0, 413 413 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 414 414 + .clkr.hw.init = &(const struct clk_init_data) { 415 415 + .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 416 416 + .parent_data = disp_cc_parent_data_0, 417 417 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 418 418 + .flags = CLK_SET_RATE_PARENT, 419 419 + .ops = &clk_dp_ops, 420 420 + }, 421 421 + }; 422 422 + 423 423 + static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 424 424 + .cmd_rcgr = 0x8288, 425 425 + .mnd_width = 0, 426 426 + .hid_width = 5, 427 427 + .parent_map = disp_cc_parent_map_1, 428 428 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 429 429 + .clkr.hw.init = &(const struct clk_init_data) { 430 430 + .name = "disp_cc_mdss_dptx2_aux_clk_src", 431 431 + .parent_data = disp_cc_parent_data_1, 432 432 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 433 433 + .flags = CLK_SET_RATE_PARENT, 434 434 + .ops = &clk_rcg2_ops, 435 435 + }, 436 436 + }; 437 437 + 438 438 + static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 439 439 + .cmd_rcgr = 0x823c, 440 440 + .mnd_width = 0, 441 441 + .hid_width = 5, 442 442 + .parent_map = disp_cc_parent_map_3, 443 443 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 444 444 + .clkr.hw.init = &(const struct clk_init_data) { 445 445 + .name = "disp_cc_mdss_dptx2_link_clk_src", 446 446 + .parent_data = disp_cc_parent_data_3, 447 447 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 448 448 + .flags = CLK_SET_RATE_PARENT, 449 449 + .ops = &clk_byte2_ops, 450 450 + }, 451 451 + }; 452 452 + 453 453 + static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 454 454 + .cmd_rcgr = 0x8258, 455 455 + .mnd_width = 16, 456 456 + .hid_width = 5, 457 457 + .parent_map = disp_cc_parent_map_0, 458 458 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 459 459 + .clkr.hw.init = &(const struct clk_init_data) { 460 460 + .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 461 461 + .parent_data = disp_cc_parent_data_0, 462 462 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 463 463 + .flags = CLK_SET_RATE_PARENT, 464 464 + .ops = &clk_dp_ops, 465 465 + }, 466 466 + }; 467 467 + 468 468 + static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 469 469 + .cmd_rcgr = 0x8270, 470 470 + .mnd_width = 16, 471 471 + .hid_width = 5, 472 472 + .parent_map = disp_cc_parent_map_0, 473 473 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 474 474 + .clkr.hw.init = &(const struct clk_init_data) { 475 475 + .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 476 476 + .parent_data = disp_cc_parent_data_0, 477 477 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 478 478 + .flags = CLK_SET_RATE_PARENT, 479 479 + .ops = &clk_dp_ops, 480 480 + }, 481 481 + }; 482 482 + 483 483 + static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 484 484 + .cmd_rcgr = 0x82d4, 485 485 + .mnd_width = 0, 486 486 + .hid_width = 5, 487 487 + .parent_map = disp_cc_parent_map_1, 488 488 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 489 489 + .clkr.hw.init = &(const struct clk_init_data) { 490 490 + .name = "disp_cc_mdss_dptx3_aux_clk_src", 491 491 + .parent_data = disp_cc_parent_data_1, 492 492 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 493 493 + .flags = CLK_SET_RATE_PARENT, 494 494 + .ops = &clk_rcg2_ops, 495 495 + }, 496 496 + }; 497 497 + 498 498 + static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 499 499 + .cmd_rcgr = 0x82b8, 500 500 + .mnd_width = 0, 501 501 + .hid_width = 5, 502 502 + .parent_map = disp_cc_parent_map_3, 503 503 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 504 504 + .clkr.hw.init = &(const struct clk_init_data) { 505 505 + .name = "disp_cc_mdss_dptx3_link_clk_src", 506 506 + .parent_data = disp_cc_parent_data_3, 507 507 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 508 508 + .flags = CLK_SET_RATE_PARENT, 509 509 + .ops = &clk_byte2_ops, 510 510 + }, 511 511 + }; 512 512 + 513 513 + static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 514 514 + .cmd_rcgr = 0x82a0, 515 515 + .mnd_width = 16, 516 516 + .hid_width = 5, 517 517 + .parent_map = disp_cc_parent_map_0, 518 518 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 519 519 + .clkr.hw.init = &(const struct clk_init_data) { 520 520 + .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 521 521 + .parent_data = disp_cc_parent_data_0, 522 522 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 523 523 + .flags = CLK_SET_RATE_PARENT, 524 524 + .ops = &clk_dp_ops, 525 525 + }, 526 526 + }; 527 527 + 528 528 + static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 529 529 + .cmd_rcgr = 0x8144, 530 530 + .mnd_width = 0, 531 531 + .hid_width = 5, 532 532 + .parent_map = disp_cc_parent_map_4, 533 533 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 534 534 + .clkr.hw.init = &(const struct clk_init_data) { 535 535 + .name = "disp_cc_mdss_esc0_clk_src", 536 536 + .parent_data = disp_cc_parent_data_4, 537 537 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 538 538 + .flags = CLK_SET_RATE_PARENT, 539 539 + .ops = &clk_rcg2_ops, 540 540 + }, 541 541 + }; 542 542 + 543 543 + static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 544 544 + .cmd_rcgr = 0x815c, 545 545 + .mnd_width = 0, 546 546 + .hid_width = 5, 547 547 + .parent_map = disp_cc_parent_map_4, 548 548 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 549 549 + .clkr.hw.init = &(const struct clk_init_data) { 550 550 + .name = "disp_cc_mdss_esc1_clk_src", 551 551 + .parent_data = disp_cc_parent_data_4, 552 552 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 553 553 + .flags = CLK_SET_RATE_PARENT, 554 554 + .ops = &clk_rcg2_ops, 555 555 + }, 556 556 + }; 557 557 + 558 558 + static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 559 559 + F(19200000, P_BI_TCXO, 1, 0, 0), 560 560 + F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 561 561 + F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 562 562 + F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 563 563 + F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 564 564 + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 565 565 + F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 566 566 + F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 567 567 + F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 568 568 + F(575000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 569 569 + { } 570 570 + }; 571 571 + 572 572 + static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 573 573 + .cmd_rcgr = 0x80dc, 574 574 + .mnd_width = 0, 575 575 + .hid_width = 5, 576 576 + .parent_map = disp_cc_parent_map_6, 577 577 + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 578 578 + .clkr.hw.init = &(const struct clk_init_data) { 579 579 + .name = "disp_cc_mdss_mdp_clk_src", 580 580 + .parent_data = disp_cc_parent_data_6, 581 581 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 582 582 + .flags = CLK_SET_RATE_PARENT, 583 583 + .ops = &clk_rcg2_shared_ops, 584 584 + }, 585 585 + }; 586 586 + 587 587 + static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 588 588 + .cmd_rcgr = 0x80ac, 589 589 + .mnd_width = 8, 590 590 + .hid_width = 5, 591 591 + .parent_map = disp_cc_parent_map_2, 592 592 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 593 593 + .clkr.hw.init = &(const struct clk_init_data) { 594 594 + .name = "disp_cc_mdss_pclk0_clk_src", 595 595 + .parent_data = disp_cc_parent_data_2, 596 596 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 597 597 + .flags = CLK_SET_RATE_PARENT, 598 598 + .ops = &clk_pixel_ops, 599 599 + }, 600 600 + }; 601 601 + 602 602 + static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 603 603 + .cmd_rcgr = 0x80c4, 604 604 + .mnd_width = 8, 605 605 + .hid_width = 5, 606 606 + .parent_map = disp_cc_parent_map_2, 607 607 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 608 608 + .clkr.hw.init = &(const struct clk_init_data) { 609 609 + .name = "disp_cc_mdss_pclk1_clk_src", 610 610 + .parent_data = disp_cc_parent_data_2, 611 611 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 612 612 + .flags = CLK_SET_RATE_PARENT, 613 613 + .ops = &clk_pixel_ops, 614 614 + }, 615 615 + }; 616 616 + 617 617 + static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 618 618 + .cmd_rcgr = 0x80f4, 619 619 + .mnd_width = 0, 620 620 + .hid_width = 5, 621 621 + .parent_map = disp_cc_parent_map_1, 622 622 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 623 623 + .clkr.hw.init = &(const struct clk_init_data) { 624 624 + .name = "disp_cc_mdss_vsync_clk_src", 625 625 + .parent_data = disp_cc_parent_data_1, 626 626 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 627 627 + .flags = CLK_SET_RATE_PARENT, 628 628 + .ops = &clk_rcg2_ops, 629 629 + }, 630 630 + }; 631 631 + 632 632 + static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 633 633 + F(32000, P_SLEEP_CLK, 1, 0, 0), 634 634 + { } 635 635 + }; 636 636 + 637 637 + static struct clk_rcg2 disp_cc_sleep_clk_src = { 638 638 + .cmd_rcgr = 0xe05c, 639 639 + .mnd_width = 0, 640 640 + .hid_width = 5, 641 641 + .parent_map = disp_cc_parent_map_7, 642 642 + .freq_tbl = ftbl_disp_cc_sleep_clk_src, 643 643 + .clkr.hw.init = &(const struct clk_init_data) { 644 644 + .name = "disp_cc_sleep_clk_src", 645 645 + .parent_data = disp_cc_parent_data_7, 646 646 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 647 647 + .flags = CLK_SET_RATE_PARENT, 648 648 + .ops = &clk_rcg2_ops, 649 649 + }, 650 650 + }; 651 651 + 652 652 + static struct clk_rcg2 disp_cc_xo_clk_src = { 653 653 + .cmd_rcgr = 0xe03c, 654 654 + .mnd_width = 0, 655 655 + .hid_width = 5, 656 656 + .parent_map = disp_cc_parent_map_1, 657 657 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 658 658 + .clkr.hw.init = &(const struct clk_init_data) { 659 659 + .name = "disp_cc_xo_clk_src", 660 660 + .parent_data = disp_cc_parent_data_1_ao, 661 661 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao), 662 662 + .flags = CLK_SET_RATE_PARENT, 663 663 + .ops = &clk_rcg2_ops, 664 664 + }, 665 665 + }; 666 666 + 667 667 + static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 668 668 + .reg = 0x8124, 669 669 + .shift = 0, 670 670 + .width = 4, 671 671 + .clkr.hw.init = &(const struct clk_init_data) { 672 672 + .name = "disp_cc_mdss_byte0_div_clk_src", 673 673 + .parent_hws = (const struct clk_hw*[]) { 674 674 + &disp_cc_mdss_byte0_clk_src.clkr.hw, 675 675 + }, 676 676 + .num_parents = 1, 677 677 + .flags = CLK_SET_RATE_PARENT, 678 678 + .ops = &clk_regmap_div_ro_ops, 679 679 + }, 680 680 + }; 681 681 + 682 682 + static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 683 683 + .reg = 0x8140, 684 684 + .shift = 0, 685 685 + .width = 4, 686 686 + .clkr.hw.init = &(const struct clk_init_data) { 687 687 + .name = "disp_cc_mdss_byte1_div_clk_src", 688 688 + .parent_hws = (const struct clk_hw*[]) { 689 689 + &disp_cc_mdss_byte1_clk_src.clkr.hw, 690 690 + }, 691 691 + .num_parents = 1, 692 692 + .flags = CLK_SET_RATE_PARENT, 693 693 + .ops = &clk_regmap_div_ro_ops, 694 694 + }, 695 695 + }; 696 696 + 697 697 + static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 698 698 + .reg = 0x818c, 699 699 + .shift = 0, 700 700 + .width = 4, 701 701 + .clkr.hw.init = &(const struct clk_init_data) { 702 702 + .name = "disp_cc_mdss_dptx0_link_div_clk_src", 703 703 + .parent_hws = (const struct clk_hw*[]) { 704 704 + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 705 705 + }, 706 706 + .num_parents = 1, 707 707 + .flags = CLK_SET_RATE_PARENT, 708 708 + .ops = &clk_regmap_div_ro_ops, 709 709 + }, 710 710 + }; 711 711 + 712 712 + static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 713 713 + .reg = 0x8220, 714 714 + .shift = 0, 715 715 + .width = 4, 716 716 + .clkr.hw.init = &(const struct clk_init_data) { 717 717 + .name = "disp_cc_mdss_dptx1_link_div_clk_src", 718 718 + .parent_hws = (const struct clk_hw*[]) { 719 719 + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 720 720 + }, 721 721 + .num_parents = 1, 722 722 + .flags = CLK_SET_RATE_PARENT, 723 723 + .ops = &clk_regmap_div_ro_ops, 724 724 + }, 725 725 + }; 726 726 + 727 727 + static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 728 728 + .reg = 0x8254, 729 729 + .shift = 0, 730 730 + .width = 4, 731 731 + .clkr.hw.init = &(const struct clk_init_data) { 732 732 + .name = "disp_cc_mdss_dptx2_link_div_clk_src", 733 733 + .parent_hws = (const struct clk_hw*[]) { 734 734 + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 735 735 + }, 736 736 + .num_parents = 1, 737 737 + .flags = CLK_SET_RATE_PARENT, 738 738 + .ops = &clk_regmap_div_ro_ops, 739 739 + }, 740 740 + }; 741 741 + 742 742 + static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 743 743 + .reg = 0x82d0, 744 744 + .shift = 0, 745 745 + .width = 4, 746 746 + .clkr.hw.init = &(const struct clk_init_data) { 747 747 + .name = "disp_cc_mdss_dptx3_link_div_clk_src", 748 748 + .parent_hws = (const struct clk_hw*[]) { 749 749 + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 750 750 + }, 751 751 + .num_parents = 1, 752 752 + .flags = CLK_SET_RATE_PARENT, 753 753 + .ops = &clk_regmap_div_ro_ops, 754 754 + }, 755 755 + }; 756 756 + 757 757 + static struct clk_branch disp_cc_mdss_accu_clk = { 758 758 + .halt_reg = 0xe058, 759 759 + .halt_check = BRANCH_HALT_VOTED, 760 760 + .clkr = { 761 761 + .enable_reg = 0xe058, 762 762 + .enable_mask = BIT(0), 763 763 + .hw.init = &(const struct clk_init_data) { 764 764 + .name = "disp_cc_mdss_accu_clk", 765 765 + .parent_hws = (const struct clk_hw*[]) { 766 766 + &disp_cc_xo_clk_src.clkr.hw, 767 767 + }, 768 768 + .num_parents = 1, 769 769 + .flags = CLK_SET_RATE_PARENT, 770 770 + .ops = &clk_branch2_ops, 771 771 + }, 772 772 + }, 773 773 + }; 774 774 + 775 775 + static struct clk_branch disp_cc_mdss_ahb1_clk = { 776 776 + .halt_reg = 0xa020, 777 777 + .halt_check = BRANCH_HALT, 778 778 + .clkr = { 779 779 + .enable_reg = 0xa020, 780 780 + .enable_mask = BIT(0), 781 781 + .hw.init = &(const struct clk_init_data) { 782 782 + .name = "disp_cc_mdss_ahb1_clk", 783 783 + .parent_hws = (const struct clk_hw*[]) { 784 784 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 785 785 + }, 786 786 + .num_parents = 1, 787 787 + .flags = CLK_SET_RATE_PARENT, 788 788 + .ops = &clk_branch2_ops, 789 789 + }, 790 790 + }, 791 791 + }; 792 792 + 793 793 + static struct clk_branch disp_cc_mdss_ahb_clk = { 794 794 + .halt_reg = 0x80a8, 795 795 + .halt_check = BRANCH_HALT, 796 796 + .clkr = { 797 797 + .enable_reg = 0x80a8, 798 798 + .enable_mask = BIT(0), 799 799 + .hw.init = &(const struct clk_init_data) { 800 800 + .name = "disp_cc_mdss_ahb_clk", 801 801 + .parent_hws = (const struct clk_hw*[]) { 802 802 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 803 803 + }, 804 804 + .num_parents = 1, 805 805 + .flags = CLK_SET_RATE_PARENT, 806 806 + .ops = &clk_branch2_ops, 807 807 + }, 808 808 + }, 809 809 + }; 810 810 + 811 811 + static struct clk_branch disp_cc_mdss_byte0_clk = { 812 812 + .halt_reg = 0x8028, 813 813 + .halt_check = BRANCH_HALT, 814 814 + .clkr = { 815 815 + .enable_reg = 0x8028, 816 816 + .enable_mask = BIT(0), 817 817 + .hw.init = &(const struct clk_init_data) { 818 818 + .name = "disp_cc_mdss_byte0_clk", 819 819 + .parent_hws = (const struct clk_hw*[]) { 820 820 + &disp_cc_mdss_byte0_clk_src.clkr.hw, 821 821 + }, 822 822 + .num_parents = 1, 823 823 + .flags = CLK_SET_RATE_PARENT, 824 824 + .ops = &clk_branch2_ops, 825 825 + }, 826 826 + }, 827 827 + }; 828 828 + 829 829 + static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 830 830 + .halt_reg = 0x802c, 831 831 + .halt_check = BRANCH_HALT, 832 832 + .clkr = { 833 833 + .enable_reg = 0x802c, 834 834 + .enable_mask = BIT(0), 835 835 + .hw.init = &(const struct clk_init_data) { 836 836 + .name = "disp_cc_mdss_byte0_intf_clk", 837 837 + .parent_hws = (const struct clk_hw*[]) { 838 838 + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 839 839 + }, 840 840 + .num_parents = 1, 841 841 + .flags = CLK_SET_RATE_PARENT, 842 842 + .ops = &clk_branch2_ops, 843 843 + }, 844 844 + }, 845 845 + }; 846 846 + 847 847 + static struct clk_branch disp_cc_mdss_byte1_clk = { 848 848 + .halt_reg = 0x8030, 849 849 + .halt_check = BRANCH_HALT, 850 850 + .clkr = { 851 851 + .enable_reg = 0x8030, 852 852 + .enable_mask = BIT(0), 853 853 + .hw.init = &(const struct clk_init_data) { 854 854 + .name = "disp_cc_mdss_byte1_clk", 855 855 + .parent_hws = (const struct clk_hw*[]) { 856 856 + &disp_cc_mdss_byte1_clk_src.clkr.hw, 857 857 + }, 858 858 + .num_parents = 1, 859 859 + .flags = CLK_SET_RATE_PARENT, 860 860 + .ops = &clk_branch2_ops, 861 861 + }, 862 862 + }, 863 863 + }; 864 864 + 865 865 + static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 866 866 + .halt_reg = 0x8034, 867 867 + .halt_check = BRANCH_HALT, 868 868 + .clkr = { 869 869 + .enable_reg = 0x8034, 870 870 + .enable_mask = BIT(0), 871 871 + .hw.init = &(const struct clk_init_data) { 872 872 + .name = "disp_cc_mdss_byte1_intf_clk", 873 873 + .parent_hws = (const struct clk_hw*[]) { 874 874 + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 875 875 + }, 876 876 + .num_parents = 1, 877 877 + .flags = CLK_SET_RATE_PARENT, 878 878 + .ops = &clk_branch2_ops, 879 879 + }, 880 880 + }, 881 881 + }; 882 882 + 883 883 + static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 884 884 + .halt_reg = 0x8058, 885 885 + .halt_check = BRANCH_HALT, 886 886 + .clkr = { 887 887 + .enable_reg = 0x8058, 888 888 + .enable_mask = BIT(0), 889 889 + .hw.init = &(const struct clk_init_data) { 890 890 + .name = "disp_cc_mdss_dptx0_aux_clk", 891 891 + .parent_hws = (const struct clk_hw*[]) { 892 892 + &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 893 893 + }, 894 894 + .num_parents = 1, 895 895 + .flags = CLK_SET_RATE_PARENT, 896 896 + .ops = &clk_branch2_ops, 897 897 + }, 898 898 + }, 899 899 + }; 900 900 + 901 901 + static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 902 902 + .halt_reg = 0x8040, 903 903 + .halt_check = BRANCH_HALT, 904 904 + .clkr = { 905 905 + .enable_reg = 0x8040, 906 906 + .enable_mask = BIT(0), 907 907 + .hw.init = &(const struct clk_init_data) { 908 908 + .name = "disp_cc_mdss_dptx0_link_clk", 909 909 + .parent_hws = (const struct clk_hw*[]) { 910 910 + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 911 911 + }, 912 912 + .num_parents = 1, 913 913 + .flags = CLK_SET_RATE_PARENT, 914 914 + .ops = &clk_branch2_ops, 915 915 + }, 916 916 + }, 917 917 + }; 918 918 + 919 919 + static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 920 920 + .halt_reg = 0x8048, 921 921 + .halt_check = BRANCH_HALT, 922 922 + .clkr = { 923 923 + .enable_reg = 0x8048, 924 924 + .enable_mask = BIT(0), 925 925 + .hw.init = &(const struct clk_init_data) { 926 926 + .name = "disp_cc_mdss_dptx0_link_intf_clk", 927 927 + .parent_hws = (const struct clk_hw*[]) { 928 928 + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 929 929 + }, 930 930 + .num_parents = 1, 931 931 + .flags = CLK_SET_RATE_PARENT, 932 932 + .ops = &clk_branch2_ops, 933 933 + }, 934 934 + }, 935 935 + }; 936 936 + 937 937 + static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 938 938 + .halt_reg = 0x8050, 939 939 + .halt_check = BRANCH_HALT, 940 940 + .clkr = { 941 941 + .enable_reg = 0x8050, 942 942 + .enable_mask = BIT(0), 943 943 + .hw.init = &(const struct clk_init_data) { 944 944 + .name = "disp_cc_mdss_dptx0_pixel0_clk", 945 945 + .parent_hws = (const struct clk_hw*[]) { 946 946 + &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 947 947 + }, 948 948 + .num_parents = 1, 949 949 + .flags = CLK_SET_RATE_PARENT, 950 950 + .ops = &clk_branch2_ops, 951 951 + }, 952 952 + }, 953 953 + }; 954 954 + 955 955 + static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 956 956 + .halt_reg = 0x8054, 957 957 + .halt_check = BRANCH_HALT, 958 958 + .clkr = { 959 959 + .enable_reg = 0x8054, 960 960 + .enable_mask = BIT(0), 961 961 + .hw.init = &(const struct clk_init_data) { 962 962 + .name = "disp_cc_mdss_dptx0_pixel1_clk", 963 963 + .parent_hws = (const struct clk_hw*[]) { 964 964 + &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 965 965 + }, 966 966 + .num_parents = 1, 967 967 + .flags = CLK_SET_RATE_PARENT, 968 968 + .ops = &clk_branch2_ops, 969 969 + }, 970 970 + }, 971 971 + }; 972 972 + 973 973 + static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 974 974 + .halt_reg = 0x8044, 975 975 + .halt_check = BRANCH_HALT, 976 976 + .clkr = { 977 977 + .enable_reg = 0x8044, 978 978 + .enable_mask = BIT(0), 979 979 + .hw.init = &(const struct clk_init_data) { 980 980 + .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 981 981 + .parent_hws = (const struct clk_hw*[]) { 982 982 + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 983 983 + }, 984 984 + .num_parents = 1, 985 985 + .flags = CLK_SET_RATE_PARENT, 986 986 + .ops = &clk_branch2_ops, 987 987 + }, 988 988 + }, 989 989 + }; 990 990 + 991 991 + static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 992 992 + .halt_reg = 0x8074, 993 993 + .halt_check = BRANCH_HALT, 994 994 + .clkr = { 995 995 + .enable_reg = 0x8074, 996 996 + .enable_mask = BIT(0), 997 997 + .hw.init = &(const struct clk_init_data) { 998 998 + .name = "disp_cc_mdss_dptx1_aux_clk", 999 999 + .parent_hws = (const struct clk_hw*[]) { 1000 1000 + &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1001 1001 + }, 1002 1002 + .num_parents = 1, 1003 1003 + .flags = CLK_SET_RATE_PARENT, 1004 1004 + .ops = &clk_branch2_ops, 1005 1005 + }, 1006 1006 + }, 1007 1007 + }; 1008 1008 + 1009 1009 + static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1010 1010 + .halt_reg = 0x8064, 1011 1011 + .halt_check = BRANCH_HALT, 1012 1012 + .clkr = { 1013 1013 + .enable_reg = 0x8064, 1014 1014 + .enable_mask = BIT(0), 1015 1015 + .hw.init = &(const struct clk_init_data) { 1016 1016 + .name = "disp_cc_mdss_dptx1_link_clk", 1017 1017 + .parent_hws = (const struct clk_hw*[]) { 1018 1018 + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1019 1019 + }, 1020 1020 + .num_parents = 1, 1021 1021 + .flags = CLK_SET_RATE_PARENT, 1022 1022 + .ops = &clk_branch2_ops, 1023 1023 + }, 1024 1024 + }, 1025 1025 + }; 1026 1026 + 1027 1027 + static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1028 1028 + .halt_reg = 0x806c, 1029 1029 + .halt_check = BRANCH_HALT, 1030 1030 + .clkr = { 1031 1031 + .enable_reg = 0x806c, 1032 1032 + .enable_mask = BIT(0), 1033 1033 + .hw.init = &(const struct clk_init_data) { 1034 1034 + .name = "disp_cc_mdss_dptx1_link_intf_clk", 1035 1035 + .parent_hws = (const struct clk_hw*[]) { 1036 1036 + &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1037 1037 + }, 1038 1038 + .num_parents = 1, 1039 1039 + .flags = CLK_SET_RATE_PARENT, 1040 1040 + .ops = &clk_branch2_ops, 1041 1041 + }, 1042 1042 + }, 1043 1043 + }; 1044 1044 + 1045 1045 + static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1046 1046 + .halt_reg = 0x805c, 1047 1047 + .halt_check = BRANCH_HALT, 1048 1048 + .clkr = { 1049 1049 + .enable_reg = 0x805c, 1050 1050 + .enable_mask = BIT(0), 1051 1051 + .hw.init = &(const struct clk_init_data) { 1052 1052 + .name = "disp_cc_mdss_dptx1_pixel0_clk", 1053 1053 + .parent_hws = (const struct clk_hw*[]) { 1054 1054 + &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1055 1055 + }, 1056 1056 + .num_parents = 1, 1057 1057 + .flags = CLK_SET_RATE_PARENT, 1058 1058 + .ops = &clk_branch2_ops, 1059 1059 + }, 1060 1060 + }, 1061 1061 + }; 1062 1062 + 1063 1063 + static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1064 1064 + .halt_reg = 0x8060, 1065 1065 + .halt_check = BRANCH_HALT, 1066 1066 + .clkr = { 1067 1067 + .enable_reg = 0x8060, 1068 1068 + .enable_mask = BIT(0), 1069 1069 + .hw.init = &(const struct clk_init_data) { 1070 1070 + .name = "disp_cc_mdss_dptx1_pixel1_clk", 1071 1071 + .parent_hws = (const struct clk_hw*[]) { 1072 1072 + &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1073 1073 + }, 1074 1074 + .num_parents = 1, 1075 1075 + .flags = CLK_SET_RATE_PARENT, 1076 1076 + .ops = &clk_branch2_ops, 1077 1077 + }, 1078 1078 + }, 1079 1079 + }; 1080 1080 + 1081 1081 + static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1082 1082 + .halt_reg = 0x8068, 1083 1083 + .halt_check = BRANCH_HALT, 1084 1084 + .clkr = { 1085 1085 + .enable_reg = 0x8068, 1086 1086 + .enable_mask = BIT(0), 1087 1087 + .hw.init = &(const struct clk_init_data) { 1088 1088 + .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1089 1089 + .parent_hws = (const struct clk_hw*[]) { 1090 1090 + &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1091 1091 + }, 1092 1092 + .num_parents = 1, 1093 1093 + .flags = CLK_SET_RATE_PARENT, 1094 1094 + .ops = &clk_branch2_ops, 1095 1095 + }, 1096 1096 + }, 1097 1097 + }; 1098 1098 + 1099 1099 + static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1100 1100 + .halt_reg = 0x8090, 1101 1101 + .halt_check = BRANCH_HALT, 1102 1102 + .clkr = { 1103 1103 + .enable_reg = 0x8090, 1104 1104 + .enable_mask = BIT(0), 1105 1105 + .hw.init = &(const struct clk_init_data) { 1106 1106 + .name = "disp_cc_mdss_dptx2_aux_clk", 1107 1107 + .parent_hws = (const struct clk_hw*[]) { 1108 1108 + &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1109 1109 + }, 1110 1110 + .num_parents = 1, 1111 1111 + .flags = CLK_SET_RATE_PARENT, 1112 1112 + .ops = &clk_branch2_ops, 1113 1113 + }, 1114 1114 + }, 1115 1115 + }; 1116 1116 + 1117 1117 + static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1118 1118 + .halt_reg = 0x8080, 1119 1119 + .halt_check = BRANCH_HALT, 1120 1120 + .clkr = { 1121 1121 + .enable_reg = 0x8080, 1122 1122 + .enable_mask = BIT(0), 1123 1123 + .hw.init = &(const struct clk_init_data) { 1124 1124 + .name = "disp_cc_mdss_dptx2_link_clk", 1125 1125 + .parent_hws = (const struct clk_hw*[]) { 1126 1126 + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1127 1127 + }, 1128 1128 + .num_parents = 1, 1129 1129 + .flags = CLK_SET_RATE_PARENT, 1130 1130 + .ops = &clk_branch2_ops, 1131 1131 + }, 1132 1132 + }, 1133 1133 + }; 1134 1134 + 1135 1135 + static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1136 1136 + .halt_reg = 0x8084, 1137 1137 + .halt_check = BRANCH_HALT, 1138 1138 + .clkr = { 1139 1139 + .enable_reg = 0x8084, 1140 1140 + .enable_mask = BIT(0), 1141 1141 + .hw.init = &(const struct clk_init_data) { 1142 1142 + .name = "disp_cc_mdss_dptx2_link_intf_clk", 1143 1143 + .parent_hws = (const struct clk_hw*[]) { 1144 1144 + &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1145 1145 + }, 1146 1146 + .num_parents = 1, 1147 1147 + .flags = CLK_SET_RATE_PARENT, 1148 1148 + .ops = &clk_branch2_ops, 1149 1149 + }, 1150 1150 + }, 1151 1151 + }; 1152 1152 + 1153 1153 + static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1154 1154 + .halt_reg = 0x8078, 1155 1155 + .halt_check = BRANCH_HALT, 1156 1156 + .clkr = { 1157 1157 + .enable_reg = 0x8078, 1158 1158 + .enable_mask = BIT(0), 1159 1159 + .hw.init = &(const struct clk_init_data) { 1160 1160 + .name = "disp_cc_mdss_dptx2_pixel0_clk", 1161 1161 + .parent_hws = (const struct clk_hw*[]) { 1162 1162 + &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1163 1163 + }, 1164 1164 + .num_parents = 1, 1165 1165 + .flags = CLK_SET_RATE_PARENT, 1166 1166 + .ops = &clk_branch2_ops, 1167 1167 + }, 1168 1168 + }, 1169 1169 + }; 1170 1170 + 1171 1171 + static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1172 1172 + .halt_reg = 0x807c, 1173 1173 + .halt_check = BRANCH_HALT, 1174 1174 + .clkr = { 1175 1175 + .enable_reg = 0x807c, 1176 1176 + .enable_mask = BIT(0), 1177 1177 + .hw.init = &(const struct clk_init_data) { 1178 1178 + .name = "disp_cc_mdss_dptx2_pixel1_clk", 1179 1179 + .parent_hws = (const struct clk_hw*[]) { 1180 1180 + &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1181 1181 + }, 1182 1182 + .num_parents = 1, 1183 1183 + .flags = CLK_SET_RATE_PARENT, 1184 1184 + .ops = &clk_branch2_ops, 1185 1185 + }, 1186 1186 + }, 1187 1187 + }; 1188 1188 + 1189 1189 + static struct clk_branch disp_cc_mdss_dptx2_usb_router_link_intf_clk = { 1190 1190 + .halt_reg = 0x8088, 1191 1191 + .halt_check = BRANCH_HALT, 1192 1192 + .clkr = { 1193 1193 + .enable_reg = 0x8088, 1194 1194 + .enable_mask = BIT(0), 1195 1195 + .hw.init = &(const struct clk_init_data) { 1196 1196 + .name = "disp_cc_mdss_dptx2_usb_router_link_intf_clk", 1197 1197 + .parent_hws = (const struct clk_hw*[]) { 1198 1198 + &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1199 1199 + }, 1200 1200 + .num_parents = 1, 1201 1201 + .flags = CLK_SET_RATE_PARENT, 1202 1202 + .ops = &clk_branch2_ops, 1203 1203 + }, 1204 1204 + }, 1205 1205 + }; 1206 1206 + 1207 1207 + static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1208 1208 + .halt_reg = 0x80a0, 1209 1209 + .halt_check = BRANCH_HALT, 1210 1210 + .clkr = { 1211 1211 + .enable_reg = 0x80a0, 1212 1212 + .enable_mask = BIT(0), 1213 1213 + .hw.init = &(const struct clk_init_data) { 1214 1214 + .name = "disp_cc_mdss_dptx3_aux_clk", 1215 1215 + .parent_hws = (const struct clk_hw*[]) { 1216 1216 + &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1217 1217 + }, 1218 1218 + .num_parents = 1, 1219 1219 + .flags = CLK_SET_RATE_PARENT, 1220 1220 + .ops = &clk_branch2_ops, 1221 1221 + }, 1222 1222 + }, 1223 1223 + }; 1224 1224 + 1225 1225 + static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1226 1226 + .halt_reg = 0x8098, 1227 1227 + .halt_check = BRANCH_HALT, 1228 1228 + .clkr = { 1229 1229 + .enable_reg = 0x8098, 1230 1230 + .enable_mask = BIT(0), 1231 1231 + .hw.init = &(const struct clk_init_data) { 1232 1232 + .name = "disp_cc_mdss_dptx3_link_clk", 1233 1233 + .parent_hws = (const struct clk_hw*[]) { 1234 1234 + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1235 1235 + }, 1236 1236 + .num_parents = 1, 1237 1237 + .flags = CLK_SET_RATE_PARENT, 1238 1238 + .ops = &clk_branch2_ops, 1239 1239 + }, 1240 1240 + }, 1241 1241 + }; 1242 1242 + 1243 1243 + static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1244 1244 + .halt_reg = 0x809c, 1245 1245 + .halt_check = BRANCH_HALT, 1246 1246 + .clkr = { 1247 1247 + .enable_reg = 0x809c, 1248 1248 + .enable_mask = BIT(0), 1249 1249 + .hw.init = &(const struct clk_init_data) { 1250 1250 + .name = "disp_cc_mdss_dptx3_link_intf_clk", 1251 1251 + .parent_hws = (const struct clk_hw*[]) { 1252 1252 + &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1253 1253 + }, 1254 1254 + .num_parents = 1, 1255 1255 + .flags = CLK_SET_RATE_PARENT, 1256 1256 + .ops = &clk_branch2_ops, 1257 1257 + }, 1258 1258 + }, 1259 1259 + }; 1260 1260 + 1261 1261 + static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1262 1262 + .halt_reg = 0x8094, 1263 1263 + .halt_check = BRANCH_HALT, 1264 1264 + .clkr = { 1265 1265 + .enable_reg = 0x8094, 1266 1266 + .enable_mask = BIT(0), 1267 1267 + .hw.init = &(const struct clk_init_data) { 1268 1268 + .name = "disp_cc_mdss_dptx3_pixel0_clk", 1269 1269 + .parent_hws = (const struct clk_hw*[]) { 1270 1270 + &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1271 1271 + }, 1272 1272 + .num_parents = 1, 1273 1273 + .flags = CLK_SET_RATE_PARENT, 1274 1274 + .ops = &clk_branch2_ops, 1275 1275 + }, 1276 1276 + }, 1277 1277 + }; 1278 1278 + 1279 1279 + static struct clk_branch disp_cc_mdss_esc0_clk = { 1280 1280 + .halt_reg = 0x8038, 1281 1281 + .halt_check = BRANCH_HALT, 1282 1282 + .clkr = { 1283 1283 + .enable_reg = 0x8038, 1284 1284 + .enable_mask = BIT(0), 1285 1285 + .hw.init = &(const struct clk_init_data) { 1286 1286 + .name = "disp_cc_mdss_esc0_clk", 1287 1287 + .parent_hws = (const struct clk_hw*[]) { 1288 1288 + &disp_cc_mdss_esc0_clk_src.clkr.hw, 1289 1289 + }, 1290 1290 + .num_parents = 1, 1291 1291 + .flags = CLK_SET_RATE_PARENT, 1292 1292 + .ops = &clk_branch2_ops, 1293 1293 + }, 1294 1294 + }, 1295 1295 + }; 1296 1296 + 1297 1297 + static struct clk_branch disp_cc_mdss_esc1_clk = { 1298 1298 + .halt_reg = 0x803c, 1299 1299 + .halt_check = BRANCH_HALT, 1300 1300 + .clkr = { 1301 1301 + .enable_reg = 0x803c, 1302 1302 + .enable_mask = BIT(0), 1303 1303 + .hw.init = &(const struct clk_init_data) { 1304 1304 + .name = "disp_cc_mdss_esc1_clk", 1305 1305 + .parent_hws = (const struct clk_hw*[]) { 1306 1306 + &disp_cc_mdss_esc1_clk_src.clkr.hw, 1307 1307 + }, 1308 1308 + .num_parents = 1, 1309 1309 + .flags = CLK_SET_RATE_PARENT, 1310 1310 + .ops = &clk_branch2_ops, 1311 1311 + }, 1312 1312 + }, 1313 1313 + }; 1314 1314 + 1315 1315 + static struct clk_branch disp_cc_mdss_mdp1_clk = { 1316 1316 + .halt_reg = 0xa004, 1317 1317 + .halt_check = BRANCH_HALT, 1318 1318 + .clkr = { 1319 1319 + .enable_reg = 0xa004, 1320 1320 + .enable_mask = BIT(0), 1321 1321 + .hw.init = &(const struct clk_init_data) { 1322 1322 + .name = "disp_cc_mdss_mdp1_clk", 1323 1323 + .parent_hws = (const struct clk_hw*[]) { 1324 1324 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 1325 1325 + }, 1326 1326 + .num_parents = 1, 1327 1327 + .flags = CLK_SET_RATE_PARENT, 1328 1328 + .ops = &clk_branch2_ops, 1329 1329 + }, 1330 1330 + }, 1331 1331 + }; 1332 1332 + 1333 1333 + static struct clk_branch disp_cc_mdss_mdp_clk = { 1334 1334 + .halt_reg = 0x800c, 1335 1335 + .halt_check = BRANCH_HALT, 1336 1336 + .clkr = { 1337 1337 + .enable_reg = 0x800c, 1338 1338 + .enable_mask = BIT(0), 1339 1339 + .hw.init = &(const struct clk_init_data) { 1340 1340 + .name = "disp_cc_mdss_mdp_clk", 1341 1341 + .parent_hws = (const struct clk_hw*[]) { 1342 1342 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 1343 1343 + }, 1344 1344 + .num_parents = 1, 1345 1345 + .flags = CLK_SET_RATE_PARENT, 1346 1346 + .ops = &clk_branch2_ops, 1347 1347 + }, 1348 1348 + }, 1349 1349 + }; 1350 1350 + 1351 1351 + static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1352 1352 + .halt_reg = 0xa010, 1353 1353 + .halt_check = BRANCH_HALT, 1354 1354 + .clkr = { 1355 1355 + .enable_reg = 0xa010, 1356 1356 + .enable_mask = BIT(0), 1357 1357 + .hw.init = &(const struct clk_init_data) { 1358 1358 + .name = "disp_cc_mdss_mdp_lut1_clk", 1359 1359 + .parent_hws = (const struct clk_hw*[]) { 1360 1360 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 1361 1361 + }, 1362 1362 + .num_parents = 1, 1363 1363 + .flags = CLK_SET_RATE_PARENT, 1364 1364 + .ops = &clk_branch2_ops, 1365 1365 + }, 1366 1366 + }, 1367 1367 + }; 1368 1368 + 1369 1369 + static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1370 1370 + .halt_reg = 0x8018, 1371 1371 + .halt_check = BRANCH_HALT_VOTED, 1372 1372 + .clkr = { 1373 1373 + .enable_reg = 0x8018, 1374 1374 + .enable_mask = BIT(0), 1375 1375 + .hw.init = &(const struct clk_init_data) { 1376 1376 + .name = "disp_cc_mdss_mdp_lut_clk", 1377 1377 + .parent_hws = (const struct clk_hw*[]) { 1378 1378 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 1379 1379 + }, 1380 1380 + .num_parents = 1, 1381 1381 + .flags = CLK_SET_RATE_PARENT, 1382 1382 + .ops = &clk_branch2_ops, 1383 1383 + }, 1384 1384 + }, 1385 1385 + }; 1386 1386 + 1387 1387 + static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1388 1388 + .halt_reg = 0xc004, 1389 1389 + .halt_check = BRANCH_HALT_VOTED, 1390 1390 + .clkr = { 1391 1391 + .enable_reg = 0xc004, 1392 1392 + .enable_mask = BIT(0), 1393 1393 + .hw.init = &(const struct clk_init_data) { 1394 1394 + .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1395 1395 + .parent_hws = (const struct clk_hw*[]) { 1396 1396 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 1397 1397 + }, 1398 1398 + .num_parents = 1, 1399 1399 + .flags = CLK_SET_RATE_PARENT, 1400 1400 + .ops = &clk_branch2_ops, 1401 1401 + }, 1402 1402 + }, 1403 1403 + }; 1404 1404 + 1405 1405 + static struct clk_branch disp_cc_mdss_pclk0_clk = { 1406 1406 + .halt_reg = 0x8004, 1407 1407 + .halt_check = BRANCH_HALT, 1408 1408 + .clkr = { 1409 1409 + .enable_reg = 0x8004, 1410 1410 + .enable_mask = BIT(0), 1411 1411 + .hw.init = &(const struct clk_init_data) { 1412 1412 + .name = "disp_cc_mdss_pclk0_clk", 1413 1413 + .parent_hws = (const struct clk_hw*[]) { 1414 1414 + &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1415 1415 + }, 1416 1416 + .num_parents = 1, 1417 1417 + .flags = CLK_SET_RATE_PARENT, 1418 1418 + .ops = &clk_branch2_ops, 1419 1419 + }, 1420 1420 + }, 1421 1421 + }; 1422 1422 + 1423 1423 + static struct clk_branch disp_cc_mdss_pclk1_clk = { 1424 1424 + .halt_reg = 0x8008, 1425 1425 + .halt_check = BRANCH_HALT, 1426 1426 + .clkr = { 1427 1427 + .enable_reg = 0x8008, 1428 1428 + .enable_mask = BIT(0), 1429 1429 + .hw.init = &(const struct clk_init_data) { 1430 1430 + .name = "disp_cc_mdss_pclk1_clk", 1431 1431 + .parent_hws = (const struct clk_hw*[]) { 1432 1432 + &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1433 1433 + }, 1434 1434 + .num_parents = 1, 1435 1435 + .flags = CLK_SET_RATE_PARENT, 1436 1436 + .ops = &clk_branch2_ops, 1437 1437 + }, 1438 1438 + }, 1439 1439 + }; 1440 1440 + 1441 1441 + static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1442 1442 + .halt_reg = 0xc00c, 1443 1443 + .halt_check = BRANCH_HALT, 1444 1444 + .clkr = { 1445 1445 + .enable_reg = 0xc00c, 1446 1446 + .enable_mask = BIT(0), 1447 1447 + .hw.init = &(const struct clk_init_data) { 1448 1448 + .name = "disp_cc_mdss_rscc_ahb_clk", 1449 1449 + .parent_hws = (const struct clk_hw*[]) { 1450 1450 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 1451 1451 + }, 1452 1452 + .num_parents = 1, 1453 1453 + .flags = CLK_SET_RATE_PARENT, 1454 1454 + .ops = &clk_branch2_ops, 1455 1455 + }, 1456 1456 + }, 1457 1457 + }; 1458 1458 + 1459 1459 + static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1460 1460 + .halt_reg = 0xc008, 1461 1461 + .halt_check = BRANCH_HALT, 1462 1462 + .clkr = { 1463 1463 + .enable_reg = 0xc008, 1464 1464 + .enable_mask = BIT(0), 1465 1465 + .hw.init = &(const struct clk_init_data) { 1466 1466 + .name = "disp_cc_mdss_rscc_vsync_clk", 1467 1467 + .parent_hws = (const struct clk_hw*[]) { 1468 1468 + &disp_cc_mdss_vsync_clk_src.clkr.hw, 1469 1469 + }, 1470 1470 + .num_parents = 1, 1471 1471 + .flags = CLK_SET_RATE_PARENT, 1472 1472 + .ops = &clk_branch2_ops, 1473 1473 + }, 1474 1474 + }, 1475 1475 + }; 1476 1476 + 1477 1477 + static struct clk_branch disp_cc_mdss_vsync1_clk = { 1478 1478 + .halt_reg = 0xa01c, 1479 1479 + .halt_check = BRANCH_HALT, 1480 1480 + .clkr = { 1481 1481 + .enable_reg = 0xa01c, 1482 1482 + .enable_mask = BIT(0), 1483 1483 + .hw.init = &(const struct clk_init_data) { 1484 1484 + .name = "disp_cc_mdss_vsync1_clk", 1485 1485 + .parent_hws = (const struct clk_hw*[]) { 1486 1486 + &disp_cc_mdss_vsync_clk_src.clkr.hw, 1487 1487 + }, 1488 1488 + .num_parents = 1, 1489 1489 + .flags = CLK_SET_RATE_PARENT, 1490 1490 + .ops = &clk_branch2_ops, 1491 1491 + }, 1492 1492 + }, 1493 1493 + }; 1494 1494 + 1495 1495 + static struct clk_branch disp_cc_mdss_vsync_clk = { 1496 1496 + .halt_reg = 0x8024, 1497 1497 + .halt_check = BRANCH_HALT, 1498 1498 + .clkr = { 1499 1499 + .enable_reg = 0x8024, 1500 1500 + .enable_mask = BIT(0), 1501 1501 + .hw.init = &(const struct clk_init_data) { 1502 1502 + .name = "disp_cc_mdss_vsync_clk", 1503 1503 + .parent_hws = (const struct clk_hw*[]) { 1504 1504 + &disp_cc_mdss_vsync_clk_src.clkr.hw, 1505 1505 + }, 1506 1506 + .num_parents = 1, 1507 1507 + .flags = CLK_SET_RATE_PARENT, 1508 1508 + .ops = &clk_branch2_ops, 1509 1509 + }, 1510 1510 + }, 1511 1511 + }; 1512 1512 + 1513 1513 + static struct gdsc mdss_gdsc = { 1514 1514 + .gdscr = 0x9000, 1515 1515 + .en_rest_wait_val = 0x2, 1516 1516 + .en_few_wait_val = 0x2, 1517 1517 + .clk_dis_wait_val = 0xf, 1518 1518 + .pd = { 1519 1519 + .name = "mdss_gdsc", 1520 1520 + }, 1521 1521 + .pwrsts = PWRSTS_OFF_ON, 1522 1522 + .flags = HW_CTRL | RETAIN_FF_ENABLE, 1523 1523 + }; 1524 1524 + 1525 1525 + static struct gdsc mdss_int2_gdsc = { 1526 1526 + .gdscr = 0xb000, 1527 1527 + .en_rest_wait_val = 0x2, 1528 1528 + .en_few_wait_val = 0x2, 1529 1529 + .clk_dis_wait_val = 0xf, 1530 1530 + .pd = { 1531 1531 + .name = "mdss_int2_gdsc", 1532 1532 + }, 1533 1533 + .pwrsts = PWRSTS_OFF_ON, 1534 1534 + .flags = HW_CTRL | RETAIN_FF_ENABLE, 1535 1535 + }; 1536 1536 + 1537 1537 + static struct clk_regmap *disp_cc_x1e80100_clocks[] = { 1538 1538 + [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr, 1539 1539 + [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1540 1540 + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1541 1541 + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1542 1542 + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1543 1543 + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1544 1544 + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1545 1545 + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1546 1546 + [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1547 1547 + [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1548 1548 + [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1549 1549 + [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1550 1550 + [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1551 1551 + [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1552 1552 + [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1553 1553 + [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1554 1554 + [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1555 1555 + [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1556 1556 + [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1557 1557 + [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1558 1558 + [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1559 1559 + [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1560 1560 + [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1561 1561 + &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1562 1562 + [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1563 1563 + [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1564 1564 + [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1565 1565 + [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1566 1566 + [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1567 1567 + [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1568 1568 + [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1569 1569 + [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1570 1570 + [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1571 1571 + [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1572 1572 + [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1573 1573 + &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1574 1574 + [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1575 1575 + [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1576 1576 + [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1577 1577 + [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1578 1578 + [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1579 1579 + [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1580 1580 + [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1581 1581 + [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1582 1582 + [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1583 1583 + [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1584 1584 + [DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK] = 1585 1585 + &disp_cc_mdss_dptx2_usb_router_link_intf_clk.clkr, 1586 1586 + [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1587 1587 + [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1588 1588 + [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1589 1589 + [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1590 1590 + [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1591 1591 + [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1592 1592 + [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1593 1593 + [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1594 1594 + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1595 1595 + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1596 1596 + [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1597 1597 + [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1598 1598 + [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1599 1599 + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1600 1600 + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1601 1601 + [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1602 1602 + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1603 1603 + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1604 1604 + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1605 1605 + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1606 1606 + [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1607 1607 + [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1608 1608 + [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1609 1609 + [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1610 1610 + [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1611 1611 + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1612 1612 + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1613 1613 + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1614 1614 + [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1615 1615 + [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1616 1616 + [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1617 1617 + }; 1618 1618 + 1619 1619 + static const struct qcom_reset_map disp_cc_x1e80100_resets[] = { 1620 1620 + [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1621 1621 + [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1622 1622 + [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1623 1623 + }; 1624 1624 + 1625 1625 + static struct gdsc *disp_cc_x1e80100_gdscs[] = { 1626 1626 + [MDSS_GDSC] = &mdss_gdsc, 1627 1627 + [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 1628 1628 + }; 1629 1629 + 1630 1630 + static const struct regmap_config disp_cc_x1e80100_regmap_config = { 1631 1631 + .reg_bits = 32, 1632 1632 + .reg_stride = 4, 1633 1633 + .val_bits = 32, 1634 1634 + .max_register = 0x11008, 1635 1635 + .fast_io = true, 1636 1636 + }; 1637 1637 + 1638 1638 + static const struct qcom_cc_desc disp_cc_x1e80100_desc = { 1639 1639 + .config = &disp_cc_x1e80100_regmap_config, 1640 1640 + .clks = disp_cc_x1e80100_clocks, 1641 1641 + .num_clks = ARRAY_SIZE(disp_cc_x1e80100_clocks), 1642 1642 + .resets = disp_cc_x1e80100_resets, 1643 1643 + .num_resets = ARRAY_SIZE(disp_cc_x1e80100_resets), 1644 1644 + .gdscs = disp_cc_x1e80100_gdscs, 1645 1645 + .num_gdscs = ARRAY_SIZE(disp_cc_x1e80100_gdscs), 1646 1646 + }; 1647 1647 + 1648 1648 + static const struct of_device_id disp_cc_x1e80100_match_table[] = { 1649 1649 + { .compatible = "qcom,x1e80100-dispcc" }, 1650 1650 + { } 1651 1651 + }; 1652 1652 + MODULE_DEVICE_TABLE(of, disp_cc_x1e80100_match_table); 1653 1653 + 1654 1654 + static int disp_cc_x1e80100_probe(struct platform_device *pdev) 1655 1655 + { 1656 1656 + struct regmap *regmap; 1657 1657 + int ret; 1658 1658 + 1659 1659 + ret = devm_pm_runtime_enable(&pdev->dev); 1660 1660 + if (ret) 1661 1661 + return ret; 1662 1662 + 1663 1663 + ret = pm_runtime_resume_and_get(&pdev->dev); 1664 1664 + if (ret) 1665 1665 + return ret; 1666 1666 + 1667 1667 + regmap = qcom_cc_map(pdev, &disp_cc_x1e80100_desc); 1668 1668 + if (IS_ERR(regmap)) { 1669 1669 + ret = PTR_ERR(regmap); 1670 1670 + goto err_put_rpm; 1671 1671 + } 1672 1672 + 1673 1673 + clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1674 1674 + clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1675 1675 + 1676 1676 + /* Enable clock gating for MDP clocks */ 1677 1677 + regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1678 1678 + 1679 1679 + /* Keep clocks always enabled */ 1680 1680 + qcom_branch_set_clk_en(regmap, 0xe074); /* DISP_CC_SLEEP_CLK */ 1681 1681 + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ 1682 1682 + 1683 1683 + ret = qcom_cc_really_probe(pdev, &disp_cc_x1e80100_desc, regmap); 1684 1684 + if (ret) 1685 1685 + goto err_put_rpm; 1686 1686 + 1687 1687 + pm_runtime_put(&pdev->dev); 1688 1688 + 1689 1689 + return 0; 1690 1690 + 1691 1691 + err_put_rpm: 1692 1692 + pm_runtime_put_sync(&pdev->dev); 1693 1693 + 1694 1694 + return ret; 1695 1695 + } 1696 1696 + 1697 1697 + static struct platform_driver disp_cc_x1e80100_driver = { 1698 1698 + .probe = disp_cc_x1e80100_probe, 1699 1699 + .driver = { 1700 1700 + .name = "dispcc-x1e80100", 1701 1701 + .of_match_table = disp_cc_x1e80100_match_table, 1702 1702 + }, 1703 1703 + }; 1704 1704 + 1705 1705 + static int __init disp_cc_x1e80100_init(void) 1706 1706 + { 1707 1707 + return platform_driver_register(&disp_cc_x1e80100_driver); 1708 1708 + } 1709 1709 + subsys_initcall(disp_cc_x1e80100_init); 1710 1710 + 1711 1711 + static void __exit disp_cc_x1e80100_exit(void) 1712 1712 + { 1713 1713 + platform_driver_unregister(&disp_cc_x1e80100_driver); 1714 1714 + } 1715 1715 + module_exit(disp_cc_x1e80100_exit); 1716 1716 + 1717 1717 + MODULE_DESCRIPTION("QTI Display Clock Controller X1E80100 Driver"); 1718 1718 + MODULE_LICENSE("GPL");

+6 -3

drivers/clk/qcom/gcc-ipq5018.c

reviewed

··· 857 857 858 858 static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = { 859 859 F(2000000, P_XO, 12, 0, 0), 860 860 + { } 860 861 }; 861 862 862 863 static struct clk_rcg2 pcie0_aux_clk_src = { ··· 1100 1099 F(100000000, P_GPLL0, 8, 0, 0), 1101 1100 F(200000000, P_GPLL0, 4, 0, 0), 1102 1101 F(320000000, P_GPLL0, 2.5, 0, 0), 1102 1102 + { } 1103 1103 }; 1104 1104 1105 1105 static struct clk_rcg2 qpic_io_macro_clk_src = { ··· 1196 1194 static const struct freq_tbl ftbl_ubi0_core_clk_src[] = { 1197 1195 F(850000000, P_UBI32_PLL, 1, 0, 0), 1198 1196 F(1000000000, P_UBI32_PLL, 1, 0, 0), 1197 1197 + { } 1199 1198 }; 1200 1199 1201 1200 static struct clk_rcg2 ubi0_core_clk_src = { ··· 1757 1754 .halt_check = BRANCH_HALT_DELAY, 1758 1755 .halt_bit = 31, 1759 1756 .clkr = { 1760 1760 - .enable_reg = 0x683190, 1757 1757 + .enable_reg = 0x68190, 1761 1758 .enable_mask = BIT(0), 1762 1759 .hw.init = &(struct clk_init_data) { 1763 1760 .name = "gcc_gmac0_sys_clk", ··· 2183 2180 }; 2184 2181 2185 2182 static struct clk_branch gcc_pcie1_pipe_clk = { 2186 2186 - .halt_reg = 8, 2183 2183 + .halt_reg = 0x76018, 2187 2184 .halt_check = BRANCH_HALT_DELAY, 2188 2185 .halt_bit = 31, 2189 2186 .clkr = { ··· 3635 3632 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, 3636 3633 [GCC_TCSR_BCR] = { 0x28000, 0 }, 3637 3634 [GCC_TLMM_BCR] = { 0x34000, 0 }, 3638 3638 - [GCC_UBI0_AXI_ARES] = { 0x680}, 3635 3635 + [GCC_UBI0_AXI_ARES] = { 0x68010, 0 }, 3639 3636 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 }, 3640 3637 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 }, 3641 3638 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },

+19

drivers/clk/qcom/gcc-ipq6018.c

reviewed

··· 1554 1554 1555 1555 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 1556 1556 F(24000000, P_XO, 1, 0, 0), 1557 1557 + { } 1557 1558 }; 1558 1559 1559 1560 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = { ··· 1735 1734 F(160000000, P_GPLL0, 5, 0, 0), 1736 1735 F(216000000, P_GPLL6, 5, 0, 0), 1737 1736 F(308570000, P_GPLL6, 3.5, 0, 0), 1737 1737 + { } 1738 1738 }; 1739 1739 1740 1740 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = { ··· 3524 3522 }, 3525 3523 }; 3526 3524 3525 3525 + static struct clk_branch gcc_qdss_at_clk = { 3526 3526 + .halt_reg = 0x29024, 3527 3527 + .clkr = { 3528 3528 + .enable_reg = 0x29024, 3529 3529 + .enable_mask = BIT(0), 3530 3530 + .hw.init = &(struct clk_init_data){ 3531 3531 + .name = "gcc_qdss_at_clk", 3532 3532 + .parent_hws = (const struct clk_hw *[]){ 3533 3533 + &qdss_at_clk_src.clkr.hw }, 3534 3534 + .num_parents = 1, 3535 3535 + .flags = CLK_SET_RATE_PARENT, 3536 3536 + .ops = &clk_branch2_ops, 3537 3537 + }, 3538 3538 + }, 3539 3539 + }; 3540 3540 + 3527 3541 static struct clk_branch gcc_qdss_dap_clk = { 3528 3542 .halt_reg = 0x29084, 3529 3543 .clkr = { ··· 4379 4361 [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr, 4380 4362 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, 4381 4363 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 4364 4364 + [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 4382 4365 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 4383 4366 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 4384 4367 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,

+2

drivers/clk/qcom/gcc-ipq8074.c

reviewed

··· 644 644 645 645 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 646 646 F(19200000, P_XO, 1, 0, 0), 647 647 + { } 647 648 }; 648 649 649 650 static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = { ··· 796 795 F(19200000, P_XO, 1, 0, 0), 797 796 F(160000000, P_GPLL0, 5, 0, 0), 798 797 F(308570000, P_GPLL6, 3.5, 0, 0), 798 798 + { } 799 799 }; 800 800 801 801 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {

+1

drivers/clk/qcom/gcc-ipq9574.c

reviewed

··· 2082 2082 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = { 2083 2083 F(150000000, P_GPLL4, 8, 0, 0), 2084 2084 F(300000000, P_GPLL4, 4, 0, 0), 2085 2085 + { } 2085 2086 }; 2086 2087 2087 2088 static struct clk_rcg2 sdcc1_ice_core_clk_src = {

+4

drivers/clk/qcom/gcc-msm8953.c

reviewed

··· 4171 4171 [GCC_USB3PHY_PHY_BCR] = { 0x3f03c }, 4172 4172 [GCC_USB3_PHY_BCR] = { 0x3f034 }, 4173 4173 [GCC_USB_30_BCR] = { 0x3f070 }, 4174 4174 + [GCC_MDSS_BCR] = { 0x4d074 }, 4175 4175 + [GCC_CRYPTO_BCR] = { 0x16000 }, 4176 4176 + [GCC_SDCC1_BCR] = { 0x42000 }, 4177 4177 + [GCC_SDCC2_BCR] = { 0x43000 }, 4174 4178 }; 4175 4179 4176 4180 static const struct regmap_config gcc_msm8953_regmap_config = {

+12 -17

drivers/clk/qcom/gcc-sa8775p.c

reviewed

··· 4662 4662 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 }, 4663 4663 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 }, 4664 4664 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 }, 4665 4665 - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 }, 4666 4666 - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 }, 4665 4665 + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 }, 4666 4666 + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 }, 4667 4667 [GCC_VIDEO_BCR] = { 0x34000 }, 4668 4668 }; 4669 4669 ··· 4742 4742 if (ret) 4743 4743 return ret; 4744 4744 4745 4745 - /* 4746 4746 - * Keep the clocks always-ON 4747 4747 - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, 4748 4748 - * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, 4749 4749 - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. 4750 4750 - */ 4751 4751 - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); 4752 4752 - regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); 4753 4753 - regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); 4754 4754 - regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); 4755 4755 - regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); 4756 4756 - regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); 4757 4757 - regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); 4758 4758 - regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); 4759 4759 - regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); 4745 4745 + /* Keep some clocks always-on */ 4746 4746 + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ 4747 4747 + qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ 4748 4748 + qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */ 4749 4749 + qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */ 4750 4750 + qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ 4751 4751 + qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ 4752 4752 + qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ 4753 4753 + qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ 4754 4754 + qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ 4760 4755 4761 4756 return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); 4762 4757 }

+9 -13

drivers/clk/qcom/gcc-sc7180.c

reviewed

··· 2443 2443 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 2444 2444 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 2445 2445 2446 2446 - /* 2447 2447 - * Keep the clocks always-ON 2448 2448 - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, 2449 2449 - * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK 2450 2450 - */ 2451 2451 - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 2452 2452 - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 2453 2453 - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 2454 2454 - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 2455 2455 - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); 2456 2456 - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); 2457 2457 - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); 2458 2458 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 2446 2446 + /* Keep some clocks always-on */ 2447 2447 + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ 2448 2448 + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ 2449 2449 + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ 2450 2450 + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ 2451 2451 + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ 2452 2452 + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ 2453 2453 + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ 2454 2454 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 2459 2455 2460 2456 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2461 2457 ARRAY_SIZE(gcc_dfs_clocks));

+8 -12

drivers/clk/qcom/gcc-sc7280.c

reviewed

··· 3453 3453 if (IS_ERR(regmap)) 3454 3454 return PTR_ERR(regmap); 3455 3455 3456 3456 - /* 3457 3457 - * Keep the clocks always-ON 3458 3458 - * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK 3459 3459 - * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK 3460 3460 - */ 3461 3461 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3462 3462 - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); 3463 3463 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3464 3464 - regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); 3465 3465 - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 3466 3466 - regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); 3467 3467 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3456 3456 + /* Keep some clocks always-on */ 3457 3457 + qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */ 3458 3458 + qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */ 3459 3459 + qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */ 3460 3460 + qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */ 3461 3461 + qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */ 3462 3462 + qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */ 3463 3463 + qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ 3468 3464 regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); 3469 3465 3470 3466 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,

+42 -20

drivers/clk/qcom/gcc-sc8180x.c

reviewed

··· 3347 3347 }, 3348 3348 }; 3349 3349 3350 3350 + static struct clk_branch gcc_ufs_card_clkref_en = { 3351 3351 + .halt_reg = 0x8c004, 3352 3352 + .halt_check = BRANCH_HALT, 3353 3353 + .clkr = { 3354 3354 + .enable_reg = 0x8c004, 3355 3355 + .enable_mask = BIT(0), 3356 3356 + .hw.init = &(const struct clk_init_data) { 3357 3357 + .name = "gcc_ufs_card_clkref_en", 3358 3358 + .ops = &clk_branch2_ops, 3359 3359 + }, 3360 3360 + }, 3361 3361 + }; 3362 3362 + 3350 3363 static struct clk_branch gcc_ufs_card_ahb_clk = { 3351 3364 .halt_reg = 0x75014, 3352 3365 .halt_check = BRANCH_HALT, ··· 3570 3557 .num_parents = 1, 3571 3558 .flags = CLK_SET_RATE_PARENT, 3572 3559 .ops = &clk_branch_simple_ops, 3560 3560 + }, 3561 3561 + }, 3562 3562 + }; 3563 3563 + 3564 3564 + static struct clk_branch gcc_ufs_mem_clkref_en = { 3565 3565 + .halt_reg = 0x8c000, 3566 3566 + .halt_check = BRANCH_HALT, 3567 3567 + .clkr = { 3568 3568 + .enable_reg = 0x8c000, 3569 3569 + .enable_mask = BIT(0), 3570 3570 + .hw.init = &(const struct clk_init_data) { 3571 3571 + .name = "gcc_ufs_mem_clkref_en", 3572 3572 + .ops = &clk_branch2_ops, 3573 3573 }, 3574 3574 }, 3575 3575 }; ··· 4439 4413 [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr, 4440 4414 [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr, 4441 4415 [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr, 4416 4416 + [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr, 4442 4417 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 4443 4418 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 4444 4419 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, ··· 4456 4429 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 4457 4430 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, 4458 4431 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, 4432 4432 + [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr, 4459 4433 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 4460 4434 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 4461 4435 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, ··· 4556 4528 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 4557 4529 [GCC_USB30_SEC_BCR] = { 0x10000 }, 4558 4530 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 4559 4559 - [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, 4560 4560 - [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, 4561 4561 - [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, 4531 4531 + [GCC_VIDEO_AXIC_CLK_BCR] = { .reg = 0xb02c, .bit = 2, .udelay = 150 }, 4532 4532 + [GCC_VIDEO_AXI0_CLK_BCR] = { .reg = 0xb024, .bit = 2, .udelay = 150 }, 4533 4533 + [GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 }, 4562 4534 }; 4563 4535 4564 4536 static struct gdsc *gcc_sc8180x_gdscs[] = { ··· 4607 4579 if (IS_ERR(regmap)) 4608 4580 return PTR_ERR(regmap); 4609 4581 4610 4610 - /* 4611 4611 - * Enable the following always-on clocks: 4612 4612 - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, 4613 4613 - * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK, 4614 4614 - * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and 4615 4615 - * GCC_GPU_CFG_AHB_CLK 4616 4616 - */ 4617 4617 - regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); 4618 4618 - regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); 4619 4619 - regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); 4620 4620 - regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); 4621 4621 - regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); 4622 4622 - regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); 4623 4623 - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 4624 4624 - regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); 4625 4625 - regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); 4626 4626 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 4582 4582 + /* Keep some clocks always-on */ 4583 4583 + qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ 4584 4584 + qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ 4585 4585 + qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ 4586 4586 + qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ 4587 4587 + qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ 4588 4588 + qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ 4589 4589 + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ 4590 4590 + qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */ 4591 4591 + qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */ 4592 4592 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 4627 4593 4628 4594 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 4629 4595 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);

+12 -17

drivers/clk/qcom/gcc-sc8280xp.c

reviewed

··· 7448 7448 [GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 }, 7449 7449 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 7450 7450 [GCC_VIDEO_BCR] = { 0x28000 }, 7451 7451 - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 }, 7452 7452 - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 }, 7451 7451 + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 }, 7452 7452 + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 }, 7453 7453 }; 7454 7454 7455 7455 static struct gdsc *gcc_sc8280xp_gdscs[] = { ··· 7543 7543 goto err_put_rpm; 7544 7544 } 7545 7545 7546 7546 - /* 7547 7547 - * Keep the clocks always-ON 7548 7548 - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, 7549 7549 - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, 7550 7550 - * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK 7551 7551 - */ 7552 7552 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 7553 7553 - regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0)); 7554 7554 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 7555 7555 - regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0)); 7556 7556 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 7557 7557 - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 7558 7558 - regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0)); 7559 7559 - regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0)); 7560 7560 - regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0)); 7546 7546 + /* Keep some clocks always-on */ 7547 7547 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 7548 7548 + qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */ 7549 7549 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 7550 7550 + qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */ 7551 7551 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 7552 7552 + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ 7553 7553 + qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */ 7554 7554 + qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */ 7555 7555 + qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */ 7561 7556 7562 7557 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 7563 7558 if (ret)

+1

drivers/clk/qcom/gcc-sdm845.c

reviewed

··· 4037 4037 MODULE_DESCRIPTION("QTI GCC SDM845 Driver"); 4038 4038 MODULE_LICENSE("GPL v2"); 4039 4039 MODULE_ALIAS("platform:gcc-sdm845"); 4040 4040 + MODULE_SOFTDEP("pre: rpmhpd");

+4 -8

drivers/clk/qcom/gcc-sdx55.c

reviewed

··· 1611 1611 if (IS_ERR(regmap)) 1612 1612 return PTR_ERR(regmap); 1613 1613 1614 1614 - /* 1615 1615 - * Keep the clocks always-ON as they are critical to the functioning 1616 1616 - * of the system: 1617 1617 - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK 1618 1618 - */ 1619 1619 - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); 1620 1620 - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); 1621 1621 - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); 1614 1614 + /* Keep some clocks always-on */ 1615 1615 + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ 1616 1616 + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ 1617 1617 + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ 1622 1618 1623 1619 return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap); 1624 1620 }

+5 -8

drivers/clk/qcom/gcc-sdx65.c

reviewed

··· 1574 1574 regmap = qcom_cc_map(pdev, &gcc_sdx65_desc); 1575 1575 if (IS_ERR(regmap)) 1576 1576 return PTR_ERR(regmap); 1577 1577 - /* 1578 1578 - * Keep the clocks always-ON as they are critical to the functioning 1579 1579 - * of the system: 1580 1580 - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK 1581 1581 - */ 1582 1582 - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); 1583 1583 - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); 1584 1584 - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); 1577 1577 + 1578 1578 + /* Keep some clocks always-on */ 1579 1579 + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ 1580 1580 + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ 1581 1581 + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ 1585 1582 1586 1583 return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap); 1587 1584 }

+3 -7

drivers/clk/qcom/gcc-sdx75.c

reviewed

··· 2936 2936 if (ret) 2937 2937 return ret; 2938 2938 2939 2939 - /* 2940 2940 - * Keep clocks always enabled: 2941 2941 - * gcc_ahb_pcie_link_clk 2942 2942 - * gcc_xo_pcie_link_clk 2943 2943 - */ 2944 2944 - regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); 2945 2945 - regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); 2939 2939 + /* Keep some clocks always-on */ 2940 2940 + qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */ 2941 2941 + qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */ 2946 2942 2947 2943 return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); 2948 2944 }

+11 -21

drivers/clk/qcom/gcc-sm4450.c

reviewed

··· 2791 2791 [GCC_VENUS_BCR] = { 0xb601c }, 2792 2792 [GCC_VIDEO_BCR] = { 0x42000 }, 2793 2793 [GCC_VIDEO_VENUS_BCR] = { 0xb6000 }, 2794 2794 - [GCC_VENUS_CTL_AXI_CLK_ARES] = { 0x4201c, 2 }, 2795 2795 - [GCC_VIDEO_VENUS_CTL_CLK_ARES] = { 0xb6038, 2 }, 2794 2794 + [GCC_VENUS_CTL_AXI_CLK_ARES] = { .reg = 0x4201c, .bit = 2, .udelay = 400 }, 2795 2795 + [GCC_VIDEO_VENUS_CTL_CLK_ARES] = { .reg = 0xb6038, .bit = 2, .udelay = 400 }, 2796 2796 }; 2797 2797 2798 2798 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { ··· 2849 2849 2850 2850 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 2851 2851 2852 2852 - /* 2853 2853 - * Keep clocks always enabled: 2854 2854 - * gcc_camera_ahb_clk 2855 2855 - * gcc_camera_sleep_clk 2856 2856 - * gcc_camera_xo_clk 2857 2857 - * gcc_disp_ahb_clk 2858 2858 - * gcc_disp_xo_clk 2859 2859 - * gcc_gpu_cfg_ahb_clk 2860 2860 - * gcc_video_ahb_clk 2861 2861 - * gcc_video_xo_clk 2862 2862 - */ 2863 2863 - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); 2864 2864 - regmap_update_bits(regmap, 0x36018, BIT(0), BIT(0)); 2865 2865 - regmap_update_bits(regmap, 0x3601c, BIT(0), BIT(0)); 2866 2866 - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); 2867 2867 - regmap_update_bits(regmap, 0x37014, BIT(0), BIT(0)); 2868 2868 - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); 2869 2869 - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); 2870 2870 - regmap_update_bits(regmap, 0x42018, BIT(0), BIT(0)); 2852 2852 + /* Keep some clocks always-on */ 2853 2853 + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ 2854 2854 + qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */ 2855 2855 + qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */ 2856 2856 + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ 2857 2857 + qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */ 2858 2858 + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ 2859 2859 + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ 2860 2860 + qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */ 2871 2861 2872 2862 regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21)); 2873 2863

+4 -7

drivers/clk/qcom/gcc-sm6375.c

reviewed

··· 3882 3882 if (ret) 3883 3883 return ret; 3884 3884 3885 3885 - /* 3886 3886 - * Keep the following clocks always on: 3887 3887 - * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK 3888 3888 - */ 3889 3889 - regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); 3890 3890 - regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); 3891 3891 - regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); 3885 3885 + /* Keep some clocks always-on */ 3886 3886 + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ 3887 3887 + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ 3888 3888 + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ 3892 3889 3893 3890 clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); 3894 3891 clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config);

+10 -15

drivers/clk/qcom/gcc-sm7150.c

reviewed

··· 2918 2918 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 2919 2919 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 2920 2920 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 }, 2921 2921 - [GCC_VIDEO_AXI_CLK_BCR] = { 0xb01c, 2 }, 2921 2921 + [GCC_VIDEO_AXI_CLK_BCR] = { .reg = 0xb01c, .bit = 2, .udelay = 150 }, 2922 2922 }; 2923 2923 2924 2924 static const struct clk_rcg_dfs_data gcc_sm7150_dfs_desc[] = { ··· 3002 3002 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3003 3003 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3004 3004 3005 3005 - /* 3006 3006 - * Keep the critical clocks always-ON 3007 3007 - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, 3008 3008 - * GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK, 3009 3009 - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK 3010 3010 - */ 3011 3011 - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 3012 3012 - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 3013 3013 - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 3014 3014 - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 3015 3015 - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); 3016 3016 - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); 3017 3017 - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); 3018 3018 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3005 3005 + /* Keep some clocks always-on */ 3006 3006 + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ 3007 3007 + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ 3008 3008 + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ 3009 3009 + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ 3010 3010 + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ 3011 3011 + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ 3012 3012 + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ 3013 3013 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3019 3014 3020 3015 ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc, 3021 3016 ARRAY_SIZE(gcc_sm7150_dfs_desc));

+212 -140

drivers/clk/qcom/gcc-sm8150.c

reviewed

··· 453 453 { } 454 454 }; 455 455 456 456 + static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 457 457 + .name = "gcc_qupv3_wrap0_s0_clk_src", 458 458 + .parent_data = gcc_parents_0, 459 459 + .num_parents = ARRAY_SIZE(gcc_parents_0), 460 460 + .flags = CLK_SET_RATE_PARENT, 461 461 + .ops = &clk_rcg2_ops, 462 462 + }; 463 463 + 456 464 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 457 465 .cmd_rcgr = 0x17148, 458 466 .mnd_width = 16, 459 467 .hid_width = 5, 460 468 .parent_map = gcc_parent_map_0, 461 469 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 462 462 - .clkr.hw.init = &(struct clk_init_data){ 463 463 - .name = "gcc_qupv3_wrap0_s0_clk_src", 464 464 - .parent_data = gcc_parents_0, 465 465 - .num_parents = ARRAY_SIZE(gcc_parents_0), 466 466 - .flags = CLK_SET_RATE_PARENT, 467 467 - .ops = &clk_rcg2_ops, 468 468 - }, 470 470 + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 471 471 + }; 472 472 + 473 473 + static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 474 474 + .name = "gcc_qupv3_wrap0_s1_clk_src", 475 475 + .parent_data = gcc_parents_0, 476 476 + .num_parents = ARRAY_SIZE(gcc_parents_0), 477 477 + .flags = CLK_SET_RATE_PARENT, 478 478 + .ops = &clk_rcg2_ops, 469 479 }; 470 480 471 481 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { ··· 484 474 .hid_width = 5, 485 475 .parent_map = gcc_parent_map_0, 486 476 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 487 487 - .clkr.hw.init = &(struct clk_init_data){ 488 488 - .name = "gcc_qupv3_wrap0_s1_clk_src", 489 489 - .parent_data = gcc_parents_0, 490 490 - .num_parents = ARRAY_SIZE(gcc_parents_0), 491 491 - .flags = CLK_SET_RATE_PARENT, 492 492 - .ops = &clk_rcg2_ops, 493 493 - }, 477 477 + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 478 478 + }; 479 479 + 480 480 + static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 481 481 + .name = "gcc_qupv3_wrap0_s2_clk_src", 482 482 + .parent_data = gcc_parents_0, 483 483 + .num_parents = ARRAY_SIZE(gcc_parents_0), 484 484 + .flags = CLK_SET_RATE_PARENT, 485 485 + .ops = &clk_rcg2_ops, 494 486 }; 495 487 496 488 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { ··· 501 489 .hid_width = 5, 502 490 .parent_map = gcc_parent_map_0, 503 491 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 504 504 - .clkr.hw.init = &(struct clk_init_data){ 505 505 - .name = "gcc_qupv3_wrap0_s2_clk_src", 506 506 - .parent_data = gcc_parents_0, 507 507 - .num_parents = ARRAY_SIZE(gcc_parents_0), 508 508 - .flags = CLK_SET_RATE_PARENT, 509 509 - .ops = &clk_rcg2_ops, 510 510 - }, 492 492 + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 493 493 + }; 494 494 + 495 495 + static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 496 496 + .name = "gcc_qupv3_wrap0_s3_clk_src", 497 497 + .parent_data = gcc_parents_0, 498 498 + .num_parents = ARRAY_SIZE(gcc_parents_0), 499 499 + .flags = CLK_SET_RATE_PARENT, 500 500 + .ops = &clk_rcg2_ops, 511 501 }; 512 502 513 503 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { ··· 518 504 .hid_width = 5, 519 505 .parent_map = gcc_parent_map_0, 520 506 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 521 521 - .clkr.hw.init = &(struct clk_init_data){ 522 522 - .name = "gcc_qupv3_wrap0_s3_clk_src", 523 523 - .parent_data = gcc_parents_0, 524 524 - .num_parents = ARRAY_SIZE(gcc_parents_0), 525 525 - .flags = CLK_SET_RATE_PARENT, 526 526 - .ops = &clk_rcg2_ops, 527 527 - }, 507 507 + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 508 508 + }; 509 509 + 510 510 + static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 511 511 + .name = "gcc_qupv3_wrap0_s4_clk_src", 512 512 + .parent_data = gcc_parents_0, 513 513 + .num_parents = ARRAY_SIZE(gcc_parents_0), 514 514 + .flags = CLK_SET_RATE_PARENT, 515 515 + .ops = &clk_rcg2_ops, 528 516 }; 529 517 530 518 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { ··· 535 519 .hid_width = 5, 536 520 .parent_map = gcc_parent_map_0, 537 521 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 538 538 - .clkr.hw.init = &(struct clk_init_data){ 539 539 - .name = "gcc_qupv3_wrap0_s4_clk_src", 540 540 - .parent_data = gcc_parents_0, 541 541 - .num_parents = ARRAY_SIZE(gcc_parents_0), 542 542 - .flags = CLK_SET_RATE_PARENT, 543 543 - .ops = &clk_rcg2_ops, 544 544 - }, 522 522 + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 523 523 + }; 524 524 + 525 525 + static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 526 526 + .name = "gcc_qupv3_wrap0_s5_clk_src", 527 527 + .parent_data = gcc_parents_0, 528 528 + .num_parents = ARRAY_SIZE(gcc_parents_0), 529 529 + .flags = CLK_SET_RATE_PARENT, 530 530 + .ops = &clk_rcg2_ops, 545 531 }; 546 532 547 533 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { ··· 552 534 .hid_width = 5, 553 535 .parent_map = gcc_parent_map_0, 554 536 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 555 555 - .clkr.hw.init = &(struct clk_init_data){ 556 556 - .name = "gcc_qupv3_wrap0_s5_clk_src", 557 557 - .parent_data = gcc_parents_0, 558 558 - .num_parents = ARRAY_SIZE(gcc_parents_0), 559 559 - .flags = CLK_SET_RATE_PARENT, 560 560 - .ops = &clk_rcg2_ops, 561 561 - }, 537 537 + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 538 538 + }; 539 539 + 540 540 + static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 541 541 + .name = "gcc_qupv3_wrap0_s6_clk_src", 542 542 + .parent_data = gcc_parents_0, 543 543 + .num_parents = ARRAY_SIZE(gcc_parents_0), 544 544 + .flags = CLK_SET_RATE_PARENT, 545 545 + .ops = &clk_rcg2_ops, 562 546 }; 563 547 564 548 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { ··· 569 549 .hid_width = 5, 570 550 .parent_map = gcc_parent_map_0, 571 551 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 572 572 - .clkr.hw.init = &(struct clk_init_data){ 573 573 - .name = "gcc_qupv3_wrap0_s6_clk_src", 574 574 - .parent_data = gcc_parents_0, 575 575 - .num_parents = ARRAY_SIZE(gcc_parents_0), 576 576 - .flags = CLK_SET_RATE_PARENT, 577 577 - .ops = &clk_rcg2_ops, 578 578 - }, 552 552 + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 553 553 + }; 554 554 + 555 555 + static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 556 556 + .name = "gcc_qupv3_wrap0_s7_clk_src", 557 557 + .parent_data = gcc_parents_0, 558 558 + .num_parents = ARRAY_SIZE(gcc_parents_0), 559 559 + .flags = CLK_SET_RATE_PARENT, 560 560 + .ops = &clk_rcg2_ops, 579 561 }; 580 562 581 563 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { ··· 586 564 .hid_width = 5, 587 565 .parent_map = gcc_parent_map_0, 588 566 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 589 589 - .clkr.hw.init = &(struct clk_init_data){ 590 590 - .name = "gcc_qupv3_wrap0_s7_clk_src", 591 591 - .parent_data = gcc_parents_0, 592 592 - .num_parents = ARRAY_SIZE(gcc_parents_0), 593 593 - .flags = CLK_SET_RATE_PARENT, 594 594 - .ops = &clk_rcg2_ops, 595 595 - }, 567 567 + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 568 568 + }; 569 569 + 570 570 + static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 571 571 + .name = "gcc_qupv3_wrap1_s0_clk_src", 572 572 + .parent_data = gcc_parents_0, 573 573 + .num_parents = ARRAY_SIZE(gcc_parents_0), 574 574 + .flags = CLK_SET_RATE_PARENT, 575 575 + .ops = &clk_rcg2_ops, 596 576 }; 597 577 598 578 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { ··· 603 579 .hid_width = 5, 604 580 .parent_map = gcc_parent_map_0, 605 581 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 606 606 - .clkr.hw.init = &(struct clk_init_data){ 607 607 - .name = "gcc_qupv3_wrap1_s0_clk_src", 608 608 - .parent_data = gcc_parents_0, 609 609 - .num_parents = ARRAY_SIZE(gcc_parents_0), 610 610 - .flags = CLK_SET_RATE_PARENT, 611 611 - .ops = &clk_rcg2_ops, 612 612 - }, 582 582 + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 583 583 + }; 584 584 + 585 585 + static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 586 586 + .name = "gcc_qupv3_wrap1_s1_clk_src", 587 587 + .parent_data = gcc_parents_0, 588 588 + .num_parents = ARRAY_SIZE(gcc_parents_0), 589 589 + .flags = CLK_SET_RATE_PARENT, 590 590 + .ops = &clk_rcg2_ops, 613 591 }; 614 592 615 593 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { ··· 620 594 .hid_width = 5, 621 595 .parent_map = gcc_parent_map_0, 622 596 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 623 623 - .clkr.hw.init = &(struct clk_init_data){ 624 624 - .name = "gcc_qupv3_wrap1_s1_clk_src", 625 625 - .parent_data = gcc_parents_0, 626 626 - .num_parents = ARRAY_SIZE(gcc_parents_0), 627 627 - .flags = CLK_SET_RATE_PARENT, 628 628 - .ops = &clk_rcg2_ops, 629 629 - }, 597 597 + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 598 598 + }; 599 599 + 600 600 + static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 601 601 + .name = "gcc_qupv3_wrap1_s2_clk_src", 602 602 + .parent_data = gcc_parents_0, 603 603 + .num_parents = ARRAY_SIZE(gcc_parents_0), 604 604 + .flags = CLK_SET_RATE_PARENT, 605 605 + .ops = &clk_rcg2_ops, 630 606 }; 631 607 632 608 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { ··· 637 609 .hid_width = 5, 638 610 .parent_map = gcc_parent_map_0, 639 611 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 640 640 - .clkr.hw.init = &(struct clk_init_data){ 641 641 - .name = "gcc_qupv3_wrap1_s2_clk_src", 642 642 - .parent_data = gcc_parents_0, 643 643 - .num_parents = ARRAY_SIZE(gcc_parents_0), 644 644 - .flags = CLK_SET_RATE_PARENT, 645 645 - .ops = &clk_rcg2_ops, 646 646 - }, 612 612 + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 613 613 + }; 614 614 + 615 615 + static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 616 616 + .name = "gcc_qupv3_wrap1_s3_clk_src", 617 617 + .parent_data = gcc_parents_0, 618 618 + .num_parents = ARRAY_SIZE(gcc_parents_0), 619 619 + .flags = CLK_SET_RATE_PARENT, 620 620 + .ops = &clk_rcg2_ops, 647 621 }; 648 622 649 623 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { ··· 654 624 .hid_width = 5, 655 625 .parent_map = gcc_parent_map_0, 656 626 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 657 657 - .clkr.hw.init = &(struct clk_init_data){ 658 658 - .name = "gcc_qupv3_wrap1_s3_clk_src", 659 659 - .parent_data = gcc_parents_0, 660 660 - .num_parents = ARRAY_SIZE(gcc_parents_0), 661 661 - .flags = CLK_SET_RATE_PARENT, 662 662 - .ops = &clk_rcg2_ops, 663 663 - }, 627 627 + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 628 628 + }; 629 629 + 630 630 + static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 631 631 + .name = "gcc_qupv3_wrap1_s4_clk_src", 632 632 + .parent_data = gcc_parents_0, 633 633 + .num_parents = ARRAY_SIZE(gcc_parents_0), 634 634 + .flags = CLK_SET_RATE_PARENT, 635 635 + .ops = &clk_rcg2_ops, 664 636 }; 665 637 666 638 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { ··· 671 639 .hid_width = 5, 672 640 .parent_map = gcc_parent_map_0, 673 641 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 674 674 - .clkr.hw.init = &(struct clk_init_data){ 675 675 - .name = "gcc_qupv3_wrap1_s4_clk_src", 676 676 - .parent_data = gcc_parents_0, 677 677 - .num_parents = ARRAY_SIZE(gcc_parents_0), 678 678 - .flags = CLK_SET_RATE_PARENT, 679 679 - .ops = &clk_rcg2_ops, 680 680 - }, 642 642 + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 643 643 + }; 644 644 + 645 645 + static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 646 646 + .name = "gcc_qupv3_wrap1_s5_clk_src", 647 647 + .parent_data = gcc_parents_0, 648 648 + .num_parents = ARRAY_SIZE(gcc_parents_0), 649 649 + .flags = CLK_SET_RATE_PARENT, 650 650 + .ops = &clk_rcg2_ops, 681 651 }; 682 652 683 653 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { ··· 688 654 .hid_width = 5, 689 655 .parent_map = gcc_parent_map_0, 690 656 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 691 691 - .clkr.hw.init = &(struct clk_init_data){ 692 692 - .name = "gcc_qupv3_wrap1_s5_clk_src", 693 693 - .parent_data = gcc_parents_0, 694 694 - .num_parents = ARRAY_SIZE(gcc_parents_0), 695 695 - .flags = CLK_SET_RATE_PARENT, 696 696 - .ops = &clk_rcg2_ops, 697 697 - }, 657 657 + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 658 658 + }; 659 659 + 660 660 + static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 661 661 + .name = "gcc_qupv3_wrap2_s0_clk_src", 662 662 + .parent_data = gcc_parents_0, 663 663 + .num_parents = ARRAY_SIZE(gcc_parents_0), 664 664 + .flags = CLK_SET_RATE_PARENT, 665 665 + .ops = &clk_rcg2_ops, 698 666 }; 699 667 700 668 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { ··· 705 669 .hid_width = 5, 706 670 .parent_map = gcc_parent_map_0, 707 671 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 708 708 - .clkr.hw.init = &(struct clk_init_data){ 709 709 - .name = "gcc_qupv3_wrap2_s0_clk_src", 710 710 - .parent_data = gcc_parents_0, 711 711 - .num_parents = ARRAY_SIZE(gcc_parents_0), 712 712 - .flags = CLK_SET_RATE_PARENT, 713 713 - .ops = &clk_rcg2_ops, 714 714 - }, 672 672 + .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 673 673 + }; 674 674 + 675 675 + static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 676 676 + .name = "gcc_qupv3_wrap2_s1_clk_src", 677 677 + .parent_data = gcc_parents_0, 678 678 + .num_parents = ARRAY_SIZE(gcc_parents_0), 679 679 + .flags = CLK_SET_RATE_PARENT, 680 680 + .ops = &clk_rcg2_ops, 715 681 }; 716 682 717 683 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { ··· 722 684 .hid_width = 5, 723 685 .parent_map = gcc_parent_map_0, 724 686 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 725 725 - .clkr.hw.init = &(struct clk_init_data){ 726 726 - .name = "gcc_qupv3_wrap2_s1_clk_src", 727 727 - .parent_data = gcc_parents_0, 728 728 - .num_parents = ARRAY_SIZE(gcc_parents_0), 729 729 - .flags = CLK_SET_RATE_PARENT, 730 730 - .ops = &clk_rcg2_ops, 731 731 - }, 687 687 + .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 688 688 + }; 689 689 + 690 690 + static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 691 691 + .name = "gcc_qupv3_wrap2_s2_clk_src", 692 692 + .parent_data = gcc_parents_0, 693 693 + .num_parents = ARRAY_SIZE(gcc_parents_0), 694 694 + .flags = CLK_SET_RATE_PARENT, 695 695 + .ops = &clk_rcg2_ops, 732 696 }; 733 697 734 698 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { ··· 739 699 .hid_width = 5, 740 700 .parent_map = gcc_parent_map_0, 741 701 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 742 742 - .clkr.hw.init = &(struct clk_init_data){ 743 743 - .name = "gcc_qupv3_wrap2_s2_clk_src", 744 744 - .parent_data = gcc_parents_0, 745 745 - .num_parents = ARRAY_SIZE(gcc_parents_0), 746 746 - .flags = CLK_SET_RATE_PARENT, 747 747 - .ops = &clk_rcg2_ops, 748 748 - }, 702 702 + .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 703 703 + }; 704 704 + 705 705 + static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 706 706 + .name = "gcc_qupv3_wrap2_s3_clk_src", 707 707 + .parent_data = gcc_parents_0, 708 708 + .num_parents = ARRAY_SIZE(gcc_parents_0), 709 709 + .flags = CLK_SET_RATE_PARENT, 710 710 + .ops = &clk_rcg2_ops, 749 711 }; 750 712 751 713 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { ··· 756 714 .hid_width = 5, 757 715 .parent_map = gcc_parent_map_0, 758 716 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 759 759 - .clkr.hw.init = &(struct clk_init_data){ 760 760 - .name = "gcc_qupv3_wrap2_s3_clk_src", 761 761 - .parent_data = gcc_parents_0, 762 762 - .num_parents = ARRAY_SIZE(gcc_parents_0), 763 763 - .flags = CLK_SET_RATE_PARENT, 764 764 - .ops = &clk_rcg2_ops, 765 765 - }, 717 717 + .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 718 718 + }; 719 719 + 720 720 + static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 721 721 + .name = "gcc_qupv3_wrap2_s4_clk_src", 722 722 + .parent_data = gcc_parents_0, 723 723 + .num_parents = ARRAY_SIZE(gcc_parents_0), 724 724 + .flags = CLK_SET_RATE_PARENT, 725 725 + .ops = &clk_rcg2_ops, 766 726 }; 767 727 768 728 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { ··· 773 729 .hid_width = 5, 774 730 .parent_map = gcc_parent_map_0, 775 731 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 776 776 - .clkr.hw.init = &(struct clk_init_data){ 777 777 - .name = "gcc_qupv3_wrap2_s4_clk_src", 778 778 - .parent_data = gcc_parents_0, 779 779 - .num_parents = ARRAY_SIZE(gcc_parents_0), 780 780 - .flags = CLK_SET_RATE_PARENT, 781 781 - .ops = &clk_rcg2_ops, 782 782 - }, 732 732 + .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 733 733 + }; 734 734 + 735 735 + static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 736 736 + .name = "gcc_qupv3_wrap2_s5_clk_src", 737 737 + .parent_data = gcc_parents_0, 738 738 + .num_parents = ARRAY_SIZE(gcc_parents_0), 739 739 + .flags = CLK_SET_RATE_PARENT, 740 740 + .ops = &clk_rcg2_ops, 783 741 }; 784 742 785 743 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { ··· 790 744 .hid_width = 5, 791 745 .parent_map = gcc_parent_map_0, 792 746 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 793 793 - .clkr.hw.init = &(struct clk_init_data){ 794 794 - .name = "gcc_qupv3_wrap2_s5_clk_src", 795 795 - .parent_data = gcc_parents_0, 796 796 - .num_parents = ARRAY_SIZE(gcc_parents_0), 797 797 - .flags = CLK_SET_RATE_PARENT, 798 798 - .ops = &clk_rcg2_ops, 799 799 - }, 747 747 + .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 800 748 }; 801 749 802 750 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { ··· 3778 3738 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3779 3739 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3780 3740 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3741 3741 + [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, 3742 3742 + [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, 3743 3743 + [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, 3781 3744 }; 3782 3745 3783 3746 static struct gdsc *gcc_sm8150_gdscs[] = { ··· 3791 3748 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3792 3749 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3793 3750 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3751 3751 + }; 3752 3752 + 3753 3753 + static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3754 3754 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3755 3755 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3756 3756 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3757 3757 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3758 3758 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3759 3759 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3760 3760 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3761 3761 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3762 3762 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3763 3763 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3764 3764 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3765 3765 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3766 3766 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3767 3767 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3768 3768 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3769 3769 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3770 3770 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3771 3771 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3772 3772 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3773 3773 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3794 3774 }; 3795 3775 3796 3776 static const struct regmap_config gcc_sm8150_regmap_config = { ··· 3843 3777 static int gcc_sm8150_probe(struct platform_device *pdev) 3844 3778 { 3845 3779 struct regmap *regmap; 3780 3780 + int ret; 3846 3781 3847 3782 regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); 3848 3783 if (IS_ERR(regmap)) ··· 3852 3785 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 3853 3786 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3854 3787 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3788 3788 + 3789 3789 + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3790 3790 + ARRAY_SIZE(gcc_dfs_clocks)); 3791 3791 + if (ret) 3792 3792 + dev_err_probe(&pdev->dev, ret, "Failed to register with DFS!\n"); 3855 3793 3856 3794 return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); 3857 3795 }

+9 -14

drivers/clk/qcom/gcc-sm8250.c

reviewed

··· 3576 3576 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3577 3577 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3578 3578 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3579 3579 - [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 }, 3580 3580 - [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 }, 3579 3579 + [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, .bit = 2, .udelay = 150 }, 3580 3580 + [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, .bit = 2, .udelay = 150 }, 3581 3581 }; 3582 3582 3583 3583 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { ··· 3643 3643 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3644 3644 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3645 3645 3646 3646 - /* 3647 3647 - * Keep the clocks always-ON 3648 3648 - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, 3649 3649 - * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, 3650 3650 - * GCC_SYS_NOC_CPUSS_AHB_CLK 3651 3651 - */ 3652 3652 - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 3653 3653 - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 3654 3654 - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 3655 3655 - regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); 3656 3656 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3657 3657 - regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); 3646 3646 + /* Keep some clocks always-on */ 3647 3647 + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ 3648 3648 + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ 3649 3649 + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ 3650 3650 + qcom_branch_set_clk_en(regmap, 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */ 3651 3651 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3652 3652 + qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ 3658 3653 3659 3654 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3660 3655 ARRAY_SIZE(gcc_dfs_clocks));

+10 -14

drivers/clk/qcom/gcc-sm8350.c

reviewed

··· 3743 3743 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3744 3744 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3745 3745 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3746 3746 - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 }, 3747 3747 - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 }, 3746 3746 + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 }, 3747 3747 + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 }, 3748 3748 [GCC_VIDEO_BCR] = { 0x28000 }, 3749 3749 }; 3750 3750 ··· 3806 3806 return PTR_ERR(regmap); 3807 3807 } 3808 3808 3809 3809 - /* 3810 3810 - * Keep the critical clock always-On 3811 3811 - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, 3812 3812 - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK 3813 3813 - */ 3814 3814 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3815 3815 - regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); 3816 3816 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3817 3817 - regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); 3818 3818 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3819 3819 - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 3820 3820 - regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); 3809 3809 + /* Keep some clocks always-on */ 3810 3810 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 3811 3811 + qcom_branch_set_clk_en(regmap, 0x26018); /* GCC_CAMERA_XO_CLK */ 3812 3812 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 3813 3813 + qcom_branch_set_clk_en(regmap, 0x2701c); /* GCC_DISP_XO_CLK */ 3814 3814 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3815 3815 + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ 3816 3816 + qcom_branch_set_clk_en(regmap, 0x28020); /* GCC_VIDEO_XO_CLK */ 3821 3817 3822 3818 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 3823 3819 if (ret)

+10 -15

drivers/clk/qcom/gcc-sm8450.c

reviewed

··· 3202 3202 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 3203 3203 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 3204 3204 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 3205 3205 - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 }, 3206 3206 - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 }, 3205 3205 + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 }, 3206 3206 + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 }, 3207 3207 [GCC_VIDEO_BCR] = { 0x42000 }, 3208 3208 }; 3209 3209 ··· 3280 3280 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3281 3281 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3282 3282 3283 3283 - /* 3284 3284 - * Keep the critical clock always-On 3285 3285 - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3286 3286 - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3287 3287 - * gcc_video_xo_clk 3288 3288 - */ 3289 3289 - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); 3290 3290 - regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); 3291 3291 - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); 3292 3292 - regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); 3293 3293 - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); 3294 3294 - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); 3295 3295 - regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); 3283 3283 + /* Keep some clocks always-on */ 3284 3284 + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ 3285 3285 + qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */ 3286 3286 + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ 3287 3287 + qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */ 3288 3288 + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ 3289 3289 + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ 3290 3290 + qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ 3296 3291 3297 3292 return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); 3298 3293 }

+10 -15

drivers/clk/qcom/gcc-sm8550.c

reviewed

··· 3276 3276 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3277 3277 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3278 3278 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3279 3279 - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3280 3280 - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 }, 3279 3279 + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 }, 3280 3280 + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 }, 3281 3281 [GCC_VIDEO_BCR] = { 0x32000 }, 3282 3282 }; 3283 3283 ··· 3352 3352 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3353 3353 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3354 3354 3355 3355 - /* 3356 3356 - * Keep the critical clock always-On 3357 3357 - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3358 3358 - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3359 3359 - * gcc_video_xo_clk 3360 3360 - */ 3361 3361 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3362 3362 - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); 3363 3363 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3364 3364 - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); 3365 3365 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3366 3366 - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); 3367 3367 - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); 3355 3355 + /* Keep some clocks always-on */ 3356 3356 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 3357 3357 + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 3358 3358 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 3359 3359 + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 3360 3360 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3361 3361 + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 3362 3362 + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 3368 3363 3369 3364 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 3370 3365 regmap_write(regmap, 0x52024, 0x0);

+10 -10

drivers/clk/qcom/gcc-sm8650.c

reviewed

··· 3734 3734 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3735 3735 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3736 3736 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3737 3737 - [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3738 3738 - [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 }, 3737 3737 + [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 }, 3738 3738 + [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 }, 3739 3739 [GCC_VIDEO_BCR] = { 0x32000 }, 3740 3740 }; 3741 3741 ··· 3808 3808 if (ret) 3809 3809 return ret; 3810 3810 3811 3811 - /* Keep the critical clock always-On */ 3812 3812 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ 3813 3813 - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */ 3814 3814 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */ 3815 3815 - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ 3816 3816 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */ 3817 3817 - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */ 3818 3818 - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */ 3811 3811 + /* Keep some clocks always-on */ 3812 3812 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 3813 3813 + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 3814 3814 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 3815 3815 + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 3816 3816 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3817 3817 + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 3818 3818 + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 3819 3819 3820 3820 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3821 3821

+8 -8

drivers/clk/qcom/gcc-x1e80100.c

reviewed

··· 6769 6769 if (ret) 6770 6770 return ret; 6771 6771 6772 6772 - /* Keep the critical clock always-On */ 6773 6773 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ 6774 6774 - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */ 6775 6775 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */ 6776 6776 - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ 6777 6777 - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */ 6778 6778 - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */ 6779 6779 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */ 6772 6772 + /* Keep some clocks always-on */ 6773 6773 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 6774 6774 + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 6775 6775 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 6776 6776 + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 6777 6777 + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 6778 6778 + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 6779 6779 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 6780 6780 6781 6781 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 6782 6782 regmap_write(regmap, 0x52224, 0x0);

+10 -2

drivers/clk/qcom/gdsc.c

reviewed

··· 557 557 */ 558 558 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) 559 559 { 560 560 - /* Do nothing but give genpd the impression that we were successful */ 561 561 - return 0; 560 560 + struct gdsc *sc = domain_to_gdsc(domain); 561 561 + int ret = 0; 562 562 + 563 563 + /* Enable the parent supply, when controlled through the regulator framework. */ 564 564 + if (sc->rsupply) 565 565 + ret = regulator_enable(sc->rsupply); 566 566 + 567 567 + /* Do nothing with the GDSC itself */ 568 568 + 569 569 + return ret; 562 570 } 563 571 EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);

+1 -11

drivers/clk/qcom/gpucc-sa8775p.c

reviewed

··· 609 609 }, 610 610 }; 611 611 612 612 - static int __init gpu_cc_sa8775p_init(void) 613 613 - { 614 614 - return platform_driver_register(&gpu_cc_sa8775p_driver); 615 615 - } 616 616 - subsys_initcall(gpu_cc_sa8775p_init); 617 617 - 618 618 - static void __exit gpu_cc_sa8775p_exit(void) 619 619 - { 620 620 - platform_driver_unregister(&gpu_cc_sa8775p_driver); 621 621 - } 622 622 - module_exit(gpu_cc_sa8775p_exit); 612 612 + module_platform_driver(gpu_cc_sa8775p_driver); 623 613 624 614 MODULE_DESCRIPTION("SA8775P GPUCC driver"); 625 615 MODULE_LICENSE("GPL");

+1 -11

drivers/clk/qcom/gpucc-sc7180.c

reviewed

··· 252 252 }, 253 253 }; 254 254 255 255 - static int __init gpu_cc_sc7180_init(void) 256 256 - { 257 257 - return platform_driver_register(&gpu_cc_sc7180_driver); 258 258 - } 259 259 - subsys_initcall(gpu_cc_sc7180_init); 260 260 - 261 261 - static void __exit gpu_cc_sc7180_exit(void) 262 262 - { 263 263 - platform_driver_unregister(&gpu_cc_sc7180_driver); 264 264 - } 265 265 - module_exit(gpu_cc_sc7180_exit); 255 255 + module_platform_driver(gpu_cc_sc7180_driver); 266 256 267 257 MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver"); 268 258 MODULE_LICENSE("GPL v2");

+4 -17

drivers/clk/qcom/gpucc-sc7280.c

reviewed

··· 457 457 458 458 clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 459 459 460 460 - /* 461 461 - * Keep the clocks always-ON 462 462 - * GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK 463 463 - */ 464 464 - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); 465 465 - regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0)); 460 460 + /* Keep some clocks always-on */ 461 461 + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ 462 462 + qcom_branch_set_clk_en(regmap, 0x1098); /* GPUCC_CX_GMU_CLK */ 466 463 regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13)); 467 464 468 465 return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap); ··· 473 476 }, 474 477 }; 475 478 476 476 - static int __init gpu_cc_sc7280_init(void) 477 477 - { 478 478 - return platform_driver_register(&gpu_cc_sc7280_driver); 479 479 - } 480 480 - subsys_initcall(gpu_cc_sc7280_init); 481 481 - 482 482 - static void __exit gpu_cc_sc7280_exit(void) 483 483 - { 484 484 - platform_driver_unregister(&gpu_cc_sc7280_driver); 485 485 - } 486 486 - module_exit(gpu_cc_sc7280_exit); 479 479 + module_platform_driver(gpu_cc_sc7280_driver); 487 480 488 481 MODULE_DESCRIPTION("QTI GPU_CC SC7280 Driver"); 489 482 MODULE_LICENSE("GPL v2");

+4 -6

drivers/clk/qcom/gpucc-sc8280xp.c

reviewed

··· 399 399 }, 400 400 .pwrsts = PWRSTS_OFF_ON, 401 401 .flags = CLAMP_IO | RETAIN_FF_ENABLE, 402 402 + .supply = "vdd-gfx", 402 403 }; 403 404 404 405 static struct gdsc *gpu_cc_sc8280xp_gdscs[] = { ··· 445 444 clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 446 445 clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 447 446 448 448 - /* 449 449 - * Keep the clocks always-ON 450 450 - * GPU_CC_CB_CLK, GPU_CC_CXO_CLK 451 451 - */ 452 452 - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); 453 453 - regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0)); 447 447 + /* Keep some clocks always-on */ 448 448 + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ 449 449 + qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */ 454 450 455 451 ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); 456 452 pm_runtime_put(&pdev->dev);

+1 -11

drivers/clk/qcom/gpucc-sdm845.c

reviewed

··· 203 203 }, 204 204 }; 205 205 206 206 - static int __init gpu_cc_sdm845_init(void) 207 207 - { 208 208 - return platform_driver_register(&gpu_cc_sdm845_driver); 209 209 - } 210 210 - subsys_initcall(gpu_cc_sdm845_init); 211 211 - 212 212 - static void __exit gpu_cc_sdm845_exit(void) 213 213 - { 214 214 - platform_driver_unregister(&gpu_cc_sdm845_driver); 215 215 - } 216 216 - module_exit(gpu_cc_sdm845_exit); 206 206 + module_platform_driver(gpu_cc_sdm845_driver); 217 207 218 208 MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver"); 219 209 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/gpucc-sm8150.c

reviewed

··· 315 315 }, 316 316 }; 317 317 318 318 - static int __init gpu_cc_sm8150_init(void) 319 319 - { 320 320 - return platform_driver_register(&gpu_cc_sm8150_driver); 321 321 - } 322 322 - subsys_initcall(gpu_cc_sm8150_init); 323 323 - 324 324 - static void __exit gpu_cc_sm8150_exit(void) 325 325 - { 326 326 - platform_driver_unregister(&gpu_cc_sm8150_driver); 327 327 - } 328 328 - module_exit(gpu_cc_sm8150_exit); 318 318 + module_platform_driver(gpu_cc_sm8150_driver); 329 319 330 320 MODULE_DESCRIPTION("QTI GPUCC SM8150 Driver"); 331 321 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/gpucc-sm8250.c

reviewed

··· 331 331 }, 332 332 }; 333 333 334 334 - static int __init gpu_cc_sm8250_init(void) 335 335 - { 336 336 - return platform_driver_register(&gpu_cc_sm8250_driver); 337 337 - } 338 338 - subsys_initcall(gpu_cc_sm8250_init); 339 339 - 340 340 - static void __exit gpu_cc_sm8250_exit(void) 341 341 - { 342 342 - platform_driver_unregister(&gpu_cc_sm8250_driver); 343 343 - } 344 344 - module_exit(gpu_cc_sm8250_exit); 334 334 + module_platform_driver(gpu_cc_sm8250_driver); 345 335 346 336 MODULE_DESCRIPTION("QTI GPU_CC SM8250 Driver"); 347 337 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/gpucc-sm8350.c

reviewed

··· 621 621 }, 622 622 }; 623 623 624 624 - static int __init gpu_cc_sm8350_init(void) 625 625 - { 626 626 - return platform_driver_register(&gpu_cc_sm8350_driver); 627 627 - } 628 628 - subsys_initcall(gpu_cc_sm8350_init); 629 629 - 630 630 - static void __exit gpu_cc_sm8350_exit(void) 631 631 - { 632 632 - platform_driver_unregister(&gpu_cc_sm8350_driver); 633 633 - } 634 634 - module_exit(gpu_cc_sm8350_exit); 624 624 + module_platform_driver(gpu_cc_sm8350_driver); 635 625 636 626 MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); 637 627 MODULE_LICENSE("GPL v2");

+4 -18

drivers/clk/qcom/gpucc-sm8550.c

reviewed

··· 575 575 clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 576 576 clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 577 577 578 578 - /* 579 579 - * Keep clocks always enabled: 580 580 - * gpu_cc_cxo_aon_clk 581 581 - * gpu_cc_demet_clk 582 582 - */ 583 583 - regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0)); 584 584 - regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0)); 578 578 + /* Keep some clocks always-on */ 579 579 + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ 580 580 + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ 585 581 586 582 return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); 587 583 } ··· 590 594 }, 591 595 }; 592 596 593 593 - static int __init gpu_cc_sm8550_init(void) 594 594 - { 595 595 - return platform_driver_register(&gpu_cc_sm8550_driver); 596 596 - } 597 597 - subsys_initcall(gpu_cc_sm8550_init); 598 598 - 599 599 - static void __exit gpu_cc_sm8550_exit(void) 600 600 - { 601 601 - platform_driver_unregister(&gpu_cc_sm8550_driver); 602 602 - } 603 603 - module_exit(gpu_cc_sm8550_exit); 597 597 + module_platform_driver(gpu_cc_sm8550_driver); 604 598 605 599 MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver"); 606 600 MODULE_LICENSE("GPL");

+656

drivers/clk/qcom/gpucc-x1e80100.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 + */ 5 5 + 6 6 + #include <linux/clk-provider.h> 7 7 + #include <linux/mod_devicetable.h> 8 8 + #include <linux/module.h> 9 9 + #include <linux/platform_device.h> 10 10 + #include <linux/regmap.h> 11 11 + 12 12 + #include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 13 13 + #include <dt-bindings/reset/qcom,x1e80100-gpucc.h> 14 14 + 15 15 + #include "clk-alpha-pll.h" 16 16 + #include "clk-branch.h" 17 17 + #include "clk-rcg.h" 18 18 + #include "clk-regmap.h" 19 19 + #include "clk-regmap-divider.h" 20 20 + #include "clk-regmap-mux.h" 21 21 + #include "gdsc.h" 22 22 + #include "reset.h" 23 23 + 24 24 + enum { 25 25 + DT_BI_TCXO, 26 26 + DT_GPLL0_OUT_MAIN, 27 27 + DT_GPLL0_OUT_MAIN_DIV, 28 28 + }; 29 29 + 30 30 + enum { 31 31 + P_BI_TCXO, 32 32 + P_GPLL0_OUT_MAIN, 33 33 + P_GPLL0_OUT_MAIN_DIV, 34 34 + P_GPU_CC_PLL0_OUT_MAIN, 35 35 + P_GPU_CC_PLL1_OUT_MAIN, 36 36 + }; 37 37 + 38 38 + static const struct pll_vco lucid_ole_vco[] = { 39 39 + { 249600000, 2300000000, 0 }, 40 40 + }; 41 41 + 42 42 + static const struct pll_vco zonda_ole_vco[] = { 43 43 + { 700000000, 3600000000, 0 }, 44 44 + }; 45 45 + 46 46 + static const struct alpha_pll_config gpu_cc_pll0_config = { 47 47 + .l = 0x29, 48 48 + .alpha = 0xa000, 49 49 + .config_ctl_val = 0x08240800, 50 50 + .config_ctl_hi_val = 0x05008001, 51 51 + .config_ctl_hi1_val = 0x00000000, 52 52 + .config_ctl_hi2_val = 0x00000000, 53 53 + .user_ctl_val = 0x00000000, 54 54 + .user_ctl_hi_val = 0x02000000, 55 55 + }; 56 56 + 57 57 + static struct clk_alpha_pll gpu_cc_pll0 = { 58 58 + .offset = 0x0, 59 59 + .vco_table = zonda_ole_vco, 60 60 + .num_vco = ARRAY_SIZE(zonda_ole_vco), 61 61 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], 62 62 + .clkr = { 63 63 + .hw.init = &(const struct clk_init_data) { 64 64 + .name = "gpu_cc_pll0", 65 65 + .parent_data = &(const struct clk_parent_data) { 66 66 + .index = DT_BI_TCXO, 67 67 + }, 68 68 + .num_parents = 1, 69 69 + .ops = &clk_alpha_pll_zonda_ole_ops, 70 70 + }, 71 71 + }, 72 72 + }; 73 73 + 74 74 + static const struct alpha_pll_config gpu_cc_pll1_config = { 75 75 + .l = 0x16, 76 76 + .alpha = 0xeaaa, 77 77 + .config_ctl_val = 0x20485699, 78 78 + .config_ctl_hi_val = 0x00182261, 79 79 + .config_ctl_hi1_val = 0x82aa299c, 80 80 + .test_ctl_val = 0x00000000, 81 81 + .test_ctl_hi_val = 0x00000003, 82 82 + .test_ctl_hi1_val = 0x00009000, 83 83 + .test_ctl_hi2_val = 0x00000034, 84 84 + .user_ctl_val = 0x00000000, 85 85 + .user_ctl_hi_val = 0x00000005, 86 86 + }; 87 87 + 88 88 + static struct clk_alpha_pll gpu_cc_pll1 = { 89 89 + .offset = 0x1000, 90 90 + .vco_table = lucid_ole_vco, 91 91 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 92 92 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 93 93 + .clkr = { 94 94 + .hw.init = &(const struct clk_init_data) { 95 95 + .name = "gpu_cc_pll1", 96 96 + .parent_data = &(const struct clk_parent_data) { 97 97 + .index = DT_BI_TCXO, 98 98 + }, 99 99 + .num_parents = 1, 100 100 + .ops = &clk_alpha_pll_lucid_evo_ops, 101 101 + }, 102 102 + }, 103 103 + }; 104 104 + 105 105 + static const struct parent_map gpu_cc_parent_map_0[] = { 106 106 + { P_BI_TCXO, 0 }, 107 107 + { P_GPLL0_OUT_MAIN, 5 }, 108 108 + { P_GPLL0_OUT_MAIN_DIV, 6 }, 109 109 + }; 110 110 + 111 111 + static const struct clk_parent_data gpu_cc_parent_data_0[] = { 112 112 + { .index = DT_BI_TCXO }, 113 113 + { .index = DT_GPLL0_OUT_MAIN }, 114 114 + { .index = DT_GPLL0_OUT_MAIN_DIV }, 115 115 + }; 116 116 + 117 117 + static const struct parent_map gpu_cc_parent_map_1[] = { 118 118 + { P_BI_TCXO, 0 }, 119 119 + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 120 120 + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 121 121 + { P_GPLL0_OUT_MAIN, 5 }, 122 122 + { P_GPLL0_OUT_MAIN_DIV, 6 }, 123 123 + }; 124 124 + 125 125 + static const struct clk_parent_data gpu_cc_parent_data_1[] = { 126 126 + { .index = DT_BI_TCXO }, 127 127 + { .hw = &gpu_cc_pll0.clkr.hw }, 128 128 + { .hw = &gpu_cc_pll1.clkr.hw }, 129 129 + { .index = DT_GPLL0_OUT_MAIN }, 130 130 + { .index = DT_GPLL0_OUT_MAIN_DIV }, 131 131 + }; 132 132 + 133 133 + static const struct parent_map gpu_cc_parent_map_2[] = { 134 134 + { P_BI_TCXO, 0 }, 135 135 + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 136 136 + { P_GPLL0_OUT_MAIN, 5 }, 137 137 + { P_GPLL0_OUT_MAIN_DIV, 6 }, 138 138 + }; 139 139 + 140 140 + static const struct clk_parent_data gpu_cc_parent_data_2[] = { 141 141 + { .index = DT_BI_TCXO }, 142 142 + { .hw = &gpu_cc_pll1.clkr.hw }, 143 143 + { .index = DT_GPLL0_OUT_MAIN }, 144 144 + { .index = DT_GPLL0_OUT_MAIN_DIV }, 145 145 + }; 146 146 + 147 147 + static const struct parent_map gpu_cc_parent_map_3[] = { 148 148 + { P_BI_TCXO, 0 }, 149 149 + }; 150 150 + 151 151 + static const struct clk_parent_data gpu_cc_parent_data_3[] = { 152 152 + { .index = DT_BI_TCXO }, 153 153 + }; 154 154 + 155 155 + static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { 156 156 + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 157 157 + { } 158 158 + }; 159 159 + 160 160 + static struct clk_rcg2 gpu_cc_ff_clk_src = { 161 161 + .cmd_rcgr = 0x9474, 162 162 + .mnd_width = 0, 163 163 + .hid_width = 5, 164 164 + .parent_map = gpu_cc_parent_map_0, 165 165 + .freq_tbl = ftbl_gpu_cc_ff_clk_src, 166 166 + .clkr.hw.init = &(const struct clk_init_data) { 167 167 + .name = "gpu_cc_ff_clk_src", 168 168 + .parent_data = gpu_cc_parent_data_0, 169 169 + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 170 170 + .flags = CLK_SET_RATE_PARENT, 171 171 + .ops = &clk_rcg2_ops, 172 172 + }, 173 173 + }; 174 174 + 175 175 + static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 176 176 + F(19200000, P_BI_TCXO, 1, 0, 0), 177 177 + F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 178 178 + F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 179 179 + { } 180 180 + }; 181 181 + 182 182 + static struct clk_rcg2 gpu_cc_gmu_clk_src = { 183 183 + .cmd_rcgr = 0x9318, 184 184 + .mnd_width = 0, 185 185 + .hid_width = 5, 186 186 + .parent_map = gpu_cc_parent_map_1, 187 187 + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 188 188 + .clkr.hw.init = &(const struct clk_init_data) { 189 189 + .name = "gpu_cc_gmu_clk_src", 190 190 + .parent_data = gpu_cc_parent_data_1, 191 191 + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 192 192 + .flags = CLK_SET_RATE_PARENT, 193 193 + .ops = &clk_rcg2_shared_ops, 194 194 + }, 195 195 + }; 196 196 + 197 197 + static struct clk_rcg2 gpu_cc_hub_clk_src = { 198 198 + .cmd_rcgr = 0x93ec, 199 199 + .mnd_width = 0, 200 200 + .hid_width = 5, 201 201 + .parent_map = gpu_cc_parent_map_2, 202 202 + .freq_tbl = ftbl_gpu_cc_ff_clk_src, 203 203 + .clkr.hw.init = &(const struct clk_init_data) { 204 204 + .name = "gpu_cc_hub_clk_src", 205 205 + .parent_data = gpu_cc_parent_data_2, 206 206 + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), 207 207 + .flags = CLK_SET_RATE_PARENT, 208 208 + .ops = &clk_rcg2_ops, 209 209 + }, 210 210 + }; 211 211 + 212 212 + static struct clk_rcg2 gpu_cc_xo_clk_src = { 213 213 + .cmd_rcgr = 0x9010, 214 214 + .mnd_width = 0, 215 215 + .hid_width = 5, 216 216 + .parent_map = gpu_cc_parent_map_3, 217 217 + .freq_tbl = NULL, 218 218 + .clkr.hw.init = &(const struct clk_init_data) { 219 219 + .name = "gpu_cc_xo_clk_src", 220 220 + .parent_data = gpu_cc_parent_data_3, 221 221 + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), 222 222 + .flags = CLK_SET_RATE_PARENT, 223 223 + .ops = &clk_rcg2_ops, 224 224 + }, 225 225 + }; 226 226 + 227 227 + static struct clk_regmap_div gpu_cc_demet_div_clk_src = { 228 228 + .reg = 0x9054, 229 229 + .shift = 0, 230 230 + .width = 4, 231 231 + .clkr.hw.init = &(const struct clk_init_data) { 232 232 + .name = "gpu_cc_demet_div_clk_src", 233 233 + .parent_hws = (const struct clk_hw*[]) { 234 234 + &gpu_cc_xo_clk_src.clkr.hw, 235 235 + }, 236 236 + .num_parents = 1, 237 237 + .flags = CLK_SET_RATE_PARENT, 238 238 + .ops = &clk_regmap_div_ro_ops, 239 239 + }, 240 240 + }; 241 241 + 242 242 + static struct clk_regmap_div gpu_cc_xo_div_clk_src = { 243 243 + .reg = 0x9050, 244 244 + .shift = 0, 245 245 + .width = 4, 246 246 + .clkr.hw.init = &(const struct clk_init_data) { 247 247 + .name = "gpu_cc_xo_div_clk_src", 248 248 + .parent_hws = (const struct clk_hw*[]) { 249 249 + &gpu_cc_xo_clk_src.clkr.hw, 250 250 + }, 251 251 + .num_parents = 1, 252 252 + .flags = CLK_SET_RATE_PARENT, 253 253 + .ops = &clk_regmap_div_ro_ops, 254 254 + }, 255 255 + }; 256 256 + 257 257 + static struct clk_branch gpu_cc_ahb_clk = { 258 258 + .halt_reg = 0x911c, 259 259 + .halt_check = BRANCH_HALT_VOTED, 260 260 + .clkr = { 261 261 + .enable_reg = 0x911c, 262 262 + .enable_mask = BIT(0), 263 263 + .hw.init = &(const struct clk_init_data) { 264 264 + .name = "gpu_cc_ahb_clk", 265 265 + .parent_hws = (const struct clk_hw*[]) { 266 266 + &gpu_cc_hub_clk_src.clkr.hw, 267 267 + }, 268 268 + .num_parents = 1, 269 269 + .flags = CLK_SET_RATE_PARENT, 270 270 + .ops = &clk_branch2_ops, 271 271 + }, 272 272 + }, 273 273 + }; 274 274 + 275 275 + static struct clk_branch gpu_cc_crc_ahb_clk = { 276 276 + .halt_reg = 0x9120, 277 277 + .halt_check = BRANCH_HALT_VOTED, 278 278 + .clkr = { 279 279 + .enable_reg = 0x9120, 280 280 + .enable_mask = BIT(0), 281 281 + .hw.init = &(const struct clk_init_data) { 282 282 + .name = "gpu_cc_crc_ahb_clk", 283 283 + .parent_hws = (const struct clk_hw*[]) { 284 284 + &gpu_cc_hub_clk_src.clkr.hw, 285 285 + }, 286 286 + .num_parents = 1, 287 287 + .flags = CLK_SET_RATE_PARENT, 288 288 + .ops = &clk_branch2_ops, 289 289 + }, 290 290 + }, 291 291 + }; 292 292 + 293 293 + static struct clk_branch gpu_cc_cx_ff_clk = { 294 294 + .halt_reg = 0x914c, 295 295 + .halt_check = BRANCH_HALT, 296 296 + .clkr = { 297 297 + .enable_reg = 0x914c, 298 298 + .enable_mask = BIT(0), 299 299 + .hw.init = &(const struct clk_init_data) { 300 300 + .name = "gpu_cc_cx_ff_clk", 301 301 + .parent_hws = (const struct clk_hw*[]) { 302 302 + &gpu_cc_ff_clk_src.clkr.hw, 303 303 + }, 304 304 + .num_parents = 1, 305 305 + .flags = CLK_SET_RATE_PARENT, 306 306 + .ops = &clk_branch2_ops, 307 307 + }, 308 308 + }, 309 309 + }; 310 310 + 311 311 + static struct clk_branch gpu_cc_cx_gmu_clk = { 312 312 + .halt_reg = 0x913c, 313 313 + .halt_check = BRANCH_HALT_VOTED, 314 314 + .clkr = { 315 315 + .enable_reg = 0x913c, 316 316 + .enable_mask = BIT(0), 317 317 + .hw.init = &(const struct clk_init_data) { 318 318 + .name = "gpu_cc_cx_gmu_clk", 319 319 + .parent_hws = (const struct clk_hw*[]) { 320 320 + &gpu_cc_gmu_clk_src.clkr.hw, 321 321 + }, 322 322 + .num_parents = 1, 323 323 + .flags = CLK_SET_RATE_PARENT, 324 324 + .ops = &clk_branch2_aon_ops, 325 325 + }, 326 326 + }, 327 327 + }; 328 328 + 329 329 + static struct clk_branch gpu_cc_cxo_aon_clk = { 330 330 + .halt_reg = 0x9004, 331 331 + .halt_check = BRANCH_HALT_VOTED, 332 332 + .clkr = { 333 333 + .enable_reg = 0x9004, 334 334 + .enable_mask = BIT(0), 335 335 + .hw.init = &(const struct clk_init_data) { 336 336 + .name = "gpu_cc_cxo_aon_clk", 337 337 + .parent_hws = (const struct clk_hw*[]) { 338 338 + &gpu_cc_xo_clk_src.clkr.hw, 339 339 + }, 340 340 + .num_parents = 1, 341 341 + .flags = CLK_SET_RATE_PARENT, 342 342 + .ops = &clk_branch2_ops, 343 343 + }, 344 344 + }, 345 345 + }; 346 346 + 347 347 + static struct clk_branch gpu_cc_cxo_clk = { 348 348 + .halt_reg = 0x9144, 349 349 + .halt_check = BRANCH_HALT, 350 350 + .clkr = { 351 351 + .enable_reg = 0x9144, 352 352 + .enable_mask = BIT(0), 353 353 + .hw.init = &(const struct clk_init_data) { 354 354 + .name = "gpu_cc_cxo_clk", 355 355 + .parent_hws = (const struct clk_hw*[]) { 356 356 + &gpu_cc_xo_clk_src.clkr.hw, 357 357 + }, 358 358 + .num_parents = 1, 359 359 + .flags = CLK_SET_RATE_PARENT, 360 360 + .ops = &clk_branch2_ops, 361 361 + }, 362 362 + }, 363 363 + }; 364 364 + 365 365 + static struct clk_branch gpu_cc_demet_clk = { 366 366 + .halt_reg = 0x900c, 367 367 + .halt_check = BRANCH_HALT, 368 368 + .clkr = { 369 369 + .enable_reg = 0x900c, 370 370 + .enable_mask = BIT(0), 371 371 + .hw.init = &(const struct clk_init_data) { 372 372 + .name = "gpu_cc_demet_clk", 373 373 + .parent_hws = (const struct clk_hw*[]) { 374 374 + &gpu_cc_demet_div_clk_src.clkr.hw, 375 375 + }, 376 376 + .num_parents = 1, 377 377 + .flags = CLK_SET_RATE_PARENT, 378 378 + .ops = &clk_branch2_aon_ops, 379 379 + }, 380 380 + }, 381 381 + }; 382 382 + 383 383 + static struct clk_branch gpu_cc_freq_measure_clk = { 384 384 + .halt_reg = 0x9008, 385 385 + .halt_check = BRANCH_HALT, 386 386 + .clkr = { 387 387 + .enable_reg = 0x9008, 388 388 + .enable_mask = BIT(0), 389 389 + .hw.init = &(const struct clk_init_data) { 390 390 + .name = "gpu_cc_freq_measure_clk", 391 391 + .parent_hws = (const struct clk_hw*[]) { 392 392 + &gpu_cc_xo_div_clk_src.clkr.hw, 393 393 + }, 394 394 + .num_parents = 1, 395 395 + .flags = CLK_SET_RATE_PARENT, 396 396 + .ops = &clk_branch2_ops, 397 397 + }, 398 398 + }, 399 399 + }; 400 400 + 401 401 + static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { 402 402 + .halt_reg = 0x7000, 403 403 + .halt_check = BRANCH_HALT_VOTED, 404 404 + .clkr = { 405 405 + .enable_reg = 0x7000, 406 406 + .enable_mask = BIT(0), 407 407 + .hw.init = &(const struct clk_init_data) { 408 408 + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 409 409 + .ops = &clk_branch2_ops, 410 410 + }, 411 411 + }, 412 412 + }; 413 413 + 414 414 + static struct clk_branch gpu_cc_gx_gmu_clk = { 415 415 + .halt_reg = 0x90bc, 416 416 + .halt_check = BRANCH_HALT, 417 417 + .clkr = { 418 418 + .enable_reg = 0x90bc, 419 419 + .enable_mask = BIT(0), 420 420 + .hw.init = &(const struct clk_init_data) { 421 421 + .name = "gpu_cc_gx_gmu_clk", 422 422 + .parent_hws = (const struct clk_hw*[]) { 423 423 + &gpu_cc_gmu_clk_src.clkr.hw, 424 424 + }, 425 425 + .num_parents = 1, 426 426 + .flags = CLK_SET_RATE_PARENT, 427 427 + .ops = &clk_branch2_ops, 428 428 + }, 429 429 + }, 430 430 + }; 431 431 + 432 432 + static struct clk_branch gpu_cc_gx_vsense_clk = { 433 433 + .halt_reg = 0x90b0, 434 434 + .halt_check = BRANCH_HALT_VOTED, 435 435 + .clkr = { 436 436 + .enable_reg = 0x90b0, 437 437 + .enable_mask = BIT(0), 438 438 + .hw.init = &(const struct clk_init_data) { 439 439 + .name = "gpu_cc_gx_vsense_clk", 440 440 + .ops = &clk_branch2_ops, 441 441 + }, 442 442 + }, 443 443 + }; 444 444 + 445 445 + static struct clk_branch gpu_cc_hub_aon_clk = { 446 446 + .halt_reg = 0x93e8, 447 447 + .halt_check = BRANCH_HALT, 448 448 + .clkr = { 449 449 + .enable_reg = 0x93e8, 450 450 + .enable_mask = BIT(0), 451 451 + .hw.init = &(const struct clk_init_data) { 452 452 + .name = "gpu_cc_hub_aon_clk", 453 453 + .parent_hws = (const struct clk_hw*[]) { 454 454 + &gpu_cc_hub_clk_src.clkr.hw, 455 455 + }, 456 456 + .num_parents = 1, 457 457 + .flags = CLK_SET_RATE_PARENT, 458 458 + .ops = &clk_branch2_aon_ops, 459 459 + }, 460 460 + }, 461 461 + }; 462 462 + 463 463 + static struct clk_branch gpu_cc_hub_cx_int_clk = { 464 464 + .halt_reg = 0x9148, 465 465 + .halt_check = BRANCH_HALT_VOTED, 466 466 + .clkr = { 467 467 + .enable_reg = 0x9148, 468 468 + .enable_mask = BIT(0), 469 469 + .hw.init = &(const struct clk_init_data) { 470 470 + .name = "gpu_cc_hub_cx_int_clk", 471 471 + .parent_hws = (const struct clk_hw*[]) { 472 472 + &gpu_cc_hub_clk_src.clkr.hw, 473 473 + }, 474 474 + .num_parents = 1, 475 475 + .flags = CLK_SET_RATE_PARENT, 476 476 + .ops = &clk_branch2_aon_ops, 477 477 + }, 478 478 + }, 479 479 + }; 480 480 + 481 481 + static struct clk_branch gpu_cc_memnoc_gfx_clk = { 482 482 + .halt_reg = 0x9150, 483 483 + .halt_check = BRANCH_HALT_VOTED, 484 484 + .clkr = { 485 485 + .enable_reg = 0x9150, 486 486 + .enable_mask = BIT(0), 487 487 + .hw.init = &(const struct clk_init_data) { 488 488 + .name = "gpu_cc_memnoc_gfx_clk", 489 489 + .ops = &clk_branch2_ops, 490 490 + }, 491 491 + }, 492 492 + }; 493 493 + 494 494 + static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { 495 495 + .halt_reg = 0x9288, 496 496 + .halt_check = BRANCH_HALT, 497 497 + .clkr = { 498 498 + .enable_reg = 0x9288, 499 499 + .enable_mask = BIT(0), 500 500 + .hw.init = &(const struct clk_init_data) { 501 501 + .name = "gpu_cc_mnd1x_0_gfx3d_clk", 502 502 + .ops = &clk_branch2_ops, 503 503 + }, 504 504 + }, 505 505 + }; 506 506 + 507 507 + static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { 508 508 + .halt_reg = 0x928c, 509 509 + .halt_check = BRANCH_HALT, 510 510 + .clkr = { 511 511 + .enable_reg = 0x928c, 512 512 + .enable_mask = BIT(0), 513 513 + .hw.init = &(const struct clk_init_data) { 514 514 + .name = "gpu_cc_mnd1x_1_gfx3d_clk", 515 515 + .ops = &clk_branch2_ops, 516 516 + }, 517 517 + }, 518 518 + }; 519 519 + 520 520 + static struct clk_branch gpu_cc_sleep_clk = { 521 521 + .halt_reg = 0x9134, 522 522 + .halt_check = BRANCH_HALT_VOTED, 523 523 + .clkr = { 524 524 + .enable_reg = 0x9134, 525 525 + .enable_mask = BIT(0), 526 526 + .hw.init = &(const struct clk_init_data) { 527 527 + .name = "gpu_cc_sleep_clk", 528 528 + .ops = &clk_branch2_ops, 529 529 + }, 530 530 + }, 531 531 + }; 532 532 + 533 533 + static struct gdsc gpu_cx_gdsc = { 534 534 + .gdscr = 0x9108, 535 535 + .gds_hw_ctrl = 0x953c, 536 536 + .en_rest_wait_val = 0x2, 537 537 + .en_few_wait_val = 0x2, 538 538 + .clk_dis_wait_val = 0xf, 539 539 + .pd = { 540 540 + .name = "gpu_cx_gdsc", 541 541 + }, 542 542 + .pwrsts = PWRSTS_OFF_ON, 543 543 + .flags = VOTABLE | RETAIN_FF_ENABLE, 544 544 + }; 545 545 + 546 546 + static struct gdsc gpu_gx_gdsc = { 547 547 + .gdscr = 0x905c, 548 548 + .clamp_io_ctrl = 0x9504, 549 549 + .en_rest_wait_val = 0x2, 550 550 + .en_few_wait_val = 0x2, 551 551 + .clk_dis_wait_val = 0xf, 552 552 + .pd = { 553 553 + .name = "gpu_gx_gdsc", 554 554 + .power_on = gdsc_gx_do_nothing_enable, 555 555 + }, 556 556 + .pwrsts = PWRSTS_OFF_ON, 557 557 + .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR, 558 558 + }; 559 559 + 560 560 + static struct clk_regmap *gpu_cc_x1e80100_clocks[] = { 561 561 + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 562 562 + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 563 563 + [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, 564 564 + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 565 565 + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 566 566 + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 567 567 + [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, 568 568 + [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, 569 569 + [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, 570 570 + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, 571 571 + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 572 572 + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 573 573 + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, 574 574 + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, 575 575 + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 576 576 + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 577 577 + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 578 578 + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, 579 579 + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, 580 580 + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, 581 581 + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 582 582 + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 583 583 + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 584 584 + [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, 585 585 + [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr, 586 586 + }; 587 587 + 588 588 + static const struct qcom_reset_map gpu_cc_x1e80100_resets[] = { 589 589 + [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, 590 590 + [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, 591 591 + [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, 592 592 + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, 593 593 + [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, 594 594 + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, 595 595 + [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, 596 596 + [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, 597 597 + [GPUCC_GPU_CC_CB_BCR] = { 0x93a0 }, 598 598 + }; 599 599 + 600 600 + static struct gdsc *gpu_cc_x1e80100_gdscs[] = { 601 601 + [GPU_CX_GDSC] = &gpu_cx_gdsc, 602 602 + [GPU_GX_GDSC] = &gpu_gx_gdsc, 603 603 + }; 604 604 + 605 605 + static const struct regmap_config gpu_cc_x1e80100_regmap_config = { 606 606 + .reg_bits = 32, 607 607 + .reg_stride = 4, 608 608 + .val_bits = 32, 609 609 + .max_register = 0x9988, 610 610 + .fast_io = true, 611 611 + }; 612 612 + 613 613 + static const struct qcom_cc_desc gpu_cc_x1e80100_desc = { 614 614 + .config = &gpu_cc_x1e80100_regmap_config, 615 615 + .clks = gpu_cc_x1e80100_clocks, 616 616 + .num_clks = ARRAY_SIZE(gpu_cc_x1e80100_clocks), 617 617 + .resets = gpu_cc_x1e80100_resets, 618 618 + .num_resets = ARRAY_SIZE(gpu_cc_x1e80100_resets), 619 619 + .gdscs = gpu_cc_x1e80100_gdscs, 620 620 + .num_gdscs = ARRAY_SIZE(gpu_cc_x1e80100_gdscs), 621 621 + }; 622 622 + 623 623 + static const struct of_device_id gpu_cc_x1e80100_match_table[] = { 624 624 + { .compatible = "qcom,x1e80100-gpucc" }, 625 625 + { } 626 626 + }; 627 627 + MODULE_DEVICE_TABLE(of, gpu_cc_x1e80100_match_table); 628 628 + 629 629 + static int gpu_cc_x1e80100_probe(struct platform_device *pdev) 630 630 + { 631 631 + struct regmap *regmap; 632 632 + 633 633 + regmap = qcom_cc_map(pdev, &gpu_cc_x1e80100_desc); 634 634 + if (IS_ERR(regmap)) 635 635 + return PTR_ERR(regmap); 636 636 + 637 637 + clk_zonda_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 638 638 + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 639 639 + 640 640 + /* Keep clocks always enabled */ 641 641 + qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ 642 642 + 643 643 + return qcom_cc_really_probe(pdev, &gpu_cc_x1e80100_desc, regmap); 644 644 + } 645 645 + 646 646 + static struct platform_driver gpu_cc_x1e80100_driver = { 647 647 + .probe = gpu_cc_x1e80100_probe, 648 648 + .driver = { 649 649 + .name = "gpucc-x1e80100", 650 650 + .of_match_table = gpu_cc_x1e80100_match_table, 651 651 + }, 652 652 + }; 653 653 + module_platform_driver(gpu_cc_x1e80100_driver); 654 654 + 655 655 + MODULE_DESCRIPTION("QTI GPU Clock Controller X1E80100 Driver"); 656 656 + MODULE_LICENSE("GPL");

+2 -5

drivers/clk/qcom/lpasscorecc-sc7180.c

reviewed

··· 401 401 goto exit; 402 402 } 403 403 404 404 - /* 405 405 - * Keep the CLK always-ON 406 406 - * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK 407 407 - */ 408 408 - regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0)); 404 404 + /* Keep some clocks always-on */ 405 405 + qcom_branch_set_clk_en(regmap, 0x24000); /* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK */ 409 406 410 407 /* PLL settings */ 411 408 regmap_write(regmap, 0x1008, 0x20);

+2

drivers/clk/qcom/mmcc-apq8084.c

reviewed

··· 348 348 F(333430000, P_MMPLL1, 3.5, 0, 0), 349 349 F(400000000, P_MMPLL0, 2, 0, 0), 350 350 F(466800000, P_MMPLL1, 2.5, 0, 0), 351 351 + { } 351 352 }; 352 353 353 354 static struct clk_rcg2 mmss_axi_clk_src = { ··· 373 372 F(150000000, P_GPLL0, 4, 0, 0), 374 373 F(228570000, P_MMPLL0, 3.5, 0, 0), 375 374 F(320000000, P_MMPLL0, 2.5, 0, 0), 375 375 + { } 376 376 }; 377 377 378 378 static struct clk_rcg2 ocmemnoc_clk_src = {

+2

drivers/clk/qcom/mmcc-msm8974.c

reviewed

··· 290 290 F(291750000, P_MMPLL1, 4, 0, 0), 291 291 F(400000000, P_MMPLL0, 2, 0, 0), 292 292 F(466800000, P_MMPLL1, 2.5, 0, 0), 293 293 + { } 293 294 }; 294 295 295 296 static struct clk_rcg2 mmss_axi_clk_src = { ··· 315 314 F(150000000, P_GPLL0, 4, 0, 0), 316 315 F(291750000, P_MMPLL1, 4, 0, 0), 317 316 F(400000000, P_MMPLL0, 2, 0, 0), 317 317 + { } 318 318 }; 319 319 320 320 static struct clk_rcg2 ocmemnoc_clk_src = {

-140

drivers/clk/qcom/mss-sc7180.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0-only 2 2 - /* 3 3 - * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 4 - */ 5 5 - 6 6 - #include <linux/clk-provider.h> 7 7 - #include <linux/platform_device.h> 8 8 - #include <linux/module.h> 9 9 - #include <linux/pm_clock.h> 10 10 - #include <linux/pm_runtime.h> 11 11 - #include <linux/regmap.h> 12 12 - 13 13 - #include <dt-bindings/clock/qcom,mss-sc7180.h> 14 14 - 15 15 - #include "clk-regmap.h" 16 16 - #include "clk-branch.h" 17 17 - #include "common.h" 18 18 - 19 19 - static struct clk_branch mss_axi_nav_clk = { 20 20 - .halt_reg = 0x20bc, 21 21 - .halt_check = BRANCH_HALT, 22 22 - .clkr = { 23 23 - .enable_reg = 0x20bc, 24 24 - .enable_mask = BIT(0), 25 25 - .hw.init = &(struct clk_init_data){ 26 26 - .name = "mss_axi_nav_clk", 27 27 - .parent_data = &(const struct clk_parent_data){ 28 28 - .fw_name = "gcc_mss_nav_axi", 29 29 - }, 30 30 - .num_parents = 1, 31 31 - .ops = &clk_branch2_ops, 32 32 - }, 33 33 - }, 34 34 - }; 35 35 - 36 36 - static struct clk_branch mss_axi_crypto_clk = { 37 37 - .halt_reg = 0x20cc, 38 38 - .halt_check = BRANCH_HALT, 39 39 - .clkr = { 40 40 - .enable_reg = 0x20cc, 41 41 - .enable_mask = BIT(0), 42 42 - .hw.init = &(struct clk_init_data){ 43 43 - .name = "mss_axi_crypto_clk", 44 44 - .parent_data = &(const struct clk_parent_data){ 45 45 - .fw_name = "gcc_mss_mfab_axis", 46 46 - }, 47 47 - .num_parents = 1, 48 48 - .ops = &clk_branch2_ops, 49 49 - }, 50 50 - }, 51 51 - }; 52 52 - 53 53 - static const struct regmap_config mss_regmap_config = { 54 54 - .reg_bits = 32, 55 55 - .reg_stride = 4, 56 56 - .val_bits = 32, 57 57 - .fast_io = true, 58 58 - .max_register = 0x41aa0cc, 59 59 - }; 60 60 - 61 61 - static struct clk_regmap *mss_sc7180_clocks[] = { 62 62 - [MSS_AXI_CRYPTO_CLK] = &mss_axi_crypto_clk.clkr, 63 63 - [MSS_AXI_NAV_CLK] = &mss_axi_nav_clk.clkr, 64 64 - }; 65 65 - 66 66 - static const struct qcom_cc_desc mss_sc7180_desc = { 67 67 - .config = &mss_regmap_config, 68 68 - .clks = mss_sc7180_clocks, 69 69 - .num_clks = ARRAY_SIZE(mss_sc7180_clocks), 70 70 - }; 71 71 - 72 72 - static int mss_sc7180_probe(struct platform_device *pdev) 73 73 - { 74 74 - int ret; 75 75 - 76 76 - ret = devm_pm_runtime_enable(&pdev->dev); 77 77 - if (ret) 78 78 - return ret; 79 79 - 80 80 - ret = devm_pm_clk_create(&pdev->dev); 81 81 - if (ret) 82 82 - return ret; 83 83 - 84 84 - ret = pm_clk_add(&pdev->dev, "cfg_ahb"); 85 85 - if (ret < 0) { 86 86 - dev_err(&pdev->dev, "failed to acquire iface clock\n"); 87 87 - return ret; 88 88 - } 89 89 - 90 90 - ret = pm_runtime_resume_and_get(&pdev->dev); 91 91 - if (ret) 92 92 - return ret; 93 93 - 94 94 - ret = qcom_cc_probe(pdev, &mss_sc7180_desc); 95 95 - if (ret < 0) 96 96 - goto err_put_rpm; 97 97 - 98 98 - pm_runtime_put(&pdev->dev); 99 99 - 100 100 - return 0; 101 101 - 102 102 - err_put_rpm: 103 103 - pm_runtime_put_sync(&pdev->dev); 104 104 - 105 105 - return ret; 106 106 - } 107 107 - 108 108 - static const struct dev_pm_ops mss_sc7180_pm_ops = { 109 109 - SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 110 110 - }; 111 111 - 112 112 - static const struct of_device_id mss_sc7180_match_table[] = { 113 113 - { .compatible = "qcom,sc7180-mss" }, 114 114 - { } 115 115 - }; 116 116 - MODULE_DEVICE_TABLE(of, mss_sc7180_match_table); 117 117 - 118 118 - static struct platform_driver mss_sc7180_driver = { 119 119 - .probe = mss_sc7180_probe, 120 120 - .driver = { 121 121 - .name = "sc7180-mss", 122 122 - .of_match_table = mss_sc7180_match_table, 123 123 - .pm = &mss_sc7180_pm_ops, 124 124 - }, 125 125 - }; 126 126 - 127 127 - static int __init mss_sc7180_init(void) 128 128 - { 129 129 - return platform_driver_register(&mss_sc7180_driver); 130 130 - } 131 131 - subsys_initcall(mss_sc7180_init); 132 132 - 133 133 - static void __exit mss_sc7180_exit(void) 134 134 - { 135 135 - platform_driver_unregister(&mss_sc7180_driver); 136 136 - } 137 137 - module_exit(mss_sc7180_exit); 138 138 - 139 139 - MODULE_DESCRIPTION("QTI MSS SC7180 Driver"); 140 140 - MODULE_LICENSE("GPL v2");

+14 -13

drivers/clk/qcom/reset.c

reviewed

··· 22 22 return 0; 23 23 } 24 24 25 25 - static int 26 26 - qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 25 25 + static int qcom_reset_set_assert(struct reset_controller_dev *rcdev, 26 26 + unsigned long id, bool assert) 27 27 { 28 28 struct qcom_reset_controller *rst; 29 29 const struct qcom_reset_map *map; ··· 33 33 map = &rst->reset_map[id]; 34 34 mask = map->bitmask ? map->bitmask : BIT(map->bit); 35 35 36 36 - return regmap_update_bits(rst->regmap, map->reg, mask, mask); 36 36 + regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0); 37 37 + 38 38 + /* Read back the register to ensure write completion, ignore the value */ 39 39 + regmap_read(rst->regmap, map->reg, &mask); 40 40 + 41 41 + return 0; 37 42 } 38 43 39 39 - static int 40 40 - qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 44 44 + static int qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 41 45 { 42 42 - struct qcom_reset_controller *rst; 43 43 - const struct qcom_reset_map *map; 44 44 - u32 mask; 46 46 + return qcom_reset_set_assert(rcdev, id, true); 47 47 + } 45 48 46 46 - rst = to_qcom_reset_controller(rcdev); 47 47 - map = &rst->reset_map[id]; 48 48 - mask = map->bitmask ? map->bitmask : BIT(map->bit); 49 49 - 50 50 - return regmap_update_bits(rst->regmap, map->reg, mask, 0); 49 49 + static int qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 50 50 + { 51 51 + return qcom_reset_set_assert(rcdev, id, false); 51 52 } 52 53 53 54 const struct reset_control_ops qcom_reset_ops = {

+1 -1

drivers/clk/qcom/reset.h

reviewed

··· 11 11 struct qcom_reset_map { 12 12 unsigned int reg; 13 13 u8 bit; 14 14 - u8 udelay; 14 14 + u16 udelay; 15 15 u32 bitmask; 16 16 }; 17 17

+285

drivers/clk/qcom/tcsrcc-x1e80100.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 + * Copyright (c) 2023, Linaro Limited 5 5 + */ 6 6 + 7 7 + #include <linux/clk-provider.h> 8 8 + #include <linux/mod_devicetable.h> 9 9 + #include <linux/module.h> 10 10 + #include <linux/platform_device.h> 11 11 + #include <linux/regmap.h> 12 12 + 13 13 + #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 14 14 + 15 15 + #include "clk-branch.h" 16 16 + #include "clk-regmap.h" 17 17 + #include "common.h" 18 18 + #include "reset.h" 19 19 + 20 20 + enum { 21 21 + DT_BI_TCXO_PAD, 22 22 + }; 23 23 + 24 24 + static struct clk_branch tcsr_edp_clkref_en = { 25 25 + .halt_reg = 0x15130, 26 26 + .halt_check = BRANCH_HALT_DELAY, 27 27 + .clkr = { 28 28 + .enable_reg = 0x15130, 29 29 + .enable_mask = BIT(0), 30 30 + .hw.init = &(const struct clk_init_data) { 31 31 + .name = "tcsr_edp_clkref_en", 32 32 + .ops = &clk_branch2_ops, 33 33 + }, 34 34 + }, 35 35 + }; 36 36 + 37 37 + static struct clk_branch tcsr_pcie_2l_4_clkref_en = { 38 38 + .halt_reg = 0x15100, 39 39 + .halt_check = BRANCH_HALT_DELAY, 40 40 + .clkr = { 41 41 + .enable_reg = 0x15100, 42 42 + .enable_mask = BIT(0), 43 43 + .hw.init = &(struct clk_init_data){ 44 44 + .name = "tcsr_pcie_2l_4_clkref_en", 45 45 + .parent_data = &(const struct clk_parent_data){ 46 46 + .index = DT_BI_TCXO_PAD, 47 47 + }, 48 48 + .num_parents = 1, 49 49 + .ops = &clk_branch2_ops, 50 50 + }, 51 51 + }, 52 52 + }; 53 53 + 54 54 + static struct clk_branch tcsr_pcie_2l_5_clkref_en = { 55 55 + .halt_reg = 0x15104, 56 56 + .halt_check = BRANCH_HALT_DELAY, 57 57 + .clkr = { 58 58 + .enable_reg = 0x15104, 59 59 + .enable_mask = BIT(0), 60 60 + .hw.init = &(struct clk_init_data){ 61 61 + .name = "tcsr_pcie_2l_5_clkref_en", 62 62 + .parent_data = &(const struct clk_parent_data){ 63 63 + .index = DT_BI_TCXO_PAD, 64 64 + }, 65 65 + .num_parents = 1, 66 66 + .ops = &clk_branch2_ops, 67 67 + }, 68 68 + }, 69 69 + }; 70 70 + 71 71 + static struct clk_branch tcsr_pcie_8l_clkref_en = { 72 72 + .halt_reg = 0x15108, 73 73 + .halt_check = BRANCH_HALT_DELAY, 74 74 + .clkr = { 75 75 + .enable_reg = 0x15108, 76 76 + .enable_mask = BIT(0), 77 77 + .hw.init = &(struct clk_init_data){ 78 78 + .name = "tcsr_pcie_8l_clkref_en", 79 79 + .parent_data = &(const struct clk_parent_data){ 80 80 + .index = DT_BI_TCXO_PAD, 81 81 + }, 82 82 + .num_parents = 1, 83 83 + .ops = &clk_branch2_ops, 84 84 + }, 85 85 + }, 86 86 + }; 87 87 + 88 88 + static struct clk_branch tcsr_usb3_mp0_clkref_en = { 89 89 + .halt_reg = 0x1510c, 90 90 + .halt_check = BRANCH_HALT_DELAY, 91 91 + .clkr = { 92 92 + .enable_reg = 0x1510c, 93 93 + .enable_mask = BIT(0), 94 94 + .hw.init = &(struct clk_init_data){ 95 95 + .name = "tcsr_usb3_mp0_clkref_en", 96 96 + .parent_data = &(const struct clk_parent_data){ 97 97 + .index = DT_BI_TCXO_PAD, 98 98 + }, 99 99 + .num_parents = 1, 100 100 + .ops = &clk_branch2_ops, 101 101 + }, 102 102 + }, 103 103 + }; 104 104 + 105 105 + static struct clk_branch tcsr_usb3_mp1_clkref_en = { 106 106 + .halt_reg = 0x15110, 107 107 + .halt_check = BRANCH_HALT_DELAY, 108 108 + .clkr = { 109 109 + .enable_reg = 0x15110, 110 110 + .enable_mask = BIT(0), 111 111 + .hw.init = &(struct clk_init_data){ 112 112 + .name = "tcsr_usb3_mp1_clkref_en", 113 113 + .parent_data = &(const struct clk_parent_data){ 114 114 + .index = DT_BI_TCXO_PAD, 115 115 + }, 116 116 + .num_parents = 1, 117 117 + .ops = &clk_branch2_ops, 118 118 + }, 119 119 + }, 120 120 + }; 121 121 + 122 122 + static struct clk_branch tcsr_usb2_1_clkref_en = { 123 123 + .halt_reg = 0x15114, 124 124 + .halt_check = BRANCH_HALT_DELAY, 125 125 + .clkr = { 126 126 + .enable_reg = 0x15114, 127 127 + .enable_mask = BIT(0), 128 128 + .hw.init = &(struct clk_init_data){ 129 129 + .name = "tcsr_usb2_1_clkref_en", 130 130 + .parent_data = &(const struct clk_parent_data){ 131 131 + .index = DT_BI_TCXO_PAD, 132 132 + }, 133 133 + .num_parents = 1, 134 134 + .ops = &clk_branch2_ops, 135 135 + }, 136 136 + }, 137 137 + }; 138 138 + 139 139 + static struct clk_branch tcsr_ufs_phy_clkref_en = { 140 140 + .halt_reg = 0x15118, 141 141 + .halt_check = BRANCH_HALT_DELAY, 142 142 + .clkr = { 143 143 + .enable_reg = 0x15118, 144 144 + .enable_mask = BIT(0), 145 145 + .hw.init = &(struct clk_init_data){ 146 146 + .name = "tcsr_ufs_phy_clkref_en", 147 147 + .parent_data = &(const struct clk_parent_data){ 148 148 + .index = DT_BI_TCXO_PAD, 149 149 + }, 150 150 + .num_parents = 1, 151 151 + .ops = &clk_branch2_ops, 152 152 + }, 153 153 + }, 154 154 + }; 155 155 + 156 156 + static struct clk_branch tcsr_usb4_1_clkref_en = { 157 157 + .halt_reg = 0x15120, 158 158 + .halt_check = BRANCH_HALT_DELAY, 159 159 + .clkr = { 160 160 + .enable_reg = 0x15120, 161 161 + .enable_mask = BIT(0), 162 162 + .hw.init = &(struct clk_init_data){ 163 163 + .name = "tcsr_usb4_1_clkref_en", 164 164 + .parent_data = &(const struct clk_parent_data){ 165 165 + .index = DT_BI_TCXO_PAD, 166 166 + }, 167 167 + .num_parents = 1, 168 168 + .ops = &clk_branch2_ops, 169 169 + }, 170 170 + }, 171 171 + }; 172 172 + 173 173 + static struct clk_branch tcsr_usb4_2_clkref_en = { 174 174 + .halt_reg = 0x15124, 175 175 + .halt_check = BRANCH_HALT_DELAY, 176 176 + .clkr = { 177 177 + .enable_reg = 0x15124, 178 178 + .enable_mask = BIT(0), 179 179 + .hw.init = &(struct clk_init_data){ 180 180 + .name = "tcsr_usb4_2_clkref_en", 181 181 + .parent_data = &(const struct clk_parent_data){ 182 182 + .index = DT_BI_TCXO_PAD, 183 183 + }, 184 184 + .num_parents = 1, 185 185 + .ops = &clk_branch2_ops, 186 186 + }, 187 187 + }, 188 188 + }; 189 189 + 190 190 + static struct clk_branch tcsr_usb2_2_clkref_en = { 191 191 + .halt_reg = 0x15128, 192 192 + .halt_check = BRANCH_HALT_DELAY, 193 193 + .clkr = { 194 194 + .enable_reg = 0x15128, 195 195 + .enable_mask = BIT(0), 196 196 + .hw.init = &(struct clk_init_data){ 197 197 + .name = "tcsr_usb2_2_clkref_en", 198 198 + .parent_data = &(const struct clk_parent_data){ 199 199 + .index = DT_BI_TCXO_PAD, 200 200 + }, 201 201 + .num_parents = 1, 202 202 + .ops = &clk_branch2_ops, 203 203 + }, 204 204 + }, 205 205 + }; 206 206 + 207 207 + static struct clk_branch tcsr_pcie_4l_clkref_en = { 208 208 + .halt_reg = 0x1512c, 209 209 + .halt_check = BRANCH_HALT_DELAY, 210 210 + .clkr = { 211 211 + .enable_reg = 0x1512c, 212 212 + .enable_mask = BIT(0), 213 213 + .hw.init = &(struct clk_init_data){ 214 214 + .name = "tcsr_pcie_4l_clkref_en", 215 215 + .parent_data = &(const struct clk_parent_data){ 216 216 + .index = DT_BI_TCXO_PAD, 217 217 + }, 218 218 + .num_parents = 1, 219 219 + .ops = &clk_branch2_ops, 220 220 + }, 221 221 + }, 222 222 + }; 223 223 + 224 224 + static struct clk_regmap *tcsr_cc_x1e80100_clocks[] = { 225 225 + [TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr, 226 226 + [TCSR_PCIE_2L_4_CLKREF_EN] = &tcsr_pcie_2l_4_clkref_en.clkr, 227 227 + [TCSR_PCIE_2L_5_CLKREF_EN] = &tcsr_pcie_2l_5_clkref_en.clkr, 228 228 + [TCSR_PCIE_8L_CLKREF_EN] = &tcsr_pcie_8l_clkref_en.clkr, 229 229 + [TCSR_USB3_MP0_CLKREF_EN] = &tcsr_usb3_mp0_clkref_en.clkr, 230 230 + [TCSR_USB3_MP1_CLKREF_EN] = &tcsr_usb3_mp1_clkref_en.clkr, 231 231 + [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr, 232 232 + [TCSR_UFS_PHY_CLKREF_EN] = &tcsr_ufs_phy_clkref_en.clkr, 233 233 + [TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr, 234 234 + [TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr, 235 235 + [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr, 236 236 + [TCSR_PCIE_4L_CLKREF_EN] = &tcsr_pcie_4l_clkref_en.clkr, 237 237 + }; 238 238 + 239 239 + static const struct regmap_config tcsr_cc_x1e80100_regmap_config = { 240 240 + .reg_bits = 32, 241 241 + .reg_stride = 4, 242 242 + .val_bits = 32, 243 243 + .max_register = 0x2f000, 244 244 + .fast_io = true, 245 245 + }; 246 246 + 247 247 + static const struct qcom_cc_desc tcsr_cc_x1e80100_desc = { 248 248 + .config = &tcsr_cc_x1e80100_regmap_config, 249 249 + .clks = tcsr_cc_x1e80100_clocks, 250 250 + .num_clks = ARRAY_SIZE(tcsr_cc_x1e80100_clocks), 251 251 + }; 252 252 + 253 253 + static const struct of_device_id tcsr_cc_x1e80100_match_table[] = { 254 254 + { .compatible = "qcom,x1e80100-tcsr" }, 255 255 + { } 256 256 + }; 257 257 + MODULE_DEVICE_TABLE(of, tcsr_cc_x1e80100_match_table); 258 258 + 259 259 + static int tcsr_cc_x1e80100_probe(struct platform_device *pdev) 260 260 + { 261 261 + return qcom_cc_probe(pdev, &tcsr_cc_x1e80100_desc); 262 262 + } 263 263 + 264 264 + static struct platform_driver tcsr_cc_x1e80100_driver = { 265 265 + .probe = tcsr_cc_x1e80100_probe, 266 266 + .driver = { 267 267 + .name = "tcsrcc-x1e80100", 268 268 + .of_match_table = tcsr_cc_x1e80100_match_table, 269 269 + }, 270 270 + }; 271 271 + 272 272 + static int __init tcsr_cc_x1e80100_init(void) 273 273 + { 274 274 + return platform_driver_register(&tcsr_cc_x1e80100_driver); 275 275 + } 276 276 + subsys_initcall(tcsr_cc_x1e80100_init); 277 277 + 278 278 + static void __exit tcsr_cc_x1e80100_exit(void) 279 279 + { 280 280 + platform_driver_unregister(&tcsr_cc_x1e80100_driver); 281 281 + } 282 282 + module_exit(tcsr_cc_x1e80100_exit); 283 283 + 284 284 + MODULE_DESCRIPTION("QTI TCSR Clock Controller X1E80100 Driver"); 285 285 + MODULE_LICENSE("GPL");

+1 -11

drivers/clk/qcom/videocc-sc7180.c

reviewed

··· 237 237 }, 238 238 }; 239 239 240 240 - static int __init video_cc_sc7180_init(void) 241 241 - { 242 242 - return platform_driver_register(&video_cc_sc7180_driver); 243 243 - } 244 244 - subsys_initcall(video_cc_sc7180_init); 245 245 - 246 246 - static void __exit video_cc_sc7180_exit(void) 247 247 - { 248 248 - platform_driver_unregister(&video_cc_sc7180_driver); 249 249 - } 250 250 - module_exit(video_cc_sc7180_exit); 240 240 + module_platform_driver(video_cc_sc7180_driver); 251 241 252 242 MODULE_LICENSE("GPL v2"); 253 243 MODULE_DESCRIPTION("QTI VIDEOCC SC7180 Driver");

+1 -11

drivers/clk/qcom/videocc-sc7280.c

reviewed

··· 309 309 }, 310 310 }; 311 311 312 312 - static int __init video_cc_sc7280_init(void) 313 313 - { 314 314 - return platform_driver_register(&video_cc_sc7280_driver); 315 315 - } 316 316 - subsys_initcall(video_cc_sc7280_init); 317 317 - 318 318 - static void __exit video_cc_sc7280_exit(void) 319 319 - { 320 320 - platform_driver_unregister(&video_cc_sc7280_driver); 321 321 - } 322 322 - module_exit(video_cc_sc7280_exit); 312 312 + module_platform_driver(video_cc_sc7280_driver); 323 313 324 314 MODULE_DESCRIPTION("QTI VIDEO_CC sc7280 Driver"); 325 315 MODULE_LICENSE("GPL v2");

+1 -11

drivers/clk/qcom/videocc-sdm845.c

reviewed

··· 340 340 }, 341 341 }; 342 342 343 343 - static int __init video_cc_sdm845_init(void) 344 344 - { 345 345 - return platform_driver_register(&video_cc_sdm845_driver); 346 346 - } 347 347 - subsys_initcall(video_cc_sdm845_init); 348 348 - 349 349 - static void __exit video_cc_sdm845_exit(void) 350 350 - { 351 351 - platform_driver_unregister(&video_cc_sdm845_driver); 352 352 - } 353 353 - module_exit(video_cc_sdm845_exit); 343 343 + module_platform_driver(video_cc_sdm845_driver); 354 344 355 345 MODULE_LICENSE("GPL v2");

+2 -12

drivers/clk/qcom/videocc-sm8150.c

reviewed

··· 215 215 }; 216 216 217 217 static const struct qcom_reset_map video_cc_sm8150_resets[] = { 218 218 - [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 }, 218 218 + [VIDEO_CC_MVSC_CORE_CLK_BCR] = { .reg = 0x850, .bit = 2, .udelay = 150 }, 219 219 [VIDEO_CC_INTERFACE_BCR] = { 0x8f0 }, 220 220 [VIDEO_CC_MVS0_BCR] = { 0x870 }, 221 221 [VIDEO_CC_MVS1_BCR] = { 0x8b0 }, ··· 277 277 }, 278 278 }; 279 279 280 280 - static int __init video_cc_sm8150_init(void) 281 281 - { 282 282 - return platform_driver_register(&video_cc_sm8150_driver); 283 283 - } 284 284 - subsys_initcall(video_cc_sm8150_init); 285 285 - 286 286 - static void __exit video_cc_sm8150_exit(void) 287 287 - { 288 288 - platform_driver_unregister(&video_cc_sm8150_driver); 289 289 - } 290 290 - module_exit(video_cc_sm8150_exit); 280 280 + module_platform_driver(video_cc_sm8150_driver); 291 281 292 282 MODULE_LICENSE("GPL v2"); 293 283 MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");

+6 -16

drivers/clk/qcom/videocc-sm8250.c

reviewed

··· 323 323 static const struct qcom_reset_map video_cc_sm8250_resets[] = { 324 324 [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 }, 325 325 [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 }, 326 326 - [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 }, 326 326 + [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, .bit = 2, .udelay = 150 }, 327 327 [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 }, 328 328 [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 }, 329 329 - [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 }, 329 329 + [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, .bit = 2, .udelay = 150 }, 330 330 [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 }, 331 331 }; 332 332 ··· 383 383 clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); 384 384 clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); 385 385 386 386 - /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */ 387 387 - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); 388 388 - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); 386 386 + /* Keep some clocks always-on */ 387 387 + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ 388 388 + qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */ 389 389 390 390 ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); 391 391 ··· 402 402 }, 403 403 }; 404 404 405 405 - static int __init video_cc_sm8250_init(void) 406 406 - { 407 407 - return platform_driver_register(&video_cc_sm8250_driver); 408 408 - } 409 409 - subsys_initcall(video_cc_sm8250_init); 410 410 - 411 411 - static void __exit video_cc_sm8250_exit(void) 412 412 - { 413 413 - platform_driver_unregister(&video_cc_sm8250_driver); 414 414 - } 415 415 - module_exit(video_cc_sm8250_exit); 405 405 + module_platform_driver(video_cc_sm8250_driver); 416 406 417 407 MODULE_LICENSE("GPL v2"); 418 408 MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver");

+5 -9

drivers/clk/qcom/videocc-sm8350.c

reviewed

··· 488 488 static const struct qcom_reset_map video_cc_sm8350_resets[] = { 489 489 [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 }, 490 490 [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 }, 491 491 - [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 }, 491 491 + [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0xc34, .bit = 2, .udelay = 400 }, 492 492 [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 }, 493 493 [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 }, 494 494 - [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 }, 494 494 + [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0xcd4, .bit = 2, .udelay = 400 }, 495 495 [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 }, 496 496 }; 497 497 ··· 558 558 clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); 559 559 clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); 560 560 561 561 - /* 562 562 - * Keep clocks always enabled: 563 563 - * video_cc_ahb_clk 564 564 - * video_cc_xo_clk 565 565 - */ 566 566 - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); 567 567 - regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0)); 561 561 + /* Keep some clocks always-on */ 562 562 + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ 563 563 + qcom_branch_set_clk_en(regmap, video_cc_xo_clk_cbcr); /* VIDEO_CC_XO_CLK */ 568 564 569 565 ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); 570 566 pm_runtime_put(&pdev->dev);

+7 -22

drivers/clk/qcom/videocc-sm8450.c

reviewed

··· 373 373 [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, 374 374 [CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc }, 375 375 [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 }, 376 376 - [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 }, 377 377 - [VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 }, 376 376 + [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, 377 377 + [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 }, 378 378 }; 379 379 380 380 static const struct regmap_config video_cc_sm8450_regmap_config = { ··· 423 423 clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); 424 424 clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); 425 425 426 426 - /* 427 427 - * Keep clocks always enabled: 428 428 - * video_cc_ahb_clk 429 429 - * video_cc_sleep_clk 430 430 - * video_cc_xo_clk 431 431 - */ 432 432 - regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0)); 433 433 - regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0)); 434 434 - regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0)); 426 426 + /* Keep some clocks always-on */ 427 427 + qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ 428 428 + qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ 429 429 + qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ 435 430 436 431 ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap); 437 432 ··· 443 448 }, 444 449 }; 445 450 446 446 - static int __init video_cc_sm8450_init(void) 447 447 - { 448 448 - return platform_driver_register(&video_cc_sm8450_driver); 449 449 - } 450 450 - subsys_initcall(video_cc_sm8450_init); 451 451 - 452 452 - static void __exit video_cc_sm8450_exit(void) 453 453 - { 454 454 - platform_driver_unregister(&video_cc_sm8450_driver); 455 455 - } 456 456 - module_exit(video_cc_sm8450_exit); 451 451 + module_platform_driver(video_cc_sm8450_driver); 457 452 458 453 MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver"); 459 454 MODULE_LICENSE("GPL");

+7 -22

drivers/clk/qcom/videocc-sm8550.c

reviewed

··· 378 378 [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, 379 379 [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 }, 380 380 [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, 381 381 - [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 }, 382 382 - [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 }, 381 381 + [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, 382 382 + [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, 383 383 }; 384 384 385 385 static const struct regmap_config video_cc_sm8550_regmap_config = { ··· 428 428 clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); 429 429 clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); 430 430 431 431 - /* 432 432 - * Keep clocks always enabled: 433 433 - * video_cc_ahb_clk 434 434 - * video_cc_sleep_clk 435 435 - * video_cc_xo_clk 436 436 - */ 437 437 - regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0)); 438 438 - regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0)); 439 439 - regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0)); 431 431 + /* Keep some clocks always-on */ 432 432 + qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ 433 433 + qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ 434 434 + qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ 440 435 441 436 ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); 442 437 ··· 448 453 }, 449 454 }; 450 455 451 451 - static int __init video_cc_sm8550_init(void) 452 452 - { 453 453 - return platform_driver_register(&video_cc_sm8550_driver); 454 454 - } 455 455 - subsys_initcall(video_cc_sm8550_init); 456 456 - 457 457 - static void __exit video_cc_sm8550_exit(void) 458 458 - { 459 459 - platform_driver_unregister(&video_cc_sm8550_driver); 460 460 - } 461 461 - module_exit(video_cc_sm8550_exit); 456 456 + module_platform_driver(video_cc_sm8550_driver); 462 457 463 458 MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver"); 464 459 MODULE_LICENSE("GPL");

+2 -4

drivers/clk/starfive/clk-starfive-jh7110-isp.c

reviewed

··· 202 202 return ret; 203 203 } 204 204 205 205 - static int jh7110_ispcrg_remove(struct platform_device *pdev) 205 205 + static void jh7110_ispcrg_remove(struct platform_device *pdev) 206 206 { 207 207 pm_runtime_put_sync(&pdev->dev); 208 208 pm_runtime_disable(&pdev->dev); 209 209 - 210 210 - return 0; 211 209 } 212 210 213 211 static const struct of_device_id jh7110_ispcrg_match[] = { ··· 216 218 217 219 static struct platform_driver jh7110_ispcrg_driver = { 218 220 .probe = jh7110_ispcrg_probe, 219 219 - .remove = jh7110_ispcrg_remove, 221 221 + .remove_new = jh7110_ispcrg_remove, 220 222 .driver = { 221 223 .name = "clk-starfive-jh7110-isp", 222 224 .of_match_table = jh7110_ispcrg_match,

+2 -4

drivers/clk/starfive/clk-starfive-jh7110-vout.c

reviewed

··· 209 209 return ret; 210 210 } 211 211 212 212 - static int jh7110_voutcrg_remove(struct platform_device *pdev) 212 212 + static void jh7110_voutcrg_remove(struct platform_device *pdev) 213 213 { 214 214 pm_runtime_put_sync(&pdev->dev); 215 215 pm_runtime_disable(&pdev->dev); 216 216 - 217 217 - return 0; 218 216 } 219 217 220 218 static const struct of_device_id jh7110_voutcrg_match[] = { ··· 223 225 224 226 static struct platform_driver jh7110_voutcrg_driver = { 225 227 .probe = jh7110_voutcrg_probe, 226 226 - .remove = jh7110_voutcrg_remove, 228 228 + .remove_new = jh7110_voutcrg_remove, 227 229 .driver = { 228 230 .name = "clk-starfive-jh7110-vout", 229 231 .of_match_table = jh7110_voutcrg_match,

+5

include/dt-bindings/clock/microchip,mpfs-clock.h

reviewed

··· 44 44 45 45 #define CLK_RTCREF 33 46 46 #define CLK_MSSPLL 34 47 47 + #define CLK_MSSPLL0 34 48 48 + #define CLK_MSSPLL1 35 49 49 + #define CLK_MSSPLL2 36 50 50 + #define CLK_MSSPLL3 37 51 51 + /* 38 is reserved for MSS PLL internals */ 47 52 48 53 /* Clock Conditioning Circuitry Clock IDs */ 49 54

+4

include/dt-bindings/clock/qcom,gcc-msm8953.h

reviewed

··· 218 218 #define GCC_USB3PHY_PHY_BCR 3 219 219 #define GCC_USB3_PHY_BCR 4 220 220 #define GCC_USB_30_BCR 5 221 221 + #define GCC_MDSS_BCR 6 222 222 + #define GCC_CRYPTO_BCR 7 223 223 + #define GCC_SDCC1_BCR 8 224 224 + #define GCC_SDCC2_BCR 9 221 225 222 226 /* GDSCs */ 223 227 #define CPP_GDSC 0

+2

include/dt-bindings/clock/qcom,gcc-sc8180x.h

reviewed

··· 246 246 #define GCC_PCIE_3_CLKREF_CLK 236 247 247 #define GCC_USB3_PRIM_CLKREF_CLK 237 248 248 #define GCC_USB3_SEC_CLKREF_CLK 238 249 249 + #define GCC_UFS_MEM_CLKREF_EN 239 250 250 + #define GCC_UFS_CARD_CLKREF_EN 240 249 251 250 252 #define GCC_EMAC_BCR 0 251 253 #define GCC_GPU_BCR 1

+3

include/dt-bindings/clock/qcom,gcc-sm8150.h

reviewed

··· 239 239 #define GCC_USB30_PRIM_BCR 26 240 240 #define GCC_USB30_SEC_BCR 27 241 241 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 242 242 + #define GCC_VIDEO_AXIC_CLK_BCR 29 243 243 + #define GCC_VIDEO_AXI0_CLK_BCR 30 244 244 + #define GCC_VIDEO_AXI1_CLK_BCR 31 242 245 243 246 /* GCC GDSCRs */ 244 247 #define PCIE_0_GDSC 0

+135

include/dt-bindings/clock/qcom,x1e80100-camcc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 2 + /* 3 3 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 + */ 5 5 + 6 6 + #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H 7 7 + #define _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H 8 8 + 9 9 + /* CAM_CC clocks */ 10 10 + #define CAM_CC_BPS_AHB_CLK 0 11 11 + #define CAM_CC_BPS_CLK 1 12 12 + #define CAM_CC_BPS_CLK_SRC 2 13 13 + #define CAM_CC_BPS_FAST_AHB_CLK 3 14 14 + #define CAM_CC_CAMNOC_AXI_NRT_CLK 4 15 15 + #define CAM_CC_CAMNOC_AXI_RT_CLK 5 16 16 + #define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6 17 17 + #define CAM_CC_CAMNOC_DCD_XO_CLK 7 18 18 + #define CAM_CC_CAMNOC_XO_CLK 8 19 19 + #define CAM_CC_CCI_0_CLK 9 20 20 + #define CAM_CC_CCI_0_CLK_SRC 10 21 21 + #define CAM_CC_CCI_1_CLK 11 22 22 + #define CAM_CC_CCI_1_CLK_SRC 12 23 23 + #define CAM_CC_CORE_AHB_CLK 13 24 24 + #define CAM_CC_CPAS_AHB_CLK 14 25 25 + #define CAM_CC_CPAS_BPS_CLK 15 26 26 + #define CAM_CC_CPAS_FAST_AHB_CLK 16 27 27 + #define CAM_CC_CPAS_IFE_0_CLK 17 28 28 + #define CAM_CC_CPAS_IFE_1_CLK 18 29 29 + #define CAM_CC_CPAS_IFE_LITE_CLK 19 30 30 + #define CAM_CC_CPAS_IPE_NPS_CLK 20 31 31 + #define CAM_CC_CPAS_SFE_0_CLK 21 32 32 + #define CAM_CC_CPHY_RX_CLK_SRC 22 33 33 + #define CAM_CC_CSI0PHYTIMER_CLK 23 34 34 + #define CAM_CC_CSI0PHYTIMER_CLK_SRC 24 35 35 + #define CAM_CC_CSI1PHYTIMER_CLK 25 36 36 + #define CAM_CC_CSI1PHYTIMER_CLK_SRC 26 37 37 + #define CAM_CC_CSI2PHYTIMER_CLK 27 38 38 + #define CAM_CC_CSI2PHYTIMER_CLK_SRC 28 39 39 + #define CAM_CC_CSI3PHYTIMER_CLK 29 40 40 + #define CAM_CC_CSI3PHYTIMER_CLK_SRC 30 41 41 + #define CAM_CC_CSI4PHYTIMER_CLK 31 42 42 + #define CAM_CC_CSI4PHYTIMER_CLK_SRC 32 43 43 + #define CAM_CC_CSI5PHYTIMER_CLK 33 44 44 + #define CAM_CC_CSI5PHYTIMER_CLK_SRC 34 45 45 + #define CAM_CC_CSID_CLK 35 46 46 + #define CAM_CC_CSID_CLK_SRC 36 47 47 + #define CAM_CC_CSID_CSIPHY_RX_CLK 37 48 48 + #define CAM_CC_CSIPHY0_CLK 38 49 49 + #define CAM_CC_CSIPHY1_CLK 39 50 50 + #define CAM_CC_CSIPHY2_CLK 40 51 51 + #define CAM_CC_CSIPHY3_CLK 41 52 52 + #define CAM_CC_CSIPHY4_CLK 42 53 53 + #define CAM_CC_CSIPHY5_CLK 43 54 54 + #define CAM_CC_FAST_AHB_CLK_SRC 44 55 55 + #define CAM_CC_GDSC_CLK 45 56 56 + #define CAM_CC_ICP_AHB_CLK 46 57 57 + #define CAM_CC_ICP_CLK 47 58 58 + #define CAM_CC_ICP_CLK_SRC 48 59 59 + #define CAM_CC_IFE_0_CLK 49 60 60 + #define CAM_CC_IFE_0_CLK_SRC 50 61 61 + #define CAM_CC_IFE_0_DSP_CLK 51 62 62 + #define CAM_CC_IFE_0_FAST_AHB_CLK 52 63 63 + #define CAM_CC_IFE_1_CLK 53 64 64 + #define CAM_CC_IFE_1_CLK_SRC 54 65 65 + #define CAM_CC_IFE_1_DSP_CLK 55 66 66 + #define CAM_CC_IFE_1_FAST_AHB_CLK 56 67 67 + #define CAM_CC_IFE_LITE_AHB_CLK 57 68 68 + #define CAM_CC_IFE_LITE_CLK 58 69 69 + #define CAM_CC_IFE_LITE_CLK_SRC 59 70 70 + #define CAM_CC_IFE_LITE_CPHY_RX_CLK 60 71 71 + #define CAM_CC_IFE_LITE_CSID_CLK 61 72 72 + #define CAM_CC_IFE_LITE_CSID_CLK_SRC 62 73 73 + #define CAM_CC_IPE_NPS_AHB_CLK 63 74 74 + #define CAM_CC_IPE_NPS_CLK 64 75 75 + #define CAM_CC_IPE_NPS_CLK_SRC 65 76 76 + #define CAM_CC_IPE_NPS_FAST_AHB_CLK 66 77 77 + #define CAM_CC_IPE_PPS_CLK 67 78 78 + #define CAM_CC_IPE_PPS_FAST_AHB_CLK 68 79 79 + #define CAM_CC_JPEG_CLK 69 80 80 + #define CAM_CC_JPEG_CLK_SRC 70 81 81 + #define CAM_CC_MCLK0_CLK 71 82 82 + #define CAM_CC_MCLK0_CLK_SRC 72 83 83 + #define CAM_CC_MCLK1_CLK 73 84 84 + #define CAM_CC_MCLK1_CLK_SRC 74 85 85 + #define CAM_CC_MCLK2_CLK 75 86 86 + #define CAM_CC_MCLK2_CLK_SRC 76 87 87 + #define CAM_CC_MCLK3_CLK 77 88 88 + #define CAM_CC_MCLK3_CLK_SRC 78 89 89 + #define CAM_CC_MCLK4_CLK 79 90 90 + #define CAM_CC_MCLK4_CLK_SRC 80 91 91 + #define CAM_CC_MCLK5_CLK 81 92 92 + #define CAM_CC_MCLK5_CLK_SRC 82 93 93 + #define CAM_CC_MCLK6_CLK 83 94 94 + #define CAM_CC_MCLK6_CLK_SRC 84 95 95 + #define CAM_CC_MCLK7_CLK 85 96 96 + #define CAM_CC_MCLK7_CLK_SRC 86 97 97 + #define CAM_CC_PLL0 87 98 98 + #define CAM_CC_PLL0_OUT_EVEN 88 99 99 + #define CAM_CC_PLL0_OUT_ODD 89 100 100 + #define CAM_CC_PLL1 90 101 101 + #define CAM_CC_PLL1_OUT_EVEN 91 102 102 + #define CAM_CC_PLL2 92 103 103 + #define CAM_CC_PLL3 93 104 104 + #define CAM_CC_PLL3_OUT_EVEN 94 105 105 + #define CAM_CC_PLL4 95 106 106 + #define CAM_CC_PLL4_OUT_EVEN 96 107 107 + #define CAM_CC_PLL6 97 108 108 + #define CAM_CC_PLL6_OUT_EVEN 98 109 109 + #define CAM_CC_PLL8 99 110 110 + #define CAM_CC_PLL8_OUT_EVEN 100 111 111 + #define CAM_CC_SFE_0_CLK 101 112 112 + #define CAM_CC_SFE_0_CLK_SRC 102 113 113 + #define CAM_CC_SFE_0_FAST_AHB_CLK 103 114 114 + #define CAM_CC_SLEEP_CLK 104 115 115 + #define CAM_CC_SLEEP_CLK_SRC 105 116 116 + #define CAM_CC_SLOW_AHB_CLK_SRC 106 117 117 + #define CAM_CC_XO_CLK_SRC 107 118 118 + 119 119 + /* CAM_CC power domains */ 120 120 + #define CAM_CC_BPS_GDSC 0 121 121 + #define CAM_CC_IFE_0_GDSC 1 122 122 + #define CAM_CC_IFE_1_GDSC 2 123 123 + #define CAM_CC_IPE_0_GDSC 3 124 124 + #define CAM_CC_SFE_0_GDSC 4 125 125 + #define CAM_CC_TITAN_TOP_GDSC 5 126 126 + 127 127 + /* CAM_CC resets */ 128 128 + #define CAM_CC_BPS_BCR 0 129 129 + #define CAM_CC_ICP_BCR 1 130 130 + #define CAM_CC_IFE_0_BCR 2 131 131 + #define CAM_CC_IFE_1_BCR 3 132 132 + #define CAM_CC_IPE_0_BCR 4 133 133 + #define CAM_CC_SFE_0_BCR 5 134 134 + 135 135 + #endif

+98

include/dt-bindings/clock/qcom,x1e80100-dispcc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 2 + /* 3 3 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 + */ 5 5 + 6 6 + #ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H 7 7 + #define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H 8 8 + 9 9 + /* DISP_CC clocks */ 10 10 + #define DISP_CC_MDSS_ACCU_CLK 0 11 11 + #define DISP_CC_MDSS_AHB1_CLK 1 12 12 + #define DISP_CC_MDSS_AHB_CLK 2 13 13 + #define DISP_CC_MDSS_AHB_CLK_SRC 3 14 14 + #define DISP_CC_MDSS_BYTE0_CLK 4 15 15 + #define DISP_CC_MDSS_BYTE0_CLK_SRC 5 16 16 + #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 17 17 + #define DISP_CC_MDSS_BYTE0_INTF_CLK 7 18 18 + #define DISP_CC_MDSS_BYTE1_CLK 8 19 19 + #define DISP_CC_MDSS_BYTE1_CLK_SRC 9 20 20 + #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 21 21 + #define DISP_CC_MDSS_BYTE1_INTF_CLK 11 22 22 + #define DISP_CC_MDSS_DPTX0_AUX_CLK 12 23 23 + #define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 24 24 + #define DISP_CC_MDSS_DPTX0_LINK_CLK 14 25 25 + #define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15 26 26 + #define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16 27 27 + #define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17 28 28 + #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18 29 29 + #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19 30 30 + #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20 31 31 + #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21 32 32 + #define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22 33 33 + #define DISP_CC_MDSS_DPTX1_AUX_CLK 23 34 34 + #define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24 35 35 + #define DISP_CC_MDSS_DPTX1_LINK_CLK 25 36 36 + #define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26 37 37 + #define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27 38 38 + #define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28 39 39 + #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29 40 40 + #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30 41 41 + #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31 42 42 + #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32 43 43 + #define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33 44 44 + #define DISP_CC_MDSS_DPTX2_AUX_CLK 34 45 45 + #define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35 46 46 + #define DISP_CC_MDSS_DPTX2_LINK_CLK 36 47 47 + #define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37 48 48 + #define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38 49 49 + #define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39 50 50 + #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40 51 51 + #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41 52 52 + #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42 53 53 + #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43 54 54 + #define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44 55 55 + #define DISP_CC_MDSS_DPTX3_AUX_CLK 45 56 56 + #define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46 57 57 + #define DISP_CC_MDSS_DPTX3_LINK_CLK 47 58 58 + #define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48 59 59 + #define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49 60 60 + #define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50 61 61 + #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51 62 62 + #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52 63 63 + #define DISP_CC_MDSS_ESC0_CLK 53 64 64 + #define DISP_CC_MDSS_ESC0_CLK_SRC 54 65 65 + #define DISP_CC_MDSS_ESC1_CLK 55 66 66 + #define DISP_CC_MDSS_ESC1_CLK_SRC 56 67 67 + #define DISP_CC_MDSS_MDP1_CLK 57 68 68 + #define DISP_CC_MDSS_MDP_CLK 58 69 69 + #define DISP_CC_MDSS_MDP_CLK_SRC 59 70 70 + #define DISP_CC_MDSS_MDP_LUT1_CLK 60 71 71 + #define DISP_CC_MDSS_MDP_LUT_CLK 61 72 72 + #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62 73 73 + #define DISP_CC_MDSS_PCLK0_CLK 63 74 74 + #define DISP_CC_MDSS_PCLK0_CLK_SRC 64 75 75 + #define DISP_CC_MDSS_PCLK1_CLK 65 76 76 + #define DISP_CC_MDSS_PCLK1_CLK_SRC 66 77 77 + #define DISP_CC_MDSS_RSCC_AHB_CLK 67 78 78 + #define DISP_CC_MDSS_RSCC_VSYNC_CLK 68 79 79 + #define DISP_CC_MDSS_VSYNC1_CLK 69 80 80 + #define DISP_CC_MDSS_VSYNC_CLK 70 81 81 + #define DISP_CC_MDSS_VSYNC_CLK_SRC 71 82 82 + #define DISP_CC_PLL0 72 83 83 + #define DISP_CC_PLL1 73 84 84 + #define DISP_CC_SLEEP_CLK 74 85 85 + #define DISP_CC_SLEEP_CLK_SRC 75 86 86 + #define DISP_CC_XO_CLK 76 87 87 + #define DISP_CC_XO_CLK_SRC 77 88 88 + 89 89 + /* DISP_CC resets */ 90 90 + #define DISP_CC_MDSS_CORE_BCR 0 91 91 + #define DISP_CC_MDSS_CORE_INT2_BCR 1 92 92 + #define DISP_CC_MDSS_RSCC_BCR 2 93 93 + 94 94 + /* DISP_CC GDSCR */ 95 95 + #define MDSS_GDSC 0 96 96 + #define MDSS_INT2_GDSC 1 97 97 + 98 98 + #endif

+41

include/dt-bindings/clock/qcom,x1e80100-gpucc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 2 + /* 3 3 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 + */ 5 5 + 6 6 + #ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H 7 7 + #define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H 8 8 + 9 9 + /* GPU_CC clocks */ 10 10 + #define GPU_CC_AHB_CLK 0 11 11 + #define GPU_CC_CB_CLK 1 12 12 + #define GPU_CC_CRC_AHB_CLK 2 13 13 + #define GPU_CC_CX_FF_CLK 3 14 14 + #define GPU_CC_CX_GMU_CLK 4 15 15 + #define GPU_CC_CXO_AON_CLK 5 16 16 + #define GPU_CC_CXO_CLK 6 17 17 + #define GPU_CC_DEMET_CLK 7 18 18 + #define GPU_CC_DEMET_DIV_CLK_SRC 8 19 19 + #define GPU_CC_FF_CLK_SRC 9 20 20 + #define GPU_CC_FREQ_MEASURE_CLK 10 21 21 + #define GPU_CC_GMU_CLK_SRC 11 22 22 + #define GPU_CC_GX_GMU_CLK 12 23 23 + #define GPU_CC_GX_VSENSE_CLK 13 24 24 + #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 25 25 + #define GPU_CC_HUB_AON_CLK 15 26 26 + #define GPU_CC_HUB_CLK_SRC 16 27 27 + #define GPU_CC_HUB_CX_INT_CLK 17 28 28 + #define GPU_CC_MEMNOC_GFX_CLK 18 29 29 + #define GPU_CC_MND1X_0_GFX3D_CLK 19 30 30 + #define GPU_CC_MND1X_1_GFX3D_CLK 20 31 31 + #define GPU_CC_PLL0 21 32 32 + #define GPU_CC_PLL1 22 33 33 + #define GPU_CC_SLEEP_CLK 23 34 34 + #define GPU_CC_XO_CLK_SRC 24 35 35 + #define GPU_CC_XO_DIV_CLK_SRC 25 36 36 + 37 37 + /* GDSCs */ 38 38 + #define GPU_CX_GDSC 0 39 39 + #define GPU_GX_GDSC 1 40 40 + 41 41 + #endif

+23

include/dt-bindings/clock/qcom,x1e80100-tcsr.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 2 + /* 3 3 + * Copyright (c) 2023, Linaro Limited 4 4 + */ 5 5 + 6 6 + #ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H 7 7 + #define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H 8 8 + 9 9 + /* TCSR CC clocks */ 10 10 + #define TCSR_PCIE_2L_4_CLKREF_EN 0 11 11 + #define TCSR_PCIE_2L_5_CLKREF_EN 1 12 12 + #define TCSR_PCIE_8L_CLKREF_EN 2 13 13 + #define TCSR_USB3_MP0_CLKREF_EN 3 14 14 + #define TCSR_USB3_MP1_CLKREF_EN 4 15 15 + #define TCSR_USB2_1_CLKREF_EN 5 16 16 + #define TCSR_UFS_PHY_CLKREF_EN 6 17 17 + #define TCSR_USB4_1_CLKREF_EN 7 18 18 + #define TCSR_USB4_2_CLKREF_EN 8 19 19 + #define TCSR_USB2_2_CLKREF_EN 9 20 20 + #define TCSR_PCIE_4L_CLKREF_EN 10 21 21 + #define TCSR_EDP_CLKREF_EN 11 22 22 + 23 23 + #endif

+19

include/dt-bindings/reset/qcom,x1e80100-gpucc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 2 + /* 3 3 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 + */ 5 5 + 6 6 + #ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H 7 7 + #define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H 8 8 + 9 9 + #define GPUCC_GPU_CC_ACD_BCR 0 10 10 + #define GPUCC_GPU_CC_CB_BCR 1 11 11 + #define GPUCC_GPU_CC_CX_BCR 2 12 12 + #define GPUCC_GPU_CC_FAST_HUB_BCR 3 13 13 + #define GPUCC_GPU_CC_FF_BCR 4 14 14 + #define GPUCC_GPU_CC_GFX3D_AON_BCR 5 15 15 + #define GPUCC_GPU_CC_GMU_BCR 6 16 16 + #define GPUCC_GPU_CC_GX_BCR 7 17 17 + #define GPUCC_GPU_CC_XO_BCR 8 18 18 + 19 19 + #endif