Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-stmmac-convert-glue-drivers-to-use-stmmac_get_phy_intf_sel'
Russell King says:
====================
net: stmmac: convert glue drivers to use stmmac_get_phy_intf_sel()
This series converts the remaining glue drivers that support
multi-interface to use stmmac_get_phy_intf_sel(). The reason these
drivers are not converted to the set_phy_intf_sel() method is
because it is unclear whether there are ordering dependencies that
would prevent it.
For example, reading the stm32mp2 documentation, it is required to
set the ETH1_SEL field while the dwmac core is in reset and before
clocks are enabled. This requirement can not be satsified at the
moment (but could with further changes.)
====================
Link: https://patch.msgid.link/aRLvrfx6tOa-RhrY@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+69
-118
+6
-12
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c
+6
-12
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c
···
38
38
#define GMAC_SHUT BIT(6)
39
39
40
40
#define PHY_INTF_SELI GENMASK(30, 28)
41
-
#define PHY_INTF_MII FIELD_PREP(PHY_INTF_SELI, 0)
42
-
#define PHY_INTF_RMII FIELD_PREP(PHY_INTF_SELI, 4)
43
41
44
42
struct ls1x_dwmac {
45
43
struct plat_stmmacenet_data *plat_dat;
···
138
140
struct ls1x_dwmac *dwmac = priv;
139
141
struct plat_stmmacenet_data *plat = dwmac->plat_dat;
140
142
struct regmap *regmap = dwmac->regmap;
143
+
int phy_intf_sel;
141
144
142
-
switch (plat->phy_interface) {
143
-
case PHY_INTERFACE_MODE_MII:
144
-
regmap_update_bits(regmap, LS1X_SYSCON1, PHY_INTF_SELI,
145
-
PHY_INTF_MII);
146
-
break;
147
-
case PHY_INTERFACE_MODE_RMII:
148
-
regmap_update_bits(regmap, LS1X_SYSCON1, PHY_INTF_SELI,
149
-
PHY_INTF_RMII);
150
-
break;
151
-
default:
145
+
phy_intf_sel = stmmac_get_phy_intf_sel(plat->phy_interface);
146
+
if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
147
+
phy_intf_sel != PHY_INTF_SEL_RMII) {
152
148
dev_err(&pdev->dev, "Unsupported PHY-mode %u\n",
153
149
plat->phy_interface);
154
150
return -EOPNOTSUPP;
155
151
}
156
152
153
+
regmap_update_bits(regmap, LS1X_SYSCON1, PHY_INTF_SELI,
154
+
FIELD_PREP(PHY_INTF_SELI, phy_intf_sel));
157
155
regmap_update_bits(regmap, LS1X_SYSCON0, GMAC0_SHUT, 0);
158
156
159
157
return 0;
+28
-49
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+28
-49
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
···
17
17
18
18
/* Peri Configuration register for mt2712 */
19
19
#define PERI_ETH_PHY_INTF_SEL 0x418
20
-
#define PHY_INTF_MII 0
21
-
#define PHY_INTF_RGMII 1
22
-
#define PHY_INTF_RMII 4
23
20
#define RMII_CLK_SRC_RXC BIT(4)
24
21
#define RMII_CLK_SRC_INTERNAL BIT(5)
25
22
···
85
88
};
86
89
87
90
struct mediatek_dwmac_variant {
88
-
int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
91
+
int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat,
92
+
u8 phy_intf_sel);
89
93
int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
90
94
91
95
/* clock ids to be requested */
···
107
109
"axi", "apb", "mac_cg", "mac_main", "ptp_ref"
108
110
};
109
111
110
-
static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
112
+
static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,
113
+
u8 phy_intf_sel)
111
114
{
112
-
int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
113
-
int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
114
-
u32 intf_val = 0;
115
+
u32 intf_val = phy_intf_sel;
115
116
116
-
/* select phy interface in top control domain */
117
-
switch (plat->phy_mode) {
118
-
case PHY_INTERFACE_MODE_MII:
119
-
intf_val |= PHY_INTF_MII;
120
-
break;
121
-
case PHY_INTERFACE_MODE_RMII:
122
-
intf_val |= (PHY_INTF_RMII | rmii_rxc | rmii_clk_from_mac);
123
-
break;
124
-
case PHY_INTERFACE_MODE_RGMII:
125
-
case PHY_INTERFACE_MODE_RGMII_TXID:
126
-
case PHY_INTERFACE_MODE_RGMII_RXID:
127
-
case PHY_INTERFACE_MODE_RGMII_ID:
128
-
intf_val |= PHY_INTF_RGMII;
129
-
break;
130
-
default:
131
-
dev_err(plat->dev, "phy interface not supported\n");
132
-
return -EINVAL;
117
+
if (phy_intf_sel == PHY_INTF_SEL_RMII) {
118
+
if (plat->rmii_clk_from_mac)
119
+
intf_val |= RMII_CLK_SRC_INTERNAL;
120
+
if (plat->rmii_rxc)
121
+
intf_val |= RMII_CLK_SRC_RXC;
133
122
}
134
123
135
124
regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);
···
273
288
.tx_delay_max = 17600,
274
289
};
275
290
276
-
static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
291
+
static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
292
+
u8 phy_intf_sel)
277
293
{
278
-
int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0;
279
-
int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0;
280
-
u32 intf_val = 0;
294
+
u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel);
281
295
282
-
/* select phy interface in top control domain */
283
-
switch (plat->phy_mode) {
284
-
case PHY_INTERFACE_MODE_MII:
285
-
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_MII);
286
-
break;
287
-
case PHY_INTERFACE_MODE_RMII:
288
-
intf_val |= (rmii_rxc | rmii_clk_from_mac);
289
-
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RMII);
290
-
break;
291
-
case PHY_INTERFACE_MODE_RGMII:
292
-
case PHY_INTERFACE_MODE_RGMII_TXID:
293
-
case PHY_INTERFACE_MODE_RGMII_RXID:
294
-
case PHY_INTERFACE_MODE_RGMII_ID:
295
-
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RGMII);
296
-
break;
297
-
default:
298
-
dev_err(plat->dev, "phy interface not supported\n");
299
-
return -EINVAL;
296
+
if (phy_intf_sel == PHY_INTF_SEL_RMII) {
297
+
if (plat->rmii_clk_from_mac)
298
+
intf_val |= MT8195_RMII_CLK_SRC_INTERNAL;
299
+
if (plat->rmii_rxc)
300
+
intf_val |= MT8195_RMII_CLK_SRC_RXC;
300
301
}
301
302
302
303
/* MT8195 only support external PHY */
···
498
527
{
499
528
struct mediatek_dwmac_plat_data *plat = priv;
500
529
const struct mediatek_dwmac_variant *variant = plat->variant;
501
-
int ret;
530
+
int phy_intf_sel, ret;
502
531
503
532
if (variant->dwmac_set_phy_interface) {
504
-
ret = variant->dwmac_set_phy_interface(plat);
533
+
phy_intf_sel = stmmac_get_phy_intf_sel(plat->phy_mode);
534
+
if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
535
+
phy_intf_sel != PHY_INTF_SEL_RGMII &&
536
+
phy_intf_sel != PHY_INTF_SEL_RMII) {
537
+
dev_err(plat->dev, "phy interface not supported\n");
538
+
return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;
539
+
}
540
+
541
+
ret = variant->dwmac_set_phy_interface(plat, phy_intf_sel);
505
542
if (ret) {
506
543
dev_err(dev, "failed to set phy interface, err = %d\n", ret);
507
544
return ret;
+6
-18
drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
+6
-18
drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
···
15
15
16
16
#include "stmmac_platform.h"
17
17
18
-
#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
19
-
#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
20
18
#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
21
19
22
20
#define JH7100_SYSMAIN_REGISTER49_DLYCHAIN 0xc8
···
33
35
struct starfive_dwmac *dwmac = plat_dat->bsp_priv;
34
36
struct regmap *regmap;
35
37
unsigned int args[2];
36
-
unsigned int mode;
38
+
int phy_intf_sel;
37
39
int err;
38
40
39
-
switch (plat_dat->phy_interface) {
40
-
case PHY_INTERFACE_MODE_RMII:
41
-
mode = STARFIVE_DWMAC_PHY_INFT_RMII;
42
-
break;
43
-
44
-
case PHY_INTERFACE_MODE_RGMII:
45
-
case PHY_INTERFACE_MODE_RGMII_ID:
46
-
case PHY_INTERFACE_MODE_RGMII_RXID:
47
-
case PHY_INTERFACE_MODE_RGMII_TXID:
48
-
mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
49
-
break;
50
-
51
-
default:
41
+
phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface);
42
+
if (phy_intf_sel != PHY_INTF_SEL_RGMII &&
43
+
phy_intf_sel != PHY_INTF_SEL_RMII) {
52
44
dev_err(dwmac->dev, "unsupported interface %s\n",
53
45
phy_modes(plat_dat->phy_interface));
54
-
return -EINVAL;
46
+
return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;
55
47
}
56
48
57
49
regmap = syscon_regmap_lookup_by_phandle_args(dwmac->dev->of_node,
···
53
65
/* args[0]:offset args[1]: shift */
54
66
err = regmap_update_bits(regmap, args[0],
55
67
STARFIVE_DWMAC_PHY_INFT_FIELD << args[1],
56
-
mode << args[1]);
68
+
phy_intf_sel << args[1]);
57
69
if (err)
58
70
return dev_err_probe(dwmac->dev, err, "error setting phy mode\n");
59
71
+24
-20
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+24
-20
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
···
47
47
*------------------------------------------
48
48
*/
49
49
#define SYSCFG_PMCR_ETH_SEL_MII BIT(20)
50
-
#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)
51
-
#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)
52
-
#define SYSCFG_PMCR_ETH_SEL_GMII 0
50
+
#define SYSCFG_PMCR_PHY_INTF_SEL_MASK GENMASK(23, 21)
53
51
#define SYSCFG_MCU_ETH_SEL_MII 0
54
52
#define SYSCFG_MCU_ETH_SEL_RMII 1
55
53
56
54
/* STM32MP2 register definitions */
57
55
#define SYSCFG_MP2_ETH_MASK GENMASK(31, 0)
58
56
57
+
#define SYSCFG_ETHCR_ETH_SEL_MASK GENMASK(6, 4)
59
58
#define SYSCFG_ETHCR_ETH_PTP_CLK_SEL BIT(2)
60
59
#define SYSCFG_ETHCR_ETH_CLK_SEL BIT(1)
61
60
#define SYSCFG_ETHCR_ETH_REF_CLK_SEL BIT(0)
62
-
63
-
#define SYSCFG_ETHCR_ETH_SEL_MII 0
64
-
#define SYSCFG_ETHCR_ETH_SEL_RGMII BIT(4)
65
-
#define SYSCFG_ETHCR_ETH_SEL_RMII BIT(6)
66
61
67
62
/* STM32MPx register definitions
68
63
*
···
227
232
return -EINVAL;
228
233
}
229
234
230
-
static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
235
+
static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat,
236
+
u8 phy_intf_sel)
231
237
{
232
238
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
233
239
u32 reg = dwmac->mode_reg;
234
-
int val = 0;
240
+
int val;
241
+
242
+
val = FIELD_PREP(SYSCFG_PMCR_PHY_INTF_SEL_MASK, phy_intf_sel);
235
243
236
244
switch (plat_dat->phy_interface) {
237
245
case PHY_INTERFACE_MODE_MII:
···
248
250
val |= SYSCFG_PMCR_ETH_SEL_MII;
249
251
break;
250
252
case PHY_INTERFACE_MODE_GMII:
251
-
val = SYSCFG_PMCR_ETH_SEL_GMII;
252
253
if (dwmac->enable_eth_ck)
253
254
val |= SYSCFG_PMCR_ETH_CLK_SEL;
254
255
break;
255
256
case PHY_INTERFACE_MODE_RMII:
256
-
val = SYSCFG_PMCR_ETH_SEL_RMII;
257
257
if (dwmac->enable_eth_ck)
258
258
val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
259
259
break;
···
259
263
case PHY_INTERFACE_MODE_RGMII_ID:
260
264
case PHY_INTERFACE_MODE_RGMII_RXID:
261
265
case PHY_INTERFACE_MODE_RGMII_TXID:
262
-
val = SYSCFG_PMCR_ETH_SEL_RGMII;
263
266
if (dwmac->enable_eth_ck)
264
267
val |= SYSCFG_PMCR_ETH_CLK_SEL;
265
268
break;
···
283
288
dwmac->mode_mask, val);
284
289
}
285
290
286
-
static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
291
+
static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat,
292
+
u8 phy_intf_sel)
287
293
{
288
294
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
289
295
u32 reg = dwmac->mode_reg;
290
-
int val = 0;
296
+
int val;
297
+
298
+
val = FIELD_PREP(SYSCFG_ETHCR_ETH_SEL_MASK, phy_intf_sel);
291
299
292
300
switch (plat_dat->phy_interface) {
293
301
case PHY_INTERFACE_MODE_MII:
294
302
/* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */
295
303
break;
296
304
case PHY_INTERFACE_MODE_RMII:
297
-
val = SYSCFG_ETHCR_ETH_SEL_RMII;
298
305
if (dwmac->enable_eth_ck) {
299
306
/* Internal clock ETH_CLK of 50MHz from RCC is used */
300
307
val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL;
···
306
309
case PHY_INTERFACE_MODE_RGMII_ID:
307
310
case PHY_INTERFACE_MODE_RGMII_RXID:
308
311
case PHY_INTERFACE_MODE_RGMII_TXID:
309
-
val = SYSCFG_ETHCR_ETH_SEL_RGMII;
310
-
fallthrough;
311
312
case PHY_INTERFACE_MODE_GMII:
312
313
if (dwmac->enable_eth_ck) {
313
314
/* Internal clock ETH_CLK of 125MHz from RCC is used */
···
332
337
static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
333
338
{
334
339
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
335
-
int ret;
340
+
int phy_intf_sel, ret;
336
341
337
342
ret = stm32mp1_select_ethck_external(plat_dat);
338
343
if (ret)
···
342
347
if (ret)
343
348
return ret;
344
349
350
+
phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface);
351
+
if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
352
+
phy_intf_sel != PHY_INTF_SEL_RGMII &&
353
+
phy_intf_sel != PHY_INTF_SEL_RMII) {
354
+
dev_err(dwmac->dev, "Mode %s not supported\n",
355
+
phy_modes(plat_dat->phy_interface));
356
+
return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;
357
+
}
358
+
345
359
if (!dwmac->ops->is_mp2)
346
-
return stm32mp1_configure_pmcr(plat_dat);
360
+
return stm32mp1_configure_pmcr(plat_dat, phy_intf_sel);
347
361
else
348
-
return stm32mp2_configure_syscfg(plat_dat);
362
+
return stm32mp2_configure_syscfg(plat_dat, phy_intf_sel);
349
363
}
350
364
351
365
static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
+5
-19
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+5
-19
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
···
42
42
43
43
#define ETHER_CLK_SEL_RX_TX_CLK_EN (ETHER_CLK_SEL_RX_CLK_EN | ETHER_CLK_SEL_TX_CLK_EN)
44
44
45
-
#define ETHER_CONFIG_INTF_MII 0
46
-
#define ETHER_CONFIG_INTF_RGMII BIT(0)
47
-
#define ETHER_CONFIG_INTF_RMII BIT(2)
48
-
49
45
struct visconti_eth {
50
46
void __iomem *reg;
51
47
struct clk *phy_ref_clk;
···
146
150
{
147
151
struct visconti_eth *dwmac = plat_dat->bsp_priv;
148
152
unsigned int clk_sel_val;
149
-
u32 phy_intf_sel;
153
+
int phy_intf_sel;
150
154
151
-
switch (plat_dat->phy_interface) {
152
-
case PHY_INTERFACE_MODE_RGMII:
153
-
case PHY_INTERFACE_MODE_RGMII_ID:
154
-
case PHY_INTERFACE_MODE_RGMII_RXID:
155
-
case PHY_INTERFACE_MODE_RGMII_TXID:
156
-
phy_intf_sel = ETHER_CONFIG_INTF_RGMII;
157
-
break;
158
-
case PHY_INTERFACE_MODE_MII:
159
-
phy_intf_sel = ETHER_CONFIG_INTF_MII;
160
-
break;
161
-
case PHY_INTERFACE_MODE_RMII:
162
-
phy_intf_sel = ETHER_CONFIG_INTF_RMII;
163
-
break;
164
-
default:
155
+
phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface);
156
+
if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
157
+
phy_intf_sel != PHY_INTF_SEL_RGMII &&
158
+
phy_intf_sel != PHY_INTF_SEL_RMII) {
165
159
dev_err(&pdev->dev, "Unsupported phy-mode (%d)\n", plat_dat->phy_interface);
166
160
return -EOPNOTSUPP;
167
161
}