Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: camcc-sc8180x: Add SC8180X camera clock controller driver
Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on SC8180X platform.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-3-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Satya Priya Kakitapalli
and committed by
Bjorn Andersson
691f3413
910ad019
+2900
+10
drivers/clk/qcom/Kconfig
+10
drivers/clk/qcom/Kconfig
···
549
549
Say Y if you want to support camera devices and functionality such as
550
550
capturing pictures.
551
551
552
+
config SC_CAMCC_8180X
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tristate "SC8180X Camera Clock Controller"
554
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depends on ARM64 || COMPILE_TEST
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select SC_GCC_8180X
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help
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Support for the camera clock controller on Qualcomm Technologies, Inc
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+
SC8180X devices.
559
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Say Y if you want to support camera devices and functionality such as
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+
capturing pictures.
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+
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config SC_CAMCC_8280XP
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tristate "SC8280XP Camera Clock Controller"
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depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
82
82
obj-$(CONFIG_QDU_GCC_1000) += gcc-qdu1000.o
83
83
obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
84
84
obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o
85
+
obj-$(CONFIG_SC_CAMCC_8180X) += camcc-sc8180x.o
85
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obj-$(CONFIG_SC_CAMCC_8280XP) += camcc-sc8280xp.o
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obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
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obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
+2889
drivers/clk/qcom/camcc-sc8180x.c
+2889
drivers/clk/qcom/camcc-sc8180x.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/pm_runtime.h>
11
+
#include <linux/regmap.h>
12
+
13
+
#include <dt-bindings/clock/qcom,sc8180x-camcc.h>
14
+
15
+
#include "clk-alpha-pll.h"
16
+
#include "clk-branch.h"
17
+
#include "clk-rcg.h"
18
+
#include "clk-regmap.h"
19
+
#include "common.h"
20
+
#include "gdsc.h"
21
+
#include "reset.h"
22
+
23
+
enum {
24
+
DT_IFACE,
25
+
DT_BI_TCXO,
26
+
DT_SLEEP_CLK,
27
+
};
28
+
29
+
enum {
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+
P_BI_TCXO,
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P_CAM_CC_PLL0_OUT_EVEN,
32
+
P_CAM_CC_PLL0_OUT_MAIN,
33
+
P_CAM_CC_PLL0_OUT_ODD,
34
+
P_CAM_CC_PLL1_OUT_EVEN,
35
+
P_CAM_CC_PLL2_OUT_EARLY,
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+
P_CAM_CC_PLL2_OUT_MAIN,
37
+
P_CAM_CC_PLL3_OUT_EVEN,
38
+
P_CAM_CC_PLL4_OUT_EVEN,
39
+
P_CAM_CC_PLL5_OUT_EVEN,
40
+
P_CAM_CC_PLL6_OUT_EVEN,
41
+
P_SLEEP_CLK,
42
+
};
43
+
44
+
static const struct pll_vco regera_vco[] = {
45
+
{ 600000000, 3300000000, 0 },
46
+
};
47
+
48
+
static const struct pll_vco trion_vco[] = {
49
+
{ 249600000, 2000000000, 0 },
50
+
};
51
+
52
+
static const struct alpha_pll_config cam_cc_pll0_config = {
53
+
.l = 0x3e,
54
+
.alpha = 0x8000,
55
+
.config_ctl_val = 0x20485699,
56
+
.config_ctl_hi_val = 0x00002267,
57
+
.config_ctl_hi1_val = 0x00000024,
58
+
.test_ctl_hi1_val = 0x00000020,
59
+
.user_ctl_val = 0x00003100,
60
+
.user_ctl_hi_val = 0x00000805,
61
+
.user_ctl_hi1_val = 0x000000d0,
62
+
};
63
+
64
+
static struct clk_alpha_pll cam_cc_pll0 = {
65
+
.offset = 0x0,
66
+
.vco_table = trion_vco,
67
+
.num_vco = ARRAY_SIZE(trion_vco),
68
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
69
+
.clkr = {
70
+
.hw.init = &(const struct clk_init_data) {
71
+
.name = "cam_cc_pll0",
72
+
.parent_data = &(const struct clk_parent_data) {
73
+
.index = DT_BI_TCXO,
74
+
},
75
+
.num_parents = 1,
76
+
.ops = &clk_alpha_pll_trion_ops,
77
+
},
78
+
},
79
+
};
80
+
81
+
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
82
+
{ 0x1, 2 },
83
+
{ }
84
+
};
85
+
86
+
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
87
+
.offset = 0x0,
88
+
.post_div_shift = 8,
89
+
.post_div_table = post_div_table_cam_cc_pll0_out_even,
90
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
91
+
.width = 4,
92
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
93
+
.clkr.hw.init = &(const struct clk_init_data) {
94
+
.name = "cam_cc_pll0_out_even",
95
+
.parent_hws = (const struct clk_hw*[]) {
96
+
&cam_cc_pll0.clkr.hw,
97
+
},
98
+
.num_parents = 1,
99
+
.flags = CLK_SET_RATE_PARENT,
100
+
.ops = &clk_alpha_pll_postdiv_trion_ops,
101
+
},
102
+
};
103
+
104
+
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
105
+
{ 0x3, 3 },
106
+
{ }
107
+
};
108
+
109
+
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
110
+
.offset = 0x0,
111
+
.post_div_shift = 12,
112
+
.post_div_table = post_div_table_cam_cc_pll0_out_odd,
113
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
114
+
.width = 4,
115
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
116
+
.clkr.hw.init = &(const struct clk_init_data) {
117
+
.name = "cam_cc_pll0_out_odd",
118
+
.parent_hws = (const struct clk_hw*[]) {
119
+
&cam_cc_pll0.clkr.hw,
120
+
},
121
+
.num_parents = 1,
122
+
.flags = CLK_SET_RATE_PARENT,
123
+
.ops = &clk_alpha_pll_postdiv_trion_ops,
124
+
},
125
+
};
126
+
127
+
static const struct alpha_pll_config cam_cc_pll1_config = {
128
+
.l = 0x13,
129
+
.alpha = 0x8800,
130
+
.config_ctl_val = 0x20485699,
131
+
.config_ctl_hi_val = 0x00002267,
132
+
.config_ctl_hi1_val = 0x00000024,
133
+
.test_ctl_hi1_val = 0x00000020,
134
+
.user_ctl_val = 0x00000000,
135
+
.user_ctl_hi_val = 0x00000805,
136
+
.user_ctl_hi1_val = 0x000000d0,
137
+
};
138
+
139
+
static struct clk_alpha_pll cam_cc_pll1 = {
140
+
.offset = 0x1000,
141
+
.vco_table = trion_vco,
142
+
.num_vco = ARRAY_SIZE(trion_vco),
143
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
144
+
.clkr = {
145
+
.hw.init = &(const struct clk_init_data) {
146
+
.name = "cam_cc_pll1",
147
+
.parent_data = &(const struct clk_parent_data) {
148
+
.index = DT_BI_TCXO,
149
+
},
150
+
.num_parents = 1,
151
+
.ops = &clk_alpha_pll_trion_ops,
152
+
},
153
+
},
154
+
};
155
+
156
+
static const struct alpha_pll_config cam_cc_pll2_config = {
157
+
.l = 0x32,
158
+
.alpha = 0x0,
159
+
.config_ctl_val = 0x10000807,
160
+
.config_ctl_hi_val = 0x00000011,
161
+
.config_ctl_hi1_val = 0x04300142,
162
+
.test_ctl_val = 0x04000400,
163
+
.test_ctl_hi_val = 0x00004000,
164
+
.test_ctl_hi1_val = 0x00000000,
165
+
.user_ctl_val = 0x00000100,
166
+
};
167
+
168
+
static struct clk_alpha_pll cam_cc_pll2 = {
169
+
.offset = 0x2000,
170
+
.vco_table = regera_vco,
171
+
.num_vco = ARRAY_SIZE(regera_vco),
172
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA],
173
+
.clkr = {
174
+
.hw.init = &(const struct clk_init_data) {
175
+
.name = "cam_cc_pll2",
176
+
.parent_data = &(const struct clk_parent_data) {
177
+
.index = DT_BI_TCXO,
178
+
},
179
+
.num_parents = 1,
180
+
.ops = &clk_alpha_pll_regera_ops,
181
+
},
182
+
},
183
+
};
184
+
185
+
static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = {
186
+
{ 0x1, 2 },
187
+
{ }
188
+
};
189
+
190
+
static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = {
191
+
.offset = 0x2000,
192
+
.post_div_shift = 8,
193
+
.post_div_table = post_div_table_cam_cc_pll2_out_main,
194
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main),
195
+
.width = 2,
196
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA],
197
+
.clkr.hw.init = &(const struct clk_init_data) {
198
+
.name = "cam_cc_pll2_out_main",
199
+
.parent_hws = (const struct clk_hw*[]) {
200
+
&cam_cc_pll2.clkr.hw,
201
+
},
202
+
.num_parents = 1,
203
+
.flags = CLK_SET_RATE_PARENT,
204
+
.ops = &clk_alpha_pll_postdiv_trion_ops,
205
+
},
206
+
};
207
+
208
+
static const struct alpha_pll_config cam_cc_pll3_config = {
209
+
.l = 0x14,
210
+
.alpha = 0xd555,
211
+
.config_ctl_val = 0x20485699,
212
+
.config_ctl_hi_val = 0x00002267,
213
+
.config_ctl_hi1_val = 0x00000024,
214
+
.test_ctl_hi1_val = 0x00000020,
215
+
.user_ctl_val = 0x00000000,
216
+
.user_ctl_hi_val = 0x00000805,
217
+
.user_ctl_hi1_val = 0x000000d0,
218
+
};
219
+
220
+
static struct clk_alpha_pll cam_cc_pll3 = {
221
+
.offset = 0x3000,
222
+
.vco_table = trion_vco,
223
+
.num_vco = ARRAY_SIZE(trion_vco),
224
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
225
+
.clkr = {
226
+
.hw.init = &(const struct clk_init_data) {
227
+
.name = "cam_cc_pll3",
228
+
.parent_data = &(const struct clk_parent_data) {
229
+
.index = DT_BI_TCXO,
230
+
},
231
+
.num_parents = 1,
232
+
.ops = &clk_alpha_pll_trion_ops,
233
+
},
234
+
},
235
+
};
236
+
237
+
static const struct alpha_pll_config cam_cc_pll4_config = {
238
+
.l = 0x14,
239
+
.alpha = 0xd555,
240
+
.config_ctl_val = 0x20485699,
241
+
.config_ctl_hi_val = 0x00002267,
242
+
.config_ctl_hi1_val = 0x00000024,
243
+
.test_ctl_hi1_val = 0x00000020,
244
+
.user_ctl_val = 0x00000000,
245
+
.user_ctl_hi_val = 0x00000805,
246
+
.user_ctl_hi1_val = 0x000000d0,
247
+
};
248
+
249
+
static struct clk_alpha_pll cam_cc_pll4 = {
250
+
.offset = 0x4000,
251
+
.vco_table = trion_vco,
252
+
.num_vco = ARRAY_SIZE(trion_vco),
253
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
254
+
.clkr = {
255
+
.hw.init = &(const struct clk_init_data) {
256
+
.name = "cam_cc_pll4",
257
+
.parent_data = &(const struct clk_parent_data) {
258
+
.index = DT_BI_TCXO,
259
+
},
260
+
.num_parents = 1,
261
+
.ops = &clk_alpha_pll_trion_ops,
262
+
},
263
+
},
264
+
};
265
+
266
+
static const struct alpha_pll_config cam_cc_pll5_config = {
267
+
.l = 0x14,
268
+
.alpha = 0xd555,
269
+
.config_ctl_val = 0x20485699,
270
+
.config_ctl_hi_val = 0x00002267,
271
+
.config_ctl_hi1_val = 0x00000024,
272
+
.test_ctl_hi1_val = 0x00000020,
273
+
.user_ctl_val = 0x00000000,
274
+
.user_ctl_hi_val = 0x00000805,
275
+
.user_ctl_hi1_val = 0x000000d0,
276
+
};
277
+
278
+
static struct clk_alpha_pll cam_cc_pll5 = {
279
+
.offset = 0x4078,
280
+
.vco_table = trion_vco,
281
+
.num_vco = ARRAY_SIZE(trion_vco),
282
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
283
+
.clkr = {
284
+
.hw.init = &(const struct clk_init_data) {
285
+
.name = "cam_cc_pll5",
286
+
.parent_data = &(const struct clk_parent_data) {
287
+
.index = DT_BI_TCXO,
288
+
},
289
+
.num_parents = 1,
290
+
.ops = &clk_alpha_pll_trion_ops,
291
+
},
292
+
},
293
+
};
294
+
295
+
static const struct alpha_pll_config cam_cc_pll6_config = {
296
+
.l = 0x14,
297
+
.alpha = 0xd555,
298
+
.config_ctl_val = 0x20485699,
299
+
.config_ctl_hi_val = 0x00002267,
300
+
.config_ctl_hi1_val = 0x00000024,
301
+
.test_ctl_hi1_val = 0x00000020,
302
+
.user_ctl_val = 0x00000000,
303
+
.user_ctl_hi_val = 0x00000805,
304
+
.user_ctl_hi1_val = 0x000000d0,
305
+
};
306
+
307
+
static struct clk_alpha_pll cam_cc_pll6 = {
308
+
.offset = 0x40f0,
309
+
.vco_table = trion_vco,
310
+
.num_vco = ARRAY_SIZE(trion_vco),
311
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
312
+
.clkr = {
313
+
.hw.init = &(const struct clk_init_data) {
314
+
.name = "cam_cc_pll6",
315
+
.parent_data = &(const struct clk_parent_data) {
316
+
.index = DT_BI_TCXO,
317
+
},
318
+
.num_parents = 1,
319
+
.ops = &clk_alpha_pll_trion_ops,
320
+
},
321
+
},
322
+
};
323
+
324
+
static const struct parent_map cam_cc_parent_map_0[] = {
325
+
{ P_BI_TCXO, 0 },
326
+
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
327
+
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
328
+
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
329
+
{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
330
+
};
331
+
332
+
static const struct clk_parent_data cam_cc_parent_data_0[] = {
333
+
{ .index = DT_BI_TCXO },
334
+
{ .hw = &cam_cc_pll0.clkr.hw },
335
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
336
+
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
337
+
{ .hw = &cam_cc_pll2_out_main.clkr.hw },
338
+
};
339
+
340
+
static const struct parent_map cam_cc_parent_map_1[] = {
341
+
{ P_BI_TCXO, 0 },
342
+
{ P_CAM_CC_PLL2_OUT_EARLY, 5 },
343
+
};
344
+
345
+
static const struct clk_parent_data cam_cc_parent_data_1[] = {
346
+
{ .index = DT_BI_TCXO },
347
+
{ .hw = &cam_cc_pll2.clkr.hw },
348
+
};
349
+
350
+
static const struct parent_map cam_cc_parent_map_2[] = {
351
+
{ P_BI_TCXO, 0 },
352
+
{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
353
+
};
354
+
355
+
static const struct clk_parent_data cam_cc_parent_data_2[] = {
356
+
{ .index = DT_BI_TCXO },
357
+
{ .hw = &cam_cc_pll3.clkr.hw },
358
+
};
359
+
360
+
static const struct parent_map cam_cc_parent_map_3[] = {
361
+
{ P_BI_TCXO, 0 },
362
+
{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
363
+
};
364
+
365
+
static const struct clk_parent_data cam_cc_parent_data_3[] = {
366
+
{ .index = DT_BI_TCXO },
367
+
{ .hw = &cam_cc_pll4.clkr.hw },
368
+
};
369
+
370
+
static const struct parent_map cam_cc_parent_map_4[] = {
371
+
{ P_BI_TCXO, 0 },
372
+
{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
373
+
};
374
+
375
+
static const struct clk_parent_data cam_cc_parent_data_4[] = {
376
+
{ .index = DT_BI_TCXO },
377
+
{ .hw = &cam_cc_pll5.clkr.hw },
378
+
};
379
+
380
+
static const struct parent_map cam_cc_parent_map_5[] = {
381
+
{ P_BI_TCXO, 0 },
382
+
{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
383
+
};
384
+
385
+
static const struct clk_parent_data cam_cc_parent_data_5[] = {
386
+
{ .index = DT_BI_TCXO },
387
+
{ .hw = &cam_cc_pll6.clkr.hw },
388
+
};
389
+
390
+
static const struct parent_map cam_cc_parent_map_6[] = {
391
+
{ P_BI_TCXO, 0 },
392
+
{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
393
+
};
394
+
395
+
static const struct clk_parent_data cam_cc_parent_data_6[] = {
396
+
{ .index = DT_BI_TCXO },
397
+
{ .hw = &cam_cc_pll1.clkr.hw },
398
+
};
399
+
400
+
static const struct parent_map cam_cc_parent_map_7[] = {
401
+
{ P_BI_TCXO, 0 },
402
+
};
403
+
404
+
static const struct clk_parent_data cam_cc_parent_data_7[] = {
405
+
{ .index = DT_BI_TCXO },
406
+
};
407
+
408
+
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
409
+
F(19200000, P_BI_TCXO, 1, 0, 0),
410
+
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
411
+
F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
412
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
413
+
F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
414
+
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
415
+
{ }
416
+
};
417
+
418
+
static struct clk_rcg2 cam_cc_bps_clk_src = {
419
+
.cmd_rcgr = 0x7010,
420
+
.mnd_width = 0,
421
+
.hid_width = 5,
422
+
.parent_map = cam_cc_parent_map_0,
423
+
.freq_tbl = ftbl_cam_cc_bps_clk_src,
424
+
.clkr.hw.init = &(const struct clk_init_data) {
425
+
.name = "cam_cc_bps_clk_src",
426
+
.parent_data = cam_cc_parent_data_0,
427
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
428
+
.flags = CLK_SET_RATE_PARENT,
429
+
.ops = &clk_rcg2_shared_ops,
430
+
},
431
+
};
432
+
433
+
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
434
+
F(19200000, P_BI_TCXO, 1, 0, 0),
435
+
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
436
+
F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0),
437
+
F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
438
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
439
+
F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
440
+
{ }
441
+
};
442
+
443
+
static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
444
+
.cmd_rcgr = 0xc170,
445
+
.mnd_width = 0,
446
+
.hid_width = 5,
447
+
.parent_map = cam_cc_parent_map_0,
448
+
.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
449
+
.clkr.hw.init = &(const struct clk_init_data) {
450
+
.name = "cam_cc_camnoc_axi_clk_src",
451
+
.parent_data = cam_cc_parent_data_0,
452
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
453
+
.flags = CLK_SET_RATE_PARENT,
454
+
.ops = &clk_rcg2_shared_ops,
455
+
},
456
+
};
457
+
458
+
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
459
+
F(19200000, P_BI_TCXO, 1, 0, 0),
460
+
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
461
+
{ }
462
+
};
463
+
464
+
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
465
+
.cmd_rcgr = 0xc108,
466
+
.mnd_width = 8,
467
+
.hid_width = 5,
468
+
.parent_map = cam_cc_parent_map_0,
469
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
470
+
.clkr.hw.init = &(const struct clk_init_data) {
471
+
.name = "cam_cc_cci_0_clk_src",
472
+
.parent_data = cam_cc_parent_data_0,
473
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
474
+
.flags = CLK_SET_RATE_PARENT,
475
+
.ops = &clk_rcg2_shared_ops,
476
+
},
477
+
};
478
+
479
+
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
480
+
.cmd_rcgr = 0xc124,
481
+
.mnd_width = 8,
482
+
.hid_width = 5,
483
+
.parent_map = cam_cc_parent_map_0,
484
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
485
+
.clkr.hw.init = &(const struct clk_init_data) {
486
+
.name = "cam_cc_cci_1_clk_src",
487
+
.parent_data = cam_cc_parent_data_0,
488
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
489
+
.flags = CLK_SET_RATE_PARENT,
490
+
.ops = &clk_rcg2_shared_ops,
491
+
},
492
+
};
493
+
494
+
static struct clk_rcg2 cam_cc_cci_2_clk_src = {
495
+
.cmd_rcgr = 0xc204,
496
+
.mnd_width = 8,
497
+
.hid_width = 5,
498
+
.parent_map = cam_cc_parent_map_0,
499
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
500
+
.clkr.hw.init = &(const struct clk_init_data) {
501
+
.name = "cam_cc_cci_2_clk_src",
502
+
.parent_data = cam_cc_parent_data_0,
503
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
504
+
.flags = CLK_SET_RATE_PARENT,
505
+
.ops = &clk_rcg2_shared_ops,
506
+
},
507
+
};
508
+
509
+
static struct clk_rcg2 cam_cc_cci_3_clk_src = {
510
+
.cmd_rcgr = 0xc220,
511
+
.mnd_width = 8,
512
+
.hid_width = 5,
513
+
.parent_map = cam_cc_parent_map_0,
514
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
515
+
.clkr.hw.init = &(const struct clk_init_data) {
516
+
.name = "cam_cc_cci_3_clk_src",
517
+
.parent_data = cam_cc_parent_data_0,
518
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
519
+
.flags = CLK_SET_RATE_PARENT,
520
+
.ops = &clk_rcg2_shared_ops,
521
+
},
522
+
};
523
+
524
+
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
525
+
F(19200000, P_BI_TCXO, 1, 0, 0),
526
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
527
+
{ }
528
+
};
529
+
530
+
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
531
+
.cmd_rcgr = 0xa064,
532
+
.mnd_width = 0,
533
+
.hid_width = 5,
534
+
.parent_map = cam_cc_parent_map_0,
535
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
536
+
.clkr.hw.init = &(const struct clk_init_data) {
537
+
.name = "cam_cc_cphy_rx_clk_src",
538
+
.parent_data = cam_cc_parent_data_0,
539
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
540
+
.flags = CLK_SET_RATE_PARENT,
541
+
.ops = &clk_rcg2_shared_ops,
542
+
},
543
+
};
544
+
545
+
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
546
+
F(19200000, P_BI_TCXO, 1, 0, 0),
547
+
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
548
+
{ }
549
+
};
550
+
551
+
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
552
+
.cmd_rcgr = 0x6004,
553
+
.mnd_width = 0,
554
+
.hid_width = 5,
555
+
.parent_map = cam_cc_parent_map_0,
556
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
557
+
.clkr.hw.init = &(const struct clk_init_data) {
558
+
.name = "cam_cc_csi0phytimer_clk_src",
559
+
.parent_data = cam_cc_parent_data_0,
560
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
561
+
.flags = CLK_SET_RATE_PARENT,
562
+
.ops = &clk_rcg2_shared_ops,
563
+
},
564
+
};
565
+
566
+
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
567
+
.cmd_rcgr = 0x6028,
568
+
.mnd_width = 0,
569
+
.hid_width = 5,
570
+
.parent_map = cam_cc_parent_map_0,
571
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
572
+
.clkr.hw.init = &(const struct clk_init_data) {
573
+
.name = "cam_cc_csi1phytimer_clk_src",
574
+
.parent_data = cam_cc_parent_data_0,
575
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
576
+
.flags = CLK_SET_RATE_PARENT,
577
+
.ops = &clk_rcg2_shared_ops,
578
+
},
579
+
};
580
+
581
+
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
582
+
.cmd_rcgr = 0x604c,
583
+
.mnd_width = 0,
584
+
.hid_width = 5,
585
+
.parent_map = cam_cc_parent_map_0,
586
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
587
+
.clkr.hw.init = &(const struct clk_init_data) {
588
+
.name = "cam_cc_csi2phytimer_clk_src",
589
+
.parent_data = cam_cc_parent_data_0,
590
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
591
+
.flags = CLK_SET_RATE_PARENT,
592
+
.ops = &clk_rcg2_shared_ops,
593
+
},
594
+
};
595
+
596
+
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
597
+
.cmd_rcgr = 0x6070,
598
+
.mnd_width = 0,
599
+
.hid_width = 5,
600
+
.parent_map = cam_cc_parent_map_0,
601
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
602
+
.clkr.hw.init = &(const struct clk_init_data) {
603
+
.name = "cam_cc_csi3phytimer_clk_src",
604
+
.parent_data = cam_cc_parent_data_0,
605
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
606
+
.flags = CLK_SET_RATE_PARENT,
607
+
.ops = &clk_rcg2_shared_ops,
608
+
},
609
+
};
610
+
611
+
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
612
+
F(19200000, P_BI_TCXO, 1, 0, 0),
613
+
F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
614
+
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
615
+
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
616
+
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
617
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
618
+
{ }
619
+
};
620
+
621
+
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
622
+
.cmd_rcgr = 0x703c,
623
+
.mnd_width = 0,
624
+
.hid_width = 5,
625
+
.parent_map = cam_cc_parent_map_0,
626
+
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
627
+
.clkr.hw.init = &(const struct clk_init_data) {
628
+
.name = "cam_cc_fast_ahb_clk_src",
629
+
.parent_data = cam_cc_parent_data_0,
630
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
631
+
.flags = CLK_SET_RATE_PARENT,
632
+
.ops = &clk_rcg2_shared_ops,
633
+
},
634
+
};
635
+
636
+
static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
637
+
F(19200000, P_BI_TCXO, 1, 0, 0),
638
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
639
+
F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
640
+
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
641
+
{ }
642
+
};
643
+
644
+
static struct clk_rcg2 cam_cc_fd_core_clk_src = {
645
+
.cmd_rcgr = 0xc0e0,
646
+
.mnd_width = 0,
647
+
.hid_width = 5,
648
+
.parent_map = cam_cc_parent_map_0,
649
+
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
650
+
.clkr.hw.init = &(const struct clk_init_data) {
651
+
.name = "cam_cc_fd_core_clk_src",
652
+
.parent_data = cam_cc_parent_data_0,
653
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
654
+
.flags = CLK_SET_RATE_PARENT,
655
+
.ops = &clk_rcg2_shared_ops,
656
+
},
657
+
};
658
+
659
+
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
660
+
F(19200000, P_BI_TCXO, 1, 0, 0),
661
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
662
+
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
663
+
{ }
664
+
};
665
+
666
+
static struct clk_rcg2 cam_cc_icp_clk_src = {
667
+
.cmd_rcgr = 0xc0b8,
668
+
.mnd_width = 0,
669
+
.hid_width = 5,
670
+
.parent_map = cam_cc_parent_map_0,
671
+
.freq_tbl = ftbl_cam_cc_icp_clk_src,
672
+
.clkr.hw.init = &(const struct clk_init_data) {
673
+
.name = "cam_cc_icp_clk_src",
674
+
.parent_data = cam_cc_parent_data_0,
675
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
676
+
.flags = CLK_SET_RATE_PARENT,
677
+
.ops = &clk_rcg2_shared_ops,
678
+
},
679
+
};
680
+
681
+
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
682
+
F(19200000, P_BI_TCXO, 1, 0, 0),
683
+
F(400000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
684
+
F(558000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
685
+
F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
686
+
F(760000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
687
+
{ }
688
+
};
689
+
690
+
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
691
+
.cmd_rcgr = 0xa010,
692
+
.mnd_width = 0,
693
+
.hid_width = 5,
694
+
.parent_map = cam_cc_parent_map_2,
695
+
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
696
+
.clkr.hw.init = &(const struct clk_init_data) {
697
+
.name = "cam_cc_ife_0_clk_src",
698
+
.parent_data = cam_cc_parent_data_2,
699
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
700
+
.flags = CLK_SET_RATE_PARENT,
701
+
.ops = &clk_rcg2_shared_ops,
702
+
},
703
+
};
704
+
705
+
static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
706
+
F(19200000, P_BI_TCXO, 1, 0, 0),
707
+
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
708
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
709
+
F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
710
+
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
711
+
{ }
712
+
};
713
+
714
+
static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
715
+
.cmd_rcgr = 0xa03c,
716
+
.mnd_width = 0,
717
+
.hid_width = 5,
718
+
.parent_map = cam_cc_parent_map_0,
719
+
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
720
+
.clkr.hw.init = &(const struct clk_init_data) {
721
+
.name = "cam_cc_ife_0_csid_clk_src",
722
+
.parent_data = cam_cc_parent_data_0,
723
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
724
+
.flags = CLK_SET_RATE_PARENT,
725
+
.ops = &clk_rcg2_shared_ops,
726
+
},
727
+
};
728
+
729
+
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
730
+
F(19200000, P_BI_TCXO, 1, 0, 0),
731
+
F(400000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
732
+
F(558000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
733
+
F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
734
+
F(760000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
735
+
{ }
736
+
};
737
+
738
+
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
739
+
.cmd_rcgr = 0xb010,
740
+
.mnd_width = 0,
741
+
.hid_width = 5,
742
+
.parent_map = cam_cc_parent_map_3,
743
+
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
744
+
.clkr.hw.init = &(const struct clk_init_data) {
745
+
.name = "cam_cc_ife_1_clk_src",
746
+
.parent_data = cam_cc_parent_data_3,
747
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
748
+
.flags = CLK_SET_RATE_PARENT,
749
+
.ops = &clk_rcg2_shared_ops,
750
+
},
751
+
};
752
+
753
+
static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
754
+
.cmd_rcgr = 0xb034,
755
+
.mnd_width = 0,
756
+
.hid_width = 5,
757
+
.parent_map = cam_cc_parent_map_0,
758
+
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
759
+
.clkr.hw.init = &(const struct clk_init_data) {
760
+
.name = "cam_cc_ife_1_csid_clk_src",
761
+
.parent_data = cam_cc_parent_data_0,
762
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
763
+
.flags = CLK_SET_RATE_PARENT,
764
+
.ops = &clk_rcg2_shared_ops,
765
+
},
766
+
};
767
+
768
+
static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
769
+
F(19200000, P_BI_TCXO, 1, 0, 0),
770
+
F(400000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
771
+
F(558000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
772
+
F(637000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
773
+
F(760000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
774
+
{ }
775
+
};
776
+
777
+
static struct clk_rcg2 cam_cc_ife_2_clk_src = {
778
+
.cmd_rcgr = 0xf010,
779
+
.mnd_width = 0,
780
+
.hid_width = 5,
781
+
.parent_map = cam_cc_parent_map_4,
782
+
.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
783
+
.clkr.hw.init = &(const struct clk_init_data) {
784
+
.name = "cam_cc_ife_2_clk_src",
785
+
.parent_data = cam_cc_parent_data_4,
786
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
787
+
.flags = CLK_SET_RATE_PARENT,
788
+
.ops = &clk_rcg2_shared_ops,
789
+
},
790
+
};
791
+
792
+
static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = {
793
+
.cmd_rcgr = 0xf03c,
794
+
.mnd_width = 0,
795
+
.hid_width = 5,
796
+
.parent_map = cam_cc_parent_map_0,
797
+
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
798
+
.clkr.hw.init = &(const struct clk_init_data) {
799
+
.name = "cam_cc_ife_2_csid_clk_src",
800
+
.parent_data = cam_cc_parent_data_0,
801
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
802
+
.flags = CLK_SET_RATE_PARENT,
803
+
.ops = &clk_rcg2_shared_ops,
804
+
},
805
+
};
806
+
807
+
static const struct freq_tbl ftbl_cam_cc_ife_3_clk_src[] = {
808
+
F(19200000, P_BI_TCXO, 1, 0, 0),
809
+
F(400000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
810
+
F(558000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
811
+
F(637000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
812
+
F(760000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
813
+
{ }
814
+
};
815
+
816
+
static struct clk_rcg2 cam_cc_ife_3_clk_src = {
817
+
.cmd_rcgr = 0xf07c,
818
+
.mnd_width = 0,
819
+
.hid_width = 5,
820
+
.parent_map = cam_cc_parent_map_5,
821
+
.freq_tbl = ftbl_cam_cc_ife_3_clk_src,
822
+
.clkr.hw.init = &(const struct clk_init_data) {
823
+
.name = "cam_cc_ife_3_clk_src",
824
+
.parent_data = cam_cc_parent_data_5,
825
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
826
+
.flags = CLK_SET_RATE_PARENT,
827
+
.ops = &clk_rcg2_shared_ops,
828
+
},
829
+
};
830
+
831
+
static struct clk_rcg2 cam_cc_ife_3_csid_clk_src = {
832
+
.cmd_rcgr = 0xf0a8,
833
+
.mnd_width = 0,
834
+
.hid_width = 5,
835
+
.parent_map = cam_cc_parent_map_0,
836
+
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
837
+
.clkr.hw.init = &(const struct clk_init_data) {
838
+
.name = "cam_cc_ife_3_csid_clk_src",
839
+
.parent_data = cam_cc_parent_data_0,
840
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
841
+
.flags = CLK_SET_RATE_PARENT,
842
+
.ops = &clk_rcg2_shared_ops,
843
+
},
844
+
};
845
+
846
+
static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = {
847
+
F(19200000, P_BI_TCXO, 1, 0, 0),
848
+
F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
849
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
850
+
F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
851
+
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
852
+
{ }
853
+
};
854
+
855
+
static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = {
856
+
.cmd_rcgr = 0xc004,
857
+
.mnd_width = 0,
858
+
.hid_width = 5,
859
+
.parent_map = cam_cc_parent_map_0,
860
+
.freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
861
+
.clkr.hw.init = &(const struct clk_init_data) {
862
+
.name = "cam_cc_ife_lite_0_clk_src",
863
+
.parent_data = cam_cc_parent_data_0,
864
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
865
+
.flags = CLK_SET_RATE_PARENT,
866
+
.ops = &clk_rcg2_shared_ops,
867
+
},
868
+
};
869
+
870
+
static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = {
871
+
.cmd_rcgr = 0xc020,
872
+
.mnd_width = 0,
873
+
.hid_width = 5,
874
+
.parent_map = cam_cc_parent_map_0,
875
+
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
876
+
.clkr.hw.init = &(const struct clk_init_data) {
877
+
.name = "cam_cc_ife_lite_0_csid_clk_src",
878
+
.parent_data = cam_cc_parent_data_0,
879
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
880
+
.flags = CLK_SET_RATE_PARENT,
881
+
.ops = &clk_rcg2_shared_ops,
882
+
},
883
+
};
884
+
885
+
static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = {
886
+
.cmd_rcgr = 0xc048,
887
+
.mnd_width = 0,
888
+
.hid_width = 5,
889
+
.parent_map = cam_cc_parent_map_0,
890
+
.freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
891
+
.clkr.hw.init = &(const struct clk_init_data) {
892
+
.name = "cam_cc_ife_lite_1_clk_src",
893
+
.parent_data = cam_cc_parent_data_0,
894
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
895
+
.flags = CLK_SET_RATE_PARENT,
896
+
.ops = &clk_rcg2_shared_ops,
897
+
},
898
+
};
899
+
900
+
static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = {
901
+
.cmd_rcgr = 0xc064,
902
+
.mnd_width = 0,
903
+
.hid_width = 5,
904
+
.parent_map = cam_cc_parent_map_0,
905
+
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
906
+
.clkr.hw.init = &(const struct clk_init_data) {
907
+
.name = "cam_cc_ife_lite_1_csid_clk_src",
908
+
.parent_data = cam_cc_parent_data_0,
909
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
910
+
.flags = CLK_SET_RATE_PARENT,
911
+
.ops = &clk_rcg2_shared_ops,
912
+
},
913
+
};
914
+
915
+
static struct clk_rcg2 cam_cc_ife_lite_2_clk_src = {
916
+
.cmd_rcgr = 0xc240,
917
+
.mnd_width = 0,
918
+
.hid_width = 5,
919
+
.parent_map = cam_cc_parent_map_0,
920
+
.freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
921
+
.clkr.hw.init = &(const struct clk_init_data) {
922
+
.name = "cam_cc_ife_lite_2_clk_src",
923
+
.parent_data = cam_cc_parent_data_0,
924
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
925
+
.flags = CLK_SET_RATE_PARENT,
926
+
.ops = &clk_rcg2_shared_ops,
927
+
},
928
+
};
929
+
930
+
static struct clk_rcg2 cam_cc_ife_lite_2_csid_clk_src = {
931
+
.cmd_rcgr = 0xc25c,
932
+
.mnd_width = 0,
933
+
.hid_width = 5,
934
+
.parent_map = cam_cc_parent_map_0,
935
+
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
936
+
.clkr.hw.init = &(const struct clk_init_data) {
937
+
.name = "cam_cc_ife_lite_2_csid_clk_src",
938
+
.parent_data = cam_cc_parent_data_0,
939
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
940
+
.flags = CLK_SET_RATE_PARENT,
941
+
.ops = &clk_rcg2_shared_ops,
942
+
},
943
+
};
944
+
945
+
static struct clk_rcg2 cam_cc_ife_lite_3_clk_src = {
946
+
.cmd_rcgr = 0xc284,
947
+
.mnd_width = 0,
948
+
.hid_width = 5,
949
+
.parent_map = cam_cc_parent_map_0,
950
+
.freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
951
+
.clkr.hw.init = &(const struct clk_init_data) {
952
+
.name = "cam_cc_ife_lite_3_clk_src",
953
+
.parent_data = cam_cc_parent_data_0,
954
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
955
+
.flags = CLK_SET_RATE_PARENT,
956
+
.ops = &clk_rcg2_shared_ops,
957
+
},
958
+
};
959
+
960
+
static struct clk_rcg2 cam_cc_ife_lite_3_csid_clk_src = {
961
+
.cmd_rcgr = 0xc2a0,
962
+
.mnd_width = 0,
963
+
.hid_width = 5,
964
+
.parent_map = cam_cc_parent_map_0,
965
+
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
966
+
.clkr.hw.init = &(const struct clk_init_data) {
967
+
.name = "cam_cc_ife_lite_3_csid_clk_src",
968
+
.parent_data = cam_cc_parent_data_0,
969
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
970
+
.flags = CLK_SET_RATE_PARENT,
971
+
.ops = &clk_rcg2_shared_ops,
972
+
},
973
+
};
974
+
975
+
static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
976
+
F(19200000, P_BI_TCXO, 1, 0, 0),
977
+
F(375000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
978
+
F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
979
+
F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
980
+
F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
981
+
{ }
982
+
};
983
+
984
+
static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
985
+
.cmd_rcgr = 0x8010,
986
+
.mnd_width = 0,
987
+
.hid_width = 5,
988
+
.parent_map = cam_cc_parent_map_6,
989
+
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
990
+
.clkr.hw.init = &(const struct clk_init_data) {
991
+
.name = "cam_cc_ipe_0_clk_src",
992
+
.parent_data = cam_cc_parent_data_6,
993
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
994
+
.flags = CLK_SET_RATE_PARENT,
995
+
.ops = &clk_rcg2_shared_ops,
996
+
},
997
+
};
998
+
999
+
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1000
+
.cmd_rcgr = 0xc08c,
1001
+
.mnd_width = 0,
1002
+
.hid_width = 5,
1003
+
.parent_map = cam_cc_parent_map_0,
1004
+
.freq_tbl = ftbl_cam_cc_bps_clk_src,
1005
+
.clkr.hw.init = &(const struct clk_init_data) {
1006
+
.name = "cam_cc_jpeg_clk_src",
1007
+
.parent_data = cam_cc_parent_data_0,
1008
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1009
+
.flags = CLK_SET_RATE_PARENT,
1010
+
.ops = &clk_rcg2_shared_ops,
1011
+
},
1012
+
};
1013
+
1014
+
static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
1015
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1016
+
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
1017
+
F(240000000, P_CAM_CC_PLL2_OUT_MAIN, 2, 0, 0),
1018
+
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
1019
+
F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
1020
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1021
+
{ }
1022
+
};
1023
+
1024
+
static struct clk_rcg2 cam_cc_lrme_clk_src = {
1025
+
.cmd_rcgr = 0xc144,
1026
+
.mnd_width = 0,
1027
+
.hid_width = 5,
1028
+
.parent_map = cam_cc_parent_map_0,
1029
+
.freq_tbl = ftbl_cam_cc_lrme_clk_src,
1030
+
.clkr.hw.init = &(const struct clk_init_data) {
1031
+
.name = "cam_cc_lrme_clk_src",
1032
+
.parent_data = cam_cc_parent_data_0,
1033
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1034
+
.flags = CLK_SET_RATE_PARENT,
1035
+
.ops = &clk_rcg2_shared_ops,
1036
+
},
1037
+
};
1038
+
1039
+
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1040
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1041
+
F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 4),
1042
+
F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 14, 0, 0),
1043
+
{ }
1044
+
};
1045
+
1046
+
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1047
+
.cmd_rcgr = 0x5004,
1048
+
.mnd_width = 8,
1049
+
.hid_width = 5,
1050
+
.parent_map = cam_cc_parent_map_1,
1051
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1052
+
.clkr.hw.init = &(const struct clk_init_data) {
1053
+
.name = "cam_cc_mclk0_clk_src",
1054
+
.parent_data = cam_cc_parent_data_1,
1055
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1056
+
.flags = CLK_SET_RATE_PARENT,
1057
+
.ops = &clk_rcg2_shared_ops,
1058
+
},
1059
+
};
1060
+
1061
+
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1062
+
.cmd_rcgr = 0x5024,
1063
+
.mnd_width = 8,
1064
+
.hid_width = 5,
1065
+
.parent_map = cam_cc_parent_map_1,
1066
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1067
+
.clkr.hw.init = &(const struct clk_init_data) {
1068
+
.name = "cam_cc_mclk1_clk_src",
1069
+
.parent_data = cam_cc_parent_data_1,
1070
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1071
+
.flags = CLK_SET_RATE_PARENT,
1072
+
.ops = &clk_rcg2_shared_ops,
1073
+
},
1074
+
};
1075
+
1076
+
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1077
+
.cmd_rcgr = 0x5044,
1078
+
.mnd_width = 8,
1079
+
.hid_width = 5,
1080
+
.parent_map = cam_cc_parent_map_1,
1081
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1082
+
.clkr.hw.init = &(const struct clk_init_data) {
1083
+
.name = "cam_cc_mclk2_clk_src",
1084
+
.parent_data = cam_cc_parent_data_1,
1085
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1086
+
.flags = CLK_SET_RATE_PARENT,
1087
+
.ops = &clk_rcg2_shared_ops,
1088
+
},
1089
+
};
1090
+
1091
+
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1092
+
.cmd_rcgr = 0x5064,
1093
+
.mnd_width = 8,
1094
+
.hid_width = 5,
1095
+
.parent_map = cam_cc_parent_map_1,
1096
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1097
+
.clkr.hw.init = &(const struct clk_init_data) {
1098
+
.name = "cam_cc_mclk3_clk_src",
1099
+
.parent_data = cam_cc_parent_data_1,
1100
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1101
+
.flags = CLK_SET_RATE_PARENT,
1102
+
.ops = &clk_rcg2_shared_ops,
1103
+
},
1104
+
};
1105
+
1106
+
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1107
+
.cmd_rcgr = 0x5084,
1108
+
.mnd_width = 8,
1109
+
.hid_width = 5,
1110
+
.parent_map = cam_cc_parent_map_1,
1111
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1112
+
.clkr.hw.init = &(const struct clk_init_data) {
1113
+
.name = "cam_cc_mclk4_clk_src",
1114
+
.parent_data = cam_cc_parent_data_1,
1115
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1116
+
.flags = CLK_SET_RATE_PARENT,
1117
+
.ops = &clk_rcg2_shared_ops,
1118
+
},
1119
+
};
1120
+
1121
+
static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1122
+
.cmd_rcgr = 0x50a4,
1123
+
.mnd_width = 8,
1124
+
.hid_width = 5,
1125
+
.parent_map = cam_cc_parent_map_1,
1126
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1127
+
.clkr.hw.init = &(const struct clk_init_data) {
1128
+
.name = "cam_cc_mclk5_clk_src",
1129
+
.parent_data = cam_cc_parent_data_1,
1130
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1131
+
.flags = CLK_SET_RATE_PARENT,
1132
+
.ops = &clk_rcg2_shared_ops,
1133
+
},
1134
+
};
1135
+
1136
+
static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1137
+
.cmd_rcgr = 0x50c4,
1138
+
.mnd_width = 8,
1139
+
.hid_width = 5,
1140
+
.parent_map = cam_cc_parent_map_1,
1141
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1142
+
.clkr.hw.init = &(const struct clk_init_data) {
1143
+
.name = "cam_cc_mclk6_clk_src",
1144
+
.parent_data = cam_cc_parent_data_1,
1145
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1146
+
.flags = CLK_SET_RATE_PARENT,
1147
+
.ops = &clk_rcg2_shared_ops,
1148
+
},
1149
+
};
1150
+
1151
+
static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1152
+
.cmd_rcgr = 0x50e4,
1153
+
.mnd_width = 8,
1154
+
.hid_width = 5,
1155
+
.parent_map = cam_cc_parent_map_1,
1156
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1157
+
.clkr.hw.init = &(const struct clk_init_data) {
1158
+
.name = "cam_cc_mclk7_clk_src",
1159
+
.parent_data = cam_cc_parent_data_1,
1160
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1161
+
.flags = CLK_SET_RATE_PARENT,
1162
+
.ops = &clk_rcg2_shared_ops,
1163
+
},
1164
+
};
1165
+
1166
+
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1167
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1168
+
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1169
+
{ }
1170
+
};
1171
+
1172
+
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1173
+
.cmd_rcgr = 0x7058,
1174
+
.mnd_width = 8,
1175
+
.hid_width = 5,
1176
+
.parent_map = cam_cc_parent_map_0,
1177
+
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1178
+
.clkr.hw.init = &(const struct clk_init_data) {
1179
+
.name = "cam_cc_slow_ahb_clk_src",
1180
+
.parent_data = cam_cc_parent_data_0,
1181
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1182
+
.flags = CLK_SET_RATE_PARENT,
1183
+
.ops = &clk_rcg2_shared_ops,
1184
+
},
1185
+
};
1186
+
1187
+
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1188
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1189
+
{ }
1190
+
};
1191
+
1192
+
static struct clk_rcg2 cam_cc_xo_clk_src = {
1193
+
.cmd_rcgr = 0xc1cc,
1194
+
.mnd_width = 0,
1195
+
.hid_width = 5,
1196
+
.parent_map = cam_cc_parent_map_7,
1197
+
.freq_tbl = ftbl_cam_cc_xo_clk_src,
1198
+
.clkr.hw.init = &(const struct clk_init_data) {
1199
+
.name = "cam_cc_xo_clk_src",
1200
+
.parent_data = cam_cc_parent_data_7,
1201
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1202
+
.flags = CLK_SET_RATE_PARENT,
1203
+
.ops = &clk_rcg2_shared_ops,
1204
+
},
1205
+
};
1206
+
1207
+
static struct clk_branch cam_cc_bps_ahb_clk = {
1208
+
.halt_reg = 0x7070,
1209
+
.halt_check = BRANCH_HALT,
1210
+
.clkr = {
1211
+
.enable_reg = 0x7070,
1212
+
.enable_mask = BIT(0),
1213
+
.hw.init = &(const struct clk_init_data) {
1214
+
.name = "cam_cc_bps_ahb_clk",
1215
+
.parent_hws = (const struct clk_hw*[]) {
1216
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1217
+
},
1218
+
.num_parents = 1,
1219
+
.flags = CLK_SET_RATE_PARENT,
1220
+
.ops = &clk_branch2_ops,
1221
+
},
1222
+
},
1223
+
};
1224
+
1225
+
static struct clk_branch cam_cc_bps_areg_clk = {
1226
+
.halt_reg = 0x7054,
1227
+
.halt_check = BRANCH_HALT,
1228
+
.clkr = {
1229
+
.enable_reg = 0x7054,
1230
+
.enable_mask = BIT(0),
1231
+
.hw.init = &(const struct clk_init_data) {
1232
+
.name = "cam_cc_bps_areg_clk",
1233
+
.parent_hws = (const struct clk_hw*[]) {
1234
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
1235
+
},
1236
+
.num_parents = 1,
1237
+
.flags = CLK_SET_RATE_PARENT,
1238
+
.ops = &clk_branch2_ops,
1239
+
},
1240
+
},
1241
+
};
1242
+
1243
+
static struct clk_branch cam_cc_bps_axi_clk = {
1244
+
.halt_reg = 0x7038,
1245
+
.halt_check = BRANCH_HALT,
1246
+
.clkr = {
1247
+
.enable_reg = 0x7038,
1248
+
.enable_mask = BIT(0),
1249
+
.hw.init = &(const struct clk_init_data) {
1250
+
.name = "cam_cc_bps_axi_clk",
1251
+
.parent_hws = (const struct clk_hw*[]) {
1252
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
1253
+
},
1254
+
.num_parents = 1,
1255
+
.flags = CLK_SET_RATE_PARENT,
1256
+
.ops = &clk_branch2_ops,
1257
+
},
1258
+
},
1259
+
};
1260
+
1261
+
static struct clk_branch cam_cc_bps_clk = {
1262
+
.halt_reg = 0x7028,
1263
+
.halt_check = BRANCH_HALT,
1264
+
.clkr = {
1265
+
.enable_reg = 0x7028,
1266
+
.enable_mask = BIT(0),
1267
+
.hw.init = &(const struct clk_init_data) {
1268
+
.name = "cam_cc_bps_clk",
1269
+
.parent_hws = (const struct clk_hw*[]) {
1270
+
&cam_cc_bps_clk_src.clkr.hw,
1271
+
},
1272
+
.num_parents = 1,
1273
+
.flags = CLK_SET_RATE_PARENT,
1274
+
.ops = &clk_branch2_ops,
1275
+
},
1276
+
},
1277
+
};
1278
+
1279
+
static struct clk_branch cam_cc_camnoc_axi_clk = {
1280
+
.halt_reg = 0xc18c,
1281
+
.halt_check = BRANCH_HALT,
1282
+
.clkr = {
1283
+
.enable_reg = 0xc18c,
1284
+
.enable_mask = BIT(0),
1285
+
.hw.init = &(const struct clk_init_data) {
1286
+
.name = "cam_cc_camnoc_axi_clk",
1287
+
.parent_hws = (const struct clk_hw*[]) {
1288
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
1289
+
},
1290
+
.num_parents = 1,
1291
+
.flags = CLK_SET_RATE_PARENT,
1292
+
.ops = &clk_branch2_ops,
1293
+
},
1294
+
},
1295
+
};
1296
+
1297
+
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1298
+
.halt_reg = 0xc194,
1299
+
.halt_check = BRANCH_HALT,
1300
+
.clkr = {
1301
+
.enable_reg = 0xc194,
1302
+
.enable_mask = BIT(0),
1303
+
.hw.init = &(const struct clk_init_data) {
1304
+
.name = "cam_cc_camnoc_dcd_xo_clk",
1305
+
.parent_hws = (const struct clk_hw*[]) {
1306
+
&cam_cc_xo_clk_src.clkr.hw,
1307
+
},
1308
+
.num_parents = 1,
1309
+
.flags = CLK_SET_RATE_PARENT,
1310
+
.ops = &clk_branch2_ops,
1311
+
},
1312
+
},
1313
+
};
1314
+
1315
+
static struct clk_branch cam_cc_cci_0_clk = {
1316
+
.halt_reg = 0xc120,
1317
+
.halt_check = BRANCH_HALT,
1318
+
.clkr = {
1319
+
.enable_reg = 0xc120,
1320
+
.enable_mask = BIT(0),
1321
+
.hw.init = &(const struct clk_init_data) {
1322
+
.name = "cam_cc_cci_0_clk",
1323
+
.parent_hws = (const struct clk_hw*[]) {
1324
+
&cam_cc_cci_0_clk_src.clkr.hw,
1325
+
},
1326
+
.num_parents = 1,
1327
+
.flags = CLK_SET_RATE_PARENT,
1328
+
.ops = &clk_branch2_ops,
1329
+
},
1330
+
},
1331
+
};
1332
+
1333
+
static struct clk_branch cam_cc_cci_1_clk = {
1334
+
.halt_reg = 0xc13c,
1335
+
.halt_check = BRANCH_HALT,
1336
+
.clkr = {
1337
+
.enable_reg = 0xc13c,
1338
+
.enable_mask = BIT(0),
1339
+
.hw.init = &(const struct clk_init_data) {
1340
+
.name = "cam_cc_cci_1_clk",
1341
+
.parent_hws = (const struct clk_hw*[]) {
1342
+
&cam_cc_cci_1_clk_src.clkr.hw,
1343
+
},
1344
+
.num_parents = 1,
1345
+
.flags = CLK_SET_RATE_PARENT,
1346
+
.ops = &clk_branch2_ops,
1347
+
},
1348
+
},
1349
+
};
1350
+
1351
+
static struct clk_branch cam_cc_cci_2_clk = {
1352
+
.halt_reg = 0xc21c,
1353
+
.halt_check = BRANCH_HALT,
1354
+
.clkr = {
1355
+
.enable_reg = 0xc21c,
1356
+
.enable_mask = BIT(0),
1357
+
.hw.init = &(const struct clk_init_data) {
1358
+
.name = "cam_cc_cci_2_clk",
1359
+
.parent_hws = (const struct clk_hw*[]) {
1360
+
&cam_cc_cci_2_clk_src.clkr.hw,
1361
+
},
1362
+
.num_parents = 1,
1363
+
.flags = CLK_SET_RATE_PARENT,
1364
+
.ops = &clk_branch2_ops,
1365
+
},
1366
+
},
1367
+
};
1368
+
1369
+
static struct clk_branch cam_cc_cci_3_clk = {
1370
+
.halt_reg = 0xc238,
1371
+
.halt_check = BRANCH_HALT,
1372
+
.clkr = {
1373
+
.enable_reg = 0xc238,
1374
+
.enable_mask = BIT(0),
1375
+
.hw.init = &(const struct clk_init_data) {
1376
+
.name = "cam_cc_cci_3_clk",
1377
+
.parent_hws = (const struct clk_hw*[]) {
1378
+
&cam_cc_cci_3_clk_src.clkr.hw,
1379
+
},
1380
+
.num_parents = 1,
1381
+
.flags = CLK_SET_RATE_PARENT,
1382
+
.ops = &clk_branch2_ops,
1383
+
},
1384
+
},
1385
+
};
1386
+
1387
+
static struct clk_branch cam_cc_core_ahb_clk = {
1388
+
.halt_reg = 0xc1c8,
1389
+
.halt_check = BRANCH_HALT_VOTED,
1390
+
.clkr = {
1391
+
.enable_reg = 0xc1c8,
1392
+
.enable_mask = BIT(0),
1393
+
.hw.init = &(const struct clk_init_data) {
1394
+
.name = "cam_cc_core_ahb_clk",
1395
+
.parent_hws = (const struct clk_hw*[]) {
1396
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1397
+
},
1398
+
.num_parents = 1,
1399
+
.flags = CLK_SET_RATE_PARENT,
1400
+
.ops = &clk_branch2_ops,
1401
+
},
1402
+
},
1403
+
};
1404
+
1405
+
static struct clk_branch cam_cc_cpas_ahb_clk = {
1406
+
.halt_reg = 0xc168,
1407
+
.halt_check = BRANCH_HALT,
1408
+
.clkr = {
1409
+
.enable_reg = 0xc168,
1410
+
.enable_mask = BIT(0),
1411
+
.hw.init = &(const struct clk_init_data) {
1412
+
.name = "cam_cc_cpas_ahb_clk",
1413
+
.parent_hws = (const struct clk_hw*[]) {
1414
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1415
+
},
1416
+
.num_parents = 1,
1417
+
.flags = CLK_SET_RATE_PARENT,
1418
+
.ops = &clk_branch2_ops,
1419
+
},
1420
+
},
1421
+
};
1422
+
1423
+
static struct clk_branch cam_cc_csi0phytimer_clk = {
1424
+
.halt_reg = 0x601c,
1425
+
.halt_check = BRANCH_HALT,
1426
+
.clkr = {
1427
+
.enable_reg = 0x601c,
1428
+
.enable_mask = BIT(0),
1429
+
.hw.init = &(const struct clk_init_data) {
1430
+
.name = "cam_cc_csi0phytimer_clk",
1431
+
.parent_hws = (const struct clk_hw*[]) {
1432
+
&cam_cc_csi0phytimer_clk_src.clkr.hw,
1433
+
},
1434
+
.num_parents = 1,
1435
+
.flags = CLK_SET_RATE_PARENT,
1436
+
.ops = &clk_branch2_ops,
1437
+
},
1438
+
},
1439
+
};
1440
+
1441
+
static struct clk_branch cam_cc_csi1phytimer_clk = {
1442
+
.halt_reg = 0x6040,
1443
+
.halt_check = BRANCH_HALT,
1444
+
.clkr = {
1445
+
.enable_reg = 0x6040,
1446
+
.enable_mask = BIT(0),
1447
+
.hw.init = &(const struct clk_init_data) {
1448
+
.name = "cam_cc_csi1phytimer_clk",
1449
+
.parent_hws = (const struct clk_hw*[]) {
1450
+
&cam_cc_csi1phytimer_clk_src.clkr.hw,
1451
+
},
1452
+
.num_parents = 1,
1453
+
.flags = CLK_SET_RATE_PARENT,
1454
+
.ops = &clk_branch2_ops,
1455
+
},
1456
+
},
1457
+
};
1458
+
1459
+
static struct clk_branch cam_cc_csi2phytimer_clk = {
1460
+
.halt_reg = 0x6064,
1461
+
.halt_check = BRANCH_HALT,
1462
+
.clkr = {
1463
+
.enable_reg = 0x6064,
1464
+
.enable_mask = BIT(0),
1465
+
.hw.init = &(const struct clk_init_data) {
1466
+
.name = "cam_cc_csi2phytimer_clk",
1467
+
.parent_hws = (const struct clk_hw*[]) {
1468
+
&cam_cc_csi2phytimer_clk_src.clkr.hw,
1469
+
},
1470
+
.num_parents = 1,
1471
+
.flags = CLK_SET_RATE_PARENT,
1472
+
.ops = &clk_branch2_ops,
1473
+
},
1474
+
},
1475
+
};
1476
+
1477
+
static struct clk_branch cam_cc_csi3phytimer_clk = {
1478
+
.halt_reg = 0x6088,
1479
+
.halt_check = BRANCH_HALT,
1480
+
.clkr = {
1481
+
.enable_reg = 0x6088,
1482
+
.enable_mask = BIT(0),
1483
+
.hw.init = &(const struct clk_init_data) {
1484
+
.name = "cam_cc_csi3phytimer_clk",
1485
+
.parent_hws = (const struct clk_hw*[]) {
1486
+
&cam_cc_csi3phytimer_clk_src.clkr.hw,
1487
+
},
1488
+
.num_parents = 1,
1489
+
.flags = CLK_SET_RATE_PARENT,
1490
+
.ops = &clk_branch2_ops,
1491
+
},
1492
+
},
1493
+
};
1494
+
1495
+
static struct clk_branch cam_cc_csiphy0_clk = {
1496
+
.halt_reg = 0x6020,
1497
+
.halt_check = BRANCH_HALT,
1498
+
.clkr = {
1499
+
.enable_reg = 0x6020,
1500
+
.enable_mask = BIT(0),
1501
+
.hw.init = &(const struct clk_init_data) {
1502
+
.name = "cam_cc_csiphy0_clk",
1503
+
.parent_hws = (const struct clk_hw*[]) {
1504
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1505
+
},
1506
+
.num_parents = 1,
1507
+
.flags = CLK_SET_RATE_PARENT,
1508
+
.ops = &clk_branch2_ops,
1509
+
},
1510
+
},
1511
+
};
1512
+
1513
+
static struct clk_branch cam_cc_csiphy1_clk = {
1514
+
.halt_reg = 0x6044,
1515
+
.halt_check = BRANCH_HALT,
1516
+
.clkr = {
1517
+
.enable_reg = 0x6044,
1518
+
.enable_mask = BIT(0),
1519
+
.hw.init = &(const struct clk_init_data) {
1520
+
.name = "cam_cc_csiphy1_clk",
1521
+
.parent_hws = (const struct clk_hw*[]) {
1522
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1523
+
},
1524
+
.num_parents = 1,
1525
+
.flags = CLK_SET_RATE_PARENT,
1526
+
.ops = &clk_branch2_ops,
1527
+
},
1528
+
},
1529
+
};
1530
+
1531
+
static struct clk_branch cam_cc_csiphy2_clk = {
1532
+
.halt_reg = 0x6068,
1533
+
.halt_check = BRANCH_HALT,
1534
+
.clkr = {
1535
+
.enable_reg = 0x6068,
1536
+
.enable_mask = BIT(0),
1537
+
.hw.init = &(const struct clk_init_data) {
1538
+
.name = "cam_cc_csiphy2_clk",
1539
+
.parent_hws = (const struct clk_hw*[]) {
1540
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1541
+
},
1542
+
.num_parents = 1,
1543
+
.flags = CLK_SET_RATE_PARENT,
1544
+
.ops = &clk_branch2_ops,
1545
+
},
1546
+
},
1547
+
};
1548
+
1549
+
static struct clk_branch cam_cc_csiphy3_clk = {
1550
+
.halt_reg = 0x608c,
1551
+
.halt_check = BRANCH_HALT,
1552
+
.clkr = {
1553
+
.enable_reg = 0x608c,
1554
+
.enable_mask = BIT(0),
1555
+
.hw.init = &(const struct clk_init_data) {
1556
+
.name = "cam_cc_csiphy3_clk",
1557
+
.parent_hws = (const struct clk_hw*[]) {
1558
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1559
+
},
1560
+
.num_parents = 1,
1561
+
.flags = CLK_SET_RATE_PARENT,
1562
+
.ops = &clk_branch2_ops,
1563
+
},
1564
+
},
1565
+
};
1566
+
1567
+
static struct clk_branch cam_cc_fd_core_clk = {
1568
+
.halt_reg = 0xc0f8,
1569
+
.halt_check = BRANCH_HALT,
1570
+
.clkr = {
1571
+
.enable_reg = 0xc0f8,
1572
+
.enable_mask = BIT(0),
1573
+
.hw.init = &(const struct clk_init_data) {
1574
+
.name = "cam_cc_fd_core_clk",
1575
+
.parent_hws = (const struct clk_hw*[]) {
1576
+
&cam_cc_fd_core_clk_src.clkr.hw,
1577
+
},
1578
+
.num_parents = 1,
1579
+
.flags = CLK_SET_RATE_PARENT,
1580
+
.ops = &clk_branch2_ops,
1581
+
},
1582
+
},
1583
+
};
1584
+
1585
+
static struct clk_branch cam_cc_fd_core_uar_clk = {
1586
+
.halt_reg = 0xc100,
1587
+
.halt_check = BRANCH_HALT,
1588
+
.clkr = {
1589
+
.enable_reg = 0xc100,
1590
+
.enable_mask = BIT(0),
1591
+
.hw.init = &(const struct clk_init_data) {
1592
+
.name = "cam_cc_fd_core_uar_clk",
1593
+
.parent_hws = (const struct clk_hw*[]) {
1594
+
&cam_cc_fd_core_clk_src.clkr.hw,
1595
+
},
1596
+
.num_parents = 1,
1597
+
.flags = CLK_SET_RATE_PARENT,
1598
+
.ops = &clk_branch2_ops,
1599
+
},
1600
+
},
1601
+
};
1602
+
1603
+
static struct clk_branch cam_cc_icp_ahb_clk = {
1604
+
.halt_reg = 0xc0d8,
1605
+
.halt_check = BRANCH_HALT,
1606
+
.clkr = {
1607
+
.enable_reg = 0xc0d8,
1608
+
.enable_mask = BIT(0),
1609
+
.hw.init = &(const struct clk_init_data) {
1610
+
.name = "cam_cc_icp_ahb_clk",
1611
+
.parent_hws = (const struct clk_hw*[]) {
1612
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1613
+
},
1614
+
.num_parents = 1,
1615
+
.flags = CLK_SET_RATE_PARENT,
1616
+
.ops = &clk_branch2_ops,
1617
+
},
1618
+
},
1619
+
};
1620
+
1621
+
static struct clk_branch cam_cc_icp_clk = {
1622
+
.halt_reg = 0xc0d0,
1623
+
.halt_check = BRANCH_HALT,
1624
+
.clkr = {
1625
+
.enable_reg = 0xc0d0,
1626
+
.enable_mask = BIT(0),
1627
+
.hw.init = &(const struct clk_init_data) {
1628
+
.name = "cam_cc_icp_clk",
1629
+
.parent_hws = (const struct clk_hw*[]) {
1630
+
&cam_cc_icp_clk_src.clkr.hw,
1631
+
},
1632
+
.num_parents = 1,
1633
+
.flags = CLK_SET_RATE_PARENT,
1634
+
.ops = &clk_branch2_ops,
1635
+
},
1636
+
},
1637
+
};
1638
+
1639
+
static struct clk_branch cam_cc_ife_0_axi_clk = {
1640
+
.halt_reg = 0xa080,
1641
+
.halt_check = BRANCH_HALT,
1642
+
.clkr = {
1643
+
.enable_reg = 0xa080,
1644
+
.enable_mask = BIT(0),
1645
+
.hw.init = &(const struct clk_init_data) {
1646
+
.name = "cam_cc_ife_0_axi_clk",
1647
+
.parent_hws = (const struct clk_hw*[]) {
1648
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
1649
+
},
1650
+
.num_parents = 1,
1651
+
.flags = CLK_SET_RATE_PARENT,
1652
+
.ops = &clk_branch2_ops,
1653
+
},
1654
+
},
1655
+
};
1656
+
1657
+
static struct clk_branch cam_cc_ife_0_clk = {
1658
+
.halt_reg = 0xa028,
1659
+
.halt_check = BRANCH_HALT,
1660
+
.clkr = {
1661
+
.enable_reg = 0xa028,
1662
+
.enable_mask = BIT(0),
1663
+
.hw.init = &(const struct clk_init_data) {
1664
+
.name = "cam_cc_ife_0_clk",
1665
+
.parent_hws = (const struct clk_hw*[]) {
1666
+
&cam_cc_ife_0_clk_src.clkr.hw,
1667
+
},
1668
+
.num_parents = 1,
1669
+
.flags = CLK_SET_RATE_PARENT,
1670
+
.ops = &clk_branch2_ops,
1671
+
},
1672
+
},
1673
+
};
1674
+
1675
+
static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1676
+
.halt_reg = 0xa07c,
1677
+
.halt_check = BRANCH_HALT,
1678
+
.clkr = {
1679
+
.enable_reg = 0xa07c,
1680
+
.enable_mask = BIT(0),
1681
+
.hw.init = &(const struct clk_init_data) {
1682
+
.name = "cam_cc_ife_0_cphy_rx_clk",
1683
+
.parent_hws = (const struct clk_hw*[]) {
1684
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1685
+
},
1686
+
.num_parents = 1,
1687
+
.flags = CLK_SET_RATE_PARENT,
1688
+
.ops = &clk_branch2_ops,
1689
+
},
1690
+
},
1691
+
};
1692
+
1693
+
static struct clk_branch cam_cc_ife_0_csid_clk = {
1694
+
.halt_reg = 0xa054,
1695
+
.halt_check = BRANCH_HALT,
1696
+
.clkr = {
1697
+
.enable_reg = 0xa054,
1698
+
.enable_mask = BIT(0),
1699
+
.hw.init = &(const struct clk_init_data) {
1700
+
.name = "cam_cc_ife_0_csid_clk",
1701
+
.parent_hws = (const struct clk_hw*[]) {
1702
+
&cam_cc_ife_0_csid_clk_src.clkr.hw,
1703
+
},
1704
+
.num_parents = 1,
1705
+
.flags = CLK_SET_RATE_PARENT,
1706
+
.ops = &clk_branch2_ops,
1707
+
},
1708
+
},
1709
+
};
1710
+
1711
+
static struct clk_branch cam_cc_ife_0_dsp_clk = {
1712
+
.halt_reg = 0xa038,
1713
+
.halt_check = BRANCH_HALT,
1714
+
.clkr = {
1715
+
.enable_reg = 0xa038,
1716
+
.enable_mask = BIT(0),
1717
+
.hw.init = &(const struct clk_init_data) {
1718
+
.name = "cam_cc_ife_0_dsp_clk",
1719
+
.parent_hws = (const struct clk_hw*[]) {
1720
+
&cam_cc_ife_0_clk_src.clkr.hw,
1721
+
},
1722
+
.num_parents = 1,
1723
+
.flags = CLK_SET_RATE_PARENT,
1724
+
.ops = &clk_branch2_ops,
1725
+
},
1726
+
},
1727
+
};
1728
+
1729
+
static struct clk_branch cam_cc_ife_1_axi_clk = {
1730
+
.halt_reg = 0xb058,
1731
+
.halt_check = BRANCH_HALT,
1732
+
.clkr = {
1733
+
.enable_reg = 0xb058,
1734
+
.enable_mask = BIT(0),
1735
+
.hw.init = &(const struct clk_init_data) {
1736
+
.name = "cam_cc_ife_1_axi_clk",
1737
+
.parent_hws = (const struct clk_hw*[]) {
1738
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
1739
+
},
1740
+
.num_parents = 1,
1741
+
.flags = CLK_SET_RATE_PARENT,
1742
+
.ops = &clk_branch2_ops,
1743
+
},
1744
+
},
1745
+
};
1746
+
1747
+
static struct clk_branch cam_cc_ife_1_clk = {
1748
+
.halt_reg = 0xb028,
1749
+
.halt_check = BRANCH_HALT,
1750
+
.clkr = {
1751
+
.enable_reg = 0xb028,
1752
+
.enable_mask = BIT(0),
1753
+
.hw.init = &(const struct clk_init_data) {
1754
+
.name = "cam_cc_ife_1_clk",
1755
+
.parent_hws = (const struct clk_hw*[]) {
1756
+
&cam_cc_ife_1_clk_src.clkr.hw,
1757
+
},
1758
+
.num_parents = 1,
1759
+
.flags = CLK_SET_RATE_PARENT,
1760
+
.ops = &clk_branch2_ops,
1761
+
},
1762
+
},
1763
+
};
1764
+
1765
+
static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1766
+
.halt_reg = 0xb054,
1767
+
.halt_check = BRANCH_HALT,
1768
+
.clkr = {
1769
+
.enable_reg = 0xb054,
1770
+
.enable_mask = BIT(0),
1771
+
.hw.init = &(const struct clk_init_data) {
1772
+
.name = "cam_cc_ife_1_cphy_rx_clk",
1773
+
.parent_hws = (const struct clk_hw*[]) {
1774
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1775
+
},
1776
+
.num_parents = 1,
1777
+
.flags = CLK_SET_RATE_PARENT,
1778
+
.ops = &clk_branch2_ops,
1779
+
},
1780
+
},
1781
+
};
1782
+
1783
+
static struct clk_branch cam_cc_ife_1_csid_clk = {
1784
+
.halt_reg = 0xb04c,
1785
+
.halt_check = BRANCH_HALT,
1786
+
.clkr = {
1787
+
.enable_reg = 0xb04c,
1788
+
.enable_mask = BIT(0),
1789
+
.hw.init = &(const struct clk_init_data) {
1790
+
.name = "cam_cc_ife_1_csid_clk",
1791
+
.parent_hws = (const struct clk_hw*[]) {
1792
+
&cam_cc_ife_1_csid_clk_src.clkr.hw,
1793
+
},
1794
+
.num_parents = 1,
1795
+
.flags = CLK_SET_RATE_PARENT,
1796
+
.ops = &clk_branch2_ops,
1797
+
},
1798
+
},
1799
+
};
1800
+
1801
+
static struct clk_branch cam_cc_ife_1_dsp_clk = {
1802
+
.halt_reg = 0xb030,
1803
+
.halt_check = BRANCH_HALT,
1804
+
.clkr = {
1805
+
.enable_reg = 0xb030,
1806
+
.enable_mask = BIT(0),
1807
+
.hw.init = &(const struct clk_init_data) {
1808
+
.name = "cam_cc_ife_1_dsp_clk",
1809
+
.parent_hws = (const struct clk_hw*[]) {
1810
+
&cam_cc_ife_1_clk_src.clkr.hw,
1811
+
},
1812
+
.num_parents = 1,
1813
+
.flags = CLK_SET_RATE_PARENT,
1814
+
.ops = &clk_branch2_ops,
1815
+
},
1816
+
},
1817
+
};
1818
+
1819
+
static struct clk_branch cam_cc_ife_2_axi_clk = {
1820
+
.halt_reg = 0xf068,
1821
+
.halt_check = BRANCH_HALT,
1822
+
.clkr = {
1823
+
.enable_reg = 0xf068,
1824
+
.enable_mask = BIT(0),
1825
+
.hw.init = &(const struct clk_init_data) {
1826
+
.name = "cam_cc_ife_2_axi_clk",
1827
+
.parent_hws = (const struct clk_hw*[]) {
1828
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
1829
+
},
1830
+
.num_parents = 1,
1831
+
.flags = CLK_SET_RATE_PARENT,
1832
+
.ops = &clk_branch2_ops,
1833
+
},
1834
+
},
1835
+
};
1836
+
1837
+
static struct clk_branch cam_cc_ife_2_clk = {
1838
+
.halt_reg = 0xf028,
1839
+
.halt_check = BRANCH_HALT,
1840
+
.clkr = {
1841
+
.enable_reg = 0xf028,
1842
+
.enable_mask = BIT(0),
1843
+
.hw.init = &(const struct clk_init_data) {
1844
+
.name = "cam_cc_ife_2_clk",
1845
+
.parent_hws = (const struct clk_hw*[]) {
1846
+
&cam_cc_ife_2_clk_src.clkr.hw,
1847
+
},
1848
+
.num_parents = 1,
1849
+
.flags = CLK_SET_RATE_PARENT,
1850
+
.ops = &clk_branch2_ops,
1851
+
},
1852
+
},
1853
+
};
1854
+
1855
+
static struct clk_branch cam_cc_ife_2_cphy_rx_clk = {
1856
+
.halt_reg = 0xf064,
1857
+
.halt_check = BRANCH_HALT,
1858
+
.clkr = {
1859
+
.enable_reg = 0xf064,
1860
+
.enable_mask = BIT(0),
1861
+
.hw.init = &(const struct clk_init_data) {
1862
+
.name = "cam_cc_ife_2_cphy_rx_clk",
1863
+
.parent_hws = (const struct clk_hw*[]) {
1864
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1865
+
},
1866
+
.num_parents = 1,
1867
+
.flags = CLK_SET_RATE_PARENT,
1868
+
.ops = &clk_branch2_ops,
1869
+
},
1870
+
},
1871
+
};
1872
+
1873
+
static struct clk_branch cam_cc_ife_2_csid_clk = {
1874
+
.halt_reg = 0xf054,
1875
+
.halt_check = BRANCH_HALT,
1876
+
.clkr = {
1877
+
.enable_reg = 0xf054,
1878
+
.enable_mask = BIT(0),
1879
+
.hw.init = &(const struct clk_init_data) {
1880
+
.name = "cam_cc_ife_2_csid_clk",
1881
+
.parent_hws = (const struct clk_hw*[]) {
1882
+
&cam_cc_ife_2_csid_clk_src.clkr.hw,
1883
+
},
1884
+
.num_parents = 1,
1885
+
.flags = CLK_SET_RATE_PARENT,
1886
+
.ops = &clk_branch2_ops,
1887
+
},
1888
+
},
1889
+
};
1890
+
1891
+
static struct clk_branch cam_cc_ife_2_dsp_clk = {
1892
+
.halt_reg = 0xf038,
1893
+
.halt_check = BRANCH_HALT,
1894
+
.clkr = {
1895
+
.enable_reg = 0xf038,
1896
+
.enable_mask = BIT(0),
1897
+
.hw.init = &(const struct clk_init_data) {
1898
+
.name = "cam_cc_ife_2_dsp_clk",
1899
+
.parent_hws = (const struct clk_hw*[]) {
1900
+
&cam_cc_ife_2_clk_src.clkr.hw,
1901
+
},
1902
+
.num_parents = 1,
1903
+
.flags = CLK_SET_RATE_PARENT,
1904
+
.ops = &clk_branch2_ops,
1905
+
},
1906
+
},
1907
+
};
1908
+
1909
+
static struct clk_branch cam_cc_ife_3_axi_clk = {
1910
+
.halt_reg = 0xf0d4,
1911
+
.halt_check = BRANCH_HALT,
1912
+
.clkr = {
1913
+
.enable_reg = 0xf0d4,
1914
+
.enable_mask = BIT(0),
1915
+
.hw.init = &(const struct clk_init_data) {
1916
+
.name = "cam_cc_ife_3_axi_clk",
1917
+
.parent_hws = (const struct clk_hw*[]) {
1918
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
1919
+
},
1920
+
.num_parents = 1,
1921
+
.flags = CLK_SET_RATE_PARENT,
1922
+
.ops = &clk_branch2_ops,
1923
+
},
1924
+
},
1925
+
};
1926
+
1927
+
static struct clk_branch cam_cc_ife_3_clk = {
1928
+
.halt_reg = 0xf094,
1929
+
.halt_check = BRANCH_HALT,
1930
+
.clkr = {
1931
+
.enable_reg = 0xf094,
1932
+
.enable_mask = BIT(0),
1933
+
.hw.init = &(const struct clk_init_data) {
1934
+
.name = "cam_cc_ife_3_clk",
1935
+
.parent_hws = (const struct clk_hw*[]) {
1936
+
&cam_cc_ife_3_clk_src.clkr.hw,
1937
+
},
1938
+
.num_parents = 1,
1939
+
.flags = CLK_SET_RATE_PARENT,
1940
+
.ops = &clk_branch2_ops,
1941
+
},
1942
+
},
1943
+
};
1944
+
1945
+
static struct clk_branch cam_cc_ife_3_cphy_rx_clk = {
1946
+
.halt_reg = 0xf0d0,
1947
+
.halt_check = BRANCH_HALT,
1948
+
.clkr = {
1949
+
.enable_reg = 0xf0d0,
1950
+
.enable_mask = BIT(0),
1951
+
.hw.init = &(const struct clk_init_data) {
1952
+
.name = "cam_cc_ife_3_cphy_rx_clk",
1953
+
.parent_hws = (const struct clk_hw*[]) {
1954
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1955
+
},
1956
+
.num_parents = 1,
1957
+
.flags = CLK_SET_RATE_PARENT,
1958
+
.ops = &clk_branch2_ops,
1959
+
},
1960
+
},
1961
+
};
1962
+
1963
+
static struct clk_branch cam_cc_ife_3_csid_clk = {
1964
+
.halt_reg = 0xf0c0,
1965
+
.halt_check = BRANCH_HALT,
1966
+
.clkr = {
1967
+
.enable_reg = 0xf0c0,
1968
+
.enable_mask = BIT(0),
1969
+
.hw.init = &(const struct clk_init_data) {
1970
+
.name = "cam_cc_ife_3_csid_clk",
1971
+
.parent_hws = (const struct clk_hw*[]) {
1972
+
&cam_cc_ife_3_csid_clk_src.clkr.hw,
1973
+
},
1974
+
.num_parents = 1,
1975
+
.flags = CLK_SET_RATE_PARENT,
1976
+
.ops = &clk_branch2_ops,
1977
+
},
1978
+
},
1979
+
};
1980
+
1981
+
static struct clk_branch cam_cc_ife_3_dsp_clk = {
1982
+
.halt_reg = 0xf0a4,
1983
+
.halt_check = BRANCH_HALT,
1984
+
.clkr = {
1985
+
.enable_reg = 0xf0a4,
1986
+
.enable_mask = BIT(0),
1987
+
.hw.init = &(const struct clk_init_data) {
1988
+
.name = "cam_cc_ife_3_dsp_clk",
1989
+
.parent_hws = (const struct clk_hw*[]) {
1990
+
&cam_cc_ife_3_clk_src.clkr.hw,
1991
+
},
1992
+
.num_parents = 1,
1993
+
.flags = CLK_SET_RATE_PARENT,
1994
+
.ops = &clk_branch2_ops,
1995
+
},
1996
+
},
1997
+
};
1998
+
1999
+
static struct clk_branch cam_cc_ife_lite_0_clk = {
2000
+
.halt_reg = 0xc01c,
2001
+
.halt_check = BRANCH_HALT,
2002
+
.clkr = {
2003
+
.enable_reg = 0xc01c,
2004
+
.enable_mask = BIT(0),
2005
+
.hw.init = &(const struct clk_init_data) {
2006
+
.name = "cam_cc_ife_lite_0_clk",
2007
+
.parent_hws = (const struct clk_hw*[]) {
2008
+
&cam_cc_ife_lite_0_clk_src.clkr.hw,
2009
+
},
2010
+
.num_parents = 1,
2011
+
.flags = CLK_SET_RATE_PARENT,
2012
+
.ops = &clk_branch2_ops,
2013
+
},
2014
+
},
2015
+
};
2016
+
2017
+
static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = {
2018
+
.halt_reg = 0xc040,
2019
+
.halt_check = BRANCH_HALT,
2020
+
.clkr = {
2021
+
.enable_reg = 0xc040,
2022
+
.enable_mask = BIT(0),
2023
+
.hw.init = &(const struct clk_init_data) {
2024
+
.name = "cam_cc_ife_lite_0_cphy_rx_clk",
2025
+
.parent_hws = (const struct clk_hw*[]) {
2026
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
2027
+
},
2028
+
.num_parents = 1,
2029
+
.flags = CLK_SET_RATE_PARENT,
2030
+
.ops = &clk_branch2_ops,
2031
+
},
2032
+
},
2033
+
};
2034
+
2035
+
static struct clk_branch cam_cc_ife_lite_0_csid_clk = {
2036
+
.halt_reg = 0xc038,
2037
+
.halt_check = BRANCH_HALT,
2038
+
.clkr = {
2039
+
.enable_reg = 0xc038,
2040
+
.enable_mask = BIT(0),
2041
+
.hw.init = &(const struct clk_init_data) {
2042
+
.name = "cam_cc_ife_lite_0_csid_clk",
2043
+
.parent_hws = (const struct clk_hw*[]) {
2044
+
&cam_cc_ife_lite_0_csid_clk_src.clkr.hw,
2045
+
},
2046
+
.num_parents = 1,
2047
+
.flags = CLK_SET_RATE_PARENT,
2048
+
.ops = &clk_branch2_ops,
2049
+
},
2050
+
},
2051
+
};
2052
+
2053
+
static struct clk_branch cam_cc_ife_lite_1_clk = {
2054
+
.halt_reg = 0xc060,
2055
+
.halt_check = BRANCH_HALT,
2056
+
.clkr = {
2057
+
.enable_reg = 0xc060,
2058
+
.enable_mask = BIT(0),
2059
+
.hw.init = &(const struct clk_init_data) {
2060
+
.name = "cam_cc_ife_lite_1_clk",
2061
+
.parent_hws = (const struct clk_hw*[]) {
2062
+
&cam_cc_ife_lite_1_clk_src.clkr.hw,
2063
+
},
2064
+
.num_parents = 1,
2065
+
.flags = CLK_SET_RATE_PARENT,
2066
+
.ops = &clk_branch2_ops,
2067
+
},
2068
+
},
2069
+
};
2070
+
2071
+
static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = {
2072
+
.halt_reg = 0xc084,
2073
+
.halt_check = BRANCH_HALT,
2074
+
.clkr = {
2075
+
.enable_reg = 0xc084,
2076
+
.enable_mask = BIT(0),
2077
+
.hw.init = &(const struct clk_init_data) {
2078
+
.name = "cam_cc_ife_lite_1_cphy_rx_clk",
2079
+
.parent_hws = (const struct clk_hw*[]) {
2080
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
2081
+
},
2082
+
.num_parents = 1,
2083
+
.flags = CLK_SET_RATE_PARENT,
2084
+
.ops = &clk_branch2_ops,
2085
+
},
2086
+
},
2087
+
};
2088
+
2089
+
static struct clk_branch cam_cc_ife_lite_1_csid_clk = {
2090
+
.halt_reg = 0xc07c,
2091
+
.halt_check = BRANCH_HALT,
2092
+
.clkr = {
2093
+
.enable_reg = 0xc07c,
2094
+
.enable_mask = BIT(0),
2095
+
.hw.init = &(const struct clk_init_data) {
2096
+
.name = "cam_cc_ife_lite_1_csid_clk",
2097
+
.parent_hws = (const struct clk_hw*[]) {
2098
+
&cam_cc_ife_lite_1_csid_clk_src.clkr.hw,
2099
+
},
2100
+
.num_parents = 1,
2101
+
.flags = CLK_SET_RATE_PARENT,
2102
+
.ops = &clk_branch2_ops,
2103
+
},
2104
+
},
2105
+
};
2106
+
2107
+
static struct clk_branch cam_cc_ife_lite_2_clk = {
2108
+
.halt_reg = 0xc258,
2109
+
.halt_check = BRANCH_HALT,
2110
+
.clkr = {
2111
+
.enable_reg = 0xc258,
2112
+
.enable_mask = BIT(0),
2113
+
.hw.init = &(const struct clk_init_data) {
2114
+
.name = "cam_cc_ife_lite_2_clk",
2115
+
.parent_hws = (const struct clk_hw*[]) {
2116
+
&cam_cc_ife_lite_2_clk_src.clkr.hw,
2117
+
},
2118
+
.num_parents = 1,
2119
+
.flags = CLK_SET_RATE_PARENT,
2120
+
.ops = &clk_branch2_ops,
2121
+
},
2122
+
},
2123
+
};
2124
+
2125
+
static struct clk_branch cam_cc_ife_lite_2_cphy_rx_clk = {
2126
+
.halt_reg = 0xc27c,
2127
+
.halt_check = BRANCH_HALT,
2128
+
.clkr = {
2129
+
.enable_reg = 0xc27c,
2130
+
.enable_mask = BIT(0),
2131
+
.hw.init = &(const struct clk_init_data) {
2132
+
.name = "cam_cc_ife_lite_2_cphy_rx_clk",
2133
+
.parent_hws = (const struct clk_hw*[]) {
2134
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
2135
+
},
2136
+
.num_parents = 1,
2137
+
.flags = CLK_SET_RATE_PARENT,
2138
+
.ops = &clk_branch2_ops,
2139
+
},
2140
+
},
2141
+
};
2142
+
2143
+
static struct clk_branch cam_cc_ife_lite_2_csid_clk = {
2144
+
.halt_reg = 0xc274,
2145
+
.halt_check = BRANCH_HALT,
2146
+
.clkr = {
2147
+
.enable_reg = 0xc274,
2148
+
.enable_mask = BIT(0),
2149
+
.hw.init = &(const struct clk_init_data) {
2150
+
.name = "cam_cc_ife_lite_2_csid_clk",
2151
+
.parent_hws = (const struct clk_hw*[]) {
2152
+
&cam_cc_ife_lite_2_csid_clk_src.clkr.hw,
2153
+
},
2154
+
.num_parents = 1,
2155
+
.flags = CLK_SET_RATE_PARENT,
2156
+
.ops = &clk_branch2_ops,
2157
+
},
2158
+
},
2159
+
};
2160
+
2161
+
static struct clk_branch cam_cc_ife_lite_3_clk = {
2162
+
.halt_reg = 0xc29c,
2163
+
.halt_check = BRANCH_HALT,
2164
+
.clkr = {
2165
+
.enable_reg = 0xc29c,
2166
+
.enable_mask = BIT(0),
2167
+
.hw.init = &(const struct clk_init_data) {
2168
+
.name = "cam_cc_ife_lite_3_clk",
2169
+
.parent_hws = (const struct clk_hw*[]) {
2170
+
&cam_cc_ife_lite_3_clk_src.clkr.hw,
2171
+
},
2172
+
.num_parents = 1,
2173
+
.flags = CLK_SET_RATE_PARENT,
2174
+
.ops = &clk_branch2_ops,
2175
+
},
2176
+
},
2177
+
};
2178
+
2179
+
static struct clk_branch cam_cc_ife_lite_3_cphy_rx_clk = {
2180
+
.halt_reg = 0xc2c0,
2181
+
.halt_check = BRANCH_HALT,
2182
+
.clkr = {
2183
+
.enable_reg = 0xc2c0,
2184
+
.enable_mask = BIT(0),
2185
+
.hw.init = &(const struct clk_init_data) {
2186
+
.name = "cam_cc_ife_lite_3_cphy_rx_clk",
2187
+
.parent_hws = (const struct clk_hw*[]) {
2188
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
2189
+
},
2190
+
.num_parents = 1,
2191
+
.flags = CLK_SET_RATE_PARENT,
2192
+
.ops = &clk_branch2_ops,
2193
+
},
2194
+
},
2195
+
};
2196
+
2197
+
static struct clk_branch cam_cc_ife_lite_3_csid_clk = {
2198
+
.halt_reg = 0xc2b8,
2199
+
.halt_check = BRANCH_HALT,
2200
+
.clkr = {
2201
+
.enable_reg = 0xc2b8,
2202
+
.enable_mask = BIT(0),
2203
+
.hw.init = &(const struct clk_init_data) {
2204
+
.name = "cam_cc_ife_lite_3_csid_clk",
2205
+
.parent_hws = (const struct clk_hw*[]) {
2206
+
&cam_cc_ife_lite_3_csid_clk_src.clkr.hw,
2207
+
},
2208
+
.num_parents = 1,
2209
+
.flags = CLK_SET_RATE_PARENT,
2210
+
.ops = &clk_branch2_ops,
2211
+
},
2212
+
},
2213
+
};
2214
+
2215
+
static struct clk_branch cam_cc_ipe_0_ahb_clk = {
2216
+
.halt_reg = 0x8040,
2217
+
.halt_check = BRANCH_HALT,
2218
+
.clkr = {
2219
+
.enable_reg = 0x8040,
2220
+
.enable_mask = BIT(0),
2221
+
.hw.init = &(const struct clk_init_data) {
2222
+
.name = "cam_cc_ipe_0_ahb_clk",
2223
+
.parent_hws = (const struct clk_hw*[]) {
2224
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
2225
+
},
2226
+
.num_parents = 1,
2227
+
.flags = CLK_SET_RATE_PARENT,
2228
+
.ops = &clk_branch2_ops,
2229
+
},
2230
+
},
2231
+
};
2232
+
2233
+
static struct clk_branch cam_cc_ipe_0_areg_clk = {
2234
+
.halt_reg = 0x803c,
2235
+
.halt_check = BRANCH_HALT,
2236
+
.clkr = {
2237
+
.enable_reg = 0x803c,
2238
+
.enable_mask = BIT(0),
2239
+
.hw.init = &(const struct clk_init_data) {
2240
+
.name = "cam_cc_ipe_0_areg_clk",
2241
+
.parent_hws = (const struct clk_hw*[]) {
2242
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
2243
+
},
2244
+
.num_parents = 1,
2245
+
.flags = CLK_SET_RATE_PARENT,
2246
+
.ops = &clk_branch2_ops,
2247
+
},
2248
+
},
2249
+
};
2250
+
2251
+
static struct clk_branch cam_cc_ipe_0_axi_clk = {
2252
+
.halt_reg = 0x8038,
2253
+
.halt_check = BRANCH_HALT,
2254
+
.clkr = {
2255
+
.enable_reg = 0x8038,
2256
+
.enable_mask = BIT(0),
2257
+
.hw.init = &(const struct clk_init_data) {
2258
+
.name = "cam_cc_ipe_0_axi_clk",
2259
+
.parent_hws = (const struct clk_hw*[]) {
2260
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
2261
+
},
2262
+
.num_parents = 1,
2263
+
.flags = CLK_SET_RATE_PARENT,
2264
+
.ops = &clk_branch2_ops,
2265
+
},
2266
+
},
2267
+
};
2268
+
2269
+
static struct clk_branch cam_cc_ipe_0_clk = {
2270
+
.halt_reg = 0x8028,
2271
+
.halt_check = BRANCH_HALT,
2272
+
.clkr = {
2273
+
.enable_reg = 0x8028,
2274
+
.enable_mask = BIT(0),
2275
+
.hw.init = &(const struct clk_init_data) {
2276
+
.name = "cam_cc_ipe_0_clk",
2277
+
.parent_hws = (const struct clk_hw*[]) {
2278
+
&cam_cc_ipe_0_clk_src.clkr.hw,
2279
+
},
2280
+
.num_parents = 1,
2281
+
.flags = CLK_SET_RATE_PARENT,
2282
+
.ops = &clk_branch2_ops,
2283
+
},
2284
+
},
2285
+
};
2286
+
2287
+
static struct clk_branch cam_cc_ipe_1_ahb_clk = {
2288
+
.halt_reg = 0x9028,
2289
+
.halt_check = BRANCH_HALT,
2290
+
.clkr = {
2291
+
.enable_reg = 0x9028,
2292
+
.enable_mask = BIT(0),
2293
+
.hw.init = &(const struct clk_init_data) {
2294
+
.name = "cam_cc_ipe_1_ahb_clk",
2295
+
.parent_hws = (const struct clk_hw*[]) {
2296
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
2297
+
},
2298
+
.num_parents = 1,
2299
+
.flags = CLK_SET_RATE_PARENT,
2300
+
.ops = &clk_branch2_ops,
2301
+
},
2302
+
},
2303
+
};
2304
+
2305
+
static struct clk_branch cam_cc_ipe_1_areg_clk = {
2306
+
.halt_reg = 0x9024,
2307
+
.halt_check = BRANCH_HALT,
2308
+
.clkr = {
2309
+
.enable_reg = 0x9024,
2310
+
.enable_mask = BIT(0),
2311
+
.hw.init = &(const struct clk_init_data) {
2312
+
.name = "cam_cc_ipe_1_areg_clk",
2313
+
.parent_hws = (const struct clk_hw*[]) {
2314
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
2315
+
},
2316
+
.num_parents = 1,
2317
+
.flags = CLK_SET_RATE_PARENT,
2318
+
.ops = &clk_branch2_ops,
2319
+
},
2320
+
},
2321
+
};
2322
+
2323
+
static struct clk_branch cam_cc_ipe_1_axi_clk = {
2324
+
.halt_reg = 0x9020,
2325
+
.halt_check = BRANCH_HALT,
2326
+
.clkr = {
2327
+
.enable_reg = 0x9020,
2328
+
.enable_mask = BIT(0),
2329
+
.hw.init = &(const struct clk_init_data) {
2330
+
.name = "cam_cc_ipe_1_axi_clk",
2331
+
.parent_hws = (const struct clk_hw*[]) {
2332
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
2333
+
},
2334
+
.num_parents = 1,
2335
+
.flags = CLK_SET_RATE_PARENT,
2336
+
.ops = &clk_branch2_ops,
2337
+
},
2338
+
},
2339
+
};
2340
+
2341
+
static struct clk_branch cam_cc_ipe_1_clk = {
2342
+
.halt_reg = 0x9010,
2343
+
.halt_check = BRANCH_HALT,
2344
+
.clkr = {
2345
+
.enable_reg = 0x9010,
2346
+
.enable_mask = BIT(0),
2347
+
.hw.init = &(const struct clk_init_data) {
2348
+
.name = "cam_cc_ipe_1_clk",
2349
+
.parent_hws = (const struct clk_hw*[]) {
2350
+
&cam_cc_ipe_0_clk_src.clkr.hw,
2351
+
},
2352
+
.num_parents = 1,
2353
+
.flags = CLK_SET_RATE_PARENT,
2354
+
.ops = &clk_branch2_ops,
2355
+
},
2356
+
},
2357
+
};
2358
+
2359
+
static struct clk_branch cam_cc_jpeg_clk = {
2360
+
.halt_reg = 0xc0a4,
2361
+
.halt_check = BRANCH_HALT,
2362
+
.clkr = {
2363
+
.enable_reg = 0xc0a4,
2364
+
.enable_mask = BIT(0),
2365
+
.hw.init = &(const struct clk_init_data) {
2366
+
.name = "cam_cc_jpeg_clk",
2367
+
.parent_hws = (const struct clk_hw*[]) {
2368
+
&cam_cc_jpeg_clk_src.clkr.hw,
2369
+
},
2370
+
.num_parents = 1,
2371
+
.flags = CLK_SET_RATE_PARENT,
2372
+
.ops = &clk_branch2_ops,
2373
+
},
2374
+
},
2375
+
};
2376
+
2377
+
static struct clk_branch cam_cc_lrme_clk = {
2378
+
.halt_reg = 0xc15c,
2379
+
.halt_check = BRANCH_HALT,
2380
+
.clkr = {
2381
+
.enable_reg = 0xc15c,
2382
+
.enable_mask = BIT(0),
2383
+
.hw.init = &(const struct clk_init_data) {
2384
+
.name = "cam_cc_lrme_clk",
2385
+
.parent_hws = (const struct clk_hw*[]) {
2386
+
&cam_cc_lrme_clk_src.clkr.hw,
2387
+
},
2388
+
.num_parents = 1,
2389
+
.flags = CLK_SET_RATE_PARENT,
2390
+
.ops = &clk_branch2_ops,
2391
+
},
2392
+
},
2393
+
};
2394
+
2395
+
static struct clk_branch cam_cc_mclk0_clk = {
2396
+
.halt_reg = 0x501c,
2397
+
.halt_check = BRANCH_HALT,
2398
+
.clkr = {
2399
+
.enable_reg = 0x501c,
2400
+
.enable_mask = BIT(0),
2401
+
.hw.init = &(const struct clk_init_data) {
2402
+
.name = "cam_cc_mclk0_clk",
2403
+
.parent_hws = (const struct clk_hw*[]) {
2404
+
&cam_cc_mclk0_clk_src.clkr.hw,
2405
+
},
2406
+
.num_parents = 1,
2407
+
.flags = CLK_SET_RATE_PARENT,
2408
+
.ops = &clk_branch2_ops,
2409
+
},
2410
+
},
2411
+
};
2412
+
2413
+
static struct clk_branch cam_cc_mclk1_clk = {
2414
+
.halt_reg = 0x503c,
2415
+
.halt_check = BRANCH_HALT,
2416
+
.clkr = {
2417
+
.enable_reg = 0x503c,
2418
+
.enable_mask = BIT(0),
2419
+
.hw.init = &(const struct clk_init_data) {
2420
+
.name = "cam_cc_mclk1_clk",
2421
+
.parent_hws = (const struct clk_hw*[]) {
2422
+
&cam_cc_mclk1_clk_src.clkr.hw,
2423
+
},
2424
+
.num_parents = 1,
2425
+
.flags = CLK_SET_RATE_PARENT,
2426
+
.ops = &clk_branch2_ops,
2427
+
},
2428
+
},
2429
+
};
2430
+
2431
+
static struct clk_branch cam_cc_mclk2_clk = {
2432
+
.halt_reg = 0x505c,
2433
+
.halt_check = BRANCH_HALT,
2434
+
.clkr = {
2435
+
.enable_reg = 0x505c,
2436
+
.enable_mask = BIT(0),
2437
+
.hw.init = &(const struct clk_init_data) {
2438
+
.name = "cam_cc_mclk2_clk",
2439
+
.parent_hws = (const struct clk_hw*[]) {
2440
+
&cam_cc_mclk2_clk_src.clkr.hw,
2441
+
},
2442
+
.num_parents = 1,
2443
+
.flags = CLK_SET_RATE_PARENT,
2444
+
.ops = &clk_branch2_ops,
2445
+
},
2446
+
},
2447
+
};
2448
+
2449
+
static struct clk_branch cam_cc_mclk3_clk = {
2450
+
.halt_reg = 0x507c,
2451
+
.halt_check = BRANCH_HALT,
2452
+
.clkr = {
2453
+
.enable_reg = 0x507c,
2454
+
.enable_mask = BIT(0),
2455
+
.hw.init = &(const struct clk_init_data) {
2456
+
.name = "cam_cc_mclk3_clk",
2457
+
.parent_hws = (const struct clk_hw*[]) {
2458
+
&cam_cc_mclk3_clk_src.clkr.hw,
2459
+
},
2460
+
.num_parents = 1,
2461
+
.flags = CLK_SET_RATE_PARENT,
2462
+
.ops = &clk_branch2_ops,
2463
+
},
2464
+
},
2465
+
};
2466
+
2467
+
static struct clk_branch cam_cc_mclk4_clk = {
2468
+
.halt_reg = 0x509c,
2469
+
.halt_check = BRANCH_HALT,
2470
+
.clkr = {
2471
+
.enable_reg = 0x509c,
2472
+
.enable_mask = BIT(0),
2473
+
.hw.init = &(const struct clk_init_data) {
2474
+
.name = "cam_cc_mclk4_clk",
2475
+
.parent_hws = (const struct clk_hw*[]) {
2476
+
&cam_cc_mclk4_clk_src.clkr.hw,
2477
+
},
2478
+
.num_parents = 1,
2479
+
.flags = CLK_SET_RATE_PARENT,
2480
+
.ops = &clk_branch2_ops,
2481
+
},
2482
+
},
2483
+
};
2484
+
2485
+
static struct clk_branch cam_cc_mclk5_clk = {
2486
+
.halt_reg = 0x50bc,
2487
+
.halt_check = BRANCH_HALT,
2488
+
.clkr = {
2489
+
.enable_reg = 0x50bc,
2490
+
.enable_mask = BIT(0),
2491
+
.hw.init = &(const struct clk_init_data) {
2492
+
.name = "cam_cc_mclk5_clk",
2493
+
.parent_hws = (const struct clk_hw*[]) {
2494
+
&cam_cc_mclk5_clk_src.clkr.hw,
2495
+
},
2496
+
.num_parents = 1,
2497
+
.flags = CLK_SET_RATE_PARENT,
2498
+
.ops = &clk_branch2_ops,
2499
+
},
2500
+
},
2501
+
};
2502
+
2503
+
static struct clk_branch cam_cc_mclk6_clk = {
2504
+
.halt_reg = 0x50dc,
2505
+
.halt_check = BRANCH_HALT,
2506
+
.clkr = {
2507
+
.enable_reg = 0x50dc,
2508
+
.enable_mask = BIT(0),
2509
+
.hw.init = &(const struct clk_init_data) {
2510
+
.name = "cam_cc_mclk6_clk",
2511
+
.parent_hws = (const struct clk_hw*[]) {
2512
+
&cam_cc_mclk6_clk_src.clkr.hw,
2513
+
},
2514
+
.num_parents = 1,
2515
+
.flags = CLK_SET_RATE_PARENT,
2516
+
.ops = &clk_branch2_ops,
2517
+
},
2518
+
},
2519
+
};
2520
+
2521
+
static struct clk_branch cam_cc_mclk7_clk = {
2522
+
.halt_reg = 0x50fc,
2523
+
.halt_check = BRANCH_HALT,
2524
+
.clkr = {
2525
+
.enable_reg = 0x50fc,
2526
+
.enable_mask = BIT(0),
2527
+
.hw.init = &(const struct clk_init_data) {
2528
+
.name = "cam_cc_mclk7_clk",
2529
+
.parent_hws = (const struct clk_hw*[]) {
2530
+
&cam_cc_mclk7_clk_src.clkr.hw,
2531
+
},
2532
+
.num_parents = 1,
2533
+
.flags = CLK_SET_RATE_PARENT,
2534
+
.ops = &clk_branch2_ops,
2535
+
},
2536
+
},
2537
+
};
2538
+
2539
+
static struct gdsc titan_top_gdsc = {
2540
+
.gdscr = 0xc1bc,
2541
+
.en_rest_wait_val = 0x2,
2542
+
.en_few_wait_val = 0x2,
2543
+
.clk_dis_wait_val = 0xf,
2544
+
.pd = {
2545
+
.name = "titan_top_gdsc",
2546
+
},
2547
+
.pwrsts = PWRSTS_OFF_ON,
2548
+
.flags = POLL_CFG_GDSCR,
2549
+
};
2550
+
2551
+
static struct gdsc bps_gdsc = {
2552
+
.gdscr = 0x7004,
2553
+
.en_rest_wait_val = 0x2,
2554
+
.en_few_wait_val = 0x2,
2555
+
.clk_dis_wait_val = 0xf,
2556
+
.pd = {
2557
+
.name = "bps_gdsc",
2558
+
},
2559
+
.pwrsts = PWRSTS_OFF_ON,
2560
+
.parent = &titan_top_gdsc.pd,
2561
+
.flags = POLL_CFG_GDSCR,
2562
+
};
2563
+
2564
+
static struct gdsc ife_0_gdsc = {
2565
+
.gdscr = 0xa004,
2566
+
.en_rest_wait_val = 0x2,
2567
+
.en_few_wait_val = 0x2,
2568
+
.clk_dis_wait_val = 0xf,
2569
+
.pd = {
2570
+
.name = "ife_0_gdsc",
2571
+
},
2572
+
.pwrsts = PWRSTS_OFF_ON,
2573
+
.parent = &titan_top_gdsc.pd,
2574
+
.flags = POLL_CFG_GDSCR,
2575
+
};
2576
+
2577
+
static struct gdsc ife_1_gdsc = {
2578
+
.gdscr = 0xb004,
2579
+
.en_rest_wait_val = 0x2,
2580
+
.en_few_wait_val = 0x2,
2581
+
.clk_dis_wait_val = 0xf,
2582
+
.pd = {
2583
+
.name = "ife_1_gdsc",
2584
+
},
2585
+
.pwrsts = PWRSTS_OFF_ON,
2586
+
.parent = &titan_top_gdsc.pd,
2587
+
.flags = POLL_CFG_GDSCR,
2588
+
};
2589
+
2590
+
static struct gdsc ife_2_gdsc = {
2591
+
.gdscr = 0xf004,
2592
+
.en_rest_wait_val = 0x2,
2593
+
.en_few_wait_val = 0x2,
2594
+
.clk_dis_wait_val = 0xf,
2595
+
.pd = {
2596
+
.name = "ife_2_gdsc",
2597
+
},
2598
+
.pwrsts = PWRSTS_OFF_ON,
2599
+
.parent = &titan_top_gdsc.pd,
2600
+
.flags = POLL_CFG_GDSCR,
2601
+
};
2602
+
2603
+
static struct gdsc ife_3_gdsc = {
2604
+
.gdscr = 0xf070,
2605
+
.en_rest_wait_val = 0x2,
2606
+
.en_few_wait_val = 0x2,
2607
+
.clk_dis_wait_val = 0xf,
2608
+
.pd = {
2609
+
.name = "ife_3_gdsc",
2610
+
},
2611
+
.pwrsts = PWRSTS_OFF_ON,
2612
+
.parent = &titan_top_gdsc.pd,
2613
+
.flags = POLL_CFG_GDSCR,
2614
+
};
2615
+
2616
+
static struct gdsc ipe_0_gdsc = {
2617
+
.gdscr = 0x8004,
2618
+
.en_rest_wait_val = 0x2,
2619
+
.en_few_wait_val = 0x2,
2620
+
.clk_dis_wait_val = 0xf,
2621
+
.pd = {
2622
+
.name = "ipe_0_gdsc",
2623
+
},
2624
+
.pwrsts = PWRSTS_OFF_ON,
2625
+
.parent = &titan_top_gdsc.pd,
2626
+
.flags = POLL_CFG_GDSCR,
2627
+
};
2628
+
2629
+
static struct gdsc ipe_1_gdsc = {
2630
+
.gdscr = 0x9004,
2631
+
.en_rest_wait_val = 0x2,
2632
+
.en_few_wait_val = 0x2,
2633
+
.clk_dis_wait_val = 0xf,
2634
+
.pd = {
2635
+
.name = "ipe_1_gdsc",
2636
+
},
2637
+
.pwrsts = PWRSTS_OFF_ON,
2638
+
.parent = &titan_top_gdsc.pd,
2639
+
.flags = POLL_CFG_GDSCR,
2640
+
};
2641
+
2642
+
static struct clk_regmap *cam_cc_sc8180x_clocks[] = {
2643
+
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2644
+
[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
2645
+
[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
2646
+
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2647
+
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2648
+
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2649
+
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2650
+
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2651
+
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2652
+
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2653
+
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2654
+
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2655
+
[CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
2656
+
[CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
2657
+
[CAM_CC_CCI_3_CLK] = &cam_cc_cci_3_clk.clkr,
2658
+
[CAM_CC_CCI_3_CLK_SRC] = &cam_cc_cci_3_clk_src.clkr,
2659
+
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2660
+
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2661
+
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2662
+
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2663
+
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2664
+
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2665
+
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2666
+
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2667
+
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2668
+
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2669
+
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2670
+
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2671
+
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2672
+
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2673
+
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2674
+
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2675
+
[CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
2676
+
[CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
2677
+
[CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
2678
+
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2679
+
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2680
+
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2681
+
[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
2682
+
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2683
+
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2684
+
[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
2685
+
[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
2686
+
[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
2687
+
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2688
+
[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
2689
+
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2690
+
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2691
+
[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
2692
+
[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
2693
+
[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
2694
+
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2695
+
[CAM_CC_IFE_2_AXI_CLK] = &cam_cc_ife_2_axi_clk.clkr,
2696
+
[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
2697
+
[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
2698
+
[CAM_CC_IFE_2_CPHY_RX_CLK] = &cam_cc_ife_2_cphy_rx_clk.clkr,
2699
+
[CAM_CC_IFE_2_CSID_CLK] = &cam_cc_ife_2_csid_clk.clkr,
2700
+
[CAM_CC_IFE_2_CSID_CLK_SRC] = &cam_cc_ife_2_csid_clk_src.clkr,
2701
+
[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
2702
+
[CAM_CC_IFE_3_AXI_CLK] = &cam_cc_ife_3_axi_clk.clkr,
2703
+
[CAM_CC_IFE_3_CLK] = &cam_cc_ife_3_clk.clkr,
2704
+
[CAM_CC_IFE_3_CLK_SRC] = &cam_cc_ife_3_clk_src.clkr,
2705
+
[CAM_CC_IFE_3_CPHY_RX_CLK] = &cam_cc_ife_3_cphy_rx_clk.clkr,
2706
+
[CAM_CC_IFE_3_CSID_CLK] = &cam_cc_ife_3_csid_clk.clkr,
2707
+
[CAM_CC_IFE_3_CSID_CLK_SRC] = &cam_cc_ife_3_csid_clk_src.clkr,
2708
+
[CAM_CC_IFE_3_DSP_CLK] = &cam_cc_ife_3_dsp_clk.clkr,
2709
+
[CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr,
2710
+
[CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr,
2711
+
[CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr,
2712
+
[CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr,
2713
+
[CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr,
2714
+
[CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr,
2715
+
[CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr,
2716
+
[CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr,
2717
+
[CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr,
2718
+
[CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr,
2719
+
[CAM_CC_IFE_LITE_2_CLK] = &cam_cc_ife_lite_2_clk.clkr,
2720
+
[CAM_CC_IFE_LITE_2_CLK_SRC] = &cam_cc_ife_lite_2_clk_src.clkr,
2721
+
[CAM_CC_IFE_LITE_2_CPHY_RX_CLK] = &cam_cc_ife_lite_2_cphy_rx_clk.clkr,
2722
+
[CAM_CC_IFE_LITE_2_CSID_CLK] = &cam_cc_ife_lite_2_csid_clk.clkr,
2723
+
[CAM_CC_IFE_LITE_2_CSID_CLK_SRC] = &cam_cc_ife_lite_2_csid_clk_src.clkr,
2724
+
[CAM_CC_IFE_LITE_3_CLK] = &cam_cc_ife_lite_3_clk.clkr,
2725
+
[CAM_CC_IFE_LITE_3_CLK_SRC] = &cam_cc_ife_lite_3_clk_src.clkr,
2726
+
[CAM_CC_IFE_LITE_3_CPHY_RX_CLK] = &cam_cc_ife_lite_3_cphy_rx_clk.clkr,
2727
+
[CAM_CC_IFE_LITE_3_CSID_CLK] = &cam_cc_ife_lite_3_csid_clk.clkr,
2728
+
[CAM_CC_IFE_LITE_3_CSID_CLK_SRC] = &cam_cc_ife_lite_3_csid_clk_src.clkr,
2729
+
[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
2730
+
[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
2731
+
[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
2732
+
[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
2733
+
[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
2734
+
[CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr,
2735
+
[CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr,
2736
+
[CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr,
2737
+
[CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr,
2738
+
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2739
+
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2740
+
[CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
2741
+
[CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
2742
+
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2743
+
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2744
+
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2745
+
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2746
+
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2747
+
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2748
+
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2749
+
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2750
+
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2751
+
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2752
+
[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2753
+
[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2754
+
[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
2755
+
[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
2756
+
[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
2757
+
[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
2758
+
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2759
+
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2760
+
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2761
+
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2762
+
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2763
+
[CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr,
2764
+
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2765
+
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2766
+
[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
2767
+
[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
2768
+
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2769
+
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2770
+
};
2771
+
2772
+
static struct gdsc *cam_cc_sc8180x_gdscs[] = {
2773
+
[BPS_GDSC] = &bps_gdsc,
2774
+
[IFE_0_GDSC] = &ife_0_gdsc,
2775
+
[IFE_1_GDSC] = &ife_1_gdsc,
2776
+
[IFE_2_GDSC] = &ife_2_gdsc,
2777
+
[IFE_3_GDSC] = &ife_3_gdsc,
2778
+
[IPE_0_GDSC] = &ipe_0_gdsc,
2779
+
[IPE_1_GDSC] = &ipe_1_gdsc,
2780
+
[TITAN_TOP_GDSC] = &titan_top_gdsc,
2781
+
};
2782
+
2783
+
static const struct qcom_reset_map cam_cc_sc8180x_resets[] = {
2784
+
[CAM_CC_BPS_BCR] = { 0x7000 },
2785
+
[CAM_CC_CAMNOC_BCR] = { 0xc16c },
2786
+
[CAM_CC_CCI_BCR] = { 0xc104 },
2787
+
[CAM_CC_CPAS_BCR] = { 0xc164 },
2788
+
[CAM_CC_CSI0PHY_BCR] = { 0x6000 },
2789
+
[CAM_CC_CSI1PHY_BCR] = { 0x6024 },
2790
+
[CAM_CC_CSI2PHY_BCR] = { 0x6048 },
2791
+
[CAM_CC_CSI3PHY_BCR] = { 0x606c },
2792
+
[CAM_CC_FD_BCR] = { 0xc0dc },
2793
+
[CAM_CC_ICP_BCR] = { 0xc0b4 },
2794
+
[CAM_CC_IFE_0_BCR] = { 0xa000 },
2795
+
[CAM_CC_IFE_1_BCR] = { 0xb000 },
2796
+
[CAM_CC_IFE_2_BCR] = { 0xf000 },
2797
+
[CAM_CC_IFE_3_BCR] = { 0xf06c },
2798
+
[CAM_CC_IFE_LITE_0_BCR] = { 0xc000 },
2799
+
[CAM_CC_IFE_LITE_1_BCR] = { 0xc044 },
2800
+
[CAM_CC_IFE_LITE_2_BCR] = { 0xc23c },
2801
+
[CAM_CC_IFE_LITE_3_BCR] = { 0xc280 },
2802
+
[CAM_CC_IPE_0_BCR] = { 0x8000 },
2803
+
[CAM_CC_IPE_1_BCR] = { 0x9000 },
2804
+
[CAM_CC_JPEG_BCR] = { 0xc088 },
2805
+
[CAM_CC_LRME_BCR] = { 0xc140 },
2806
+
[CAM_CC_MCLK0_BCR] = { 0x5000 },
2807
+
[CAM_CC_MCLK1_BCR] = { 0x5020 },
2808
+
[CAM_CC_MCLK2_BCR] = { 0x5040 },
2809
+
[CAM_CC_MCLK3_BCR] = { 0x5060 },
2810
+
[CAM_CC_MCLK4_BCR] = { 0x5080 },
2811
+
[CAM_CC_MCLK5_BCR] = { 0x50a0 },
2812
+
[CAM_CC_MCLK6_BCR] = { 0x50c0 },
2813
+
[CAM_CC_MCLK7_BCR] = { 0x50e0 },
2814
+
};
2815
+
2816
+
static const struct regmap_config cam_cc_sc8180x_regmap_config = {
2817
+
.reg_bits = 32,
2818
+
.reg_stride = 4,
2819
+
.val_bits = 32,
2820
+
.max_register = 0xf0d4,
2821
+
.fast_io = true,
2822
+
};
2823
+
2824
+
static const struct qcom_cc_desc cam_cc_sc8180x_desc = {
2825
+
.config = &cam_cc_sc8180x_regmap_config,
2826
+
.clks = cam_cc_sc8180x_clocks,
2827
+
.num_clks = ARRAY_SIZE(cam_cc_sc8180x_clocks),
2828
+
.resets = cam_cc_sc8180x_resets,
2829
+
.num_resets = ARRAY_SIZE(cam_cc_sc8180x_resets),
2830
+
.gdscs = cam_cc_sc8180x_gdscs,
2831
+
.num_gdscs = ARRAY_SIZE(cam_cc_sc8180x_gdscs),
2832
+
};
2833
+
2834
+
static const struct of_device_id cam_cc_sc8180x_match_table[] = {
2835
+
{ .compatible = "qcom,sc8180x-camcc" },
2836
+
{ }
2837
+
};
2838
+
MODULE_DEVICE_TABLE(of, cam_cc_sc8180x_match_table);
2839
+
2840
+
static int cam_cc_sc8180x_probe(struct platform_device *pdev)
2841
+
{
2842
+
struct regmap *regmap;
2843
+
int ret;
2844
+
2845
+
ret = devm_pm_runtime_enable(&pdev->dev);
2846
+
if (ret)
2847
+
return ret;
2848
+
2849
+
ret = pm_runtime_resume_and_get(&pdev->dev);
2850
+
if (ret)
2851
+
return ret;
2852
+
2853
+
regmap = qcom_cc_map(pdev, &cam_cc_sc8180x_desc);
2854
+
if (IS_ERR(regmap)) {
2855
+
pm_runtime_put(&pdev->dev);
2856
+
return PTR_ERR(regmap);
2857
+
}
2858
+
2859
+
clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2860
+
clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2861
+
clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2862
+
clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2863
+
clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2864
+
clk_trion_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
2865
+
clk_trion_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
2866
+
2867
+
/* Keep some clocks always enabled */
2868
+
qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAM_CC_GDSC_CLK */
2869
+
qcom_branch_set_clk_en(regmap, 0xc200); /* CAM_CC_SLEEP_CLK */
2870
+
2871
+
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc8180x_desc, regmap);
2872
+
2873
+
pm_runtime_put(&pdev->dev);
2874
+
2875
+
return ret;
2876
+
}
2877
+
2878
+
static struct platform_driver cam_cc_sc8180x_driver = {
2879
+
.probe = cam_cc_sc8180x_probe,
2880
+
.driver = {
2881
+
.name = "camcc-sc8180x",
2882
+
.of_match_table = cam_cc_sc8180x_match_table,
2883
+
},
2884
+
};
2885
+
2886
+
module_platform_driver(cam_cc_sc8180x_driver);
2887
+
2888
+
MODULE_DESCRIPTION("QTI CAMCC SC8180X Driver");
2889
+
MODULE_LICENSE("GPL");