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Merge tag 'mfd-next-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
"Samsung Exynos ACPM:
- Populate child platform devices from device tree data
- Introduce a new API, 'devm_acpm_get_by_node()', for child devices
to get the ACPM handle

ROHM PMICs:
- Add support for the ROHM BD96802 scalable companion PMIC to the
BD96801 core driver
- Add support for controlling the BD96802 using the BD96801 regulator
driver
- Add support to the BD96805, which is almost identical to the
BD96801
- Add support to the BD96806, which is similar to the BD96802

Maxim MAX77759:
- Add a core driver for the MAX77759 companion PMIC
- Add a GPIO driver for the expander functions on the MAX77759
- Add an NVMEM driver to expose the non-volatile memory on the
MAX77759

STMicroelectronics STM32MP25:
- Add support for the STM32MP25 SoC to the stm32-lptimer
- Add support for the STM32MP25 to the clocksource driver, handling
new register access requirements
- Add support for the STM32MP25 to the PWM driver, enabling up to two
PWM outputs

Broadcom BCM590xx:
- Add support for the BCM59054 PMU
- Parse the PMU ID and revision to support behavioral differences
between chip revisions
- Add regulator support for the BCM59054

Samsung S2MPG10:
- Add support for the S2MPG10 PMIC, which communicates via the
Samsung ACPM firmware instead of I2C

Exynos ACPM:
- Improve timeout detection reliability by using ktime APIs instead
of a loop counter assumption
- Allow PMIC access during late system shutdown by switching to
'udelay()' instead of a sleeping function
- Fix an issue where reading command results longer than 8 bytes
would fail
- Silence non-error '-EPROBE_DEFER' messages during boot to clean up
logs

Exynos LPASS:
- Fix an error handling path by switching to
'devm_regmap_init_mmio()' to prevent resource leaks
- Fix a bug where 'exynos_lpass_disable()' was called twice in the
remove function
- Fix another resource leak in the probe's error path by using
'devm_add_action_or_reset()'

Samsung SEC:
- Handle the s2dos05, which does not have IRQ support, explicitly to
prevent warnings
- Fix the core driver to correctly handle errors from
'sec_irq_init()' instead of ignoring them

STMPE-SPI:
- Correct an undeclared identifier in the 'MODULE_DEVICE_TABLE' macro

MAINTAINERS:
- Adjust a file path for the Siemens IPC LED drivers entry to fix a
broken reference

Maxim Drivers:
- Correct the spelling of "Electronics" in Samsung copyright headers
across multiple files

General:
- Fix wakeup source memory leaks on device unbind for 88pm886,
as3722, max14577, max77541, max77705, max8925, rt5033, and
sprd-sc27xx drivers

Samsung SEC Drivers:
- Split the driver into a transport-agnostic core ('sec-core') and
transport-specific ('sec-i2c', 'sec-acpm') modules to support
non-I2C devices
- Merge the 'sec-core' and 'sec-irq' modules to reduce memory
consumption
- Move internal APIs to a private header to clean up the public API
- Improve code style by sorting includes, cleaning up headers,
sorting device tables, and using helper macros like
'dev_err_probe()', 'MFD_CELL', and 'REGMAP_IRQ_REG'
- Make regmap configuration for s2dos05/s2mpu05 explicit to improve
clarity
- Rework platform data and regmap instantiation to use OF match data
instead of a large switch statement

ROHM BD96801/2:
- Prepare the driver for new models by separating chip-specific data
into its own structure
- Drop IC name prefix from IRQ resource names in both the MFD and
regulator drivers for simplification

Broadcom BCM590xx:
- Refactor the regulator driver to store descriptions in a table to
ease support for new chips
- Rename BCM59056-specific data to prepare for the addition of other
regulators
- Use 'dev_err_probe()' for cleaner error handling

Exynos ACPM:
- Correct kerneldoc warnings and use the conventional 'np' argument
name

General MFD:
- Convert 'aat2870' and 'tps65010' to use the per-client debugfs
directory provided by the I2C core
- Convert 'sm501', 'tps65010' and 'ucb1x00' to use the new GPIO line
value setter callbacks
- Constify 'regmap_irq_chip' and other structures in '88pm886' to
move data to read-only sections

BCM590xx:
- Drop the unused "id" member from the 'bcm590xx' struct in
preparation for a replacement

Samsung SEC Core:
- Remove forward declarations for functions that no longer exist

SM501:
- Remove the unused 'sm501_find_clock()' function

New Compatibles:
- Google: Add a PMIC child node to the 'google,gs101-acpm-ipc'
binding
- ROHM: Add new bindings for 'rohm,bd96802-regulator' and
'rohm,bd96802-pmic', and add compatibles for BD96805 and BD96806
- Maxim: Add new bindings for 'maxim,max77759-gpio',
'maxim,max77759-nvmem', and the top-level 'maxim,max77759'
- STM: Add 'stm32mp25' compatible to the 'stm32-lptimer' binding
- Broadcom: Add 'bcm59054' compatible
- Atmel/Microchip: Add 'microchip,sama7d65-gpbr' and
'microchip,sama7d65-secumod' compatibles
- Samsung: Add 's2mpg10' compatible to the 'samsung,s2mps11' MFD
binding
- MediaTek: Add compatibles for 'mt6893' (scpsys), 'mt7988-topmisc',
and 'mt8365-infracfg-nao'
- Qualcomm: Add 'qcom,apq8064-mmss-sfpb' and 'qcom,apq8064-sps-sic'
syscon compatibles

Refactoring & Cleanup:
- Convert Broadcom BCM59056 devicetree bindings to YAML and split
them into MFD and regulator parts
- Convert the Microchip AT91 secumod binding to YAML
- Drop unrelated consumer nodes from binding examples to reduce bloat
- Correct indentation and style in various DTS examples"

* tag 'mfd-next-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (81 commits)
mfd: maxim: Correct Samsung "Electronics" spelling in copyright headers
mfd: maxim: Correct Samsung "Electronics" spelling in headers
mfd: sm501: Remove unused sm501_find_clock
mfd: 88pm886: Constify struct regmap_irq_chip and some other structures
dt-bindings: mfd: syscon: Add mediatek,mt8365-infracfg-nao
mfd: sprd-sc27xx: Fix wakeup source leaks on device unbind
mfd: rt5033: Fix wakeup source leaks on device unbind
mfd: max8925: Fix wakeup source leaks on device unbind
mfd: max77705: Fix wakeup source leaks on device unbind
mfd: max77541: Fix wakeup source leaks on device unbind
mfd: max14577: Fix wakeup source leaks on device unbind
mfd: as3722: Fix wakeup source leaks on device unbind
mfd: 88pm886: Fix wakeup source leaks on device unbind
dt-bindings: mfd: Correct indentation and style in DTS example
dt-bindings: mfd: Drop unrelated nodes from DTS example
dt-bindings: mfd: syscon: Add qcom,apq8064-sps-sic
dt-bindings: mfd: syscon: Add qcom,apq8064-mmss-sfpb
mfd: stmpe-spi: Correct the name used in MODULE_DEVICE_TABLE
dt-bindings: mfd: syscon: Add mt7988-topmisc
mfd: exynos-lpass: Fix another error handling path in exynos_lpass_probe()
...

Linus Torvalds 69352bd5 2043ae90

+4908 -1645
+49
Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/arm/atmel,sama5d2-secumod.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Microchip AT91 Security Module (SECUMOD) 8 + 9 + maintainers: 10 + - Nicolas Ferre <nicolas.ferre@microchip.com> 11 + 12 + description: 13 + The Security Module also offers the PIOBU pins which can be used as GPIO pins. 14 + Note that they maintain their voltage during Backup/Self-refresh. 15 + 16 + properties: 17 + compatible: 18 + oneOf: 19 + - items: 20 + - const: atmel,sama5d2-secumod 21 + - const: syscon 22 + - items: 23 + - enum: 24 + - microchip,sama7d65-secumod 25 + - microchip,sama7g5-secumod 26 + - const: atmel,sama5d2-secumod 27 + - const: syscon 28 + reg: 29 + maxItems: 1 30 + 31 + gpio-controller: true 32 + 33 + "#gpio-cells": 34 + const: 2 35 + 36 + required: 37 + - compatible 38 + - reg 39 + 40 + unevaluatedProperties: false 41 + 42 + examples: 43 + - | 44 + security-module@fc040000 { 45 + compatible = "atmel,sama5d2-secumod", "syscon"; 46 + reg = <0xfc040000 0x100>; 47 + gpio-controller; 48 + #gpio-cells = <2>; 49 + };
-25
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
··· 46 46 reg = <0xffffe800 0x200>; 47 47 }; 48 48 49 - Security Module (SECUMOD) 50 - 51 - The Security Module macrocell provides all necessary secure functions to avoid 52 - voltage, temperature, frequency and mechanical attacks on the chip. It also 53 - embeds secure memories that can be scrambled. 54 - 55 - The Security Module also offers the PIOBU pins which can be used as GPIO pins. 56 - Note that they maintain their voltage during Backup/Self-refresh. 57 - 58 - required properties: 59 - - compatible: Should be "atmel,<chip>-secumod", "syscon". 60 - <chip> can be "sama5d2". 61 - - reg: Should contain registers location and length 62 - - gpio-controller: Marks the port as GPIO controller. 63 - - #gpio-cells: There are 2. The pin number is the 64 - first, the second represents additional 65 - parameters such as GPIO_ACTIVE_HIGH/LOW. 66 - 67 - 68 - secumod@fc040000 { 69 - compatible = "atmel,sama5d2-secumod", "syscon"; 70 - reg = <0xfc040000 0x100>; 71 - gpio-controller; 72 - #gpio-cells = <2>; 73 - };
+1
Documentation/devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml
··· 19 19 - items: 20 20 - enum: 21 21 - atmel,at91sam9260-gpbr 22 + - microchip,sama7d65-gpbr 22 23 - const: syscon 23 24 - items: 24 25 - enum:
-39
Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt
··· 1 - ------------------------------- 2 - BCM590xx Power Management Units 3 - ------------------------------- 4 - 5 - Required properties: 6 - - compatible: "brcm,bcm59056" 7 - - reg: I2C slave address 8 - - interrupts: interrupt for the PMU. Generic interrupt client node bindings 9 - are described in interrupt-controller/interrupts.txt 10 - 11 - ------------------ 12 - Voltage Regulators 13 - ------------------ 14 - 15 - Optional child nodes: 16 - - regulators: container node for regulators following the generic 17 - regulator binding in regulator/regulator.txt 18 - 19 - The valid regulator node names for BCM59056 are: 20 - rfldo, camldo1, camldo2, simldo1, simldo2, sdldo, sdxldo, 21 - mmcldo1, mmcldo2, audldo, micldo, usbldo, vibldo, 22 - csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr, 23 - gpldo1, gpldo2, gpldo3, gpldo4, gpldo5, gpldo6, 24 - vbus 25 - 26 - Example: 27 - pmu: bcm59056@8 { 28 - compatible = "brcm,bcm59056"; 29 - reg = <0x08>; 30 - interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 31 - regulators { 32 - rfldo_reg: rfldo { 33 - regulator-min-microvolt = <1200000>; 34 - regulator-max-microvolt = <3300000>; 35 - }; 36 - 37 - ... 38 - }; 39 - };
+76
Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/brcm,bcm59056.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM590xx Power Management Units 8 + 9 + maintainers: 10 + - Artur Weber <aweber.kernel@gmail.com> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - brcm,bcm59054 16 + - brcm,bcm59056 17 + 18 + reg: 19 + maxItems: 1 20 + 21 + interrupts: 22 + maxItems: 1 23 + 24 + regulators: 25 + type: object 26 + 27 + required: 28 + - compatible 29 + - reg 30 + - interrupts 31 + 32 + additionalProperties: false 33 + 34 + allOf: 35 + - if: 36 + properties: 37 + compatible: 38 + contains: 39 + const: brcm,bcm59054 40 + then: 41 + properties: 42 + regulators: 43 + $ref: /schemas/regulator/brcm,bcm59054.yaml# 44 + 45 + - if: 46 + properties: 47 + compatible: 48 + contains: 49 + const: brcm,bcm59056 50 + then: 51 + properties: 52 + regulators: 53 + $ref: /schemas/regulator/brcm,bcm59056.yaml# 54 + 55 + examples: 56 + - | 57 + #include <dt-bindings/interrupt-controller/arm-gic.h> 58 + #include <dt-bindings/interrupt-controller/irq.h> 59 + 60 + i2c { 61 + #address-cells = <1>; 62 + #size-cells = <0>; 63 + 64 + pmic@8 { 65 + compatible = "brcm,bcm59056"; 66 + reg = <0x08>; 67 + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 68 + 69 + regulators { 70 + rfldo { 71 + regulator-min-microvolt = <1200000>; 72 + regulator-max-microvolt = <3300000>; 73 + }; 74 + }; 75 + }; 76 + };
+71 -80
Documentation/devicetree/bindings/mfd/iqs62x.yaml
··· 60 60 #include <dt-bindings/interrupt-controller/irq.h> 61 61 62 62 i2c { 63 - #address-cells = <1>; 64 - #size-cells = <0>; 63 + #address-cells = <1>; 64 + #size-cells = <0>; 65 65 66 - iqs620a@44 { 67 - compatible = "azoteq,iqs620a"; 68 - reg = <0x44>; 69 - interrupt-parent = <&gpio>; 70 - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 66 + iqs620a@44 { 67 + compatible = "azoteq,iqs620a"; 68 + reg = <0x44>; 69 + interrupt-parent = <&gpio>; 70 + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 71 71 72 - keys { 73 - compatible = "azoteq,iqs620a-keys"; 72 + keys { 73 + compatible = "azoteq,iqs620a-keys"; 74 74 75 - linux,keycodes = <KEY_SELECT>, 76 - <KEY_MENU>, 77 - <KEY_OK>, 78 - <KEY_MENU>; 75 + linux,keycodes = <KEY_SELECT>, 76 + <KEY_MENU>, 77 + <KEY_OK>, 78 + <KEY_MENU>; 79 79 80 - hall-switch-south { 81 - linux,code = <SW_LID>; 82 - azoteq,use-prox; 83 - }; 84 - }; 85 - 86 - iqs620a_pwm: pwm { 87 - compatible = "azoteq,iqs620a-pwm"; 88 - #pwm-cells = <2>; 89 - }; 80 + hall-switch-south { 81 + linux,code = <SW_LID>; 82 + azoteq,use-prox; 83 + }; 90 84 }; 91 - }; 92 85 93 - pwmleds { 94 - compatible = "pwm-leds"; 95 - 96 - led-1 { 97 - pwms = <&iqs620a_pwm 0 1000000>; 98 - max-brightness = <255>; 86 + iqs620a_pwm: pwm { 87 + compatible = "azoteq,iqs620a-pwm"; 88 + #pwm-cells = <2>; 99 89 }; 90 + }; 100 91 }; 101 92 102 93 - | ··· 96 105 #include <dt-bindings/interrupt-controller/irq.h> 97 106 98 107 i2c { 99 - #address-cells = <1>; 100 - #size-cells = <0>; 108 + #address-cells = <1>; 109 + #size-cells = <0>; 101 110 102 - iqs620a@44 { 103 - compatible = "azoteq,iqs620a"; 104 - reg = <0x44>; 105 - interrupt-parent = <&gpio>; 106 - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 111 + iqs620a@44 { 112 + compatible = "azoteq,iqs620a"; 113 + reg = <0x44>; 114 + interrupt-parent = <&gpio>; 115 + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 107 116 108 - firmware-name = "iqs620a_coil.bin"; 117 + firmware-name = "iqs620a_coil.bin"; 109 118 110 - keys { 111 - compatible = "azoteq,iqs620a-keys"; 119 + keys { 120 + compatible = "azoteq,iqs620a-keys"; 112 121 113 - linux,keycodes = <0>, 114 - <0>, 115 - <0>, 116 - <0>, 117 - <0>, 118 - <0>, 119 - <KEY_MUTE>; 122 + linux,keycodes = <0>, 123 + <0>, 124 + <0>, 125 + <0>, 126 + <0>, 127 + <0>, 128 + <KEY_MUTE>; 120 129 121 - hall-switch-north { 122 - linux,code = <SW_DOCK>; 123 - }; 130 + hall-switch-north { 131 + linux,code = <SW_DOCK>; 132 + }; 124 133 125 - hall-switch-south { 126 - linux,code = <SW_TABLET_MODE>; 127 - }; 128 - }; 134 + hall-switch-south { 135 + linux,code = <SW_TABLET_MODE>; 136 + }; 129 137 }; 138 + }; 130 139 }; 131 140 132 141 - | ··· 135 144 #include <dt-bindings/interrupt-controller/irq.h> 136 145 137 146 i2c { 138 - #address-cells = <1>; 139 - #size-cells = <0>; 147 + #address-cells = <1>; 148 + #size-cells = <0>; 140 149 141 - iqs624@44 { 142 - compatible = "azoteq,iqs624"; 143 - reg = <0x44>; 144 - interrupt-parent = <&gpio>; 145 - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 150 + iqs624@44 { 151 + compatible = "azoteq,iqs624"; 152 + reg = <0x44>; 153 + interrupt-parent = <&gpio>; 154 + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 146 155 147 - keys { 148 - compatible = "azoteq,iqs624-keys"; 156 + keys { 157 + compatible = "azoteq,iqs624-keys"; 149 158 150 - linux,keycodes = <BTN_0>, 151 - <0>, 152 - <BTN_1>, 153 - <0>, 154 - <0>, 155 - <0>, 156 - <0>, 157 - <0>, 158 - <0>, 159 - <0>, 160 - <0>, 161 - <0>, 162 - <0>, 163 - <0>, 164 - <KEY_VOLUMEUP>, 165 - <KEY_VOLUMEDOWN>; 166 - }; 159 + linux,keycodes = <BTN_0>, 160 + <0>, 161 + <BTN_1>, 162 + <0>, 163 + <0>, 164 + <0>, 165 + <0>, 166 + <0>, 167 + <0>, 168 + <0>, 169 + <0>, 170 + <0>, 171 + <0>, 172 + <0>, 173 + <KEY_VOLUMEUP>, 174 + <KEY_VOLUMEDOWN>; 167 175 }; 176 + }; 168 177 }; 169 178 170 179 ...
+1
Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
··· 18 18 compatible: 19 19 items: 20 20 - enum: 21 + - mediatek,mt6893-scpsys 21 22 - mediatek,mt8167-scpsys 22 23 - mediatek,mt8173-scpsys 23 24 - mediatek,mt8183-scpsys
-6
Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
··· 76 76 77 77 examples: 78 78 - | 79 - ocelot_clock: ocelot-clock { 80 - compatible = "fixed-clock"; 81 - #clock-cells = <0>; 82 - clock-frequency = <125000000>; 83 - }; 84 - 85 79 spi { 86 80 #address-cells = <1>; 87 81 #size-cells = <0>;
+12 -23
Documentation/devicetree/bindings/mfd/netronix,ntxec.yaml
··· 48 48 - | 49 49 #include <dt-bindings/interrupt-controller/irq.h> 50 50 i2c { 51 - #address-cells = <1>; 52 - #size-cells = <0>; 51 + #address-cells = <1>; 52 + #size-cells = <0>; 53 53 54 - ec: embedded-controller@43 { 55 - pinctrl-names = "default"; 56 - pinctrl-0 = <&pinctrl_ntxec>; 54 + ec: embedded-controller@43 { 55 + pinctrl-names = "default"; 56 + pinctrl-0 = <&pinctrl_ntxec>; 57 57 58 - compatible = "netronix,ntxec"; 59 - reg = <0x43>; 60 - system-power-controller; 61 - interrupt-parent = <&gpio4>; 62 - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 63 - #pwm-cells = <2>; 64 - }; 65 - }; 66 - 67 - backlight { 68 - compatible = "pwm-backlight"; 69 - pwms = <&ec 0 50000>; 70 - power-supply = <&backlight_regulator>; 71 - }; 72 - 73 - backlight_regulator: regulator-dummy { 74 - compatible = "regulator-fixed"; 75 - regulator-name = "backlight"; 58 + compatible = "netronix,ntxec"; 59 + reg = <0x43>; 60 + system-power-controller; 61 + interrupt-parent = <&gpio4>; 62 + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 63 + #pwm-cells = <2>; 64 + }; 76 65 };
+23 -23
Documentation/devicetree/bindings/mfd/rohm,bd9571mwv.yaml
··· 99 99 #include <dt-bindings/interrupt-controller/irq.h> 100 100 101 101 i2c { 102 - #address-cells = <1>; 103 - #size-cells = <0>; 102 + #address-cells = <1>; 103 + #size-cells = <0>; 104 104 105 - pmic: pmic@30 { 106 - compatible = "rohm,bd9571mwv"; 107 - reg = <0x30>; 108 - interrupt-parent = <&gpio2>; 109 - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 110 - interrupt-controller; 111 - #interrupt-cells = <2>; 112 - gpio-controller; 113 - #gpio-cells = <2>; 114 - rohm,ddr-backup-power = <0xf>; 115 - rohm,rstbmode-pulse; 105 + pmic: pmic@30 { 106 + compatible = "rohm,bd9571mwv"; 107 + reg = <0x30>; 108 + interrupt-parent = <&gpio2>; 109 + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 110 + interrupt-controller; 111 + #interrupt-cells = <2>; 112 + gpio-controller; 113 + #gpio-cells = <2>; 114 + rohm,ddr-backup-power = <0xf>; 115 + rohm,rstbmode-pulse; 116 116 117 - regulators { 118 - dvfs: dvfs { 119 - regulator-name = "dvfs"; 120 - regulator-min-microvolt = <750000>; 121 - regulator-max-microvolt = <1030000>; 122 - regulator-boot-on; 123 - regulator-always-on; 124 - }; 125 - }; 126 - }; 117 + regulators { 118 + dvfs: dvfs { 119 + regulator-name = "dvfs"; 120 + regulator-min-microvolt = <750000>; 121 + regulator-max-microvolt = <1030000>; 122 + regulator-boot-on; 123 + regulator-always-on; 124 + }; 125 + }; 126 + }; 127 127 };
+6 -4
Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml
··· 4 4 $id: http://devicetree.org/schemas/mfd/rohm,bd96801-pmic.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: ROHM BD96801 Scalable Power Management Integrated Circuit 7 + title: ROHM BD96801/BD96805 Scalable Power Management Integrated Circuit 8 8 9 9 maintainers: 10 10 - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> 11 11 12 12 description: 13 - BD96801 is an automotive grade single-chip power management IC. 14 - It integrates 4 buck converters and 3 LDOs with safety features like 13 + BD96801 and BD96805 are automotive grade, single-chip power management ICs. 14 + They both integrate 4 buck converters and 3 LDOs with safety features like 15 15 over-/under voltage and over current detection and a watchdog. 16 16 17 17 properties: 18 18 compatible: 19 - const: rohm,bd96801 19 + enum: 20 + - rohm,bd96801 21 + - rohm,bd96805 20 22 21 23 reg: 22 24 maxItems: 1
+101
Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/rohm,bd96802-pmic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ROHM BD96802 / BD96806 Scalable Power Management Integrated Circuit 8 + 9 + maintainers: 10 + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> 11 + 12 + description: | 13 + BD96802Qxx-C and BD96806 are automotive grade configurable Power Management 14 + Integrated Circuits supporting Functional Safety features for application 15 + processors, SoCs and FPGAs 16 + 17 + properties: 18 + compatible: 19 + enum: 20 + - rohm,bd96802 21 + - rohm,bd96806 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + interrupts: 27 + description: 28 + The PMIC provides intb and errb IRQ lines. The errb IRQ line is used 29 + for fatal IRQs which will cause the PMIC to shut down power outputs. 30 + In many systems this will shut down the SoC contolling the PMIC and 31 + connecting/handling the errb can be omitted. However, there are cases 32 + where the SoC is not powered by the PMIC or has a short time backup 33 + energy to handle shutdown of critical hardware. In that case it may be 34 + useful to connect the errb and handle errb events. 35 + minItems: 1 36 + maxItems: 2 37 + 38 + interrupt-names: 39 + minItems: 1 40 + items: 41 + - enum: [intb, errb] 42 + - const: errb 43 + 44 + regulators: 45 + $ref: ../regulator/rohm,bd96802-regulator.yaml 46 + description: 47 + List of child nodes that specify the regulators. 48 + 49 + required: 50 + - compatible 51 + - reg 52 + - interrupts 53 + - interrupt-names 54 + - regulators 55 + 56 + additionalProperties: false 57 + 58 + examples: 59 + - | 60 + #include <dt-bindings/interrupt-controller/irq.h> 61 + #include <dt-bindings/leds/common.h> 62 + i2c { 63 + #address-cells = <1>; 64 + #size-cells = <0>; 65 + pmic: pmic@62 { 66 + reg = <0x62>; 67 + compatible = "rohm,bd96802"; 68 + interrupt-parent = <&gpio1>; 69 + interrupts = <29 IRQ_TYPE_LEVEL_LOW>, <6 IRQ_TYPE_LEVEL_LOW>; 70 + interrupt-names = "intb", "errb"; 71 + 72 + regulators { 73 + buck1 { 74 + regulator-name = "buck1"; 75 + regulator-ramp-delay = <1250>; 76 + /* 0.5V min INITIAL - 150 mV tune */ 77 + regulator-min-microvolt = <350000>; 78 + /* 3.3V + 150mV tune */ 79 + regulator-max-microvolt = <3450000>; 80 + 81 + /* These can be set only when PMIC is in STBY */ 82 + rohm,initial-voltage-microvolt = <500000>; 83 + regulator-ov-error-microvolt = <230000>; 84 + regulator-uv-error-microvolt = <230000>; 85 + regulator-temp-protection-kelvin = <1>; 86 + regulator-temp-warn-kelvin = <0>; 87 + }; 88 + buck2 { 89 + regulator-name = "buck2"; 90 + regulator-min-microvolt = <350000>; 91 + regulator-max-microvolt = <3450000>; 92 + 93 + rohm,initial-voltage-microvolt = <3000000>; 94 + regulator-ov-error-microvolt = <18000>; 95 + regulator-uv-error-microvolt = <18000>; 96 + regulator-temp-protection-kelvin = <1>; 97 + regulator-temp-warn-kelvin = <1>; 98 + }; 99 + }; 100 + }; 101 + };
+25 -1
Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml
··· 20 20 properties: 21 21 compatible: 22 22 enum: 23 + - samsung,s2mpg10-pmic 23 24 - samsung,s2mps11-pmic 24 25 - samsung,s2mps13-pmic 25 26 - samsung,s2mps14-pmic ··· 59 58 reset (setting buck voltages to default values). 60 59 type: boolean 61 60 61 + system-power-controller: true 62 + 62 63 wakeup-source: true 63 64 64 65 required: 65 66 - compatible 66 - - reg 67 67 - regulators 68 68 69 69 additionalProperties: false 70 70 71 71 allOf: 72 + - if: 73 + properties: 74 + compatible: 75 + contains: 76 + const: samsung,s2mpg10-pmic 77 + then: 78 + properties: 79 + reg: false 80 + samsung,s2mps11-acokb-ground: false 81 + samsung,s2mps11-wrstbi-ground: false 82 + 83 + oneOf: 84 + - required: [interrupts] 85 + - required: [interrupts-extended] 86 + 87 + else: 88 + properties: 89 + system-power-controller: false 90 + 91 + required: 92 + - reg 93 + 72 94 - if: 73 95 properties: 74 96 compatible:
+34 -6
Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
··· 21 21 22 22 properties: 23 23 compatible: 24 - const: st,stm32-lptimer 24 + oneOf: 25 + - items: 26 + - const: st,stm32mp25-lptimer 27 + - const: st,stm32-lptimer 28 + - items: 29 + - const: st,stm32-lptimer 25 30 26 31 reg: 27 32 maxItems: 1 ··· 53 48 minItems: 1 54 49 maxItems: 2 55 50 51 + power-domains: 52 + maxItems: 1 53 + 56 54 pwm: 57 55 type: object 58 56 additionalProperties: false 59 57 60 58 properties: 61 59 compatible: 62 - const: st,stm32-pwm-lp 60 + oneOf: 61 + - items: 62 + - const: st,stm32mp25-pwm-lp 63 + - const: st,stm32-pwm-lp 64 + - items: 65 + - const: st,stm32-pwm-lp 63 66 64 67 "#pwm-cells": 65 68 const: 3 ··· 82 69 83 70 properties: 84 71 compatible: 85 - const: st,stm32-lptimer-counter 72 + oneOf: 73 + - items: 74 + - const: st,stm32mp25-lptimer-counter 75 + - const: st,stm32-lptimer-counter 76 + - items: 77 + - const: st,stm32-lptimer-counter 86 78 87 79 required: 88 80 - compatible ··· 98 80 99 81 properties: 100 82 compatible: 101 - const: st,stm32-lptimer-timer 83 + oneOf: 84 + - items: 85 + - const: st,stm32mp25-lptimer-timer 86 + - const: st,stm32-lptimer-timer 87 + - items: 88 + - const: st,stm32-lptimer-timer 102 89 103 90 required: 104 91 - compatible ··· 115 92 116 93 properties: 117 94 compatible: 118 - const: st,stm32-lptimer-trigger 95 + oneOf: 96 + - items: 97 + - const: st,stm32mp25-lptimer-trigger 98 + - const: st,stm32-lptimer-trigger 99 + - items: 100 + - const: st,stm32-lptimer-trigger 119 101 120 102 reg: 121 103 description: Identify trigger hardware block. 122 104 items: 123 105 minimum: 0 124 - maximum: 2 106 + maximum: 4 125 107 126 108 required: 127 109 - compatible
+7
Documentation/devicetree/bindings/mfd/syscon.yaml
··· 84 84 - mediatek,mt2701-pctl-a-syscfg 85 85 - mediatek,mt2712-pctl-a-syscfg 86 86 - mediatek,mt6397-pctl-pmic-syscfg 87 + - mediatek,mt7988-topmisc 87 88 - mediatek,mt8135-pctl-a-syscfg 88 89 - mediatek,mt8135-pctl-b-syscfg 89 90 - mediatek,mt8173-pctl-a-syscfg ··· 99 98 - mstar,msc313-pmsleep 100 99 - nuvoton,ma35d1-sys 101 100 - nuvoton,wpcm450-shm 101 + - qcom,apq8064-mmss-sfpb 102 + - qcom,apq8064-sps-sic 102 103 - rockchip,px30-qos 103 104 - rockchip,rk3036-qos 104 105 - rockchip,rk3066-qos ··· 190 187 - mediatek,mt2701-pctl-a-syscfg 191 188 - mediatek,mt2712-pctl-a-syscfg 192 189 - mediatek,mt6397-pctl-pmic-syscfg 190 + - mediatek,mt7988-topmisc 193 191 - mediatek,mt8135-pctl-a-syscfg 194 192 - mediatek,mt8135-pctl-b-syscfg 195 193 - mediatek,mt8173-pctl-a-syscfg 194 + - mediatek,mt8365-infracfg-nao 196 195 - mediatek,mt8365-syscfg 197 196 - microchip,lan966x-cpu-syscon 198 197 - microchip,mpfs-sysreg-scb ··· 206 201 - mstar,msc313-pmsleep 207 202 - nuvoton,ma35d1-sys 208 203 - nuvoton,wpcm450-shm 204 + - qcom,apq8064-mmss-sfpb 205 + - qcom,apq8064-sps-sic 209 206 - rockchip,px30-qos 210 207 - rockchip,rk3036-qos 211 208 - rockchip,rk3066-qos
+84 -84
Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
··· 316 316 317 317 examples: 318 318 - | 319 - i2c { 320 - #address-cells = <1>; 321 - #size-cells = <0>; 319 + i2c { 320 + #address-cells = <1>; 321 + #size-cells = <0>; 322 322 323 - pmic@30 { 324 - compatible = "x-powers,axp152"; 325 - reg = <0x30>; 326 - interrupts = <0>; 327 - interrupt-controller; 328 - #interrupt-cells = <1>; 329 - }; 330 - }; 323 + pmic@30 { 324 + compatible = "x-powers,axp152"; 325 + reg = <0x30>; 326 + interrupts = <0>; 327 + interrupt-controller; 328 + #interrupt-cells = <1>; 329 + }; 330 + }; 331 331 332 332 - | 333 - #include <dt-bindings/interrupt-controller/irq.h> 333 + #include <dt-bindings/interrupt-controller/irq.h> 334 334 335 - i2c { 336 - #address-cells = <1>; 337 - #size-cells = <0>; 335 + i2c { 336 + #address-cells = <1>; 337 + #size-cells = <0>; 338 338 339 - pmic@34 { 340 - compatible = "x-powers,axp209"; 341 - reg = <0x34>; 342 - interrupt-parent = <&nmi_intc>; 343 - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 344 - interrupt-controller; 345 - #interrupt-cells = <1>; 339 + pmic@34 { 340 + compatible = "x-powers,axp209"; 341 + reg = <0x34>; 342 + interrupt-parent = <&nmi_intc>; 343 + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 344 + interrupt-controller; 345 + #interrupt-cells = <1>; 346 346 347 - ac_power_supply: ac-power { 348 - compatible = "x-powers,axp202-ac-power-supply"; 349 - }; 347 + ac_power_supply: ac-power { 348 + compatible = "x-powers,axp202-ac-power-supply"; 349 + }; 350 350 351 - axp_adc: adc { 352 - compatible = "x-powers,axp209-adc"; 353 - #io-channel-cells = <1>; 354 - }; 351 + axp_adc: adc { 352 + compatible = "x-powers,axp209-adc"; 353 + #io-channel-cells = <1>; 354 + }; 355 355 356 - axp_gpio: gpio { 357 - compatible = "x-powers,axp209-gpio"; 358 - gpio-controller; 359 - #gpio-cells = <2>; 356 + axp_gpio: gpio { 357 + compatible = "x-powers,axp209-gpio"; 358 + gpio-controller; 359 + #gpio-cells = <2>; 360 360 361 - gpio0-adc-pin { 362 - pins = "GPIO0"; 363 - function = "adc"; 364 - }; 365 - }; 361 + gpio0-adc-pin { 362 + pins = "GPIO0"; 363 + function = "adc"; 364 + }; 365 + }; 366 366 367 - battery_power_supply: battery-power { 368 - compatible = "x-powers,axp209-battery-power-supply"; 369 - }; 367 + battery_power_supply: battery-power { 368 + compatible = "x-powers,axp209-battery-power-supply"; 369 + }; 370 370 371 - regulators { 372 - /* Default work frequency for buck regulators */ 373 - x-powers,dcdc-freq = <1500>; 371 + regulators { 372 + /* Default work frequency for buck regulators */ 373 + x-powers,dcdc-freq = <1500>; 374 374 375 - reg_dcdc2: dcdc2 { 376 - regulator-always-on; 377 - regulator-min-microvolt = <1000000>; 378 - regulator-max-microvolt = <1450000>; 379 - regulator-name = "vdd-cpu"; 380 - }; 375 + reg_dcdc2: dcdc2 { 376 + regulator-always-on; 377 + regulator-min-microvolt = <1000000>; 378 + regulator-max-microvolt = <1450000>; 379 + regulator-name = "vdd-cpu"; 380 + }; 381 381 382 - reg_dcdc3: dcdc3 { 383 - regulator-always-on; 384 - regulator-min-microvolt = <1000000>; 385 - regulator-max-microvolt = <1400000>; 386 - regulator-name = "vdd-int-dll"; 387 - }; 382 + reg_dcdc3: dcdc3 { 383 + regulator-always-on; 384 + regulator-min-microvolt = <1000000>; 385 + regulator-max-microvolt = <1400000>; 386 + regulator-name = "vdd-int-dll"; 387 + }; 388 388 389 - reg_ldo1: ldo1 { 390 - /* LDO1 is a fixed output regulator */ 391 - regulator-always-on; 392 - regulator-min-microvolt = <1300000>; 393 - regulator-max-microvolt = <1300000>; 394 - regulator-name = "vdd-rtc"; 395 - }; 389 + reg_ldo1: ldo1 { 390 + /* LDO1 is a fixed output regulator */ 391 + regulator-always-on; 392 + regulator-min-microvolt = <1300000>; 393 + regulator-max-microvolt = <1300000>; 394 + regulator-name = "vdd-rtc"; 395 + }; 396 396 397 - reg_ldo2: ldo2 { 398 - regulator-always-on; 399 - regulator-min-microvolt = <3000000>; 400 - regulator-max-microvolt = <3000000>; 401 - regulator-name = "avcc"; 402 - }; 397 + reg_ldo2: ldo2 { 398 + regulator-always-on; 399 + regulator-min-microvolt = <3000000>; 400 + regulator-max-microvolt = <3000000>; 401 + regulator-name = "avcc"; 402 + }; 403 403 404 - reg_ldo3: ldo3 { 405 - regulator-name = "ldo3"; 406 - }; 404 + reg_ldo3: ldo3 { 405 + regulator-name = "ldo3"; 406 + }; 407 407 408 - reg_ldo4: ldo4 { 409 - regulator-name = "ldo4"; 410 - }; 408 + reg_ldo4: ldo4 { 409 + regulator-name = "ldo4"; 410 + }; 411 411 412 - reg_ldo5: ldo5 { 413 - regulator-name = "ldo5"; 414 - }; 415 - }; 412 + reg_ldo5: ldo5 { 413 + regulator-name = "ldo5"; 414 + }; 415 + }; 416 416 417 - usb_power_supply: usb-power { 418 - compatible = "x-powers,axp202-usb-power-supply"; 419 - }; 420 - }; 421 - }; 417 + usb_power_supply: usb-power { 418 + compatible = "x-powers,axp202-usb-power-supply"; 419 + }; 420 + }; 421 + };
+56
Documentation/devicetree/bindings/regulator/brcm,bcm59054.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/regulator/brcm,bcm59054.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM59054 Power Management Unit regulators 8 + 9 + description: | 10 + This is a part of device tree bindings for the BCM59054 power 11 + management unit. 12 + 13 + See Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml for 14 + additional information and example. 15 + 16 + maintainers: 17 + - Artur Weber <aweber.kernel@gmail.com> 18 + 19 + patternProperties: 20 + "^(cam|sim|mmc)ldo[1-2]$": 21 + type: object 22 + $ref: /schemas/regulator/regulator.yaml# 23 + unevaluatedProperties: false 24 + 25 + "^(rf|sd|sdx|aud|mic|usb|vib|tcx)ldo$": 26 + type: object 27 + $ref: /schemas/regulator/regulator.yaml# 28 + unevaluatedProperties: false 29 + 30 + "^(c|mm|v)sr$": 31 + type: object 32 + $ref: /schemas/regulator/regulator.yaml# 33 + unevaluatedProperties: false 34 + 35 + "^(io|sd)sr[1-2]$": 36 + type: object 37 + $ref: /schemas/regulator/regulator.yaml# 38 + unevaluatedProperties: false 39 + 40 + "^gpldo[1-3]$": 41 + type: object 42 + $ref: /schemas/regulator/regulator.yaml# 43 + unevaluatedProperties: false 44 + 45 + "^lvldo[1-2]$": 46 + type: object 47 + $ref: /schemas/regulator/regulator.yaml# 48 + unevaluatedProperties: false 49 + 50 + properties: 51 + vbus: 52 + type: object 53 + $ref: /schemas/regulator/regulator.yaml# 54 + unevaluatedProperties: false 55 + 56 + additionalProperties: false
+51
Documentation/devicetree/bindings/regulator/brcm,bcm59056.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/regulator/brcm,bcm59056.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM59056 Power Management Unit regulators 8 + 9 + description: | 10 + This is a part of device tree bindings for the BCM59056 power 11 + management unit. 12 + 13 + See Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml for 14 + additional information and example. 15 + 16 + maintainers: 17 + - Artur Weber <aweber.kernel@gmail.com> 18 + 19 + patternProperties: 20 + "^(cam|sim|mmc)ldo[1-2]$": 21 + type: object 22 + $ref: /schemas/regulator/regulator.yaml# 23 + unevaluatedProperties: false 24 + 25 + "^(rf|sd|sdx|aud|mic|usb|vib)ldo$": 26 + type: object 27 + $ref: /schemas/regulator/regulator.yaml# 28 + unevaluatedProperties: false 29 + 30 + "^(c|m|v)sr$": 31 + type: object 32 + $ref: /schemas/regulator/regulator.yaml# 33 + unevaluatedProperties: false 34 + 35 + "^(io|sd)sr[1-2]$": 36 + type: object 37 + $ref: /schemas/regulator/regulator.yaml# 38 + unevaluatedProperties: false 39 + 40 + "^gpldo[1-6]$": 41 + type: object 42 + $ref: /schemas/regulator/regulator.yaml# 43 + unevaluatedProperties: false 44 + 45 + properties: 46 + vbus: 47 + type: object 48 + $ref: /schemas/regulator/regulator.yaml# 49 + unevaluatedProperties: false 50 + 51 + additionalProperties: false
+44
Documentation/devicetree/bindings/regulator/rohm,bd96802-regulator.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/regulator/rohm,bd96802-regulator.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ROHM BD96802 Power Management Integrated Circuit regulators 8 + 9 + maintainers: 10 + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> 11 + 12 + description: 13 + This module is part of the ROHM BD96802 MFD device. For more details 14 + see Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml. 15 + 16 + The regulator controller is represented as a sub-node of the PMIC node 17 + on the device tree. 18 + 19 + Regulator nodes should be named to buck1 and buck2. 20 + 21 + patternProperties: 22 + "^buck[1-2]$": 23 + type: object 24 + description: 25 + Properties for single BUCK regulator. 26 + $ref: regulator.yaml# 27 + 28 + properties: 29 + rohm,initial-voltage-microvolt: 30 + description: 31 + Initial voltage for regulator. Voltage can be tuned +/-150 mV from 32 + this value. NOTE, This can be modified via I2C only when PMIC is in 33 + STBY state. 34 + minimum: 500000 35 + maximum: 3300000 36 + 37 + rohm,keep-on-stby: 38 + description: 39 + Keep the regulator powered when PMIC transitions to STBY state. 40 + type: boolean 41 + 42 + unevaluatedProperties: false 43 + 44 + additionalProperties: false
+4 -2
MAINTAINERS
··· 21475 21475 F: include/linux/mfd/rohm-bd718x7.h 21476 21476 F: include/linux/mfd/rohm-bd957x.h 21477 21477 F: include/linux/mfd/rohm-bd96801.h 21478 + F: include/linux/mfd/rohm-bd96802.h 21478 21479 F: include/linux/mfd/rohm-generic.h 21479 21480 F: include/linux/mfd/rohm-shared.h 21480 21481 ··· 21913 21912 21914 21913 SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS 21915 21914 M: Krzysztof Kozlowski <krzk@kernel.org> 21915 + R: André Draszik <andre.draszik@linaro.org> 21916 21916 L: linux-kernel@vger.kernel.org 21917 21917 L: linux-samsung-soc@vger.kernel.org 21918 21918 S: Maintained ··· 21924 21922 F: Documentation/devicetree/bindings/regulator/samsung,s2m*.yaml 21925 21923 F: Documentation/devicetree/bindings/regulator/samsung,s5m*.yaml 21926 21924 F: drivers/clk/clk-s2mps11.c 21927 - F: drivers/mfd/sec*.c 21925 + F: drivers/mfd/sec*.[ch] 21928 21926 F: drivers/regulator/s2m*.c 21929 21927 F: drivers/regulator/s5m*.c 21930 21928 F: drivers/rtc/rtc-s5m.c ··· 22577 22575 M: Tobias Schaffner <tobias.schaffner@siemens.com> 22578 22576 L: linux-leds@vger.kernel.org 22579 22577 S: Maintained 22580 - F: drivers/leds/simple/ 22578 + F: drivers/leds/simatic/ 22581 22579 22582 22580 SIEMENS IPC PLATFORM DRIVERS 22583 22581 M: Bao Cheng Su <baocheng.su@siemens.com>
+1 -1
arch/arm/configs/exynos_defconfig
··· 167 167 CONFIG_MFD_MAX77693=y 168 168 CONFIG_MFD_MAX8997=y 169 169 CONFIG_MFD_MAX8998=y 170 - CONFIG_MFD_SEC_CORE=y 170 + CONFIG_MFD_SEC_I2C=y 171 171 CONFIG_MFD_STMPE=y 172 172 CONFIG_STMPE_I2C=y 173 173 CONFIG_MFD_TPS65090=y
+1 -1
arch/arm/configs/multi_v7_defconfig
··· 612 612 CONFIG_MFD_SPMI_PMIC=y 613 613 CONFIG_MFD_RK8XX_I2C=y 614 614 CONFIG_MFD_RN5T618=y 615 - CONFIG_MFD_SEC_CORE=y 615 + CONFIG_MFD_SEC_I2C=y 616 616 CONFIG_MFD_STMPE=y 617 617 CONFIG_MFD_PALMAS=y 618 618 CONFIG_MFD_TPS65090=y
+1 -1
arch/arm/configs/pxa_defconfig
··· 335 335 CONFIG_MFD_MAX8907=m 336 336 CONFIG_EZX_PCAP=y 337 337 CONFIG_UCB1400_CORE=m 338 - CONFIG_MFD_SEC_CORE=y 338 + CONFIG_MFD_SEC_I2C=y 339 339 CONFIG_MFD_PALMAS=y 340 340 CONFIG_MFD_TPS65090=y 341 341 CONFIG_MFD_TPS6586X=y
+1 -1
arch/arm64/configs/defconfig
··· 774 774 CONFIG_MFD_SPMI_PMIC=y 775 775 CONFIG_MFD_RK8XX_I2C=y 776 776 CONFIG_MFD_RK8XX_SPI=y 777 - CONFIG_MFD_SEC_CORE=y 777 + CONFIG_MFD_SEC_I2C=y 778 778 CONFIG_MFD_SL28CPLD=y 779 779 CONFIG_RZ_MTU3=y 780 780 CONFIG_MFD_TI_AM335X_TSCADC=m
+57 -4
drivers/clocksource/timer-stm32-lp.c
··· 5 5 * Pascal Paillet <p.paillet@st.com> for STMicroelectronics. 6 6 */ 7 7 8 + #include <linux/bitfield.h> 8 9 #include <linux/clk.h> 9 10 #include <linux/clockchips.h> 10 11 #include <linux/interrupt.h> ··· 28 27 u32 psc; 29 28 struct device *dev; 30 29 struct clk *clk; 30 + u32 version; 31 31 }; 32 32 33 33 static struct stm32_lp_private* ··· 49 47 return 0; 50 48 } 51 49 52 - static int stm32_clkevent_lp_set_timer(unsigned long evt, 53 - struct clock_event_device *clkevt, 54 - int is_periodic) 50 + static int stm32mp25_clkevent_lp_set_evt(struct stm32_lp_private *priv, unsigned long evt) 55 51 { 56 - struct stm32_lp_private *priv = to_priv(clkevt); 52 + int ret; 53 + u32 val; 57 54 55 + regmap_read(priv->reg, STM32_LPTIM_CR, &val); 56 + if (!FIELD_GET(STM32_LPTIM_ENABLE, val)) { 57 + /* Enable LPTIMER to be able to write into IER and ARR registers */ 58 + regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); 59 + /* 60 + * After setting the ENABLE bit, a delay of two counter clock cycles is needed 61 + * before the LPTIM is actually enabled. For 32KHz rate, this makes approximately 62 + * 62.5 micro-seconds, round it up. 63 + */ 64 + udelay(63); 65 + } 66 + /* set next event counter */ 67 + regmap_write(priv->reg, STM32_LPTIM_ARR, evt); 68 + /* enable ARR interrupt */ 69 + regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE); 70 + 71 + /* Poll DIEROK and ARROK to ensure register access has completed */ 72 + ret = regmap_read_poll_timeout_atomic(priv->reg, STM32_LPTIM_ISR, val, 73 + (val & STM32_LPTIM_DIEROK_ARROK) == 74 + STM32_LPTIM_DIEROK_ARROK, 75 + 10, 500); 76 + if (ret) { 77 + dev_err(priv->dev, "access to LPTIM timed out\n"); 78 + /* Disable LPTIMER */ 79 + regmap_write(priv->reg, STM32_LPTIM_CR, 0); 80 + return ret; 81 + } 82 + /* Clear DIEROK and ARROK flags */ 83 + regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_DIEROKCF_ARROKCF); 84 + 85 + return 0; 86 + } 87 + 88 + static void stm32_clkevent_lp_set_evt(struct stm32_lp_private *priv, unsigned long evt) 89 + { 58 90 /* disable LPTIMER to be able to write into IER register*/ 59 91 regmap_write(priv->reg, STM32_LPTIM_CR, 0); 60 92 /* enable ARR interrupt */ ··· 97 61 regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); 98 62 /* set next event counter */ 99 63 regmap_write(priv->reg, STM32_LPTIM_ARR, evt); 64 + } 65 + 66 + static int stm32_clkevent_lp_set_timer(unsigned long evt, 67 + struct clock_event_device *clkevt, 68 + int is_periodic) 69 + { 70 + struct stm32_lp_private *priv = to_priv(clkevt); 71 + int ret; 72 + 73 + if (priv->version == STM32_LPTIM_VERR_23) { 74 + ret = stm32mp25_clkevent_lp_set_evt(priv, evt); 75 + if (ret) 76 + return ret; 77 + } else { 78 + stm32_clkevent_lp_set_evt(priv, evt); 79 + } 100 80 101 81 /* start counter */ 102 82 if (is_periodic) ··· 228 176 return -ENOMEM; 229 177 230 178 priv->reg = ddata->regmap; 179 + priv->version = ddata->version; 231 180 priv->clk = ddata->clk; 232 181 ret = clk_prepare_enable(priv->clk); 233 182 if (ret)
+9 -5
drivers/mfd/88pm886.c
··· 16 16 .max_register = PM886_REG_RTC_SPARE6, 17 17 }; 18 18 19 - static struct regmap_irq pm886_regmap_irqs[] = { 19 + static const struct regmap_irq pm886_regmap_irqs[] = { 20 20 REGMAP_IRQ_REG(PM886_IRQ_ONKEY, 0, PM886_INT_ENA1_ONKEY), 21 21 }; 22 22 23 - static struct regmap_irq_chip pm886_regmap_irq_chip = { 23 + static const struct regmap_irq_chip pm886_regmap_irq_chip = { 24 24 .name = "88pm886", 25 25 .irqs = pm886_regmap_irqs, 26 26 .num_irqs = ARRAY_SIZE(pm886_regmap_irqs), ··· 30 30 .unmask_base = PM886_REG_INT_ENA_1, 31 31 }; 32 32 33 - static struct resource pm886_onkey_resources[] = { 33 + static const struct resource pm886_onkey_resources[] = { 34 34 DEFINE_RES_IRQ_NAMED(PM886_IRQ_ONKEY, "88pm886-onkey"), 35 35 }; 36 36 37 - static struct mfd_cell pm886_devs[] = { 37 + static const struct mfd_cell pm886_devs[] = { 38 38 MFD_CELL_RES("88pm886-onkey", pm886_onkey_resources), 39 39 MFD_CELL_NAME("88pm886-regulator"), 40 40 MFD_CELL_NAME("88pm886-rtc"), ··· 124 124 if (err) 125 125 return dev_err_probe(dev, err, "Failed to register power off handler\n"); 126 126 127 - device_init_wakeup(dev, device_property_read_bool(dev, "wakeup-source")); 127 + if (device_property_read_bool(dev, "wakeup-source")) { 128 + err = devm_device_init_wakeup(dev); 129 + if (err) 130 + return dev_err_probe(dev, err, "Failed to init wakeup\n"); 131 + } 128 132 129 133 return 0; 130 134 }
+28 -7
drivers/mfd/Kconfig
··· 1312 1312 functionality of the device. 1313 1313 1314 1314 config MFD_SEC_CORE 1315 - tristate "Samsung Electronics PMIC Series Support" 1315 + tristate 1316 + select MFD_CORE 1317 + select REGMAP_IRQ 1318 + 1319 + config MFD_SEC_ACPM 1320 + tristate "Samsung Electronics S2MPG1x PMICs" 1321 + depends on EXYNOS_ACPM_PROTOCOL 1322 + depends on OF 1323 + select MFD_SEC_CORE 1324 + help 1325 + Support for the Samsung Electronics PMICs with ACPM interface. 1326 + This is a Power Management IC for mobile applications with buck 1327 + converters, various LDOs, power meters, RTC, clock outputs, and 1328 + additional GPIOs interfaces. 1329 + This driver provides common support for accessing the device; 1330 + additional drivers must be enabled in order to use the functionality 1331 + of the device. 1332 + 1333 + To compile this driver as a module, choose M here: the module will be 1334 + called sec-acpm. 1335 + 1336 + config MFD_SEC_I2C 1337 + tristate "Samsung Electronics S2MPA/S2MPS1X/S2MPU/S5M series PMICs" 1316 1338 depends on I2C=y 1317 1339 depends on OF 1318 - select MFD_CORE 1340 + select MFD_SEC_CORE 1319 1341 select REGMAP_I2C 1320 - select REGMAP_IRQ 1321 1342 help 1322 - Support for the Samsung Electronics PMIC devices coming 1323 - usually along with Samsung Exynos SoC chipset. 1343 + Support for the Samsung Electronics PMIC devices with I2C interface 1344 + coming usually along with Samsung Exynos SoC chipset. 1324 1345 This driver provides common support for accessing the device, 1325 1346 additional drivers must be enabled in order to use the functionality 1326 - of the device 1347 + of the device. 1327 1348 1328 1349 To compile this driver as a module, choose M here: the 1329 - module will be called sec-core. 1350 + module will be called sec-i2c. 1330 1351 Have in mind that important core drivers (like regulators) depend 1331 1352 on this driver so building this as a module might require proper 1332 1353 initial ramdisk or might not boot up as well in certain scenarios.
+4 -1
drivers/mfd/Makefile
··· 229 229 obj-$(CONFIG_MFD_RK8XX_I2C) += rk8xx-i2c.o 230 230 obj-$(CONFIG_MFD_RK8XX_SPI) += rk8xx-spi.o 231 231 obj-$(CONFIG_MFD_RN5T618) += rn5t618.o 232 - obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o 232 + sec-core-objs := sec-common.o sec-irq.o 233 + obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o 234 + obj-$(CONFIG_MFD_SEC_ACPM) += sec-acpm.o 235 + obj-$(CONFIG_MFD_SEC_I2C) += sec-i2c.o 233 236 obj-$(CONFIG_MFD_SYSCON) += syscon.o 234 237 obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o 235 238 obj-$(CONFIG_MFD_VEXPRESS_SYSREG) += vexpress-sysreg.o
+1 -3
drivers/mfd/aat2870-core.c
··· 320 320 321 321 static void aat2870_init_debugfs(struct aat2870_data *aat2870) 322 322 { 323 - aat2870->dentry_root = debugfs_create_dir("aat2870", NULL); 324 - 325 - debugfs_create_file("regs", 0644, aat2870->dentry_root, aat2870, 323 + debugfs_create_file("regs", 0644, aat2870->client->debugfs, aat2870, 326 324 &aat2870_reg_fops); 327 325 } 328 326
+3 -1
drivers/mfd/as3722.c
··· 394 394 return ret; 395 395 } 396 396 397 - device_init_wakeup(as3722->dev, true); 397 + ret = devm_device_init_wakeup(as3722->dev); 398 + if (ret) 399 + return dev_err_probe(as3722->dev, ret, "Failed to init wakeup\n"); 398 400 399 401 dev_dbg(as3722->dev, "AS3722 core driver initialized successfully\n"); 400 402 return 0;
+65 -1
drivers/mfd/bcm590xx.c
··· 17 17 #include <linux/regmap.h> 18 18 #include <linux/slab.h> 19 19 20 + /* Under primary I2C address: */ 21 + #define BCM590XX_REG_PMUID 0x1e 22 + 23 + #define BCM590XX_REG_PMUREV 0x1f 24 + #define BCM590XX_PMUREV_DIG_MASK 0xF 25 + #define BCM590XX_PMUREV_DIG_SHIFT 0 26 + #define BCM590XX_PMUREV_ANA_MASK 0xF0 27 + #define BCM590XX_PMUREV_ANA_SHIFT 4 28 + 20 29 static const struct mfd_cell bcm590xx_devs[] = { 21 30 { 22 31 .name = "bcm590xx-vregs", ··· 46 37 .cache_type = REGCACHE_MAPLE, 47 38 }; 48 39 40 + /* Map PMU ID value to model name string */ 41 + static const char * const bcm590xx_names[] = { 42 + [BCM590XX_PMUID_BCM59054] = "BCM59054", 43 + [BCM590XX_PMUID_BCM59056] = "BCM59056", 44 + }; 45 + 46 + static int bcm590xx_parse_version(struct bcm590xx *bcm590xx) 47 + { 48 + unsigned int id, rev; 49 + int ret; 50 + 51 + /* Get PMU ID and verify that it matches compatible */ 52 + ret = regmap_read(bcm590xx->regmap_pri, BCM590XX_REG_PMUID, &id); 53 + if (ret) { 54 + dev_err(bcm590xx->dev, "failed to read PMU ID: %d\n", ret); 55 + return ret; 56 + } 57 + 58 + if (id != bcm590xx->pmu_id) { 59 + dev_err(bcm590xx->dev, "Incorrect ID for %s: expected %x, got %x.\n", 60 + bcm590xx_names[bcm590xx->pmu_id], bcm590xx->pmu_id, id); 61 + return -ENODEV; 62 + } 63 + 64 + /* Get PMU revision and store it in the info struct */ 65 + ret = regmap_read(bcm590xx->regmap_pri, BCM590XX_REG_PMUREV, &rev); 66 + if (ret) { 67 + dev_err(bcm590xx->dev, "failed to read PMU revision: %d\n", ret); 68 + return ret; 69 + } 70 + 71 + bcm590xx->rev_digital = (rev & BCM590XX_PMUREV_DIG_MASK) >> BCM590XX_PMUREV_DIG_SHIFT; 72 + 73 + bcm590xx->rev_analog = (rev & BCM590XX_PMUREV_ANA_MASK) >> BCM590XX_PMUREV_ANA_SHIFT; 74 + 75 + dev_dbg(bcm590xx->dev, "PMU ID 0x%x (%s), revision: digital %d, analog %d", 76 + id, bcm590xx_names[id], bcm590xx->rev_digital, bcm590xx->rev_analog); 77 + 78 + return 0; 79 + } 80 + 49 81 static int bcm590xx_i2c_probe(struct i2c_client *i2c_pri) 50 82 { 51 83 struct bcm590xx *bcm590xx; ··· 99 49 i2c_set_clientdata(i2c_pri, bcm590xx); 100 50 bcm590xx->dev = &i2c_pri->dev; 101 51 bcm590xx->i2c_pri = i2c_pri; 52 + 53 + bcm590xx->pmu_id = (uintptr_t) of_device_get_match_data(bcm590xx->dev); 102 54 103 55 bcm590xx->regmap_pri = devm_regmap_init_i2c(i2c_pri, 104 56 &bcm590xx_regmap_config_pri); ··· 128 76 goto err; 129 77 } 130 78 79 + ret = bcm590xx_parse_version(bcm590xx); 80 + if (ret) 81 + goto err; 82 + 131 83 ret = devm_mfd_add_devices(&i2c_pri->dev, -1, bcm590xx_devs, 132 84 ARRAY_SIZE(bcm590xx_devs), NULL, 0, NULL); 133 85 if (ret < 0) { ··· 147 91 } 148 92 149 93 static const struct of_device_id bcm590xx_of_match[] = { 150 - { .compatible = "brcm,bcm59056" }, 94 + { 95 + .compatible = "brcm,bcm59054", 96 + .data = (void *)BCM590XX_PMUID_BCM59054, 97 + }, 98 + { 99 + .compatible = "brcm,bcm59056", 100 + .data = (void *)BCM590XX_PMUID_BCM59056, 101 + }, 151 102 { } 152 103 }; 153 104 MODULE_DEVICE_TABLE(of, bcm590xx_of_match); 154 105 155 106 static const struct i2c_device_id bcm590xx_i2c_id[] = { 107 + { "bcm59054" }, 156 108 { "bcm59056" }, 157 109 { } 158 110 };
+17 -14
drivers/mfd/exynos-lpass.c
··· 104 104 .fast_io = true, 105 105 }; 106 106 107 + static void exynos_lpass_disable_lpass(void *data) 108 + { 109 + struct platform_device *pdev = data; 110 + struct exynos_lpass *lpass = platform_get_drvdata(pdev); 111 + 112 + pm_runtime_disable(&pdev->dev); 113 + if (!pm_runtime_status_suspended(&pdev->dev)) 114 + exynos_lpass_disable(lpass); 115 + } 116 + 107 117 static int exynos_lpass_probe(struct platform_device *pdev) 108 118 { 109 119 struct device *dev = &pdev->dev; 110 120 struct exynos_lpass *lpass; 111 121 void __iomem *base_top; 122 + int ret; 112 123 113 124 lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL); 114 125 if (!lpass) ··· 133 122 if (IS_ERR(lpass->sfr0_clk)) 134 123 return PTR_ERR(lpass->sfr0_clk); 135 124 136 - lpass->top = regmap_init_mmio(dev, base_top, 137 - &exynos_lpass_reg_conf); 125 + lpass->top = devm_regmap_init_mmio(dev, base_top, 126 + &exynos_lpass_reg_conf); 138 127 if (IS_ERR(lpass->top)) { 139 128 dev_err(dev, "LPASS top regmap initialization failed\n"); 140 129 return PTR_ERR(lpass->top); ··· 145 134 pm_runtime_enable(dev); 146 135 exynos_lpass_enable(lpass); 147 136 137 + ret = devm_add_action_or_reset(dev, exynos_lpass_disable_lpass, pdev); 138 + if (ret) 139 + return ret; 140 + 148 141 return devm_of_platform_populate(dev); 149 - } 150 - 151 - static void exynos_lpass_remove(struct platform_device *pdev) 152 - { 153 - struct exynos_lpass *lpass = platform_get_drvdata(pdev); 154 - 155 - exynos_lpass_disable(lpass); 156 - pm_runtime_disable(&pdev->dev); 157 - if (!pm_runtime_status_suspended(&pdev->dev)) 158 - exynos_lpass_disable(lpass); 159 - regmap_exit(lpass->top); 160 142 } 161 143 162 144 static int __maybe_unused exynos_lpass_suspend(struct device *dev) ··· 189 185 .of_match_table = exynos_lpass_of_match, 190 186 }, 191 187 .probe = exynos_lpass_probe, 192 - .remove = exynos_lpass_remove, 193 188 }; 194 189 module_platform_driver(exynos_lpass_driver); 195 190
+1
drivers/mfd/max14577.c
··· 456 456 { 457 457 struct max14577 *max14577 = i2c_get_clientdata(i2c); 458 458 459 + device_init_wakeup(max14577->dev, false); 459 460 mfd_remove_devices(max14577->dev); 460 461 regmap_del_irq_chip(max14577->irq, max14577->irq_data); 461 462 if (max14577->dev_type == MAXIM_DEVICE_TYPE_MAX77836)
+1 -1
drivers/mfd/max77541.c
··· 152 152 if (ret) 153 153 return dev_err_probe(dev, ret, "Failed to initialize IRQ\n"); 154 154 155 - ret = device_init_wakeup(dev, true); 155 + ret = devm_device_init_wakeup(dev); 156 156 if (ret) 157 157 return dev_err_probe(dev, ret, "Unable to init wakeup\n"); 158 158
+3 -1
drivers/mfd/max77705.c
··· 131 131 if (ret) 132 132 return dev_err_probe(dev, ret, "Failed to register child devices\n"); 133 133 134 - device_init_wakeup(dev, true); 134 + ret = devm_device_init_wakeup(dev); 135 + if (ret) 136 + return dev_err_probe(dev, ret, "Failed to init wakeup\n"); 135 137 136 138 return 0; 137 139 }
+1
drivers/mfd/max8925-i2c.c
··· 201 201 struct max8925_chip *chip = i2c_get_clientdata(client); 202 202 203 203 max8925_device_exit(chip); 204 + device_init_wakeup(&client->dev, false); 204 205 i2c_unregister_device(chip->adc); 205 206 i2c_unregister_device(chip->rtc); 206 207 }
+423 -110
drivers/mfd/rohm-bd96801.c
··· 38 38 #include <linux/types.h> 39 39 40 40 #include <linux/mfd/rohm-bd96801.h> 41 + #include <linux/mfd/rohm-bd96802.h> 41 42 #include <linux/mfd/rohm-generic.h> 42 43 43 - static const struct resource regulator_errb_irqs[] = { 44 - DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "bd96801-otp-err"), 45 - DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "bd96801-dbist-err"), 46 - DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "bd96801-eep-err"), 47 - DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "bd96801-abist-err"), 48 - DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "bd96801-prstb-err"), 49 - DEFINE_RES_IRQ_NAMED(BD96801_DRMOS1_ERR_STAT, "bd96801-drmoserr1"), 50 - DEFINE_RES_IRQ_NAMED(BD96801_DRMOS2_ERR_STAT, "bd96801-drmoserr2"), 51 - DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "bd96801-slave-err"), 52 - DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "bd96801-vref-err"), 53 - DEFINE_RES_IRQ_NAMED(BD96801_TSD_ERR_STAT, "bd96801-tsd"), 54 - DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "bd96801-uvlo-err"), 55 - DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "bd96801-ovlo-err"), 56 - DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "bd96801-osc-err"), 57 - DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "bd96801-pon-err"), 58 - DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "bd96801-poff-err"), 59 - DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "bd96801-cmd-shdn-err"), 44 + struct bd968xx { 45 + const struct resource *errb_irqs; 46 + const struct resource *intb_irqs; 47 + int num_errb_irqs; 48 + int num_intb_irqs; 49 + const struct regmap_irq_chip *errb_irq_chip; 50 + const struct regmap_irq_chip *intb_irq_chip; 51 + const struct regmap_config *regmap_config; 52 + struct mfd_cell *cells; 53 + int num_cells; 54 + int unlock_reg; 55 + int unlock_val; 56 + }; 57 + 58 + static const struct resource bd96801_reg_errb_irqs[] = { 59 + DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "otp-err"), 60 + DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "dbist-err"), 61 + DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "eep-err"), 62 + DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "abist-err"), 63 + DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "prstb-err"), 64 + DEFINE_RES_IRQ_NAMED(BD96801_DRMOS1_ERR_STAT, "drmoserr1"), 65 + DEFINE_RES_IRQ_NAMED(BD96801_DRMOS2_ERR_STAT, "drmoserr2"), 66 + DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "slave-err"), 67 + DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "vref-err"), 68 + DEFINE_RES_IRQ_NAMED(BD96801_TSD_ERR_STAT, "tsd"), 69 + DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "uvlo-err"), 70 + DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "ovlo-err"), 71 + DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "osc-err"), 72 + DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "pon-err"), 73 + DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "poff-err"), 74 + DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "cmd-shdn-err"), 60 75 61 76 DEFINE_RES_IRQ_NAMED(BD96801_INT_PRSTB_WDT_ERR, "bd96801-prstb-wdt-err"), 62 77 DEFINE_RES_IRQ_NAMED(BD96801_INT_CHIP_IF_ERR, "bd96801-chip-if-err"), 63 - DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "bd96801-int-shdn-err"), 64 78 65 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "bd96801-buck1-pvin-err"), 66 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "bd96801-buck1-ovp-err"), 67 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "bd96801-buck1-uvp-err"), 68 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "bd96801-buck1-shdn-err"), 79 + DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "int-shdn-err"), 69 80 70 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "bd96801-buck2-pvin-err"), 71 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "bd96801-buck2-ovp-err"), 72 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "bd96801-buck2-uvp-err"), 73 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "bd96801-buck2-shdn-err"), 81 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "buck1-pvin-err"), 82 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "buck1-ovp-err"), 83 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "buck1-uvp-err"), 84 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "buck1-shdn-err"), 74 85 75 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "bd96801-buck3-pvin-err"), 76 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "bd96801-buck3-ovp-err"), 77 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "bd96801-buck3-uvp-err"), 78 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "bd96801-buck3-shdn-err"), 86 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "buck2-pvin-err"), 87 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "buck2-ovp-err"), 88 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "buck2-uvp-err"), 89 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "buck2-shdn-err"), 79 90 80 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "bd96801-buck4-pvin-err"), 81 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "bd96801-buck4-ovp-err"), 82 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "bd96801-buck4-uvp-err"), 83 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "bd96801-buck4-shdn-err"), 91 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "buck3-pvin-err"), 92 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "buck3-ovp-err"), 93 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "buck3-uvp-err"), 94 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "buck3-shdn-err"), 84 95 85 - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "bd96801-ldo5-pvin-err"), 86 - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "bd96801-ldo5-ovp-err"), 87 - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "bd96801-ldo5-uvp-err"), 88 - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "bd96801-ldo5-shdn-err"), 96 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "buck4-pvin-err"), 97 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "buck4-ovp-err"), 98 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "buck4-uvp-err"), 99 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "buck4-shdn-err"), 89 100 90 - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "bd96801-ldo6-pvin-err"), 91 - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "bd96801-ldo6-ovp-err"), 92 - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "bd96801-ldo6-uvp-err"), 93 - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "bd96801-ldo6-shdn-err"), 101 + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "ldo5-pvin-err"), 102 + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "ldo5-ovp-err"), 103 + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "ldo5-uvp-err"), 104 + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "ldo5-shdn-err"), 94 105 95 - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "bd96801-ldo7-pvin-err"), 96 - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "bd96801-ldo7-ovp-err"), 97 - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "bd96801-ldo7-uvp-err"), 98 - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "bd96801-ldo7-shdn-err"), 106 + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "ldo6-pvin-err"), 107 + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "ldo6-ovp-err"), 108 + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "ldo6-uvp-err"), 109 + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "ldo6-shdn-err"), 110 + 111 + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "ldo7-pvin-err"), 112 + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "ldo7-ovp-err"), 113 + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "ldo7-uvp-err"), 114 + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "ldo7-shdn-err"), 99 115 }; 100 116 101 - static const struct resource regulator_intb_irqs[] = { 102 - DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"), 117 + static const struct resource bd96802_reg_errb_irqs[] = { 118 + DEFINE_RES_IRQ_NAMED(BD96802_OTP_ERR_STAT, "otp-err"), 119 + DEFINE_RES_IRQ_NAMED(BD96802_DBIST_ERR_STAT, "dbist-err"), 120 + DEFINE_RES_IRQ_NAMED(BD96802_EEP_ERR_STAT, "eep-err"), 121 + DEFINE_RES_IRQ_NAMED(BD96802_ABIST_ERR_STAT, "abist-err"), 122 + DEFINE_RES_IRQ_NAMED(BD96802_PRSTB_ERR_STAT, "prstb-err"), 123 + DEFINE_RES_IRQ_NAMED(BD96802_DRMOS1_ERR_STAT, "drmoserr1"), 124 + DEFINE_RES_IRQ_NAMED(BD96802_DRMOS1_ERR_STAT, "drmoserr2"), 125 + DEFINE_RES_IRQ_NAMED(BD96802_SLAVE_ERR_STAT, "slave-err"), 126 + DEFINE_RES_IRQ_NAMED(BD96802_VREF_ERR_STAT, "vref-err"), 127 + DEFINE_RES_IRQ_NAMED(BD96802_TSD_ERR_STAT, "tsd"), 128 + DEFINE_RES_IRQ_NAMED(BD96802_UVLO_ERR_STAT, "uvlo-err"), 129 + DEFINE_RES_IRQ_NAMED(BD96802_OVLO_ERR_STAT, "ovlo-err"), 130 + DEFINE_RES_IRQ_NAMED(BD96802_OSC_ERR_STAT, "osc-err"), 131 + DEFINE_RES_IRQ_NAMED(BD96802_PON_ERR_STAT, "pon-err"), 132 + DEFINE_RES_IRQ_NAMED(BD96802_POFF_ERR_STAT, "poff-err"), 133 + DEFINE_RES_IRQ_NAMED(BD96802_CMD_SHDN_ERR_STAT, "cmd-shdn-err"), 134 + DEFINE_RES_IRQ_NAMED(BD96802_INT_SHDN_ERR_STAT, "int-shdn-err"), 103 135 104 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "bd96801-buck1-overcurr-h"), 105 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "bd96801-buck1-overcurr-l"), 106 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "bd96801-buck1-overcurr-n"), 107 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "bd96801-buck1-overvolt"), 108 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "bd96801-buck1-undervolt"), 109 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "bd96801-buck1-thermal"), 136 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_PVIN_ERR_STAT, "buck1-pvin-err"), 137 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OVP_ERR_STAT, "buck1-ovp-err"), 138 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_UVP_ERR_STAT, "buck1-uvp-err"), 139 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_SHDN_ERR_STAT, "buck1-shdn-err"), 110 140 111 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "bd96801-buck2-overcurr-h"), 112 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "bd96801-buck2-overcurr-l"), 113 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "bd96801-buck2-overcurr-n"), 114 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "bd96801-buck2-overvolt"), 115 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "bd96801-buck2-undervolt"), 116 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "bd96801-buck2-thermal"), 141 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_PVIN_ERR_STAT, "buck2-pvin-err"), 142 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OVP_ERR_STAT, "buck2-ovp-err"), 143 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_UVP_ERR_STAT, "buck2-uvp-err"), 144 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_SHDN_ERR_STAT, "buck2-shdn-err"), 145 + }; 117 146 118 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "bd96801-buck3-overcurr-h"), 119 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "bd96801-buck3-overcurr-l"), 120 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "bd96801-buck3-overcurr-n"), 121 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "bd96801-buck3-overvolt"), 122 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "bd96801-buck3-undervolt"), 123 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "bd96801-buck3-thermal"), 147 + static const struct resource bd96801_reg_intb_irqs[] = { 148 + DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "core-thermal"), 124 149 125 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "bd96801-buck4-overcurr-h"), 126 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "bd96801-buck4-overcurr-l"), 127 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "bd96801-buck4-overcurr-n"), 128 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "bd96801-buck4-overvolt"), 129 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "bd96801-buck4-undervolt"), 130 - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "bd96801-buck4-thermal"), 150 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "buck1-overcurr-h"), 151 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "buck1-overcurr-l"), 152 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "buck1-overcurr-n"), 153 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "buck1-overvolt"), 154 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "buck1-undervolt"), 155 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "buck1-thermal"), 131 156 132 - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "bd96801-ldo5-overcurr"), 133 - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "bd96801-ldo5-overvolt"), 134 - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "bd96801-ldo5-undervolt"), 157 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "buck2-overcurr-h"), 158 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "buck2-overcurr-l"), 159 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "buck2-overcurr-n"), 160 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "buck2-overvolt"), 161 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "buck2-undervolt"), 162 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "buck2-thermal"), 135 163 136 - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "bd96801-ldo6-overcurr"), 137 - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "bd96801-ldo6-overvolt"), 138 - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "bd96801-ldo6-undervolt"), 164 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "buck3-overcurr-h"), 165 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "buck3-overcurr-l"), 166 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "buck3-overcurr-n"), 167 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "buck3-overvolt"), 168 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "buck3-undervolt"), 169 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "buck3-thermal"), 139 170 140 - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OCPH_STAT, "bd96801-ldo7-overcurr"), 141 - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVD_STAT, "bd96801-ldo7-overvolt"), 142 - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"), 171 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "buck4-overcurr-h"), 172 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "buck4-overcurr-l"), 173 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "buck4-overcurr-n"), 174 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "buck4-overvolt"), 175 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "buck4-undervolt"), 176 + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "buck4-thermal"), 177 + 178 + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "ldo5-overcurr"), 179 + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "ldo5-overvolt"), 180 + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "ldo5-undervolt"), 181 + 182 + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "ldo6-overcurr"), 183 + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "ldo6-overvolt"), 184 + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "ldo6-undervolt"), 185 + 186 + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OCPH_STAT, "ldo7-overcurr"), 187 + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVD_STAT, "ldo7-overvolt"), 188 + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "ldo7-undervolt"), 189 + }; 190 + 191 + static const struct resource bd96802_reg_intb_irqs[] = { 192 + DEFINE_RES_IRQ_NAMED(BD96802_TW_STAT, "core-thermal"), 193 + 194 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPH_STAT, "buck1-overcurr-h"), 195 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPL_STAT, "buck1-overcurr-l"), 196 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPN_STAT, "buck1-overcurr-n"), 197 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OVD_STAT, "buck1-overvolt"), 198 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_UVD_STAT, "buck1-undervolt"), 199 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_TW_CH_STAT, "buck1-thermal"), 200 + 201 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPH_STAT, "buck2-overcurr-h"), 202 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPL_STAT, "buck2-overcurr-l"), 203 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPN_STAT, "buck2-overcurr-n"), 204 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OVD_STAT, "buck2-overvolt"), 205 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_UVD_STAT, "buck2-undervolt"), 206 + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_TW_CH_STAT, "buck2-thermal"), 143 207 }; 144 208 145 209 enum { ··· 214 150 static struct mfd_cell bd96801_cells[] = { 215 151 [WDG_CELL] = { .name = "bd96801-wdt", }, 216 152 [REGULATOR_CELL] = { .name = "bd96801-regulator", }, 153 + }; 154 + 155 + static struct mfd_cell bd96802_cells[] = { 156 + [WDG_CELL] = { .name = "bd96801-wdt", }, 157 + [REGULATOR_CELL] = { .name = "bd96802-regulator", }, 158 + }; 159 + static struct mfd_cell bd96805_cells[] = { 160 + [WDG_CELL] = { .name = "bd96801-wdt", }, 161 + [REGULATOR_CELL] = { .name = "bd96805-regulator", }, 162 + }; 163 + 164 + static struct mfd_cell bd96806_cells[] = { 165 + [WDG_CELL] = { .name = "bd96806-wdt", }, 166 + [REGULATOR_CELL] = { .name = "bd96806-regulator", }, 217 167 }; 218 168 219 169 static const struct regmap_range bd96801_volatile_ranges[] = { ··· 247 169 regmap_reg_range(BD96801_LDO5_VOL_LVL_REG, BD96801_LDO7_VOL_LVL_REG), 248 170 }; 249 171 250 - static const struct regmap_access_table volatile_regs = { 172 + static const struct regmap_range bd96802_volatile_ranges[] = { 173 + /* Status regs */ 174 + regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT), 175 + regmap_reg_range(BD96801_REG_WD_ASK, BD96801_REG_WD_ASK), 176 + regmap_reg_range(BD96801_REG_WD_STATUS, BD96801_REG_WD_STATUS), 177 + regmap_reg_range(BD96801_REG_PMIC_STATE, BD96801_REG_INT_BUCK2_ERRB), 178 + regmap_reg_range(BD96801_REG_INT_SYS_INTB, BD96801_REG_INT_BUCK2_INTB), 179 + /* Registers which do not update value unless PMIC is in STBY */ 180 + regmap_reg_range(BD96801_REG_SSCG_CTRL, BD96801_REG_SHD_INTB), 181 + regmap_reg_range(BD96801_REG_BUCK_OVP, BD96801_REG_BOOT_OVERTIME), 182 + }; 183 + 184 + static const struct regmap_access_table bd96801_volatile_regs = { 251 185 .yes_ranges = bd96801_volatile_ranges, 252 186 .n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges), 187 + }; 188 + 189 + static const struct regmap_access_table bd96802_volatile_regs = { 190 + .yes_ranges = bd96802_volatile_ranges, 191 + .n_yes_ranges = ARRAY_SIZE(bd96802_volatile_ranges), 253 192 }; 254 193 255 194 /* ··· 283 188 static unsigned int bit6_offsets[] = {8}; /* LDO 6 stat */ 284 189 static unsigned int bit7_offsets[] = {9}; /* LDO 7 stat */ 285 190 286 - static const struct regmap_irq_sub_irq_map errb_sub_irq_offsets[] = { 191 + static const struct regmap_irq_sub_irq_map bd96801_errb_sub_irq_offsets[] = { 287 192 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 288 193 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 289 194 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), ··· 292 197 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 293 198 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 294 199 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 200 + }; 201 + 202 + static const struct regmap_irq_sub_irq_map bd96802_errb_sub_irq_offsets[] = { 203 + REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 204 + REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 205 + REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 295 206 }; 296 207 297 208 static const struct regmap_irq bd96801_errb_irqs[] = { ··· 360 259 REGMAP_IRQ_REG(BD96801_LDO7_SHDN_ERR_STAT, 9, BD96801_OUT_SHDN_ERR_MASK), 361 260 }; 362 261 262 + static const struct regmap_irq bd96802_errb_irqs[] = { 263 + /* Reg 0x52 Fatal ERRB1 */ 264 + REGMAP_IRQ_REG(BD96802_OTP_ERR_STAT, 0, BD96801_OTP_ERR_MASK), 265 + REGMAP_IRQ_REG(BD96802_DBIST_ERR_STAT, 0, BD96801_DBIST_ERR_MASK), 266 + REGMAP_IRQ_REG(BD96802_EEP_ERR_STAT, 0, BD96801_EEP_ERR_MASK), 267 + REGMAP_IRQ_REG(BD96802_ABIST_ERR_STAT, 0, BD96801_ABIST_ERR_MASK), 268 + REGMAP_IRQ_REG(BD96802_PRSTB_ERR_STAT, 0, BD96801_PRSTB_ERR_MASK), 269 + REGMAP_IRQ_REG(BD96802_DRMOS1_ERR_STAT, 0, BD96801_DRMOS1_ERR_MASK), 270 + REGMAP_IRQ_REG(BD96802_DRMOS2_ERR_STAT, 0, BD96801_DRMOS2_ERR_MASK), 271 + REGMAP_IRQ_REG(BD96802_SLAVE_ERR_STAT, 0, BD96801_SLAVE_ERR_MASK), 272 + /* 0x53 Fatal ERRB2 */ 273 + REGMAP_IRQ_REG(BD96802_VREF_ERR_STAT, 1, BD96801_VREF_ERR_MASK), 274 + REGMAP_IRQ_REG(BD96802_TSD_ERR_STAT, 1, BD96801_TSD_ERR_MASK), 275 + REGMAP_IRQ_REG(BD96802_UVLO_ERR_STAT, 1, BD96801_UVLO_ERR_MASK), 276 + REGMAP_IRQ_REG(BD96802_OVLO_ERR_STAT, 1, BD96801_OVLO_ERR_MASK), 277 + REGMAP_IRQ_REG(BD96802_OSC_ERR_STAT, 1, BD96801_OSC_ERR_MASK), 278 + REGMAP_IRQ_REG(BD96802_PON_ERR_STAT, 1, BD96801_PON_ERR_MASK), 279 + REGMAP_IRQ_REG(BD96802_POFF_ERR_STAT, 1, BD96801_POFF_ERR_MASK), 280 + REGMAP_IRQ_REG(BD96802_CMD_SHDN_ERR_STAT, 1, BD96801_CMD_SHDN_ERR_MASK), 281 + /* 0x54 Fatal INTB shadowed to ERRB */ 282 + REGMAP_IRQ_REG(BD96802_INT_SHDN_ERR_STAT, 2, BD96801_INT_SHDN_ERR_MASK), 283 + /* Reg 0x55 BUCK1 ERR IRQs */ 284 + REGMAP_IRQ_REG(BD96802_BUCK1_PVIN_ERR_STAT, 3, BD96801_OUT_PVIN_ERR_MASK), 285 + REGMAP_IRQ_REG(BD96802_BUCK1_OVP_ERR_STAT, 3, BD96801_OUT_OVP_ERR_MASK), 286 + REGMAP_IRQ_REG(BD96802_BUCK1_UVP_ERR_STAT, 3, BD96801_OUT_UVP_ERR_MASK), 287 + REGMAP_IRQ_REG(BD96802_BUCK1_SHDN_ERR_STAT, 3, BD96801_OUT_SHDN_ERR_MASK), 288 + /* Reg 0x56 BUCK2 ERR IRQs */ 289 + REGMAP_IRQ_REG(BD96802_BUCK2_PVIN_ERR_STAT, 4, BD96801_OUT_PVIN_ERR_MASK), 290 + REGMAP_IRQ_REG(BD96802_BUCK2_OVP_ERR_STAT, 4, BD96801_OUT_OVP_ERR_MASK), 291 + REGMAP_IRQ_REG(BD96802_BUCK2_UVP_ERR_STAT, 4, BD96801_OUT_UVP_ERR_MASK), 292 + REGMAP_IRQ_REG(BD96802_BUCK2_SHDN_ERR_STAT, 4, BD96801_OUT_SHDN_ERR_MASK), 293 + }; 294 + 363 295 static const struct regmap_irq bd96801_intb_irqs[] = { 364 296 /* STATUS SYSTEM INTB */ 365 297 REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK), ··· 441 307 REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK), 442 308 }; 443 309 310 + static const struct regmap_irq bd96802_intb_irqs[] = { 311 + /* STATUS SYSTEM INTB */ 312 + REGMAP_IRQ_REG(BD96802_TW_STAT, 0, BD96801_TW_STAT_MASK), 313 + REGMAP_IRQ_REG(BD96802_WDT_ERR_STAT, 0, BD96801_WDT_ERR_STAT_MASK), 314 + REGMAP_IRQ_REG(BD96802_I2C_ERR_STAT, 0, BD96801_I2C_ERR_STAT_MASK), 315 + REGMAP_IRQ_REG(BD96802_CHIP_IF_ERR_STAT, 0, BD96801_CHIP_IF_ERR_STAT_MASK), 316 + /* STATUS BUCK1 INTB */ 317 + REGMAP_IRQ_REG(BD96802_BUCK1_OCPH_STAT, 1, BD96801_BUCK_OCPH_STAT_MASK), 318 + REGMAP_IRQ_REG(BD96802_BUCK1_OCPL_STAT, 1, BD96801_BUCK_OCPL_STAT_MASK), 319 + REGMAP_IRQ_REG(BD96802_BUCK1_OCPN_STAT, 1, BD96801_BUCK_OCPN_STAT_MASK), 320 + REGMAP_IRQ_REG(BD96802_BUCK1_OVD_STAT, 1, BD96801_BUCK_OVD_STAT_MASK), 321 + REGMAP_IRQ_REG(BD96802_BUCK1_UVD_STAT, 1, BD96801_BUCK_UVD_STAT_MASK), 322 + REGMAP_IRQ_REG(BD96802_BUCK1_TW_CH_STAT, 1, BD96801_BUCK_TW_CH_STAT_MASK), 323 + /* BUCK 2 INTB */ 324 + REGMAP_IRQ_REG(BD96802_BUCK2_OCPH_STAT, 2, BD96801_BUCK_OCPH_STAT_MASK), 325 + REGMAP_IRQ_REG(BD96802_BUCK2_OCPL_STAT, 2, BD96801_BUCK_OCPL_STAT_MASK), 326 + REGMAP_IRQ_REG(BD96802_BUCK2_OCPN_STAT, 2, BD96801_BUCK_OCPN_STAT_MASK), 327 + REGMAP_IRQ_REG(BD96802_BUCK2_OVD_STAT, 2, BD96801_BUCK_OVD_STAT_MASK), 328 + REGMAP_IRQ_REG(BD96802_BUCK2_UVD_STAT, 2, BD96801_BUCK_UVD_STAT_MASK), 329 + REGMAP_IRQ_REG(BD96802_BUCK2_TW_CH_STAT, 2, BD96801_BUCK_TW_CH_STAT_MASK), 330 + }; 331 + 332 + /* 333 + * The IRQ stuff is a bit hairy. The BD96801 / BD96802 provide two physical 334 + * IRQ lines called INTB and ERRB. They share the same main status register. 335 + * 336 + * For ERRB, mapping from main status to sub-status is such that the 337 + * 'global' faults are mapped to first 3 sub-status registers - and indicated 338 + * by the first bit[0] in main status reg. 339 + * 340 + * Rest of the status registers are for indicating stuff for individual 341 + * regulators, 1 sub register / regulator and 1 main status register bit / 342 + * regulator, starting from bit[1]. 343 + * 344 + * Eg, regulator specific stuff has 1 to 1 mapping from main-status to sub 345 + * registers but 'global' ERRB IRQs require mapping from main status bit[0] to 346 + * 3 status registers. 347 + * 348 + * Furthermore, the BD96801 has 7 regulators where the BD96802 has only 2. 349 + * 350 + * INTB has only 1 sub status register for 'global' events and then own sub 351 + * status register for each of the regulators. So, for INTB we have direct 352 + * 1 to 1 mapping - BD96801 just having 5 register and 5 main status bits 353 + * more than the BD96802. 354 + * 355 + * Sharing the main status bits could be a problem if we had both INTB and 356 + * ERRB IRQs asserted but for different sub-status offsets. This might lead 357 + * IRQ controller code to go read a sub status register which indicates no 358 + * active IRQs. I assume this occurring repeteadly might lead the IRQ to be 359 + * disabled by core as a result of repeteadly returned IRQ_NONEs. 360 + * 361 + * I don't consider this as a fatal problem for now because: 362 + * a) Having ERRB asserted leads to PMIC fault state which will kill 363 + * the SoC powered by the PMIC. (So, relevant only for potential 364 + * case of not powering the processor with this PMIC). 365 + * b) Having ERRB set without having respective INTB is unlikely 366 + * (haven't actually verified this). 367 + * 368 + * So, let's proceed with main status enabled for both INTB and ERRB. We can 369 + * later disable main-status usage on systems where this ever proves to be 370 + * a problem. 371 + */ 372 + 444 373 static const struct regmap_irq_chip bd96801_irq_chip_errb = { 445 374 .name = "bd96801-irq-errb", 446 375 .domain_suffix = "errb", ··· 517 320 .init_ack_masked = true, 518 321 .num_regs = 10, 519 322 .irq_reg_stride = 1, 520 - .sub_reg_offsets = &errb_sub_irq_offsets[0], 323 + .sub_reg_offsets = &bd96801_errb_sub_irq_offsets[0], 324 + }; 325 + 326 + static const struct regmap_irq_chip bd96802_irq_chip_errb = { 327 + .name = "bd96802-irq-errb", 328 + .domain_suffix = "errb", 329 + .main_status = BD96801_REG_INT_MAIN, 330 + .num_main_regs = 1, 331 + .irqs = &bd96802_errb_irqs[0], 332 + .num_irqs = ARRAY_SIZE(bd96802_errb_irqs), 333 + .status_base = BD96801_REG_INT_SYS_ERRB1, 334 + .mask_base = BD96801_REG_MASK_SYS_ERRB, 335 + .ack_base = BD96801_REG_INT_SYS_ERRB1, 336 + .init_ack_masked = true, 337 + .num_regs = 5, 338 + .irq_reg_stride = 1, 339 + .sub_reg_offsets = &bd96802_errb_sub_irq_offsets[0], 521 340 }; 522 341 523 342 static const struct regmap_irq_chip bd96801_irq_chip_intb = { ··· 551 338 .irq_reg_stride = 1, 552 339 }; 553 340 341 + static const struct regmap_irq_chip bd96802_irq_chip_intb = { 342 + .name = "bd96802-irq-intb", 343 + .domain_suffix = "intb", 344 + .main_status = BD96801_REG_INT_MAIN, 345 + .num_main_regs = 1, 346 + .irqs = &bd96802_intb_irqs[0], 347 + .num_irqs = ARRAY_SIZE(bd96802_intb_irqs), 348 + .status_base = BD96801_REG_INT_SYS_INTB, 349 + .mask_base = BD96801_REG_MASK_SYS_INTB, 350 + .ack_base = BD96801_REG_INT_SYS_INTB, 351 + .init_ack_masked = true, 352 + .num_regs = 3, 353 + .irq_reg_stride = 1, 354 + }; 355 + 554 356 static const struct regmap_config bd96801_regmap_config = { 555 357 .reg_bits = 8, 556 358 .val_bits = 8, 557 - .volatile_table = &volatile_regs, 359 + .volatile_table = &bd96801_volatile_regs, 558 360 .cache_type = REGCACHE_MAPLE, 361 + }; 362 + 363 + static const struct regmap_config bd96802_regmap_config = { 364 + .reg_bits = 8, 365 + .val_bits = 8, 366 + .volatile_table = &bd96802_volatile_regs, 367 + .cache_type = REGCACHE_MAPLE, 368 + }; 369 + 370 + static const struct bd968xx bd96801_data = { 371 + .errb_irqs = bd96801_reg_errb_irqs, 372 + .intb_irqs = bd96801_reg_intb_irqs, 373 + .num_errb_irqs = ARRAY_SIZE(bd96801_reg_errb_irqs), 374 + .num_intb_irqs = ARRAY_SIZE(bd96801_reg_intb_irqs), 375 + .errb_irq_chip = &bd96801_irq_chip_errb, 376 + .intb_irq_chip = &bd96801_irq_chip_intb, 377 + .regmap_config = &bd96801_regmap_config, 378 + .cells = bd96801_cells, 379 + .num_cells = ARRAY_SIZE(bd96801_cells), 380 + .unlock_reg = BD96801_LOCK_REG, 381 + .unlock_val = BD96801_UNLOCK, 382 + }; 383 + 384 + static const struct bd968xx bd96802_data = { 385 + .errb_irqs = bd96802_reg_errb_irqs, 386 + .intb_irqs = bd96802_reg_intb_irqs, 387 + .num_errb_irqs = ARRAY_SIZE(bd96802_reg_errb_irqs), 388 + .num_intb_irqs = ARRAY_SIZE(bd96802_reg_intb_irqs), 389 + .errb_irq_chip = &bd96802_irq_chip_errb, 390 + .intb_irq_chip = &bd96802_irq_chip_intb, 391 + .regmap_config = &bd96802_regmap_config, 392 + .cells = bd96802_cells, 393 + .num_cells = ARRAY_SIZE(bd96802_cells), 394 + .unlock_reg = BD96801_LOCK_REG, 395 + .unlock_val = BD96801_UNLOCK, 396 + }; 397 + 398 + static const struct bd968xx bd96805_data = { 399 + .errb_irqs = bd96801_reg_errb_irqs, 400 + .intb_irqs = bd96801_reg_intb_irqs, 401 + .num_errb_irqs = ARRAY_SIZE(bd96801_reg_errb_irqs), 402 + .num_intb_irqs = ARRAY_SIZE(bd96801_reg_intb_irqs), 403 + .errb_irq_chip = &bd96801_irq_chip_errb, 404 + .intb_irq_chip = &bd96801_irq_chip_intb, 405 + .regmap_config = &bd96801_regmap_config, 406 + .cells = bd96805_cells, 407 + .num_cells = ARRAY_SIZE(bd96805_cells), 408 + .unlock_reg = BD96801_LOCK_REG, 409 + .unlock_val = BD96801_UNLOCK, 410 + }; 411 + 412 + static struct bd968xx bd96806_data = { 413 + .errb_irqs = bd96802_reg_errb_irqs, 414 + .intb_irqs = bd96802_reg_intb_irqs, 415 + .num_errb_irqs = ARRAY_SIZE(bd96802_reg_errb_irqs), 416 + .num_intb_irqs = ARRAY_SIZE(bd96802_reg_intb_irqs), 417 + .errb_irq_chip = &bd96802_irq_chip_errb, 418 + .intb_irq_chip = &bd96802_irq_chip_intb, 419 + .regmap_config = &bd96802_regmap_config, 420 + .cells = bd96806_cells, 421 + .num_cells = ARRAY_SIZE(bd96806_cells), 422 + .unlock_reg = BD96801_LOCK_REG, 423 + .unlock_val = BD96801_UNLOCK, 559 424 }; 560 425 561 426 static int bd96801_i2c_probe(struct i2c_client *i2c) 562 427 { 563 428 struct regmap_irq_chip_data *intb_irq_data, *errb_irq_data; 564 429 struct irq_domain *intb_domain, *errb_domain; 430 + const struct bd968xx *ddata; 565 431 const struct fwnode_handle *fwnode; 566 432 struct resource *regulator_res; 567 433 struct resource wdg_irq; 568 434 struct regmap *regmap; 569 - int intb_irq, errb_irq, num_intb, num_errb = 0; 435 + int intb_irq, errb_irq, num_errb = 0; 570 436 int num_regu_irqs, wdg_irq_no; 437 + unsigned int chip_type; 571 438 int i, ret; 439 + 440 + chip_type = (unsigned int)(uintptr_t)device_get_match_data(&i2c->dev); 441 + switch (chip_type) { 442 + case ROHM_CHIP_TYPE_BD96801: 443 + ddata = &bd96801_data; 444 + break; 445 + case ROHM_CHIP_TYPE_BD96802: 446 + ddata = &bd96802_data; 447 + break; 448 + case ROHM_CHIP_TYPE_BD96805: 449 + ddata = &bd96805_data; 450 + break; 451 + case ROHM_CHIP_TYPE_BD96806: 452 + ddata = &bd96806_data; 453 + break; 454 + default: 455 + dev_err(&i2c->dev, "Unknown IC\n"); 456 + return -EINVAL; 457 + } 572 458 573 459 fwnode = dev_fwnode(&i2c->dev); 574 460 if (!fwnode) ··· 677 365 if (intb_irq < 0) 678 366 return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n"); 679 367 680 - num_intb = ARRAY_SIZE(regulator_intb_irqs); 681 - 682 368 /* ERRB may be omitted if processor is powered by the PMIC */ 683 369 errb_irq = fwnode_irq_get_byname(fwnode, "errb"); 684 - if (errb_irq < 0) 685 - errb_irq = 0; 370 + if (errb_irq == -EPROBE_DEFER) 371 + return errb_irq; 686 372 687 - if (errb_irq) 688 - num_errb = ARRAY_SIZE(regulator_errb_irqs); 373 + if (errb_irq > 0) 374 + num_errb = ddata->num_errb_irqs; 689 375 690 - num_regu_irqs = num_intb + num_errb; 376 + num_regu_irqs = ddata->num_intb_irqs + num_errb; 691 377 692 378 regulator_res = devm_kcalloc(&i2c->dev, num_regu_irqs, 693 379 sizeof(*regulator_res), GFP_KERNEL); 694 380 if (!regulator_res) 695 381 return -ENOMEM; 696 382 697 - regmap = devm_regmap_init_i2c(i2c, &bd96801_regmap_config); 383 + regmap = devm_regmap_init_i2c(i2c, ddata->regmap_config); 698 384 if (IS_ERR(regmap)) 699 385 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 700 386 "Regmap initialization failed\n"); 701 387 702 - ret = regmap_write(regmap, BD96801_LOCK_REG, BD96801_UNLOCK); 388 + ret = regmap_write(regmap, ddata->unlock_reg, ddata->unlock_val); 703 389 if (ret) 704 390 return dev_err_probe(&i2c->dev, ret, "Failed to unlock PMIC\n"); 705 391 706 392 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, intb_irq, 707 - IRQF_ONESHOT, 0, &bd96801_irq_chip_intb, 393 + IRQF_ONESHOT, 0, ddata->intb_irq_chip, 708 394 &intb_irq_data); 709 395 if (ret) 710 396 return dev_err_probe(&i2c->dev, ret, "Failed to add INTB IRQ chip\n"); ··· 714 404 * has two domains so we do IRQ mapping here and provide the 715 405 * already mapped IRQ numbers to sub-devices. 716 406 */ 717 - for (i = 0; i < num_intb; i++) { 407 + for (i = 0; i < ddata->num_intb_irqs; i++) { 718 408 struct resource *res = &regulator_res[i]; 719 409 720 - *res = regulator_intb_irqs[i]; 410 + *res = ddata->intb_irqs[i]; 721 411 res->start = res->end = irq_create_mapping(intb_domain, 722 412 res->start); 723 413 } 724 414 725 415 wdg_irq_no = irq_create_mapping(intb_domain, BD96801_WDT_ERR_STAT); 726 416 wdg_irq = DEFINE_RES_IRQ_NAMED(wdg_irq_no, "bd96801-wdg"); 727 - bd96801_cells[WDG_CELL].resources = &wdg_irq; 728 - bd96801_cells[WDG_CELL].num_resources = 1; 417 + 418 + ddata->cells[WDG_CELL].resources = &wdg_irq; 419 + ddata->cells[WDG_CELL].num_resources = 1; 729 420 730 421 if (!num_errb) 731 422 goto skip_errb; 732 423 733 424 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, errb_irq, IRQF_ONESHOT, 734 - 0, &bd96801_irq_chip_errb, &errb_irq_data); 425 + 0, ddata->errb_irq_chip, &errb_irq_data); 735 426 if (ret) 736 427 return dev_err_probe(&i2c->dev, ret, 737 428 "Failed to add ERRB IRQ chip\n"); ··· 740 429 errb_domain = regmap_irq_get_domain(errb_irq_data); 741 430 742 431 for (i = 0; i < num_errb; i++) { 743 - struct resource *res = &regulator_res[num_intb + i]; 432 + struct resource *res = &regulator_res[ddata->num_intb_irqs + i]; 744 433 745 - *res = regulator_errb_irqs[i]; 434 + *res = ddata->errb_irqs[i]; 746 435 res->start = res->end = irq_create_mapping(errb_domain, res->start); 747 436 } 748 437 749 438 skip_errb: 750 - bd96801_cells[REGULATOR_CELL].resources = regulator_res; 751 - bd96801_cells[REGULATOR_CELL].num_resources = num_regu_irqs; 752 - 753 - ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, bd96801_cells, 754 - ARRAY_SIZE(bd96801_cells), NULL, 0, NULL); 439 + ddata->cells[REGULATOR_CELL].resources = regulator_res; 440 + ddata->cells[REGULATOR_CELL].num_resources = num_regu_irqs; 441 + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, ddata->cells, 442 + ddata->num_cells, NULL, 0, NULL); 755 443 if (ret) 756 444 dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); 757 445 ··· 758 448 } 759 449 760 450 static const struct of_device_id bd96801_of_match[] = { 761 - { .compatible = "rohm,bd96801", }, 451 + { .compatible = "rohm,bd96801", .data = (void *)ROHM_CHIP_TYPE_BD96801 }, 452 + { .compatible = "rohm,bd96802", .data = (void *)ROHM_CHIP_TYPE_BD96802 }, 453 + { .compatible = "rohm,bd96805", .data = (void *)ROHM_CHIP_TYPE_BD96805 }, 454 + { .compatible = "rohm,bd96806", .data = (void *)ROHM_CHIP_TYPE_BD96806 }, 762 455 { } 763 456 }; 764 457 MODULE_DEVICE_TABLE(of, bd96801_of_match); ··· 789 476 module_exit(bd96801_i2c_exit); 790 477 791 478 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 792 - MODULE_DESCRIPTION("ROHM BD96801 Power Management IC driver"); 479 + MODULE_DESCRIPTION("ROHM BD9680X Power Management IC driver"); 793 480 MODULE_LICENSE("GPL");
+5 -1
drivers/mfd/rt5033.c
··· 98 98 return ret; 99 99 } 100 100 101 - device_init_wakeup(rt5033->dev, rt5033->wakeup); 101 + if (rt5033->wakeup) { 102 + ret = devm_device_init_wakeup(rt5033->dev); 103 + if (ret) 104 + return dev_err_probe(rt5033->dev, ret, "Failed to init wakeup\n"); 105 + } 102 106 103 107 return 0; 104 108 }
+442
drivers/mfd/sec-acpm.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright 2020 Google Inc 4 + * Copyright 2025 Linaro Ltd. 5 + * 6 + * Samsung S2MPG1x ACPM driver 7 + */ 8 + 9 + #include <linux/array_size.h> 10 + #include <linux/bitops.h> 11 + #include <linux/device.h> 12 + #include <linux/firmware/samsung/exynos-acpm-protocol.h> 13 + #include <linux/mfd/samsung/core.h> 14 + #include <linux/mfd/samsung/rtc.h> 15 + #include <linux/mfd/samsung/s2mpg10.h> 16 + #include <linux/mod_devicetable.h> 17 + #include <linux/module.h> 18 + #include <linux/of.h> 19 + #include <linux/platform_device.h> 20 + #include <linux/pm.h> 21 + #include <linux/property.h> 22 + #include <linux/regmap.h> 23 + #include "sec-core.h" 24 + 25 + #define ACPM_ADDR_BITS 8 26 + #define ACPM_MAX_BULK_DATA 8 27 + 28 + struct sec_pmic_acpm_platform_data { 29 + int device_type; 30 + 31 + unsigned int acpm_chan_id; 32 + u8 speedy_channel; 33 + 34 + const struct regmap_config *regmap_cfg_common; 35 + const struct regmap_config *regmap_cfg_pmic; 36 + const struct regmap_config *regmap_cfg_rtc; 37 + const struct regmap_config *regmap_cfg_meter; 38 + }; 39 + 40 + static const struct regmap_range s2mpg10_common_registers[] = { 41 + regmap_reg_range(0x00, 0x02), /* CHIP_ID_M, INT, INT_MASK */ 42 + regmap_reg_range(0x0a, 0x0c), /* Speedy control */ 43 + regmap_reg_range(0x1a, 0x2a), /* Debug */ 44 + }; 45 + 46 + static const struct regmap_range s2mpg10_common_ro_registers[] = { 47 + regmap_reg_range(0x00, 0x01), /* CHIP_ID_M, INT */ 48 + regmap_reg_range(0x28, 0x2a), /* Debug */ 49 + }; 50 + 51 + static const struct regmap_range s2mpg10_common_nonvolatile_registers[] = { 52 + regmap_reg_range(0x00, 0x00), /* CHIP_ID_M */ 53 + regmap_reg_range(0x02, 0x02), /* INT_MASK */ 54 + regmap_reg_range(0x0a, 0x0c), /* Speedy control */ 55 + }; 56 + 57 + static const struct regmap_range s2mpg10_common_precious_registers[] = { 58 + regmap_reg_range(0x01, 0x01), /* INT */ 59 + }; 60 + 61 + static const struct regmap_access_table s2mpg10_common_wr_table = { 62 + .yes_ranges = s2mpg10_common_registers, 63 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_common_registers), 64 + .no_ranges = s2mpg10_common_ro_registers, 65 + .n_no_ranges = ARRAY_SIZE(s2mpg10_common_ro_registers), 66 + }; 67 + 68 + static const struct regmap_access_table s2mpg10_common_rd_table = { 69 + .yes_ranges = s2mpg10_common_registers, 70 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_common_registers), 71 + }; 72 + 73 + static const struct regmap_access_table s2mpg10_common_volatile_table = { 74 + .no_ranges = s2mpg10_common_nonvolatile_registers, 75 + .n_no_ranges = ARRAY_SIZE(s2mpg10_common_nonvolatile_registers), 76 + }; 77 + 78 + static const struct regmap_access_table s2mpg10_common_precious_table = { 79 + .yes_ranges = s2mpg10_common_precious_registers, 80 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_common_precious_registers), 81 + }; 82 + 83 + static const struct regmap_config s2mpg10_regmap_config_common = { 84 + .name = "common", 85 + .reg_bits = ACPM_ADDR_BITS, 86 + .val_bits = 8, 87 + .max_register = S2MPG10_COMMON_SPD_DEBUG4, 88 + .wr_table = &s2mpg10_common_wr_table, 89 + .rd_table = &s2mpg10_common_rd_table, 90 + .volatile_table = &s2mpg10_common_volatile_table, 91 + .precious_table = &s2mpg10_common_precious_table, 92 + .num_reg_defaults_raw = S2MPG10_COMMON_SPD_DEBUG4 + 1, 93 + .cache_type = REGCACHE_FLAT, 94 + }; 95 + 96 + static const struct regmap_range s2mpg10_pmic_registers[] = { 97 + regmap_reg_range(0x00, 0xf6), /* All PMIC registers */ 98 + }; 99 + 100 + static const struct regmap_range s2mpg10_pmic_ro_registers[] = { 101 + regmap_reg_range(0x00, 0x05), /* INTx */ 102 + regmap_reg_range(0x0c, 0x0f), /* STATUSx PWRONSRC OFFSRC */ 103 + regmap_reg_range(0xc7, 0xc7), /* GPIO input */ 104 + }; 105 + 106 + static const struct regmap_range s2mpg10_pmic_nonvolatile_registers[] = { 107 + regmap_reg_range(0x06, 0x0b), /* INTxM */ 108 + }; 109 + 110 + static const struct regmap_range s2mpg10_pmic_precious_registers[] = { 111 + regmap_reg_range(0x00, 0x05), /* INTx */ 112 + }; 113 + 114 + static const struct regmap_access_table s2mpg10_pmic_wr_table = { 115 + .yes_ranges = s2mpg10_pmic_registers, 116 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_pmic_registers), 117 + .no_ranges = s2mpg10_pmic_ro_registers, 118 + .n_no_ranges = ARRAY_SIZE(s2mpg10_pmic_ro_registers), 119 + }; 120 + 121 + static const struct regmap_access_table s2mpg10_pmic_rd_table = { 122 + .yes_ranges = s2mpg10_pmic_registers, 123 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_pmic_registers), 124 + }; 125 + 126 + static const struct regmap_access_table s2mpg10_pmic_volatile_table = { 127 + .no_ranges = s2mpg10_pmic_nonvolatile_registers, 128 + .n_no_ranges = ARRAY_SIZE(s2mpg10_pmic_nonvolatile_registers), 129 + }; 130 + 131 + static const struct regmap_access_table s2mpg10_pmic_precious_table = { 132 + .yes_ranges = s2mpg10_pmic_precious_registers, 133 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_pmic_precious_registers), 134 + }; 135 + 136 + static const struct regmap_config s2mpg10_regmap_config_pmic = { 137 + .name = "pmic", 138 + .reg_bits = ACPM_ADDR_BITS, 139 + .val_bits = 8, 140 + .max_register = S2MPG10_PMIC_LDO_SENSE4, 141 + .wr_table = &s2mpg10_pmic_wr_table, 142 + .rd_table = &s2mpg10_pmic_rd_table, 143 + .volatile_table = &s2mpg10_pmic_volatile_table, 144 + .precious_table = &s2mpg10_pmic_precious_table, 145 + .num_reg_defaults_raw = S2MPG10_PMIC_LDO_SENSE4 + 1, 146 + .cache_type = REGCACHE_FLAT, 147 + }; 148 + 149 + static const struct regmap_range s2mpg10_rtc_registers[] = { 150 + regmap_reg_range(0x00, 0x2b), /* All RTC registers */ 151 + }; 152 + 153 + static const struct regmap_range s2mpg10_rtc_volatile_registers[] = { 154 + regmap_reg_range(0x01, 0x01), /* RTC_UPDATE */ 155 + regmap_reg_range(0x05, 0x0c), /* Time / date */ 156 + }; 157 + 158 + static const struct regmap_access_table s2mpg10_rtc_rd_table = { 159 + .yes_ranges = s2mpg10_rtc_registers, 160 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_rtc_registers), 161 + }; 162 + 163 + static const struct regmap_access_table s2mpg10_rtc_volatile_table = { 164 + .yes_ranges = s2mpg10_rtc_volatile_registers, 165 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_rtc_volatile_registers), 166 + }; 167 + 168 + static const struct regmap_config s2mpg10_regmap_config_rtc = { 169 + .name = "rtc", 170 + .reg_bits = ACPM_ADDR_BITS, 171 + .val_bits = 8, 172 + .max_register = S2MPG10_RTC_OSC_CTRL, 173 + .rd_table = &s2mpg10_rtc_rd_table, 174 + .volatile_table = &s2mpg10_rtc_volatile_table, 175 + .num_reg_defaults_raw = S2MPG10_RTC_OSC_CTRL + 1, 176 + .cache_type = REGCACHE_FLAT, 177 + }; 178 + 179 + static const struct regmap_range s2mpg10_meter_registers[] = { 180 + regmap_reg_range(0x00, 0x21), /* Meter config */ 181 + regmap_reg_range(0x40, 0x8a), /* Meter data */ 182 + regmap_reg_range(0xee, 0xee), /* Offset */ 183 + regmap_reg_range(0xf1, 0xf1), /* Trim */ 184 + }; 185 + 186 + static const struct regmap_range s2mpg10_meter_ro_registers[] = { 187 + regmap_reg_range(0x40, 0x8a), /* Meter data */ 188 + }; 189 + 190 + static const struct regmap_access_table s2mpg10_meter_wr_table = { 191 + .yes_ranges = s2mpg10_meter_registers, 192 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_meter_registers), 193 + .no_ranges = s2mpg10_meter_ro_registers, 194 + .n_no_ranges = ARRAY_SIZE(s2mpg10_meter_ro_registers), 195 + }; 196 + 197 + static const struct regmap_access_table s2mpg10_meter_rd_table = { 198 + .yes_ranges = s2mpg10_meter_registers, 199 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_meter_registers), 200 + }; 201 + 202 + static const struct regmap_access_table s2mpg10_meter_volatile_table = { 203 + .yes_ranges = s2mpg10_meter_ro_registers, 204 + .n_yes_ranges = ARRAY_SIZE(s2mpg10_meter_ro_registers), 205 + }; 206 + 207 + static const struct regmap_config s2mpg10_regmap_config_meter = { 208 + .name = "meter", 209 + .reg_bits = ACPM_ADDR_BITS, 210 + .val_bits = 8, 211 + .max_register = S2MPG10_METER_BUCK_METER_TRIM3, 212 + .wr_table = &s2mpg10_meter_wr_table, 213 + .rd_table = &s2mpg10_meter_rd_table, 214 + .volatile_table = &s2mpg10_meter_volatile_table, 215 + .num_reg_defaults_raw = S2MPG10_METER_BUCK_METER_TRIM3 + 1, 216 + .cache_type = REGCACHE_FLAT, 217 + }; 218 + 219 + struct sec_pmic_acpm_shared_bus_context { 220 + const struct acpm_handle *acpm; 221 + unsigned int acpm_chan_id; 222 + u8 speedy_channel; 223 + }; 224 + 225 + enum sec_pmic_acpm_accesstype { 226 + SEC_PMIC_ACPM_ACCESSTYPE_COMMON = 0x00, 227 + SEC_PMIC_ACPM_ACCESSTYPE_PMIC = 0x01, 228 + SEC_PMIC_ACPM_ACCESSTYPE_RTC = 0x02, 229 + SEC_PMIC_ACPM_ACCESSTYPE_METER = 0x0a, 230 + SEC_PMIC_ACPM_ACCESSTYPE_WLWP = 0x0b, 231 + SEC_PMIC_ACPM_ACCESSTYPE_TRIM = 0x0f, 232 + }; 233 + 234 + struct sec_pmic_acpm_bus_context { 235 + struct sec_pmic_acpm_shared_bus_context *shared; 236 + enum sec_pmic_acpm_accesstype type; 237 + }; 238 + 239 + static int sec_pmic_acpm_bus_write(void *context, const void *data, 240 + size_t count) 241 + { 242 + struct sec_pmic_acpm_bus_context *ctx = context; 243 + const struct acpm_handle *acpm = ctx->shared->acpm; 244 + const struct acpm_pmic_ops *pmic_ops = &acpm->ops.pmic_ops; 245 + size_t val_count = count - BITS_TO_BYTES(ACPM_ADDR_BITS); 246 + const u8 *d = data; 247 + const u8 *vals = &d[BITS_TO_BYTES(ACPM_ADDR_BITS)]; 248 + u8 reg; 249 + 250 + if (val_count < 1 || val_count > ACPM_MAX_BULK_DATA) 251 + return -EINVAL; 252 + 253 + reg = d[0]; 254 + 255 + return pmic_ops->bulk_write(acpm, ctx->shared->acpm_chan_id, ctx->type, reg, 256 + ctx->shared->speedy_channel, val_count, vals); 257 + } 258 + 259 + static int sec_pmic_acpm_bus_read(void *context, const void *reg_buf, size_t reg_size, 260 + void *val_buf, size_t val_size) 261 + { 262 + struct sec_pmic_acpm_bus_context *ctx = context; 263 + const struct acpm_handle *acpm = ctx->shared->acpm; 264 + const struct acpm_pmic_ops *pmic_ops = &acpm->ops.pmic_ops; 265 + const u8 *r = reg_buf; 266 + u8 reg; 267 + 268 + if (reg_size != BITS_TO_BYTES(ACPM_ADDR_BITS) || !val_size || 269 + val_size > ACPM_MAX_BULK_DATA) 270 + return -EINVAL; 271 + 272 + reg = r[0]; 273 + 274 + return pmic_ops->bulk_read(acpm, ctx->shared->acpm_chan_id, ctx->type, reg, 275 + ctx->shared->speedy_channel, val_size, val_buf); 276 + } 277 + 278 + static int sec_pmic_acpm_bus_reg_update_bits(void *context, unsigned int reg, unsigned int mask, 279 + unsigned int val) 280 + { 281 + struct sec_pmic_acpm_bus_context *ctx = context; 282 + const struct acpm_handle *acpm = ctx->shared->acpm; 283 + const struct acpm_pmic_ops *pmic_ops = &acpm->ops.pmic_ops; 284 + 285 + return pmic_ops->update_reg(acpm, ctx->shared->acpm_chan_id, ctx->type, reg & 0xff, 286 + ctx->shared->speedy_channel, val, mask); 287 + } 288 + 289 + static const struct regmap_bus sec_pmic_acpm_regmap_bus = { 290 + .write = sec_pmic_acpm_bus_write, 291 + .read = sec_pmic_acpm_bus_read, 292 + .reg_update_bits = sec_pmic_acpm_bus_reg_update_bits, 293 + .max_raw_read = ACPM_MAX_BULK_DATA, 294 + .max_raw_write = ACPM_MAX_BULK_DATA, 295 + }; 296 + 297 + static struct regmap *sec_pmic_acpm_regmap_init(struct device *dev, 298 + struct sec_pmic_acpm_shared_bus_context *shared_ctx, 299 + enum sec_pmic_acpm_accesstype type, 300 + const struct regmap_config *cfg, bool do_attach) 301 + { 302 + struct sec_pmic_acpm_bus_context *ctx; 303 + struct regmap *regmap; 304 + 305 + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 306 + if (!ctx) 307 + return ERR_PTR(-ENOMEM); 308 + 309 + ctx->shared = shared_ctx; 310 + ctx->type = type; 311 + 312 + regmap = devm_regmap_init(dev, &sec_pmic_acpm_regmap_bus, ctx, cfg); 313 + if (IS_ERR(regmap)) 314 + return dev_err_cast_probe(dev, regmap, "regmap init (%s) failed\n", cfg->name); 315 + 316 + if (do_attach) { 317 + int ret; 318 + 319 + ret = regmap_attach_dev(dev, regmap, cfg); 320 + if (ret) 321 + return dev_err_ptr_probe(dev, ret, "regmap attach (%s) failed\n", 322 + cfg->name); 323 + } 324 + 325 + return regmap; 326 + } 327 + 328 + static void sec_pmic_acpm_mask_common_irqs(void *regmap_common) 329 + { 330 + regmap_write(regmap_common, S2MPG10_COMMON_INT_MASK, S2MPG10_COMMON_INT_SRC); 331 + } 332 + 333 + static int sec_pmic_acpm_probe(struct platform_device *pdev) 334 + { 335 + struct regmap *regmap_common, *regmap_pmic, *regmap; 336 + const struct sec_pmic_acpm_platform_data *pdata; 337 + struct sec_pmic_acpm_shared_bus_context *shared_ctx; 338 + const struct acpm_handle *acpm; 339 + struct device *dev = &pdev->dev; 340 + int ret, irq; 341 + 342 + pdata = device_get_match_data(dev); 343 + if (!pdata) 344 + return dev_err_probe(dev, -ENODEV, "unsupported device type\n"); 345 + 346 + acpm = devm_acpm_get_by_node(dev, dev->parent->of_node); 347 + if (IS_ERR(acpm)) 348 + return dev_err_probe(dev, PTR_ERR(acpm), "failed to get acpm\n"); 349 + 350 + irq = platform_get_irq(pdev, 0); 351 + if (irq < 0) 352 + return irq; 353 + 354 + shared_ctx = devm_kzalloc(dev, sizeof(*shared_ctx), GFP_KERNEL); 355 + if (!shared_ctx) 356 + return -ENOMEM; 357 + 358 + shared_ctx->acpm = acpm; 359 + shared_ctx->acpm_chan_id = pdata->acpm_chan_id; 360 + shared_ctx->speedy_channel = pdata->speedy_channel; 361 + 362 + regmap_common = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_COMMON, 363 + pdata->regmap_cfg_common, false); 364 + if (IS_ERR(regmap_common)) 365 + return PTR_ERR(regmap_common); 366 + 367 + /* Mask all interrupts from 'common' block, until successful init */ 368 + ret = regmap_write(regmap_common, S2MPG10_COMMON_INT_MASK, S2MPG10_COMMON_INT_SRC); 369 + if (ret) 370 + return dev_err_probe(dev, ret, "failed to mask common block interrupts\n"); 371 + 372 + regmap_pmic = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_PMIC, 373 + pdata->regmap_cfg_pmic, false); 374 + if (IS_ERR(regmap_pmic)) 375 + return PTR_ERR(regmap_pmic); 376 + 377 + regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_RTC, 378 + pdata->regmap_cfg_rtc, true); 379 + if (IS_ERR(regmap)) 380 + return PTR_ERR(regmap); 381 + 382 + regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_METER, 383 + pdata->regmap_cfg_meter, true); 384 + if (IS_ERR(regmap)) 385 + return PTR_ERR(regmap); 386 + 387 + ret = sec_pmic_probe(dev, pdata->device_type, irq, regmap_pmic, NULL); 388 + if (ret) 389 + return ret; 390 + 391 + if (device_property_read_bool(dev, "wakeup-source")) 392 + devm_device_init_wakeup(dev); 393 + 394 + /* Unmask PMIC interrupt from 'common' block, now that everything is in place. */ 395 + ret = regmap_clear_bits(regmap_common, S2MPG10_COMMON_INT_MASK, 396 + S2MPG10_COMMON_INT_SRC_PMIC); 397 + if (ret) 398 + return dev_err_probe(dev, ret, "failed to unmask PMIC interrupt\n"); 399 + 400 + /* Mask all interrupts from 'common' block on shutdown */ 401 + ret = devm_add_action_or_reset(dev, sec_pmic_acpm_mask_common_irqs, regmap_common); 402 + if (ret) 403 + return ret; 404 + 405 + return 0; 406 + } 407 + 408 + static void sec_pmic_acpm_shutdown(struct platform_device *pdev) 409 + { 410 + sec_pmic_shutdown(&pdev->dev); 411 + } 412 + 413 + static const struct sec_pmic_acpm_platform_data s2mpg10_data = { 414 + .device_type = S2MPG10, 415 + .acpm_chan_id = 2, 416 + .speedy_channel = 0, 417 + .regmap_cfg_common = &s2mpg10_regmap_config_common, 418 + .regmap_cfg_pmic = &s2mpg10_regmap_config_pmic, 419 + .regmap_cfg_rtc = &s2mpg10_regmap_config_rtc, 420 + .regmap_cfg_meter = &s2mpg10_regmap_config_meter, 421 + }; 422 + 423 + static const struct of_device_id sec_pmic_acpm_of_match[] = { 424 + { .compatible = "samsung,s2mpg10-pmic", .data = &s2mpg10_data, }, 425 + { }, 426 + }; 427 + MODULE_DEVICE_TABLE(of, sec_pmic_acpm_of_match); 428 + 429 + static struct platform_driver sec_pmic_acpm_driver = { 430 + .driver = { 431 + .name = "sec-pmic-acpm", 432 + .pm = pm_sleep_ptr(&sec_pmic_pm_ops), 433 + .of_match_table = sec_pmic_acpm_of_match, 434 + }, 435 + .probe = sec_pmic_acpm_probe, 436 + .shutdown = sec_pmic_acpm_shutdown, 437 + }; 438 + module_platform_driver(sec_pmic_acpm_driver); 439 + 440 + MODULE_AUTHOR("André Draszik <andre.draszik@linaro.org>"); 441 + MODULE_DESCRIPTION("ACPM driver for the Samsung S2MPG1x"); 442 + MODULE_LICENSE("GPL");
+301
drivers/mfd/sec-common.c
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright 2012 Samsung Electronics Co., Ltd 4 + * http://www.samsung.com 5 + * Copyright 2025 Linaro Ltd. 6 + * 7 + * Samsung SxM core driver 8 + */ 9 + 10 + #include <linux/device.h> 11 + #include <linux/err.h> 12 + #include <linux/export.h> 13 + #include <linux/interrupt.h> 14 + #include <linux/mfd/core.h> 15 + #include <linux/mfd/samsung/core.h> 16 + #include <linux/mfd/samsung/irq.h> 17 + #include <linux/mfd/samsung/s2mps11.h> 18 + #include <linux/mfd/samsung/s2mps13.h> 19 + #include <linux/module.h> 20 + #include <linux/of.h> 21 + #include <linux/pm.h> 22 + #include <linux/pm_runtime.h> 23 + #include <linux/regmap.h> 24 + #include "sec-core.h" 25 + 26 + static const struct mfd_cell s5m8767_devs[] = { 27 + MFD_CELL_NAME("s5m8767-pmic"), 28 + MFD_CELL_NAME("s5m-rtc"), 29 + MFD_CELL_OF("s5m8767-clk", NULL, NULL, 0, 0, "samsung,s5m8767-clk"), 30 + }; 31 + 32 + static const struct mfd_cell s2dos05_devs[] = { 33 + MFD_CELL_NAME("s2dos05-regulator"), 34 + }; 35 + 36 + static const struct mfd_cell s2mpg10_devs[] = { 37 + MFD_CELL_NAME("s2mpg10-meter"), 38 + MFD_CELL_NAME("s2mpg10-regulator"), 39 + MFD_CELL_NAME("s2mpg10-rtc"), 40 + MFD_CELL_OF("s2mpg10-clk", NULL, NULL, 0, 0, "samsung,s2mpg10-clk"), 41 + MFD_CELL_OF("s2mpg10-gpio", NULL, NULL, 0, 0, "samsung,s2mpg10-gpio"), 42 + }; 43 + 44 + static const struct mfd_cell s2mps11_devs[] = { 45 + MFD_CELL_NAME("s2mps11-regulator"), 46 + MFD_CELL_NAME("s2mps14-rtc"), 47 + MFD_CELL_OF("s2mps11-clk", NULL, NULL, 0, 0, "samsung,s2mps11-clk"), 48 + }; 49 + 50 + static const struct mfd_cell s2mps13_devs[] = { 51 + MFD_CELL_NAME("s2mps13-regulator"), 52 + MFD_CELL_NAME("s2mps13-rtc"), 53 + MFD_CELL_OF("s2mps13-clk", NULL, NULL, 0, 0, "samsung,s2mps13-clk"), 54 + }; 55 + 56 + static const struct mfd_cell s2mps14_devs[] = { 57 + MFD_CELL_NAME("s2mps14-regulator"), 58 + MFD_CELL_NAME("s2mps14-rtc"), 59 + MFD_CELL_OF("s2mps14-clk", NULL, NULL, 0, 0, "samsung,s2mps14-clk"), 60 + }; 61 + 62 + static const struct mfd_cell s2mps15_devs[] = { 63 + MFD_CELL_NAME("s2mps15-regulator"), 64 + MFD_CELL_NAME("s2mps15-rtc"), 65 + MFD_CELL_OF("s2mps13-clk", NULL, NULL, 0, 0, "samsung,s2mps13-clk"), 66 + }; 67 + 68 + static const struct mfd_cell s2mpa01_devs[] = { 69 + MFD_CELL_NAME("s2mpa01-pmic"), 70 + MFD_CELL_NAME("s2mps14-rtc"), 71 + }; 72 + 73 + static const struct mfd_cell s2mpu02_devs[] = { 74 + MFD_CELL_NAME("s2mpu02-regulator"), 75 + }; 76 + 77 + static const struct mfd_cell s2mpu05_devs[] = { 78 + MFD_CELL_NAME("s2mpu05-regulator"), 79 + MFD_CELL_NAME("s2mps15-rtc"), 80 + }; 81 + 82 + static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) 83 + { 84 + unsigned int val; 85 + 86 + /* For s2mpg1x, the revision is in a different regmap */ 87 + if (sec_pmic->device_type == S2MPG10) 88 + return; 89 + 90 + /* For each device type, the REG_ID is always the first register */ 91 + if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val)) 92 + dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val); 93 + } 94 + 95 + static void sec_pmic_configure(struct sec_pmic_dev *sec_pmic) 96 + { 97 + int err; 98 + 99 + if (sec_pmic->device_type != S2MPS13X) 100 + return; 101 + 102 + if (sec_pmic->pdata->disable_wrstbi) { 103 + /* 104 + * If WRSTBI pin is pulled down this feature must be disabled 105 + * because each Suspend to RAM will trigger buck voltage reset 106 + * to default values. 107 + */ 108 + err = regmap_update_bits(sec_pmic->regmap_pmic, 109 + S2MPS13_REG_WRSTBI, 110 + S2MPS13_REG_WRSTBI_MASK, 0x0); 111 + if (err) 112 + dev_warn(sec_pmic->dev, 113 + "Cannot initialize WRSTBI config: %d\n", 114 + err); 115 + } 116 + } 117 + 118 + /* 119 + * Only the common platform data elements for s5m8767 are parsed here from the 120 + * device tree. Other sub-modules of s5m8767 such as pmic, rtc , charger and 121 + * others have to parse their own platform data elements from device tree. 122 + * 123 + * The s5m8767 platform data structure is instantiated here and the drivers for 124 + * the sub-modules need not instantiate another instance while parsing their 125 + * platform data. 126 + */ 127 + static struct sec_platform_data * 128 + sec_pmic_parse_dt_pdata(struct device *dev) 129 + { 130 + struct sec_platform_data *pd; 131 + 132 + pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); 133 + if (!pd) 134 + return ERR_PTR(-ENOMEM); 135 + 136 + pd->manual_poweroff = of_property_read_bool(dev->of_node, 137 + "samsung,s2mps11-acokb-ground"); 138 + pd->disable_wrstbi = of_property_read_bool(dev->of_node, 139 + "samsung,s2mps11-wrstbi-ground"); 140 + return pd; 141 + } 142 + 143 + int sec_pmic_probe(struct device *dev, int device_type, unsigned int irq, 144 + struct regmap *regmap, struct i2c_client *client) 145 + { 146 + struct sec_platform_data *pdata; 147 + const struct mfd_cell *sec_devs; 148 + struct sec_pmic_dev *sec_pmic; 149 + int ret, num_sec_devs; 150 + 151 + sec_pmic = devm_kzalloc(dev, sizeof(*sec_pmic), GFP_KERNEL); 152 + if (!sec_pmic) 153 + return -ENOMEM; 154 + 155 + dev_set_drvdata(dev, sec_pmic); 156 + sec_pmic->dev = dev; 157 + sec_pmic->device_type = device_type; 158 + sec_pmic->i2c = client; 159 + sec_pmic->irq = irq; 160 + sec_pmic->regmap_pmic = regmap; 161 + 162 + pdata = sec_pmic_parse_dt_pdata(sec_pmic->dev); 163 + if (IS_ERR(pdata)) { 164 + ret = PTR_ERR(pdata); 165 + return ret; 166 + } 167 + 168 + sec_pmic->pdata = pdata; 169 + 170 + ret = sec_irq_init(sec_pmic); 171 + if (ret) 172 + return ret; 173 + 174 + pm_runtime_set_active(sec_pmic->dev); 175 + 176 + switch (sec_pmic->device_type) { 177 + case S5M8767X: 178 + sec_devs = s5m8767_devs; 179 + num_sec_devs = ARRAY_SIZE(s5m8767_devs); 180 + break; 181 + case S2DOS05: 182 + sec_devs = s2dos05_devs; 183 + num_sec_devs = ARRAY_SIZE(s2dos05_devs); 184 + break; 185 + case S2MPA01: 186 + sec_devs = s2mpa01_devs; 187 + num_sec_devs = ARRAY_SIZE(s2mpa01_devs); 188 + break; 189 + case S2MPG10: 190 + sec_devs = s2mpg10_devs; 191 + num_sec_devs = ARRAY_SIZE(s2mpg10_devs); 192 + break; 193 + case S2MPS11X: 194 + sec_devs = s2mps11_devs; 195 + num_sec_devs = ARRAY_SIZE(s2mps11_devs); 196 + break; 197 + case S2MPS13X: 198 + sec_devs = s2mps13_devs; 199 + num_sec_devs = ARRAY_SIZE(s2mps13_devs); 200 + break; 201 + case S2MPS14X: 202 + sec_devs = s2mps14_devs; 203 + num_sec_devs = ARRAY_SIZE(s2mps14_devs); 204 + break; 205 + case S2MPS15X: 206 + sec_devs = s2mps15_devs; 207 + num_sec_devs = ARRAY_SIZE(s2mps15_devs); 208 + break; 209 + case S2MPU02: 210 + sec_devs = s2mpu02_devs; 211 + num_sec_devs = ARRAY_SIZE(s2mpu02_devs); 212 + break; 213 + case S2MPU05: 214 + sec_devs = s2mpu05_devs; 215 + num_sec_devs = ARRAY_SIZE(s2mpu05_devs); 216 + break; 217 + default: 218 + return dev_err_probe(sec_pmic->dev, -EINVAL, 219 + "Unsupported device type %d\n", 220 + sec_pmic->device_type); 221 + } 222 + ret = devm_mfd_add_devices(sec_pmic->dev, -1, sec_devs, num_sec_devs, 223 + NULL, 0, NULL); 224 + if (ret) 225 + return ret; 226 + 227 + sec_pmic_configure(sec_pmic); 228 + sec_pmic_dump_rev(sec_pmic); 229 + 230 + return ret; 231 + } 232 + EXPORT_SYMBOL_GPL(sec_pmic_probe); 233 + 234 + void sec_pmic_shutdown(struct device *dev) 235 + { 236 + struct sec_pmic_dev *sec_pmic = dev_get_drvdata(dev); 237 + unsigned int reg, mask; 238 + 239 + if (!sec_pmic->pdata->manual_poweroff) 240 + return; 241 + 242 + switch (sec_pmic->device_type) { 243 + case S2MPS11X: 244 + reg = S2MPS11_REG_CTRL1; 245 + mask = S2MPS11_CTRL1_PWRHOLD_MASK; 246 + break; 247 + default: 248 + /* 249 + * Currently only one board with S2MPS11 needs this, so just 250 + * ignore the rest. 251 + */ 252 + dev_warn(sec_pmic->dev, 253 + "Unsupported device %d for manual power off\n", 254 + sec_pmic->device_type); 255 + return; 256 + } 257 + 258 + regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0); 259 + } 260 + EXPORT_SYMBOL_GPL(sec_pmic_shutdown); 261 + 262 + static int sec_pmic_suspend(struct device *dev) 263 + { 264 + struct sec_pmic_dev *sec_pmic = dev_get_drvdata(dev); 265 + 266 + if (device_may_wakeup(dev)) 267 + enable_irq_wake(sec_pmic->irq); 268 + /* 269 + * PMIC IRQ must be disabled during suspend for RTC alarm 270 + * to work properly. 271 + * When device is woken up from suspend, an 272 + * interrupt occurs before resuming I2C bus controller. 273 + * The interrupt is handled by regmap_irq_thread which tries 274 + * to read RTC registers. This read fails (I2C is still 275 + * suspended) and RTC Alarm interrupt is disabled. 276 + */ 277 + disable_irq(sec_pmic->irq); 278 + 279 + return 0; 280 + } 281 + 282 + static int sec_pmic_resume(struct device *dev) 283 + { 284 + struct sec_pmic_dev *sec_pmic = dev_get_drvdata(dev); 285 + 286 + if (device_may_wakeup(dev)) 287 + disable_irq_wake(sec_pmic->irq); 288 + enable_irq(sec_pmic->irq); 289 + 290 + return 0; 291 + } 292 + 293 + DEFINE_SIMPLE_DEV_PM_OPS(sec_pmic_pm_ops, sec_pmic_suspend, sec_pmic_resume); 294 + EXPORT_SYMBOL_GPL(sec_pmic_pm_ops); 295 + 296 + MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>"); 297 + MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>"); 298 + MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); 299 + MODULE_AUTHOR("André Draszik <andre.draszik@linaro.org>"); 300 + MODULE_DESCRIPTION("Core driver for the Samsung S5M"); 301 + MODULE_LICENSE("GPL");
-481
drivers/mfd/sec-core.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - // 3 - // Copyright (c) 2012 Samsung Electronics Co., Ltd 4 - // http://www.samsung.com 5 - 6 - #include <linux/module.h> 7 - #include <linux/moduleparam.h> 8 - #include <linux/init.h> 9 - #include <linux/err.h> 10 - #include <linux/slab.h> 11 - #include <linux/i2c.h> 12 - #include <linux/of.h> 13 - #include <linux/interrupt.h> 14 - #include <linux/pm_runtime.h> 15 - #include <linux/mutex.h> 16 - #include <linux/mfd/core.h> 17 - #include <linux/mfd/samsung/core.h> 18 - #include <linux/mfd/samsung/irq.h> 19 - #include <linux/mfd/samsung/s2mpa01.h> 20 - #include <linux/mfd/samsung/s2mps11.h> 21 - #include <linux/mfd/samsung/s2mps13.h> 22 - #include <linux/mfd/samsung/s2mps14.h> 23 - #include <linux/mfd/samsung/s2mps15.h> 24 - #include <linux/mfd/samsung/s2mpu02.h> 25 - #include <linux/mfd/samsung/s5m8767.h> 26 - #include <linux/regmap.h> 27 - 28 - static const struct mfd_cell s5m8767_devs[] = { 29 - { .name = "s5m8767-pmic", }, 30 - { .name = "s5m-rtc", }, 31 - { 32 - .name = "s5m8767-clk", 33 - .of_compatible = "samsung,s5m8767-clk", 34 - }, 35 - }; 36 - 37 - static const struct mfd_cell s2dos05_devs[] = { 38 - { .name = "s2dos05-regulator", }, 39 - }; 40 - 41 - static const struct mfd_cell s2mps11_devs[] = { 42 - { .name = "s2mps11-regulator", }, 43 - { .name = "s2mps14-rtc", }, 44 - { 45 - .name = "s2mps11-clk", 46 - .of_compatible = "samsung,s2mps11-clk", 47 - }, 48 - }; 49 - 50 - static const struct mfd_cell s2mps13_devs[] = { 51 - { .name = "s2mps13-regulator", }, 52 - { .name = "s2mps13-rtc", }, 53 - { 54 - .name = "s2mps13-clk", 55 - .of_compatible = "samsung,s2mps13-clk", 56 - }, 57 - }; 58 - 59 - static const struct mfd_cell s2mps14_devs[] = { 60 - { .name = "s2mps14-regulator", }, 61 - { .name = "s2mps14-rtc", }, 62 - { 63 - .name = "s2mps14-clk", 64 - .of_compatible = "samsung,s2mps14-clk", 65 - }, 66 - }; 67 - 68 - static const struct mfd_cell s2mps15_devs[] = { 69 - { .name = "s2mps15-regulator", }, 70 - { .name = "s2mps15-rtc", }, 71 - { 72 - .name = "s2mps13-clk", 73 - .of_compatible = "samsung,s2mps13-clk", 74 - }, 75 - }; 76 - 77 - static const struct mfd_cell s2mpa01_devs[] = { 78 - { .name = "s2mpa01-pmic", }, 79 - { .name = "s2mps14-rtc", }, 80 - }; 81 - 82 - static const struct mfd_cell s2mpu02_devs[] = { 83 - { .name = "s2mpu02-regulator", }, 84 - }; 85 - 86 - static const struct mfd_cell s2mpu05_devs[] = { 87 - { .name = "s2mpu05-regulator", }, 88 - { .name = "s2mps15-rtc", }, 89 - }; 90 - 91 - static const struct of_device_id sec_dt_match[] = { 92 - { 93 - .compatible = "samsung,s5m8767-pmic", 94 - .data = (void *)S5M8767X, 95 - }, { 96 - .compatible = "samsung,s2dos05", 97 - .data = (void *)S2DOS05, 98 - }, { 99 - .compatible = "samsung,s2mps11-pmic", 100 - .data = (void *)S2MPS11X, 101 - }, { 102 - .compatible = "samsung,s2mps13-pmic", 103 - .data = (void *)S2MPS13X, 104 - }, { 105 - .compatible = "samsung,s2mps14-pmic", 106 - .data = (void *)S2MPS14X, 107 - }, { 108 - .compatible = "samsung,s2mps15-pmic", 109 - .data = (void *)S2MPS15X, 110 - }, { 111 - .compatible = "samsung,s2mpa01-pmic", 112 - .data = (void *)S2MPA01, 113 - }, { 114 - .compatible = "samsung,s2mpu02-pmic", 115 - .data = (void *)S2MPU02, 116 - }, { 117 - .compatible = "samsung,s2mpu05-pmic", 118 - .data = (void *)S2MPU05, 119 - }, { 120 - /* Sentinel */ 121 - }, 122 - }; 123 - MODULE_DEVICE_TABLE(of, sec_dt_match); 124 - 125 - static bool s2mpa01_volatile(struct device *dev, unsigned int reg) 126 - { 127 - switch (reg) { 128 - case S2MPA01_REG_INT1M: 129 - case S2MPA01_REG_INT2M: 130 - case S2MPA01_REG_INT3M: 131 - return false; 132 - default: 133 - return true; 134 - } 135 - } 136 - 137 - static bool s2mps11_volatile(struct device *dev, unsigned int reg) 138 - { 139 - switch (reg) { 140 - case S2MPS11_REG_INT1M: 141 - case S2MPS11_REG_INT2M: 142 - case S2MPS11_REG_INT3M: 143 - return false; 144 - default: 145 - return true; 146 - } 147 - } 148 - 149 - static bool s2mpu02_volatile(struct device *dev, unsigned int reg) 150 - { 151 - switch (reg) { 152 - case S2MPU02_REG_INT1M: 153 - case S2MPU02_REG_INT2M: 154 - case S2MPU02_REG_INT3M: 155 - return false; 156 - default: 157 - return true; 158 - } 159 - } 160 - 161 - static const struct regmap_config sec_regmap_config = { 162 - .reg_bits = 8, 163 - .val_bits = 8, 164 - }; 165 - 166 - static const struct regmap_config s2mpa01_regmap_config = { 167 - .reg_bits = 8, 168 - .val_bits = 8, 169 - 170 - .max_register = S2MPA01_REG_LDO_OVCB4, 171 - .volatile_reg = s2mpa01_volatile, 172 - .cache_type = REGCACHE_FLAT, 173 - }; 174 - 175 - static const struct regmap_config s2mps11_regmap_config = { 176 - .reg_bits = 8, 177 - .val_bits = 8, 178 - 179 - .max_register = S2MPS11_REG_L38CTRL, 180 - .volatile_reg = s2mps11_volatile, 181 - .cache_type = REGCACHE_FLAT, 182 - }; 183 - 184 - static const struct regmap_config s2mps13_regmap_config = { 185 - .reg_bits = 8, 186 - .val_bits = 8, 187 - 188 - .max_register = S2MPS13_REG_LDODSCH5, 189 - .volatile_reg = s2mps11_volatile, 190 - .cache_type = REGCACHE_FLAT, 191 - }; 192 - 193 - static const struct regmap_config s2mps14_regmap_config = { 194 - .reg_bits = 8, 195 - .val_bits = 8, 196 - 197 - .max_register = S2MPS14_REG_LDODSCH3, 198 - .volatile_reg = s2mps11_volatile, 199 - .cache_type = REGCACHE_FLAT, 200 - }; 201 - 202 - static const struct regmap_config s2mps15_regmap_config = { 203 - .reg_bits = 8, 204 - .val_bits = 8, 205 - 206 - .max_register = S2MPS15_REG_LDODSCH4, 207 - .volatile_reg = s2mps11_volatile, 208 - .cache_type = REGCACHE_FLAT, 209 - }; 210 - 211 - static const struct regmap_config s2mpu02_regmap_config = { 212 - .reg_bits = 8, 213 - .val_bits = 8, 214 - 215 - .max_register = S2MPU02_REG_DVSDATA, 216 - .volatile_reg = s2mpu02_volatile, 217 - .cache_type = REGCACHE_FLAT, 218 - }; 219 - 220 - static const struct regmap_config s5m8767_regmap_config = { 221 - .reg_bits = 8, 222 - .val_bits = 8, 223 - 224 - .max_register = S5M8767_REG_LDO28CTRL, 225 - .volatile_reg = s2mps11_volatile, 226 - .cache_type = REGCACHE_FLAT, 227 - }; 228 - 229 - static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) 230 - { 231 - unsigned int val; 232 - 233 - /* For each device type, the REG_ID is always the first register */ 234 - if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val)) 235 - dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val); 236 - } 237 - 238 - static void sec_pmic_configure(struct sec_pmic_dev *sec_pmic) 239 - { 240 - int err; 241 - 242 - if (sec_pmic->device_type != S2MPS13X) 243 - return; 244 - 245 - if (sec_pmic->pdata->disable_wrstbi) { 246 - /* 247 - * If WRSTBI pin is pulled down this feature must be disabled 248 - * because each Suspend to RAM will trigger buck voltage reset 249 - * to default values. 250 - */ 251 - err = regmap_update_bits(sec_pmic->regmap_pmic, 252 - S2MPS13_REG_WRSTBI, 253 - S2MPS13_REG_WRSTBI_MASK, 0x0); 254 - if (err) 255 - dev_warn(sec_pmic->dev, 256 - "Cannot initialize WRSTBI config: %d\n", 257 - err); 258 - } 259 - } 260 - 261 - /* 262 - * Only the common platform data elements for s5m8767 are parsed here from the 263 - * device tree. Other sub-modules of s5m8767 such as pmic, rtc , charger and 264 - * others have to parse their own platform data elements from device tree. 265 - * 266 - * The s5m8767 platform data structure is instantiated here and the drivers for 267 - * the sub-modules need not instantiate another instance while parsing their 268 - * platform data. 269 - */ 270 - static struct sec_platform_data * 271 - sec_pmic_i2c_parse_dt_pdata(struct device *dev) 272 - { 273 - struct sec_platform_data *pd; 274 - 275 - pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); 276 - if (!pd) 277 - return ERR_PTR(-ENOMEM); 278 - 279 - pd->manual_poweroff = of_property_read_bool(dev->of_node, 280 - "samsung,s2mps11-acokb-ground"); 281 - pd->disable_wrstbi = of_property_read_bool(dev->of_node, 282 - "samsung,s2mps11-wrstbi-ground"); 283 - return pd; 284 - } 285 - 286 - static int sec_pmic_probe(struct i2c_client *i2c) 287 - { 288 - const struct regmap_config *regmap; 289 - struct sec_platform_data *pdata; 290 - const struct mfd_cell *sec_devs; 291 - struct sec_pmic_dev *sec_pmic; 292 - int ret, num_sec_devs; 293 - 294 - sec_pmic = devm_kzalloc(&i2c->dev, sizeof(struct sec_pmic_dev), 295 - GFP_KERNEL); 296 - if (sec_pmic == NULL) 297 - return -ENOMEM; 298 - 299 - i2c_set_clientdata(i2c, sec_pmic); 300 - sec_pmic->dev = &i2c->dev; 301 - sec_pmic->i2c = i2c; 302 - sec_pmic->irq = i2c->irq; 303 - 304 - pdata = sec_pmic_i2c_parse_dt_pdata(sec_pmic->dev); 305 - if (IS_ERR(pdata)) { 306 - ret = PTR_ERR(pdata); 307 - return ret; 308 - } 309 - 310 - sec_pmic->device_type = (unsigned long)of_device_get_match_data(sec_pmic->dev); 311 - sec_pmic->pdata = pdata; 312 - 313 - switch (sec_pmic->device_type) { 314 - case S2MPA01: 315 - regmap = &s2mpa01_regmap_config; 316 - break; 317 - case S2MPS11X: 318 - regmap = &s2mps11_regmap_config; 319 - break; 320 - case S2MPS13X: 321 - regmap = &s2mps13_regmap_config; 322 - break; 323 - case S2MPS14X: 324 - regmap = &s2mps14_regmap_config; 325 - break; 326 - case S2MPS15X: 327 - regmap = &s2mps15_regmap_config; 328 - break; 329 - case S5M8767X: 330 - regmap = &s5m8767_regmap_config; 331 - break; 332 - case S2MPU02: 333 - regmap = &s2mpu02_regmap_config; 334 - break; 335 - default: 336 - regmap = &sec_regmap_config; 337 - break; 338 - } 339 - 340 - sec_pmic->regmap_pmic = devm_regmap_init_i2c(i2c, regmap); 341 - if (IS_ERR(sec_pmic->regmap_pmic)) { 342 - ret = PTR_ERR(sec_pmic->regmap_pmic); 343 - dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 344 - ret); 345 - return ret; 346 - } 347 - 348 - sec_irq_init(sec_pmic); 349 - 350 - pm_runtime_set_active(sec_pmic->dev); 351 - 352 - switch (sec_pmic->device_type) { 353 - case S5M8767X: 354 - sec_devs = s5m8767_devs; 355 - num_sec_devs = ARRAY_SIZE(s5m8767_devs); 356 - break; 357 - case S2DOS05: 358 - sec_devs = s2dos05_devs; 359 - num_sec_devs = ARRAY_SIZE(s2dos05_devs); 360 - break; 361 - case S2MPA01: 362 - sec_devs = s2mpa01_devs; 363 - num_sec_devs = ARRAY_SIZE(s2mpa01_devs); 364 - break; 365 - case S2MPS11X: 366 - sec_devs = s2mps11_devs; 367 - num_sec_devs = ARRAY_SIZE(s2mps11_devs); 368 - break; 369 - case S2MPS13X: 370 - sec_devs = s2mps13_devs; 371 - num_sec_devs = ARRAY_SIZE(s2mps13_devs); 372 - break; 373 - case S2MPS14X: 374 - sec_devs = s2mps14_devs; 375 - num_sec_devs = ARRAY_SIZE(s2mps14_devs); 376 - break; 377 - case S2MPS15X: 378 - sec_devs = s2mps15_devs; 379 - num_sec_devs = ARRAY_SIZE(s2mps15_devs); 380 - break; 381 - case S2MPU02: 382 - sec_devs = s2mpu02_devs; 383 - num_sec_devs = ARRAY_SIZE(s2mpu02_devs); 384 - break; 385 - case S2MPU05: 386 - sec_devs = s2mpu05_devs; 387 - num_sec_devs = ARRAY_SIZE(s2mpu05_devs); 388 - break; 389 - default: 390 - dev_err(&i2c->dev, "Unsupported device type (%lu)\n", 391 - sec_pmic->device_type); 392 - return -ENODEV; 393 - } 394 - ret = devm_mfd_add_devices(sec_pmic->dev, -1, sec_devs, num_sec_devs, 395 - NULL, 0, NULL); 396 - if (ret) 397 - return ret; 398 - 399 - sec_pmic_configure(sec_pmic); 400 - sec_pmic_dump_rev(sec_pmic); 401 - 402 - return ret; 403 - } 404 - 405 - static void sec_pmic_shutdown(struct i2c_client *i2c) 406 - { 407 - struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c); 408 - unsigned int reg, mask; 409 - 410 - if (!sec_pmic->pdata->manual_poweroff) 411 - return; 412 - 413 - switch (sec_pmic->device_type) { 414 - case S2MPS11X: 415 - reg = S2MPS11_REG_CTRL1; 416 - mask = S2MPS11_CTRL1_PWRHOLD_MASK; 417 - break; 418 - default: 419 - /* 420 - * Currently only one board with S2MPS11 needs this, so just 421 - * ignore the rest. 422 - */ 423 - dev_warn(sec_pmic->dev, 424 - "Unsupported device %lu for manual power off\n", 425 - sec_pmic->device_type); 426 - return; 427 - } 428 - 429 - regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0); 430 - } 431 - 432 - static int sec_pmic_suspend(struct device *dev) 433 - { 434 - struct i2c_client *i2c = to_i2c_client(dev); 435 - struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c); 436 - 437 - if (device_may_wakeup(dev)) 438 - enable_irq_wake(sec_pmic->irq); 439 - /* 440 - * PMIC IRQ must be disabled during suspend for RTC alarm 441 - * to work properly. 442 - * When device is woken up from suspend, an 443 - * interrupt occurs before resuming I2C bus controller. 444 - * The interrupt is handled by regmap_irq_thread which tries 445 - * to read RTC registers. This read fails (I2C is still 446 - * suspended) and RTC Alarm interrupt is disabled. 447 - */ 448 - disable_irq(sec_pmic->irq); 449 - 450 - return 0; 451 - } 452 - 453 - static int sec_pmic_resume(struct device *dev) 454 - { 455 - struct i2c_client *i2c = to_i2c_client(dev); 456 - struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c); 457 - 458 - if (device_may_wakeup(dev)) 459 - disable_irq_wake(sec_pmic->irq); 460 - enable_irq(sec_pmic->irq); 461 - 462 - return 0; 463 - } 464 - 465 - static DEFINE_SIMPLE_DEV_PM_OPS(sec_pmic_pm_ops, 466 - sec_pmic_suspend, sec_pmic_resume); 467 - 468 - static struct i2c_driver sec_pmic_driver = { 469 - .driver = { 470 - .name = "sec_pmic", 471 - .pm = pm_sleep_ptr(&sec_pmic_pm_ops), 472 - .of_match_table = sec_dt_match, 473 - }, 474 - .probe = sec_pmic_probe, 475 - .shutdown = sec_pmic_shutdown, 476 - }; 477 - module_i2c_driver(sec_pmic_driver); 478 - 479 - MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); 480 - MODULE_DESCRIPTION("Core support for the S5M MFD"); 481 - MODULE_LICENSE("GPL");
+23
drivers/mfd/sec-core.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0+ */ 2 + /* 3 + * Copyright 2012 Samsung Electronics Co., Ltd 4 + * http://www.samsung.com 5 + * Copyright 2025 Linaro Ltd. 6 + * 7 + * Samsung SxM core driver internal data 8 + */ 9 + 10 + #ifndef __SEC_CORE_INT_H 11 + #define __SEC_CORE_INT_H 12 + 13 + struct i2c_client; 14 + 15 + extern const struct dev_pm_ops sec_pmic_pm_ops; 16 + 17 + int sec_pmic_probe(struct device *dev, int device_type, unsigned int irq, 18 + struct regmap *regmap, struct i2c_client *client); 19 + void sec_pmic_shutdown(struct device *dev); 20 + 21 + int sec_irq_init(struct sec_pmic_dev *sec_pmic); 22 + 23 + #endif /* __SEC_CORE_INT_H */
+239
drivers/mfd/sec-i2c.c
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright 2012 Samsung Electronics Co., Ltd 4 + * http://www.samsung.com 5 + * Copyright 2025 Linaro Ltd. 6 + * 7 + * Samsung SxM I2C driver 8 + */ 9 + 10 + #include <linux/dev_printk.h> 11 + #include <linux/err.h> 12 + #include <linux/i2c.h> 13 + #include <linux/mfd/samsung/core.h> 14 + #include <linux/mfd/samsung/s2mpa01.h> 15 + #include <linux/mfd/samsung/s2mps11.h> 16 + #include <linux/mfd/samsung/s2mps13.h> 17 + #include <linux/mfd/samsung/s2mps14.h> 18 + #include <linux/mfd/samsung/s2mps15.h> 19 + #include <linux/mfd/samsung/s2mpu02.h> 20 + #include <linux/mfd/samsung/s5m8767.h> 21 + #include <linux/mod_devicetable.h> 22 + #include <linux/module.h> 23 + #include <linux/pm.h> 24 + #include <linux/property.h> 25 + #include <linux/regmap.h> 26 + #include "sec-core.h" 27 + 28 + struct sec_pmic_i2c_platform_data { 29 + const struct regmap_config *regmap_cfg; 30 + int device_type; 31 + }; 32 + 33 + static bool s2mpa01_volatile(struct device *dev, unsigned int reg) 34 + { 35 + switch (reg) { 36 + case S2MPA01_REG_INT1M: 37 + case S2MPA01_REG_INT2M: 38 + case S2MPA01_REG_INT3M: 39 + return false; 40 + default: 41 + return true; 42 + } 43 + } 44 + 45 + static bool s2mps11_volatile(struct device *dev, unsigned int reg) 46 + { 47 + switch (reg) { 48 + case S2MPS11_REG_INT1M: 49 + case S2MPS11_REG_INT2M: 50 + case S2MPS11_REG_INT3M: 51 + return false; 52 + default: 53 + return true; 54 + } 55 + } 56 + 57 + static bool s2mpu02_volatile(struct device *dev, unsigned int reg) 58 + { 59 + switch (reg) { 60 + case S2MPU02_REG_INT1M: 61 + case S2MPU02_REG_INT2M: 62 + case S2MPU02_REG_INT3M: 63 + return false; 64 + default: 65 + return true; 66 + } 67 + } 68 + 69 + static const struct regmap_config s2dos05_regmap_config = { 70 + .reg_bits = 8, 71 + .val_bits = 8, 72 + }; 73 + 74 + static const struct regmap_config s2mpa01_regmap_config = { 75 + .reg_bits = 8, 76 + .val_bits = 8, 77 + 78 + .max_register = S2MPA01_REG_LDO_OVCB4, 79 + .volatile_reg = s2mpa01_volatile, 80 + .cache_type = REGCACHE_FLAT, 81 + }; 82 + 83 + static const struct regmap_config s2mps11_regmap_config = { 84 + .reg_bits = 8, 85 + .val_bits = 8, 86 + 87 + .max_register = S2MPS11_REG_L38CTRL, 88 + .volatile_reg = s2mps11_volatile, 89 + .cache_type = REGCACHE_FLAT, 90 + }; 91 + 92 + static const struct regmap_config s2mps13_regmap_config = { 93 + .reg_bits = 8, 94 + .val_bits = 8, 95 + 96 + .max_register = S2MPS13_REG_LDODSCH5, 97 + .volatile_reg = s2mps11_volatile, 98 + .cache_type = REGCACHE_FLAT, 99 + }; 100 + 101 + static const struct regmap_config s2mps14_regmap_config = { 102 + .reg_bits = 8, 103 + .val_bits = 8, 104 + 105 + .max_register = S2MPS14_REG_LDODSCH3, 106 + .volatile_reg = s2mps11_volatile, 107 + .cache_type = REGCACHE_FLAT, 108 + }; 109 + 110 + static const struct regmap_config s2mps15_regmap_config = { 111 + .reg_bits = 8, 112 + .val_bits = 8, 113 + 114 + .max_register = S2MPS15_REG_LDODSCH4, 115 + .volatile_reg = s2mps11_volatile, 116 + .cache_type = REGCACHE_FLAT, 117 + }; 118 + 119 + static const struct regmap_config s2mpu02_regmap_config = { 120 + .reg_bits = 8, 121 + .val_bits = 8, 122 + 123 + .max_register = S2MPU02_REG_DVSDATA, 124 + .volatile_reg = s2mpu02_volatile, 125 + .cache_type = REGCACHE_FLAT, 126 + }; 127 + 128 + static const struct regmap_config s2mpu05_regmap_config = { 129 + .reg_bits = 8, 130 + .val_bits = 8, 131 + }; 132 + 133 + static const struct regmap_config s5m8767_regmap_config = { 134 + .reg_bits = 8, 135 + .val_bits = 8, 136 + 137 + .max_register = S5M8767_REG_LDO28CTRL, 138 + .volatile_reg = s2mps11_volatile, 139 + .cache_type = REGCACHE_FLAT, 140 + }; 141 + 142 + static int sec_pmic_i2c_probe(struct i2c_client *client) 143 + { 144 + const struct sec_pmic_i2c_platform_data *pdata; 145 + struct regmap *regmap_pmic; 146 + 147 + pdata = device_get_match_data(&client->dev); 148 + if (!pdata) 149 + return dev_err_probe(&client->dev, -ENODEV, 150 + "Unsupported device type\n"); 151 + 152 + regmap_pmic = devm_regmap_init_i2c(client, pdata->regmap_cfg); 153 + if (IS_ERR(regmap_pmic)) 154 + return dev_err_probe(&client->dev, PTR_ERR(regmap_pmic), 155 + "regmap init failed\n"); 156 + 157 + return sec_pmic_probe(&client->dev, pdata->device_type, client->irq, 158 + regmap_pmic, client); 159 + } 160 + 161 + static void sec_pmic_i2c_shutdown(struct i2c_client *i2c) 162 + { 163 + sec_pmic_shutdown(&i2c->dev); 164 + } 165 + 166 + static const struct sec_pmic_i2c_platform_data s2dos05_data = { 167 + .regmap_cfg = &s2dos05_regmap_config, 168 + .device_type = S2DOS05 169 + }; 170 + 171 + static const struct sec_pmic_i2c_platform_data s2mpa01_data = { 172 + .regmap_cfg = &s2mpa01_regmap_config, 173 + .device_type = S2MPA01, 174 + }; 175 + 176 + static const struct sec_pmic_i2c_platform_data s2mps11_data = { 177 + .regmap_cfg = &s2mps11_regmap_config, 178 + .device_type = S2MPS11X, 179 + }; 180 + 181 + static const struct sec_pmic_i2c_platform_data s2mps13_data = { 182 + .regmap_cfg = &s2mps13_regmap_config, 183 + .device_type = S2MPS13X, 184 + }; 185 + 186 + static const struct sec_pmic_i2c_platform_data s2mps14_data = { 187 + .regmap_cfg = &s2mps14_regmap_config, 188 + .device_type = S2MPS14X, 189 + }; 190 + 191 + static const struct sec_pmic_i2c_platform_data s2mps15_data = { 192 + .regmap_cfg = &s2mps15_regmap_config, 193 + .device_type = S2MPS15X, 194 + }; 195 + 196 + static const struct sec_pmic_i2c_platform_data s2mpu02_data = { 197 + .regmap_cfg = &s2mpu02_regmap_config, 198 + .device_type = S2MPU02, 199 + }; 200 + 201 + static const struct sec_pmic_i2c_platform_data s2mpu05_data = { 202 + .regmap_cfg = &s2mpu05_regmap_config, 203 + .device_type = S2MPU05, 204 + }; 205 + 206 + static const struct sec_pmic_i2c_platform_data s5m8767_data = { 207 + .regmap_cfg = &s5m8767_regmap_config, 208 + .device_type = S5M8767X, 209 + }; 210 + 211 + static const struct of_device_id sec_pmic_i2c_of_match[] = { 212 + { .compatible = "samsung,s2dos05", .data = &s2dos05_data, }, 213 + { .compatible = "samsung,s2mpa01-pmic", .data = &s2mpa01_data, }, 214 + { .compatible = "samsung,s2mps11-pmic", .data = &s2mps11_data, }, 215 + { .compatible = "samsung,s2mps13-pmic", .data = &s2mps13_data, }, 216 + { .compatible = "samsung,s2mps14-pmic", .data = &s2mps14_data, }, 217 + { .compatible = "samsung,s2mps15-pmic", .data = &s2mps15_data, }, 218 + { .compatible = "samsung,s2mpu02-pmic", .data = &s2mpu02_data, }, 219 + { .compatible = "samsung,s2mpu05-pmic", .data = &s2mpu05_data, }, 220 + { .compatible = "samsung,s5m8767-pmic", .data = &s5m8767_data, }, 221 + { }, 222 + }; 223 + MODULE_DEVICE_TABLE(of, sec_pmic_i2c_of_match); 224 + 225 + static struct i2c_driver sec_pmic_i2c_driver = { 226 + .driver = { 227 + .name = "sec-pmic-i2c", 228 + .pm = pm_sleep_ptr(&sec_pmic_pm_ops), 229 + .of_match_table = sec_pmic_i2c_of_match, 230 + }, 231 + .probe = sec_pmic_i2c_probe, 232 + .shutdown = sec_pmic_i2c_shutdown, 233 + }; 234 + module_i2c_driver(sec_pmic_i2c_driver); 235 + 236 + MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); 237 + MODULE_AUTHOR("André Draszik <andre.draszik@linaro.org>"); 238 + MODULE_DESCRIPTION("I2C driver for the Samsung S5M"); 239 + MODULE_LICENSE("GPL");
+165 -295
drivers/mfd/sec-irq.c
··· 3 3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd 4 4 // http://www.samsung.com 5 5 6 - #include <linux/device.h> 6 + #include <linux/array_size.h> 7 + #include <linux/build_bug.h> 8 + #include <linux/dev_printk.h> 7 9 #include <linux/interrupt.h> 8 10 #include <linux/irq.h> 9 - #include <linux/module.h> 10 - #include <linux/regmap.h> 11 - 12 11 #include <linux/mfd/samsung/core.h> 13 12 #include <linux/mfd/samsung/irq.h> 13 + #include <linux/mfd/samsung/s2mpg10.h> 14 14 #include <linux/mfd/samsung/s2mps11.h> 15 15 #include <linux/mfd/samsung/s2mps14.h> 16 16 #include <linux/mfd/samsung/s2mpu02.h> 17 17 #include <linux/mfd/samsung/s2mpu05.h> 18 18 #include <linux/mfd/samsung/s5m8767.h> 19 + #include <linux/regmap.h> 20 + #include "sec-core.h" 21 + 22 + static const struct regmap_irq s2mpg10_irqs[] = { 23 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWRONF, 0, S2MPG10_IRQ_PWRONF_MASK), 24 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWRONR, 0, S2MPG10_IRQ_PWRONR_MASK), 25 + REGMAP_IRQ_REG(S2MPG10_IRQ_JIGONBF, 0, S2MPG10_IRQ_JIGONBF_MASK), 26 + REGMAP_IRQ_REG(S2MPG10_IRQ_JIGONBR, 0, S2MPG10_IRQ_JIGONBR_MASK), 27 + REGMAP_IRQ_REG(S2MPG10_IRQ_ACOKBF, 0, S2MPG10_IRQ_ACOKBF_MASK), 28 + REGMAP_IRQ_REG(S2MPG10_IRQ_ACOKBR, 0, S2MPG10_IRQ_ACOKBR_MASK), 29 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWRON1S, 0, S2MPG10_IRQ_PWRON1S_MASK), 30 + REGMAP_IRQ_REG(S2MPG10_IRQ_MRB, 0, S2MPG10_IRQ_MRB_MASK), 31 + 32 + REGMAP_IRQ_REG(S2MPG10_IRQ_RTC60S, 1, S2MPG10_IRQ_RTC60S_MASK), 33 + REGMAP_IRQ_REG(S2MPG10_IRQ_RTCA1, 1, S2MPG10_IRQ_RTCA1_MASK), 34 + REGMAP_IRQ_REG(S2MPG10_IRQ_RTCA0, 1, S2MPG10_IRQ_RTCA0_MASK), 35 + REGMAP_IRQ_REG(S2MPG10_IRQ_RTC1S, 1, S2MPG10_IRQ_RTC1S_MASK), 36 + REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR_COLDRST, 1, S2MPG10_IRQ_WTSR_COLDRST_MASK), 37 + REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR, 1, S2MPG10_IRQ_WTSR_MASK), 38 + REGMAP_IRQ_REG(S2MPG10_IRQ_WRST, 1, S2MPG10_IRQ_WRST_MASK), 39 + REGMAP_IRQ_REG(S2MPG10_IRQ_SMPL, 1, S2MPG10_IRQ_SMPL_MASK), 40 + 41 + REGMAP_IRQ_REG(S2MPG10_IRQ_120C, 2, S2MPG10_IRQ_INT120C_MASK), 42 + REGMAP_IRQ_REG(S2MPG10_IRQ_140C, 2, S2MPG10_IRQ_INT140C_MASK), 43 + REGMAP_IRQ_REG(S2MPG10_IRQ_TSD, 2, S2MPG10_IRQ_TSD_MASK), 44 + REGMAP_IRQ_REG(S2MPG10_IRQ_PIF_TIMEOUT1, 2, S2MPG10_IRQ_PIF_TIMEOUT1_MASK), 45 + REGMAP_IRQ_REG(S2MPG10_IRQ_PIF_TIMEOUT2, 2, S2MPG10_IRQ_PIF_TIMEOUT2_MASK), 46 + REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_PARITY_ERR, 2, S2MPG10_IRQ_SPD_PARITY_ERR_MASK), 47 + REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_ABNORMAL_STOP, 2, S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK), 48 + REGMAP_IRQ_REG(S2MPG10_IRQ_PMETER_OVERF, 2, S2MPG10_IRQ_PMETER_OVERF_MASK), 49 + 50 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B1M, 3, S2MPG10_IRQ_OCP_B1M_MASK), 51 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B2M, 3, S2MPG10_IRQ_OCP_B2M_MASK), 52 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B3M, 3, S2MPG10_IRQ_OCP_B3M_MASK), 53 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B4M, 3, S2MPG10_IRQ_OCP_B4M_MASK), 54 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B5M, 3, S2MPG10_IRQ_OCP_B5M_MASK), 55 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B6M, 3, S2MPG10_IRQ_OCP_B6M_MASK), 56 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B7M, 3, S2MPG10_IRQ_OCP_B7M_MASK), 57 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B8M, 3, S2MPG10_IRQ_OCP_B8M_MASK), 58 + 59 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B9M, 4, S2MPG10_IRQ_OCP_B9M_MASK), 60 + REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B10M, 4, S2MPG10_IRQ_OCP_B10M_MASK), 61 + REGMAP_IRQ_REG(S2MPG10_IRQ_WLWP_ACC, 4, S2MPG10_IRQ_WLWP_ACC_MASK), 62 + REGMAP_IRQ_REG(S2MPG10_IRQ_SMPL_TIMEOUT, 4, S2MPG10_IRQ_SMPL_TIMEOUT_MASK), 63 + REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR_TIMEOUT, 4, S2MPG10_IRQ_WTSR_TIMEOUT_MASK), 64 + REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_SRP_PKT_RST, 4, S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK), 65 + 66 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH0, 5, S2MPG10_IRQ_PWR_WARN_CH0_MASK), 67 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH1, 5, S2MPG10_IRQ_PWR_WARN_CH1_MASK), 68 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH2, 5, S2MPG10_IRQ_PWR_WARN_CH2_MASK), 69 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH3, 5, S2MPG10_IRQ_PWR_WARN_CH3_MASK), 70 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH4, 5, S2MPG10_IRQ_PWR_WARN_CH4_MASK), 71 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH5, 5, S2MPG10_IRQ_PWR_WARN_CH5_MASK), 72 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH6, 5, S2MPG10_IRQ_PWR_WARN_CH6_MASK), 73 + REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK), 74 + }; 19 75 20 76 static const struct regmap_irq s2mps11_irqs[] = { 21 - [S2MPS11_IRQ_PWRONF] = { 22 - .reg_offset = 0, 23 - .mask = S2MPS11_IRQ_PWRONF_MASK, 24 - }, 25 - [S2MPS11_IRQ_PWRONR] = { 26 - .reg_offset = 0, 27 - .mask = S2MPS11_IRQ_PWRONR_MASK, 28 - }, 29 - [S2MPS11_IRQ_JIGONBF] = { 30 - .reg_offset = 0, 31 - .mask = S2MPS11_IRQ_JIGONBF_MASK, 32 - }, 33 - [S2MPS11_IRQ_JIGONBR] = { 34 - .reg_offset = 0, 35 - .mask = S2MPS11_IRQ_JIGONBR_MASK, 36 - }, 37 - [S2MPS11_IRQ_ACOKBF] = { 38 - .reg_offset = 0, 39 - .mask = S2MPS11_IRQ_ACOKBF_MASK, 40 - }, 41 - [S2MPS11_IRQ_ACOKBR] = { 42 - .reg_offset = 0, 43 - .mask = S2MPS11_IRQ_ACOKBR_MASK, 44 - }, 45 - [S2MPS11_IRQ_PWRON1S] = { 46 - .reg_offset = 0, 47 - .mask = S2MPS11_IRQ_PWRON1S_MASK, 48 - }, 49 - [S2MPS11_IRQ_MRB] = { 50 - .reg_offset = 0, 51 - .mask = S2MPS11_IRQ_MRB_MASK, 52 - }, 53 - [S2MPS11_IRQ_RTC60S] = { 54 - .reg_offset = 1, 55 - .mask = S2MPS11_IRQ_RTC60S_MASK, 56 - }, 57 - [S2MPS11_IRQ_RTCA1] = { 58 - .reg_offset = 1, 59 - .mask = S2MPS11_IRQ_RTCA1_MASK, 60 - }, 61 - [S2MPS11_IRQ_RTCA0] = { 62 - .reg_offset = 1, 63 - .mask = S2MPS11_IRQ_RTCA0_MASK, 64 - }, 65 - [S2MPS11_IRQ_SMPL] = { 66 - .reg_offset = 1, 67 - .mask = S2MPS11_IRQ_SMPL_MASK, 68 - }, 69 - [S2MPS11_IRQ_RTC1S] = { 70 - .reg_offset = 1, 71 - .mask = S2MPS11_IRQ_RTC1S_MASK, 72 - }, 73 - [S2MPS11_IRQ_WTSR] = { 74 - .reg_offset = 1, 75 - .mask = S2MPS11_IRQ_WTSR_MASK, 76 - }, 77 - [S2MPS11_IRQ_INT120C] = { 78 - .reg_offset = 2, 79 - .mask = S2MPS11_IRQ_INT120C_MASK, 80 - }, 81 - [S2MPS11_IRQ_INT140C] = { 82 - .reg_offset = 2, 83 - .mask = S2MPS11_IRQ_INT140C_MASK, 84 - }, 77 + REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 78 + REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 79 + REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 80 + REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 81 + REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 82 + REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 83 + REGMAP_IRQ_REG(S2MPS11_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 84 + REGMAP_IRQ_REG(S2MPS11_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 85 + 86 + REGMAP_IRQ_REG(S2MPS11_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 87 + REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 88 + REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 89 + REGMAP_IRQ_REG(S2MPS11_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 90 + REGMAP_IRQ_REG(S2MPS11_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 91 + REGMAP_IRQ_REG(S2MPS11_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 92 + 93 + REGMAP_IRQ_REG(S2MPS11_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 94 + REGMAP_IRQ_REG(S2MPS11_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 85 95 }; 86 96 87 97 static const struct regmap_irq s2mps14_irqs[] = { 88 - [S2MPS14_IRQ_PWRONF] = { 89 - .reg_offset = 0, 90 - .mask = S2MPS11_IRQ_PWRONF_MASK, 91 - }, 92 - [S2MPS14_IRQ_PWRONR] = { 93 - .reg_offset = 0, 94 - .mask = S2MPS11_IRQ_PWRONR_MASK, 95 - }, 96 - [S2MPS14_IRQ_JIGONBF] = { 97 - .reg_offset = 0, 98 - .mask = S2MPS11_IRQ_JIGONBF_MASK, 99 - }, 100 - [S2MPS14_IRQ_JIGONBR] = { 101 - .reg_offset = 0, 102 - .mask = S2MPS11_IRQ_JIGONBR_MASK, 103 - }, 104 - [S2MPS14_IRQ_ACOKBF] = { 105 - .reg_offset = 0, 106 - .mask = S2MPS11_IRQ_ACOKBF_MASK, 107 - }, 108 - [S2MPS14_IRQ_ACOKBR] = { 109 - .reg_offset = 0, 110 - .mask = S2MPS11_IRQ_ACOKBR_MASK, 111 - }, 112 - [S2MPS14_IRQ_PWRON1S] = { 113 - .reg_offset = 0, 114 - .mask = S2MPS11_IRQ_PWRON1S_MASK, 115 - }, 116 - [S2MPS14_IRQ_MRB] = { 117 - .reg_offset = 0, 118 - .mask = S2MPS11_IRQ_MRB_MASK, 119 - }, 120 - [S2MPS14_IRQ_RTC60S] = { 121 - .reg_offset = 1, 122 - .mask = S2MPS11_IRQ_RTC60S_MASK, 123 - }, 124 - [S2MPS14_IRQ_RTCA1] = { 125 - .reg_offset = 1, 126 - .mask = S2MPS11_IRQ_RTCA1_MASK, 127 - }, 128 - [S2MPS14_IRQ_RTCA0] = { 129 - .reg_offset = 1, 130 - .mask = S2MPS11_IRQ_RTCA0_MASK, 131 - }, 132 - [S2MPS14_IRQ_SMPL] = { 133 - .reg_offset = 1, 134 - .mask = S2MPS11_IRQ_SMPL_MASK, 135 - }, 136 - [S2MPS14_IRQ_RTC1S] = { 137 - .reg_offset = 1, 138 - .mask = S2MPS11_IRQ_RTC1S_MASK, 139 - }, 140 - [S2MPS14_IRQ_WTSR] = { 141 - .reg_offset = 1, 142 - .mask = S2MPS11_IRQ_WTSR_MASK, 143 - }, 144 - [S2MPS14_IRQ_INT120C] = { 145 - .reg_offset = 2, 146 - .mask = S2MPS11_IRQ_INT120C_MASK, 147 - }, 148 - [S2MPS14_IRQ_INT140C] = { 149 - .reg_offset = 2, 150 - .mask = S2MPS11_IRQ_INT140C_MASK, 151 - }, 152 - [S2MPS14_IRQ_TSD] = { 153 - .reg_offset = 2, 154 - .mask = S2MPS14_IRQ_TSD_MASK, 155 - }, 98 + REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 99 + REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 100 + REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 101 + REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 102 + REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 103 + REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 104 + REGMAP_IRQ_REG(S2MPS14_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 105 + REGMAP_IRQ_REG(S2MPS14_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 106 + 107 + REGMAP_IRQ_REG(S2MPS14_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 108 + REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 109 + REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 110 + REGMAP_IRQ_REG(S2MPS14_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 111 + REGMAP_IRQ_REG(S2MPS14_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 112 + REGMAP_IRQ_REG(S2MPS14_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 113 + 114 + REGMAP_IRQ_REG(S2MPS14_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 115 + REGMAP_IRQ_REG(S2MPS14_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 116 + REGMAP_IRQ_REG(S2MPS14_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK), 156 117 }; 157 118 158 119 static const struct regmap_irq s2mpu02_irqs[] = { 159 - [S2MPU02_IRQ_PWRONF] = { 160 - .reg_offset = 0, 161 - .mask = S2MPS11_IRQ_PWRONF_MASK, 162 - }, 163 - [S2MPU02_IRQ_PWRONR] = { 164 - .reg_offset = 0, 165 - .mask = S2MPS11_IRQ_PWRONR_MASK, 166 - }, 167 - [S2MPU02_IRQ_JIGONBF] = { 168 - .reg_offset = 0, 169 - .mask = S2MPS11_IRQ_JIGONBF_MASK, 170 - }, 171 - [S2MPU02_IRQ_JIGONBR] = { 172 - .reg_offset = 0, 173 - .mask = S2MPS11_IRQ_JIGONBR_MASK, 174 - }, 175 - [S2MPU02_IRQ_ACOKBF] = { 176 - .reg_offset = 0, 177 - .mask = S2MPS11_IRQ_ACOKBF_MASK, 178 - }, 179 - [S2MPU02_IRQ_ACOKBR] = { 180 - .reg_offset = 0, 181 - .mask = S2MPS11_IRQ_ACOKBR_MASK, 182 - }, 183 - [S2MPU02_IRQ_PWRON1S] = { 184 - .reg_offset = 0, 185 - .mask = S2MPS11_IRQ_PWRON1S_MASK, 186 - }, 187 - [S2MPU02_IRQ_MRB] = { 188 - .reg_offset = 0, 189 - .mask = S2MPS11_IRQ_MRB_MASK, 190 - }, 191 - [S2MPU02_IRQ_RTC60S] = { 192 - .reg_offset = 1, 193 - .mask = S2MPS11_IRQ_RTC60S_MASK, 194 - }, 195 - [S2MPU02_IRQ_RTCA1] = { 196 - .reg_offset = 1, 197 - .mask = S2MPS11_IRQ_RTCA1_MASK, 198 - }, 199 - [S2MPU02_IRQ_RTCA0] = { 200 - .reg_offset = 1, 201 - .mask = S2MPS11_IRQ_RTCA0_MASK, 202 - }, 203 - [S2MPU02_IRQ_SMPL] = { 204 - .reg_offset = 1, 205 - .mask = S2MPS11_IRQ_SMPL_MASK, 206 - }, 207 - [S2MPU02_IRQ_RTC1S] = { 208 - .reg_offset = 1, 209 - .mask = S2MPS11_IRQ_RTC1S_MASK, 210 - }, 211 - [S2MPU02_IRQ_WTSR] = { 212 - .reg_offset = 1, 213 - .mask = S2MPS11_IRQ_WTSR_MASK, 214 - }, 215 - [S2MPU02_IRQ_INT120C] = { 216 - .reg_offset = 2, 217 - .mask = S2MPS11_IRQ_INT120C_MASK, 218 - }, 219 - [S2MPU02_IRQ_INT140C] = { 220 - .reg_offset = 2, 221 - .mask = S2MPS11_IRQ_INT140C_MASK, 222 - }, 223 - [S2MPU02_IRQ_TSD] = { 224 - .reg_offset = 2, 225 - .mask = S2MPS14_IRQ_TSD_MASK, 226 - }, 120 + REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 121 + REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 122 + REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 123 + REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 124 + REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 125 + REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 126 + REGMAP_IRQ_REG(S2MPU02_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 127 + REGMAP_IRQ_REG(S2MPU02_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 128 + 129 + REGMAP_IRQ_REG(S2MPU02_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 130 + REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 131 + REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 132 + REGMAP_IRQ_REG(S2MPU02_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 133 + REGMAP_IRQ_REG(S2MPU02_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 134 + REGMAP_IRQ_REG(S2MPU02_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 135 + 136 + REGMAP_IRQ_REG(S2MPU02_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 137 + REGMAP_IRQ_REG(S2MPU02_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 138 + REGMAP_IRQ_REG(S2MPU02_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK), 227 139 }; 228 140 229 141 static const struct regmap_irq s2mpu05_irqs[] = { ··· 159 247 }; 160 248 161 249 static const struct regmap_irq s5m8767_irqs[] = { 162 - [S5M8767_IRQ_PWRR] = { 163 - .reg_offset = 0, 164 - .mask = S5M8767_IRQ_PWRR_MASK, 165 - }, 166 - [S5M8767_IRQ_PWRF] = { 167 - .reg_offset = 0, 168 - .mask = S5M8767_IRQ_PWRF_MASK, 169 - }, 170 - [S5M8767_IRQ_PWR1S] = { 171 - .reg_offset = 0, 172 - .mask = S5M8767_IRQ_PWR1S_MASK, 173 - }, 174 - [S5M8767_IRQ_JIGR] = { 175 - .reg_offset = 0, 176 - .mask = S5M8767_IRQ_JIGR_MASK, 177 - }, 178 - [S5M8767_IRQ_JIGF] = { 179 - .reg_offset = 0, 180 - .mask = S5M8767_IRQ_JIGF_MASK, 181 - }, 182 - [S5M8767_IRQ_LOWBAT2] = { 183 - .reg_offset = 0, 184 - .mask = S5M8767_IRQ_LOWBAT2_MASK, 185 - }, 186 - [S5M8767_IRQ_LOWBAT1] = { 187 - .reg_offset = 0, 188 - .mask = S5M8767_IRQ_LOWBAT1_MASK, 189 - }, 190 - [S5M8767_IRQ_MRB] = { 191 - .reg_offset = 1, 192 - .mask = S5M8767_IRQ_MRB_MASK, 193 - }, 194 - [S5M8767_IRQ_DVSOK2] = { 195 - .reg_offset = 1, 196 - .mask = S5M8767_IRQ_DVSOK2_MASK, 197 - }, 198 - [S5M8767_IRQ_DVSOK3] = { 199 - .reg_offset = 1, 200 - .mask = S5M8767_IRQ_DVSOK3_MASK, 201 - }, 202 - [S5M8767_IRQ_DVSOK4] = { 203 - .reg_offset = 1, 204 - .mask = S5M8767_IRQ_DVSOK4_MASK, 205 - }, 206 - [S5M8767_IRQ_RTC60S] = { 207 - .reg_offset = 2, 208 - .mask = S5M8767_IRQ_RTC60S_MASK, 209 - }, 210 - [S5M8767_IRQ_RTCA1] = { 211 - .reg_offset = 2, 212 - .mask = S5M8767_IRQ_RTCA1_MASK, 213 - }, 214 - [S5M8767_IRQ_RTCA2] = { 215 - .reg_offset = 2, 216 - .mask = S5M8767_IRQ_RTCA2_MASK, 217 - }, 218 - [S5M8767_IRQ_SMPL] = { 219 - .reg_offset = 2, 220 - .mask = S5M8767_IRQ_SMPL_MASK, 221 - }, 222 - [S5M8767_IRQ_RTC1S] = { 223 - .reg_offset = 2, 224 - .mask = S5M8767_IRQ_RTC1S_MASK, 225 - }, 226 - [S5M8767_IRQ_WTSR] = { 227 - .reg_offset = 2, 228 - .mask = S5M8767_IRQ_WTSR_MASK, 229 - }, 250 + REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK), 251 + REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK), 252 + REGMAP_IRQ_REG(S5M8767_IRQ_PWR1S, 0, S5M8767_IRQ_PWR1S_MASK), 253 + REGMAP_IRQ_REG(S5M8767_IRQ_JIGR, 0, S5M8767_IRQ_JIGR_MASK), 254 + REGMAP_IRQ_REG(S5M8767_IRQ_JIGF, 0, S5M8767_IRQ_JIGF_MASK), 255 + REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT2, 0, S5M8767_IRQ_LOWBAT2_MASK), 256 + REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT1, 0, S5M8767_IRQ_LOWBAT1_MASK), 257 + 258 + REGMAP_IRQ_REG(S5M8767_IRQ_MRB, 1, S5M8767_IRQ_MRB_MASK), 259 + REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK2, 1, S5M8767_IRQ_DVSOK2_MASK), 260 + REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK3, 1, S5M8767_IRQ_DVSOK3_MASK), 261 + REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK4, 1, S5M8767_IRQ_DVSOK4_MASK), 262 + 263 + REGMAP_IRQ_REG(S5M8767_IRQ_RTC60S, 2, S5M8767_IRQ_RTC60S_MASK), 264 + REGMAP_IRQ_REG(S5M8767_IRQ_RTCA1, 2, S5M8767_IRQ_RTCA1_MASK), 265 + REGMAP_IRQ_REG(S5M8767_IRQ_RTCA2, 2, S5M8767_IRQ_RTCA2_MASK), 266 + REGMAP_IRQ_REG(S5M8767_IRQ_SMPL, 2, S5M8767_IRQ_SMPL_MASK), 267 + REGMAP_IRQ_REG(S5M8767_IRQ_RTC1S, 2, S5M8767_IRQ_RTC1S_MASK), 268 + REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK), 269 + }; 270 + 271 + /* All S2MPG10 interrupt sources are read-only and don't require clearing */ 272 + static const struct regmap_irq_chip s2mpg10_irq_chip = { 273 + .name = "s2mpg10", 274 + .irqs = s2mpg10_irqs, 275 + .num_irqs = ARRAY_SIZE(s2mpg10_irqs), 276 + .num_regs = 6, 277 + .status_base = S2MPG10_PMIC_INT1, 278 + .mask_base = S2MPG10_PMIC_INT1M, 230 279 }; 231 280 232 281 static const struct regmap_irq_chip s2mps11_irq_chip = { ··· 255 382 256 383 int sec_irq_init(struct sec_pmic_dev *sec_pmic) 257 384 { 258 - int ret = 0; 259 - int type = sec_pmic->device_type; 260 385 const struct regmap_irq_chip *sec_irq_chip; 386 + int ret; 261 387 262 - if (!sec_pmic->irq) { 263 - dev_warn(sec_pmic->dev, 264 - "No interrupt specified, no interrupts\n"); 265 - return 0; 266 - } 267 - 268 - switch (type) { 388 + switch (sec_pmic->device_type) { 269 389 case S5M8767X: 270 390 sec_irq_chip = &s5m8767_irq_chip; 271 391 break; 392 + case S2DOS05: 393 + return 0; 272 394 case S2MPA01: 273 395 sec_irq_chip = &s2mps14_irq_chip; 396 + break; 397 + case S2MPG10: 398 + sec_irq_chip = &s2mpg10_irq_chip; 274 399 break; 275 400 case S2MPS11X: 276 401 sec_irq_chip = &s2mps11_irq_chip; ··· 289 418 sec_irq_chip = &s2mpu05_irq_chip; 290 419 break; 291 420 default: 292 - dev_err(sec_pmic->dev, "Unknown device type %lu\n", 293 - sec_pmic->device_type); 294 - return -EINVAL; 421 + return dev_err_probe(sec_pmic->dev, -EINVAL, 422 + "Unsupported device type %d\n", 423 + sec_pmic->device_type); 424 + } 425 + 426 + if (!sec_pmic->irq) { 427 + dev_warn(sec_pmic->dev, 428 + "No interrupt specified, no interrupts\n"); 429 + return 0; 295 430 } 296 431 297 432 ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic, 298 433 sec_pmic->irq, IRQF_ONESHOT, 299 434 0, sec_irq_chip, &sec_pmic->irq_data); 300 - if (ret != 0) { 301 - dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret); 302 - return ret; 303 - } 435 + if (ret) 436 + return dev_err_probe(sec_pmic->dev, ret, 437 + "Failed to add %s IRQ chip\n", 438 + sec_irq_chip->name); 304 439 305 440 /* 306 441 * The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11 ··· 316 439 317 440 return 0; 318 441 } 319 - EXPORT_SYMBOL_GPL(sec_irq_init); 320 - 321 - MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); 322 - MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>"); 323 - MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>"); 324 - MODULE_DESCRIPTION("Interrupt support for the S5M MFD"); 325 - MODULE_LICENSE("GPL");
+5 -45
drivers/mfd/sm501.c
··· 631 631 632 632 EXPORT_SYMBOL_GPL(sm501_set_clock); 633 633 634 - /* sm501_find_clock 635 - * 636 - * finds the closest available frequency for a given clock 637 - */ 638 - 639 - unsigned long sm501_find_clock(struct device *dev, 640 - int clksrc, 641 - unsigned long req_freq) 642 - { 643 - struct sm501_devdata *sm = dev_get_drvdata(dev); 644 - unsigned long sm501_freq; /* the frequency achieveable by the 501 */ 645 - struct sm501_clock to; 646 - 647 - switch (clksrc) { 648 - case SM501_CLOCK_P2XCLK: 649 - if (sm->rev >= 0xC0) { 650 - /* SM502 -> use the programmable PLL */ 651 - sm501_freq = (sm501_calc_pll(2 * req_freq, 652 - &to, 5) / 2); 653 - } else { 654 - sm501_freq = (sm501_select_clock(2 * req_freq, 655 - &to, 5) / 2); 656 - } 657 - break; 658 - 659 - case SM501_CLOCK_V2XCLK: 660 - sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 661 - break; 662 - 663 - case SM501_CLOCK_MCLK: 664 - case SM501_CLOCK_M1XCLK: 665 - sm501_freq = sm501_select_clock(req_freq, &to, 3); 666 - break; 667 - 668 - default: 669 - sm501_freq = 0; /* error */ 670 - } 671 - 672 - return sm501_freq; 673 - } 674 - 675 - EXPORT_SYMBOL_GPL(sm501_find_clock); 676 - 677 634 static struct sm501_device *to_sm_device(struct platform_device *pdev) 678 635 { 679 636 return container_of(pdev, struct sm501_device, pdev); ··· 872 915 } 873 916 } 874 917 875 - static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 918 + static int sm501_gpio_set(struct gpio_chip *chip, unsigned int offset, 919 + int value) 876 920 877 921 { 878 922 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); ··· 897 939 sm501_gpio_ensure_gpio(smchip, bit); 898 940 899 941 spin_unlock_irqrestore(&smgpio->lock, save); 942 + 943 + return 0; 900 944 } 901 945 902 946 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) ··· 965 1005 .ngpio = 32, 966 1006 .direction_input = sm501_gpio_input, 967 1007 .direction_output = sm501_gpio_output, 968 - .set = sm501_gpio_set, 1008 + .set_rv = sm501_gpio_set, 969 1009 .get = sm501_gpio_get, 970 1010 }; 971 1011
+4 -1
drivers/mfd/sprd-sc27xx-spi.c
··· 210 210 return ret; 211 211 } 212 212 213 - device_init_wakeup(&spi->dev, true); 213 + ret = devm_device_init_wakeup(&spi->dev); 214 + if (ret) 215 + return dev_err_probe(&spi->dev, ret, "Failed to init wakeup\n"); 216 + 214 217 return 0; 215 218 } 216 219
+32 -1
drivers/mfd/stm32-lptimer.c
··· 6 6 * Inspired by Benjamin Gaignard's stm32-timers driver 7 7 */ 8 8 9 + #include <linux/bitfield.h> 9 10 #include <linux/mfd/stm32-lptimer.h> 10 11 #include <linux/module.h> 11 12 #include <linux/of_platform.h> ··· 50 49 return 0; 51 50 } 52 51 52 + static int stm32_lptimer_detect_hwcfgr(struct stm32_lptimer *ddata) 53 + { 54 + u32 val; 55 + int ret; 56 + 57 + ret = regmap_read(ddata->regmap, STM32_LPTIM_VERR, &ddata->version); 58 + if (ret) 59 + return ret; 60 + 61 + /* Try to guess parameters from HWCFGR: e.g. encoder mode (STM32MP15) */ 62 + ret = regmap_read(ddata->regmap, STM32_LPTIM_HWCFGR1, &val); 63 + if (ret) 64 + return ret; 65 + 66 + /* Fallback to legacy init if HWCFGR isn't present */ 67 + if (!val) 68 + return stm32_lptimer_detect_encoder(ddata); 69 + 70 + ddata->has_encoder = FIELD_GET(STM32_LPTIM_HWCFGR1_ENCODER, val); 71 + 72 + ret = regmap_read(ddata->regmap, STM32_LPTIM_HWCFGR2, &val); 73 + if (ret) 74 + return ret; 75 + 76 + /* Number of capture/compare channels */ 77 + ddata->num_cc_chans = FIELD_GET(STM32_LPTIM_HWCFGR2_CHAN_NUM, val); 78 + 79 + return 0; 80 + } 81 + 53 82 static int stm32_lptimer_probe(struct platform_device *pdev) 54 83 { 55 84 struct device *dev = &pdev->dev; ··· 104 73 if (IS_ERR(ddata->clk)) 105 74 return PTR_ERR(ddata->clk); 106 75 107 - ret = stm32_lptimer_detect_encoder(ddata); 76 + ret = stm32_lptimer_detect_hwcfgr(ddata); 108 77 if (ret) 109 78 return ret; 110 79
+1 -1
drivers/mfd/stmpe-spi.c
··· 129 129 { "stmpe2403", STMPE2403 }, 130 130 { } 131 131 }; 132 - MODULE_DEVICE_TABLE(spi, stmpe_id); 132 + MODULE_DEVICE_TABLE(spi, stmpe_spi_id); 133 133 134 134 static struct spi_driver stmpe_spi_driver = { 135 135 .driver = {
+5 -4
drivers/mfd/tps65010.c
··· 446 446 * offsets 4..5 == LED1/nPG, LED2 (we set one of the non-BLINK modes) 447 447 * offset 6 == vibrator motor driver 448 448 */ 449 - static void 449 + static int 450 450 tps65010_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 451 451 { 452 452 if (offset < 4) ··· 455 455 tps65010_set_led(offset - 3, value ? ON : OFF); 456 456 else 457 457 tps65010_set_vib(value); 458 + 459 + return 0; 458 460 } 459 461 460 462 static int ··· 514 512 if (client->irq > 0) 515 513 free_irq(client->irq, tps); 516 514 cancel_delayed_work_sync(&tps->work); 517 - debugfs_remove(tps->file); 518 515 the_tps = NULL; 519 516 } 520 517 ··· 609 608 610 609 tps65010_work(&tps->work.work); 611 610 612 - tps->file = debugfs_create_file(DRIVER_NAME, S_IRUGO, NULL, 611 + tps->file = debugfs_create_file(DRIVER_NAME, S_IRUGO, client->debugfs, 613 612 tps, DEBUG_FOPS); 614 613 615 614 /* optionally register GPIOs */ ··· 620 619 tps->chip.parent = &client->dev; 621 620 tps->chip.owner = THIS_MODULE; 622 621 623 - tps->chip.set = tps65010_gpio_set; 622 + tps->chip.set_rv = tps65010_gpio_set; 624 623 tps->chip.direction_output = tps65010_output; 625 624 626 625 /* NOTE: only partial support for inputs; nyet IRQs */
+5 -2
drivers/mfd/ucb1x00-core.c
··· 104 104 return ucb1x00_reg_read(ucb, UCB_IO_DATA); 105 105 } 106 106 107 - static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 107 + static int ucb1x00_gpio_set(struct gpio_chip *chip, unsigned int offset, 108 + int value) 108 109 { 109 110 struct ucb1x00 *ucb = gpiochip_get_data(chip); 110 111 unsigned long flags; ··· 120 119 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); 121 120 ucb1x00_disable(ucb); 122 121 spin_unlock_irqrestore(&ucb->io_lock, flags); 122 + 123 + return 0; 123 124 } 124 125 125 126 static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) ··· 570 567 ucb->gpio.owner = THIS_MODULE; 571 568 ucb->gpio.base = pdata->gpio_base; 572 569 ucb->gpio.ngpio = 10; 573 - ucb->gpio.set = ucb1x00_gpio_set; 570 + ucb->gpio.set_rv = ucb1x00_gpio_set; 574 571 ucb->gpio.get = ucb1x00_gpio_get; 575 572 ucb->gpio.direction_input = ucb1x00_gpio_direction_input; 576 573 ucb->gpio.direction_output = ucb1x00_gpio_direction_output;
+192 -25
drivers/pwm/pwm-stm32-lp.c
··· 20 20 struct stm32_pwm_lp { 21 21 struct clk *clk; 22 22 struct regmap *regmap; 23 + unsigned int num_cc_chans; 23 24 }; 24 25 25 26 static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) ··· 31 30 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */ 32 31 #define STM32_LPTIM_MAX_PRESCALER 128 33 32 33 + static int stm32_pwm_lp_update_allowed(struct stm32_pwm_lp *priv, int channel) 34 + { 35 + int ret; 36 + u32 ccmr1; 37 + unsigned long ccmr; 38 + 39 + /* Only one PWM on this LPTIMER: enable, prescaler and reload value can be changed */ 40 + if (!priv->num_cc_chans) 41 + return true; 42 + 43 + ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); 44 + if (ret) 45 + return ret; 46 + ccmr = ccmr1 & (STM32_LPTIM_CC1E | STM32_LPTIM_CC2E); 47 + 48 + /* More than one channel enabled: enable, prescaler or ARR value can't be changed */ 49 + if (bitmap_weight(&ccmr, sizeof(u32) * BITS_PER_BYTE) > 1) 50 + return false; 51 + 52 + /* 53 + * Only one channel is enabled (or none): check status on the other channel, to 54 + * report if enable, prescaler or ARR value can be changed. 55 + */ 56 + if (channel) 57 + return !(ccmr1 & STM32_LPTIM_CC1E); 58 + else 59 + return !(ccmr1 & STM32_LPTIM_CC2E); 60 + } 61 + 62 + static int stm32_pwm_lp_compare_channel_apply(struct stm32_pwm_lp *priv, int channel, 63 + bool enable, enum pwm_polarity polarity) 64 + { 65 + u32 ccmr1, val, mask; 66 + bool reenable; 67 + int ret; 68 + 69 + /* No dedicated CC channel: nothing to do */ 70 + if (!priv->num_cc_chans) 71 + return 0; 72 + 73 + ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); 74 + if (ret) 75 + return ret; 76 + 77 + if (channel) { 78 + /* Must disable CC channel (CCxE) to modify polarity (CCxP), then re-enable */ 79 + reenable = (enable && FIELD_GET(STM32_LPTIM_CC2E, ccmr1)) && 80 + (polarity != FIELD_GET(STM32_LPTIM_CC2P, ccmr1)); 81 + 82 + mask = STM32_LPTIM_CC2SEL | STM32_LPTIM_CC2E | STM32_LPTIM_CC2P; 83 + val = FIELD_PREP(STM32_LPTIM_CC2P, polarity); 84 + val |= FIELD_PREP(STM32_LPTIM_CC2E, enable); 85 + } else { 86 + reenable = (enable && FIELD_GET(STM32_LPTIM_CC1E, ccmr1)) && 87 + (polarity != FIELD_GET(STM32_LPTIM_CC1P, ccmr1)); 88 + 89 + mask = STM32_LPTIM_CC1SEL | STM32_LPTIM_CC1E | STM32_LPTIM_CC1P; 90 + val = FIELD_PREP(STM32_LPTIM_CC1P, polarity); 91 + val |= FIELD_PREP(STM32_LPTIM_CC1E, enable); 92 + } 93 + 94 + if (reenable) { 95 + u32 cfgr, presc; 96 + unsigned long rate; 97 + unsigned int delay_us; 98 + 99 + ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, 100 + channel ? STM32_LPTIM_CC2E : STM32_LPTIM_CC1E, 0); 101 + if (ret) 102 + return ret; 103 + /* 104 + * After a write to the LPTIM_CCMRx register, a new write operation can only be 105 + * performed after a delay of at least (PRESC × 3) clock cycles 106 + */ 107 + ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); 108 + if (ret) 109 + return ret; 110 + presc = FIELD_GET(STM32_LPTIM_PRESC, cfgr); 111 + rate = clk_get_rate(priv->clk) >> presc; 112 + if (!rate) 113 + return -EINVAL; 114 + delay_us = 3 * DIV_ROUND_UP(USEC_PER_SEC, rate); 115 + usleep_range(delay_us, delay_us * 2); 116 + } 117 + 118 + return regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, mask, val); 119 + } 120 + 34 121 static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, 35 122 const struct pwm_state *state) 36 123 { 37 124 struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); 38 125 unsigned long long prd, div, dty; 39 126 struct pwm_state cstate; 40 - u32 val, mask, cfgr, presc = 0; 127 + u32 arr, val, mask, cfgr, presc = 0; 41 128 bool reenable; 42 129 int ret; 43 130 ··· 134 45 135 46 if (!state->enabled) { 136 47 if (cstate.enabled) { 137 - /* Disable LP timer */ 138 - ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); 48 + /* Disable CC channel if any */ 49 + ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, false, 50 + state->polarity); 139 51 if (ret) 140 52 return ret; 53 + ret = regmap_write(priv->regmap, pwm->hwpwm ? 54 + STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, 0); 55 + if (ret) 56 + return ret; 57 + 58 + /* Check if the timer can be disabled */ 59 + ret = stm32_pwm_lp_update_allowed(priv, pwm->hwpwm); 60 + if (ret < 0) 61 + return ret; 62 + 63 + if (ret) { 64 + /* Disable LP timer */ 65 + ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); 66 + if (ret) 67 + return ret; 68 + } 69 + 141 70 /* disable clock to PWM counter */ 142 71 clk_disable(priv->clk); 143 72 } ··· 186 79 dty = prd * state->duty_cycle; 187 80 do_div(dty, state->period); 188 81 82 + ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); 83 + if (ret) 84 + return ret; 85 + 86 + /* 87 + * When there are several channels, they share the same prescaler and reload value. 88 + * Check if this can be changed, or the values are the same for all channels. 89 + */ 90 + if (!stm32_pwm_lp_update_allowed(priv, pwm->hwpwm)) { 91 + ret = regmap_read(priv->regmap, STM32_LPTIM_ARR, &arr); 92 + if (ret) 93 + return ret; 94 + 95 + if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || (arr != prd - 1)) 96 + return -EBUSY; 97 + } 98 + 189 99 if (!cstate.enabled) { 190 100 /* enable clock to drive PWM counter */ 191 101 ret = clk_enable(priv->clk); ··· 210 86 return ret; 211 87 } 212 88 213 - ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); 214 - if (ret) 215 - goto err; 216 - 217 89 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || 218 - (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) { 90 + ((FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity) && !priv->num_cc_chans)) { 219 91 val = FIELD_PREP(STM32_LPTIM_PRESC, presc); 220 - val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); 221 - mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; 92 + mask = STM32_LPTIM_PRESC; 93 + 94 + if (!priv->num_cc_chans) { 95 + /* 96 + * WAVPOL bit is only available when no capature compare channel is used, 97 + * e.g. on LPTIMER instances that have only one output channel. CCMR1 is 98 + * used otherwise. 99 + */ 100 + val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); 101 + mask |= STM32_LPTIM_WAVPOL; 102 + } 222 103 223 104 /* Must disable LP timer to modify CFGR */ 224 105 reenable = true; ··· 249 120 if (ret) 250 121 goto err; 251 122 252 - ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty)); 123 + /* Write CMP/CCRx register and ensure it's been properly written */ 124 + ret = regmap_write(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, 125 + prd - (1 + dty)); 253 126 if (ret) 254 127 goto err; 255 128 256 - /* ensure CMP & ARR registers are properly written */ 257 - ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, 129 + /* ensure ARR and CMP/CCRx registers are properly written */ 130 + ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, pwm->hwpwm ? 131 + (val & STM32_LPTIM_CMP2_ARROK) == STM32_LPTIM_CMP2_ARROK : 258 132 (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, 259 133 100, 1000); 260 134 if (ret) { 261 135 dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n"); 262 136 goto err; 263 137 } 264 - ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, 265 - STM32_LPTIM_CMPOKCF_ARROKCF); 138 + ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, pwm->hwpwm ? 139 + STM32_LPTIM_CMP2OKCF_ARROKCF : STM32_LPTIM_CMPOKCF_ARROKCF); 140 + if (ret) 141 + goto err; 142 + 143 + ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, true, state->polarity); 266 144 if (ret) 267 145 goto err; 268 146 ··· 297 161 { 298 162 struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); 299 163 unsigned long rate = clk_get_rate(priv->clk); 300 - u32 val, presc, prd; 164 + u32 val, presc, prd, ccmr1; 165 + bool enabled; 301 166 u64 tmp; 302 167 303 168 regmap_read(priv->regmap, STM32_LPTIM_CR, &val); 304 - state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); 169 + enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); 170 + if (priv->num_cc_chans) { 171 + /* There's a CC chan, need to also check if it's enabled */ 172 + regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); 173 + if (pwm->hwpwm) 174 + enabled &= !!FIELD_GET(STM32_LPTIM_CC2E, ccmr1); 175 + else 176 + enabled &= !!FIELD_GET(STM32_LPTIM_CC1E, ccmr1); 177 + } 178 + state->enabled = enabled; 179 + 305 180 /* Keep PWM counter clock refcount in sync with PWM initial state */ 306 181 if (state->enabled) { 307 182 int ret = clk_enable(priv->clk); ··· 323 176 324 177 regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val); 325 178 presc = FIELD_GET(STM32_LPTIM_PRESC, val); 326 - state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); 179 + if (priv->num_cc_chans) { 180 + if (pwm->hwpwm) 181 + state->polarity = FIELD_GET(STM32_LPTIM_CC2P, ccmr1); 182 + else 183 + state->polarity = FIELD_GET(STM32_LPTIM_CC1P, ccmr1); 184 + } else { 185 + state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); 186 + } 327 187 328 188 regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd); 329 189 tmp = prd + 1; 330 190 tmp = (tmp << presc) * NSEC_PER_SEC; 331 191 state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); 332 192 333 - regmap_read(priv->regmap, STM32_LPTIM_CMP, &val); 193 + regmap_read(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, &val); 334 194 tmp = prd - val; 335 195 tmp = (tmp << presc) * NSEC_PER_SEC; 336 196 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); ··· 355 201 struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent); 356 202 struct stm32_pwm_lp *priv; 357 203 struct pwm_chip *chip; 204 + unsigned int npwm; 358 205 int ret; 359 206 360 - chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*priv)); 207 + if (!ddata->num_cc_chans) { 208 + /* No dedicated CC channel, so there's only one PWM channel */ 209 + npwm = 1; 210 + } else { 211 + /* There are dedicated CC channels, each with one PWM output */ 212 + npwm = ddata->num_cc_chans; 213 + } 214 + 215 + chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*priv)); 361 216 if (IS_ERR(chip)) 362 217 return PTR_ERR(chip); 363 218 priv = to_stm32_pwm_lp(chip); 364 219 365 220 priv->regmap = ddata->regmap; 366 221 priv->clk = ddata->clk; 222 + priv->num_cc_chans = ddata->num_cc_chans; 367 223 chip->ops = &stm32_pwm_lp_ops; 368 224 369 225 ret = devm_pwmchip_add(&pdev->dev, chip); ··· 389 225 { 390 226 struct pwm_chip *chip = dev_get_drvdata(dev); 391 227 struct pwm_state state; 228 + unsigned int i; 392 229 393 - pwm_get_state(&chip->pwms[0], &state); 394 - if (state.enabled) { 395 - dev_err(dev, "The consumer didn't stop us (%s)\n", 396 - chip->pwms[0].label); 397 - return -EBUSY; 230 + for (i = 0; i < chip->npwm; i++) { 231 + pwm_get_state(&chip->pwms[i], &state); 232 + if (state.enabled) { 233 + dev_err(dev, "The consumer didn't stop us (%s)\n", 234 + chip->pwms[i].label); 235 + return -EBUSY; 236 + } 398 237 } 399 238 400 239 return pinctrl_pm_select_sleep_state(dev);
+1078 -267
drivers/regulator/bcm590xx-regulator.c
··· 18 18 #include <linux/regulator/of_regulator.h> 19 19 #include <linux/slab.h> 20 20 21 - /* I2C slave 0 registers */ 22 - #define BCM590XX_RFLDOPMCTRL1 0x60 23 - #define BCM590XX_IOSR1PMCTRL1 0x7a 24 - #define BCM590XX_IOSR2PMCTRL1 0x7c 25 - #define BCM590XX_CSRPMCTRL1 0x7e 26 - #define BCM590XX_SDSR1PMCTRL1 0x82 27 - #define BCM590XX_SDSR2PMCTRL1 0x86 28 - #define BCM590XX_MSRPMCTRL1 0x8a 29 - #define BCM590XX_VSRPMCTRL1 0x8e 30 - #define BCM590XX_RFLDOCTRL 0x96 31 - #define BCM590XX_CSRVOUT1 0xc0 32 - 33 - /* I2C slave 1 registers */ 34 - #define BCM590XX_GPLDO5PMCTRL1 0x16 35 - #define BCM590XX_GPLDO6PMCTRL1 0x18 36 - #define BCM590XX_GPLDO1CTRL 0x1a 37 - #define BCM590XX_GPLDO2CTRL 0x1b 38 - #define BCM590XX_GPLDO3CTRL 0x1c 39 - #define BCM590XX_GPLDO4CTRL 0x1d 40 - #define BCM590XX_GPLDO5CTRL 0x1e 41 - #define BCM590XX_GPLDO6CTRL 0x1f 42 - #define BCM590XX_OTG_CTRL 0x40 43 - #define BCM590XX_GPLDO1PMCTRL1 0x57 44 - #define BCM590XX_GPLDO2PMCTRL1 0x59 45 - #define BCM590XX_GPLDO3PMCTRL1 0x5b 46 - #define BCM590XX_GPLDO4PMCTRL1 0x5d 47 - 48 21 #define BCM590XX_REG_ENABLE BIT(7) 49 22 #define BCM590XX_VBUS_ENABLE BIT(2) 50 23 #define BCM590XX_LDO_VSEL_MASK GENMASK(5, 3) 51 24 #define BCM590XX_SR_VSEL_MASK GENMASK(5, 0) 52 25 53 - /* 54 - * RFLDO to VSR regulators are 55 - * accessed via I2C slave 0 56 - */ 57 - 58 - /* LDO regulator IDs */ 59 - #define BCM590XX_REG_RFLDO 0 60 - #define BCM590XX_REG_CAMLDO1 1 61 - #define BCM590XX_REG_CAMLDO2 2 62 - #define BCM590XX_REG_SIMLDO1 3 63 - #define BCM590XX_REG_SIMLDO2 4 64 - #define BCM590XX_REG_SDLDO 5 65 - #define BCM590XX_REG_SDXLDO 6 66 - #define BCM590XX_REG_MMCLDO1 7 67 - #define BCM590XX_REG_MMCLDO2 8 68 - #define BCM590XX_REG_AUDLDO 9 69 - #define BCM590XX_REG_MICLDO 10 70 - #define BCM590XX_REG_USBLDO 11 71 - #define BCM590XX_REG_VIBLDO 12 72 - 73 - /* DCDC regulator IDs */ 74 - #define BCM590XX_REG_CSR 13 75 - #define BCM590XX_REG_IOSR1 14 76 - #define BCM590XX_REG_IOSR2 15 77 - #define BCM590XX_REG_MSR 16 78 - #define BCM590XX_REG_SDSR1 17 79 - #define BCM590XX_REG_SDSR2 18 80 - #define BCM590XX_REG_VSR 19 81 - 82 - /* 83 - * GPLDO1 to VBUS regulators are 84 - * accessed via I2C slave 1 85 - */ 86 - 87 - #define BCM590XX_REG_GPLDO1 20 88 - #define BCM590XX_REG_GPLDO2 21 89 - #define BCM590XX_REG_GPLDO3 22 90 - #define BCM590XX_REG_GPLDO4 23 91 - #define BCM590XX_REG_GPLDO5 24 92 - #define BCM590XX_REG_GPLDO6 25 93 - #define BCM590XX_REG_VBUS 26 94 - 95 - #define BCM590XX_NUM_REGS 27 96 - 97 - #define BCM590XX_REG_IS_LDO(n) (n < BCM590XX_REG_CSR) 98 - #define BCM590XX_REG_IS_GPLDO(n) \ 99 - ((n > BCM590XX_REG_VSR) && (n < BCM590XX_REG_VBUS)) 100 - #define BCM590XX_REG_IS_VBUS(n) (n == BCM590XX_REG_VBUS) 101 - 102 - /* LDO group A: supported voltages in microvolts */ 103 - static const unsigned int ldo_a_table[] = { 104 - 1200000, 1800000, 2500000, 2700000, 2800000, 105 - 2900000, 3000000, 3300000, 26 + enum bcm590xx_reg_type { 27 + BCM590XX_REG_TYPE_LDO, 28 + BCM590XX_REG_TYPE_GPLDO, 29 + BCM590XX_REG_TYPE_SR, 30 + BCM590XX_REG_TYPE_VBUS 106 31 }; 107 32 108 - /* LDO group C: supported voltages in microvolts */ 109 - static const unsigned int ldo_c_table[] = { 110 - 3100000, 1800000, 2500000, 2700000, 2800000, 111 - 2900000, 3000000, 3300000, 112 - }; 113 - 114 - static const unsigned int ldo_vbus[] = { 115 - 5000000, 116 - }; 117 - 118 - /* DCDC group CSR: supported voltages in microvolts */ 119 - static const struct linear_range dcdc_csr_ranges[] = { 120 - REGULATOR_LINEAR_RANGE(860000, 2, 50, 10000), 121 - REGULATOR_LINEAR_RANGE(1360000, 51, 55, 20000), 122 - REGULATOR_LINEAR_RANGE(900000, 56, 63, 0), 123 - }; 124 - 125 - /* DCDC group IOSR1: supported voltages in microvolts */ 126 - static const struct linear_range dcdc_iosr1_ranges[] = { 127 - REGULATOR_LINEAR_RANGE(860000, 2, 51, 10000), 128 - REGULATOR_LINEAR_RANGE(1500000, 52, 52, 0), 129 - REGULATOR_LINEAR_RANGE(1800000, 53, 53, 0), 130 - REGULATOR_LINEAR_RANGE(900000, 54, 63, 0), 131 - }; 132 - 133 - /* DCDC group SDSR1: supported voltages in microvolts */ 134 - static const struct linear_range dcdc_sdsr1_ranges[] = { 135 - REGULATOR_LINEAR_RANGE(860000, 2, 50, 10000), 136 - REGULATOR_LINEAR_RANGE(1340000, 51, 51, 0), 137 - REGULATOR_LINEAR_RANGE(900000, 52, 63, 0), 138 - }; 139 - 140 - struct bcm590xx_info { 141 - const char *name; 142 - const char *vin_name; 143 - u8 n_voltages; 144 - const unsigned int *volt_table; 145 - u8 n_linear_ranges; 146 - const struct linear_range *linear_ranges; 147 - }; 148 - 149 - #define BCM590XX_REG_TABLE(_name, _table) \ 150 - { \ 151 - .name = #_name, \ 152 - .n_voltages = ARRAY_SIZE(_table), \ 153 - .volt_table = _table, \ 154 - } 155 - 156 - #define BCM590XX_REG_RANGES(_name, _ranges) \ 157 - { \ 158 - .name = #_name, \ 159 - .n_voltages = 64, \ 160 - .n_linear_ranges = ARRAY_SIZE(_ranges), \ 161 - .linear_ranges = _ranges, \ 162 - } 163 - 164 - static struct bcm590xx_info bcm590xx_regs[] = { 165 - BCM590XX_REG_TABLE(rfldo, ldo_a_table), 166 - BCM590XX_REG_TABLE(camldo1, ldo_c_table), 167 - BCM590XX_REG_TABLE(camldo2, ldo_c_table), 168 - BCM590XX_REG_TABLE(simldo1, ldo_a_table), 169 - BCM590XX_REG_TABLE(simldo2, ldo_a_table), 170 - BCM590XX_REG_TABLE(sdldo, ldo_c_table), 171 - BCM590XX_REG_TABLE(sdxldo, ldo_a_table), 172 - BCM590XX_REG_TABLE(mmcldo1, ldo_a_table), 173 - BCM590XX_REG_TABLE(mmcldo2, ldo_a_table), 174 - BCM590XX_REG_TABLE(audldo, ldo_a_table), 175 - BCM590XX_REG_TABLE(micldo, ldo_a_table), 176 - BCM590XX_REG_TABLE(usbldo, ldo_a_table), 177 - BCM590XX_REG_TABLE(vibldo, ldo_c_table), 178 - BCM590XX_REG_RANGES(csr, dcdc_csr_ranges), 179 - BCM590XX_REG_RANGES(iosr1, dcdc_iosr1_ranges), 180 - BCM590XX_REG_RANGES(iosr2, dcdc_iosr1_ranges), 181 - BCM590XX_REG_RANGES(msr, dcdc_iosr1_ranges), 182 - BCM590XX_REG_RANGES(sdsr1, dcdc_sdsr1_ranges), 183 - BCM590XX_REG_RANGES(sdsr2, dcdc_iosr1_ranges), 184 - BCM590XX_REG_RANGES(vsr, dcdc_iosr1_ranges), 185 - BCM590XX_REG_TABLE(gpldo1, ldo_a_table), 186 - BCM590XX_REG_TABLE(gpldo2, ldo_a_table), 187 - BCM590XX_REG_TABLE(gpldo3, ldo_a_table), 188 - BCM590XX_REG_TABLE(gpldo4, ldo_a_table), 189 - BCM590XX_REG_TABLE(gpldo5, ldo_a_table), 190 - BCM590XX_REG_TABLE(gpldo6, ldo_a_table), 191 - BCM590XX_REG_TABLE(vbus, ldo_vbus), 33 + struct bcm590xx_reg_data { 34 + enum bcm590xx_reg_type type; 35 + enum bcm590xx_regmap_type regmap; 36 + const struct regulator_desc desc; 192 37 }; 193 38 194 39 struct bcm590xx_reg { 195 - struct regulator_desc *desc; 196 40 struct bcm590xx *mfd; 41 + unsigned int n_regulators; 42 + const struct bcm590xx_reg_data *regs; 197 43 }; 198 - 199 - static int bcm590xx_get_vsel_register(int id) 200 - { 201 - if (BCM590XX_REG_IS_LDO(id)) 202 - return BCM590XX_RFLDOCTRL + id; 203 - else if (BCM590XX_REG_IS_GPLDO(id)) 204 - return BCM590XX_GPLDO1CTRL + id; 205 - else 206 - return BCM590XX_CSRVOUT1 + (id - BCM590XX_REG_CSR) * 3; 207 - } 208 - 209 - static int bcm590xx_get_enable_register(int id) 210 - { 211 - int reg = 0; 212 - 213 - if (BCM590XX_REG_IS_LDO(id)) 214 - reg = BCM590XX_RFLDOPMCTRL1 + id * 2; 215 - else if (BCM590XX_REG_IS_GPLDO(id)) 216 - reg = BCM590XX_GPLDO1PMCTRL1 + id * 2; 217 - else 218 - switch (id) { 219 - case BCM590XX_REG_CSR: 220 - reg = BCM590XX_CSRPMCTRL1; 221 - break; 222 - case BCM590XX_REG_IOSR1: 223 - reg = BCM590XX_IOSR1PMCTRL1; 224 - break; 225 - case BCM590XX_REG_IOSR2: 226 - reg = BCM590XX_IOSR2PMCTRL1; 227 - break; 228 - case BCM590XX_REG_MSR: 229 - reg = BCM590XX_MSRPMCTRL1; 230 - break; 231 - case BCM590XX_REG_SDSR1: 232 - reg = BCM590XX_SDSR1PMCTRL1; 233 - break; 234 - case BCM590XX_REG_SDSR2: 235 - reg = BCM590XX_SDSR2PMCTRL1; 236 - break; 237 - case BCM590XX_REG_VSR: 238 - reg = BCM590XX_VSRPMCTRL1; 239 - break; 240 - case BCM590XX_REG_VBUS: 241 - reg = BCM590XX_OTG_CTRL; 242 - break; 243 - } 244 - 245 - 246 - return reg; 247 - } 248 44 249 45 static const struct regulator_ops bcm590xx_ops_ldo = { 250 46 .is_enabled = regulator_is_enabled_regmap, ··· 50 254 .set_voltage_sel = regulator_set_voltage_sel_regmap, 51 255 .list_voltage = regulator_list_voltage_table, 52 256 .map_voltage = regulator_map_voltage_iterate, 257 + }; 258 + 259 + /* 260 + * LDO ops without voltage selection, used for MICLDO on BCM59054. 261 + * (These are currently the same as VBUS ops, but will be different 262 + * in the future once full PMMODE support is implemented.) 263 + */ 264 + static const struct regulator_ops bcm590xx_ops_ldo_novolt = { 265 + .is_enabled = regulator_is_enabled_regmap, 266 + .enable = regulator_enable_regmap, 267 + .disable = regulator_disable_regmap, 53 268 }; 54 269 55 270 static const struct regulator_ops bcm590xx_ops_dcdc = { ··· 79 272 .disable = regulator_disable_regmap, 80 273 }; 81 274 275 + #define BCM590XX_REG_DESC(_model, _name, _name_lower) \ 276 + .id = _model##_REG_##_name, \ 277 + .name = #_name_lower, \ 278 + .of_match = of_match_ptr(#_name_lower), \ 279 + .regulators_node = of_match_ptr("regulators"), \ 280 + .type = REGULATOR_VOLTAGE, \ 281 + .owner = THIS_MODULE \ 282 + 283 + #define BCM590XX_LDO_DESC(_model, _model_lower, _name, _name_lower, _table) \ 284 + BCM590XX_REG_DESC(_model, _name, _name_lower), \ 285 + .ops = &bcm590xx_ops_ldo, \ 286 + .n_voltages = ARRAY_SIZE(_model_lower##_##_table), \ 287 + .volt_table = _model_lower##_##_table, \ 288 + .vsel_reg = _model##_##_name##CTRL, \ 289 + .vsel_mask = BCM590XX_LDO_VSEL_MASK, \ 290 + .enable_reg = _model##_##_name##PMCTRL1, \ 291 + .enable_mask = BCM590XX_REG_ENABLE, \ 292 + .enable_is_inverted = true 293 + 294 + #define BCM590XX_SR_DESC(_model, _model_lower, _name, _name_lower, _ranges) \ 295 + BCM590XX_REG_DESC(_model, _name, _name_lower), \ 296 + .ops = &bcm590xx_ops_dcdc, \ 297 + .n_voltages = 64, \ 298 + .linear_ranges = _model_lower##_##_ranges, \ 299 + .n_linear_ranges = ARRAY_SIZE(_model_lower##_##_ranges), \ 300 + .vsel_reg = _model##_##_name##VOUT1, \ 301 + .vsel_mask = BCM590XX_SR_VSEL_MASK, \ 302 + .enable_reg = _model##_##_name##PMCTRL1, \ 303 + .enable_mask = BCM590XX_REG_ENABLE, \ 304 + .enable_is_inverted = true 305 + 306 + #define BCM59056_REG_DESC(_name, _name_lower) \ 307 + BCM590XX_REG_DESC(BCM59056, _name, _name_lower) 308 + #define BCM59056_LDO_DESC(_name, _name_lower, _table) \ 309 + BCM590XX_LDO_DESC(BCM59056, bcm59056, _name, _name_lower, _table) 310 + #define BCM59056_SR_DESC(_name, _name_lower, _ranges) \ 311 + BCM590XX_SR_DESC(BCM59056, bcm59056, _name, _name_lower, _ranges) 312 + 313 + #define BCM59054_REG_DESC(_name, _name_lower) \ 314 + BCM590XX_REG_DESC(BCM59054, _name, _name_lower) 315 + #define BCM59054_LDO_DESC(_name, _name_lower, _table) \ 316 + BCM590XX_LDO_DESC(BCM59054, bcm59054, _name, _name_lower, _table) 317 + #define BCM59054_SR_DESC(_name, _name_lower, _ranges) \ 318 + BCM590XX_SR_DESC(BCM59054, bcm59054, _name, _name_lower, _ranges) 319 + 320 + /* BCM59056 data */ 321 + 322 + /* I2C slave 0 registers */ 323 + #define BCM59056_RFLDOPMCTRL1 0x60 324 + #define BCM59056_CAMLDO1PMCTRL1 0x62 325 + #define BCM59056_CAMLDO2PMCTRL1 0x64 326 + #define BCM59056_SIMLDO1PMCTRL1 0x66 327 + #define BCM59056_SIMLDO2PMCTRL1 0x68 328 + #define BCM59056_SDLDOPMCTRL1 0x6a 329 + #define BCM59056_SDXLDOPMCTRL1 0x6c 330 + #define BCM59056_MMCLDO1PMCTRL1 0x6e 331 + #define BCM59056_MMCLDO2PMCTRL1 0x70 332 + #define BCM59056_AUDLDOPMCTRL1 0x72 333 + #define BCM59056_MICLDOPMCTRL1 0x74 334 + #define BCM59056_USBLDOPMCTRL1 0x76 335 + #define BCM59056_VIBLDOPMCTRL1 0x78 336 + #define BCM59056_IOSR1PMCTRL1 0x7a 337 + #define BCM59056_IOSR2PMCTRL1 0x7c 338 + #define BCM59056_CSRPMCTRL1 0x7e 339 + #define BCM59056_SDSR1PMCTRL1 0x82 340 + #define BCM59056_SDSR2PMCTRL1 0x86 341 + #define BCM59056_MSRPMCTRL1 0x8a 342 + #define BCM59056_VSRPMCTRL1 0x8e 343 + #define BCM59056_RFLDOCTRL 0x96 344 + #define BCM59056_CAMLDO1CTRL 0x97 345 + #define BCM59056_CAMLDO2CTRL 0x98 346 + #define BCM59056_SIMLDO1CTRL 0x99 347 + #define BCM59056_SIMLDO2CTRL 0x9a 348 + #define BCM59056_SDLDOCTRL 0x9b 349 + #define BCM59056_SDXLDOCTRL 0x9c 350 + #define BCM59056_MMCLDO1CTRL 0x9d 351 + #define BCM59056_MMCLDO2CTRL 0x9e 352 + #define BCM59056_AUDLDOCTRL 0x9f 353 + #define BCM59056_MICLDOCTRL 0xa0 354 + #define BCM59056_USBLDOCTRL 0xa1 355 + #define BCM59056_VIBLDOCTRL 0xa2 356 + #define BCM59056_CSRVOUT1 0xc0 357 + #define BCM59056_IOSR1VOUT1 0xc3 358 + #define BCM59056_IOSR2VOUT1 0xc6 359 + #define BCM59056_MSRVOUT1 0xc9 360 + #define BCM59056_SDSR1VOUT1 0xcc 361 + #define BCM59056_SDSR2VOUT1 0xcf 362 + #define BCM59056_VSRVOUT1 0xd2 363 + 364 + /* I2C slave 1 registers */ 365 + #define BCM59056_GPLDO5PMCTRL1 0x16 366 + #define BCM59056_GPLDO6PMCTRL1 0x18 367 + #define BCM59056_GPLDO1CTRL 0x1a 368 + #define BCM59056_GPLDO2CTRL 0x1b 369 + #define BCM59056_GPLDO3CTRL 0x1c 370 + #define BCM59056_GPLDO4CTRL 0x1d 371 + #define BCM59056_GPLDO5CTRL 0x1e 372 + #define BCM59056_GPLDO6CTRL 0x1f 373 + #define BCM59056_OTG_CTRL 0x40 374 + #define BCM59056_GPLDO1PMCTRL1 0x57 375 + #define BCM59056_GPLDO2PMCTRL1 0x59 376 + #define BCM59056_GPLDO3PMCTRL1 0x5b 377 + #define BCM59056_GPLDO4PMCTRL1 0x5d 378 + 379 + /* 380 + * RFLDO to VSR regulators are 381 + * accessed via I2C slave 0 382 + */ 383 + 384 + /* LDO regulator IDs */ 385 + #define BCM59056_REG_RFLDO 0 386 + #define BCM59056_REG_CAMLDO1 1 387 + #define BCM59056_REG_CAMLDO2 2 388 + #define BCM59056_REG_SIMLDO1 3 389 + #define BCM59056_REG_SIMLDO2 4 390 + #define BCM59056_REG_SDLDO 5 391 + #define BCM59056_REG_SDXLDO 6 392 + #define BCM59056_REG_MMCLDO1 7 393 + #define BCM59056_REG_MMCLDO2 8 394 + #define BCM59056_REG_AUDLDO 9 395 + #define BCM59056_REG_MICLDO 10 396 + #define BCM59056_REG_USBLDO 11 397 + #define BCM59056_REG_VIBLDO 12 398 + 399 + /* DCDC regulator IDs */ 400 + #define BCM59056_REG_CSR 13 401 + #define BCM59056_REG_IOSR1 14 402 + #define BCM59056_REG_IOSR2 15 403 + #define BCM59056_REG_MSR 16 404 + #define BCM59056_REG_SDSR1 17 405 + #define BCM59056_REG_SDSR2 18 406 + #define BCM59056_REG_VSR 19 407 + 408 + /* 409 + * GPLDO1 to VBUS regulators are 410 + * accessed via I2C slave 1 411 + */ 412 + 413 + #define BCM59056_REG_GPLDO1 20 414 + #define BCM59056_REG_GPLDO2 21 415 + #define BCM59056_REG_GPLDO3 22 416 + #define BCM59056_REG_GPLDO4 23 417 + #define BCM59056_REG_GPLDO5 24 418 + #define BCM59056_REG_GPLDO6 25 419 + #define BCM59056_REG_VBUS 26 420 + 421 + #define BCM59056_NUM_REGS 27 422 + 423 + /* LDO group A: supported voltages in microvolts */ 424 + static const unsigned int bcm59056_ldo_a_table[] = { 425 + 1200000, 1800000, 2500000, 2700000, 2800000, 426 + 2900000, 3000000, 3300000, 427 + }; 428 + 429 + /* LDO group C: supported voltages in microvolts */ 430 + static const unsigned int bcm59056_ldo_c_table[] = { 431 + 3100000, 1800000, 2500000, 2700000, 2800000, 432 + 2900000, 3000000, 3300000, 433 + }; 434 + 435 + /* DCDC group CSR: supported voltages in microvolts */ 436 + static const struct linear_range bcm59056_dcdc_csr_ranges[] = { 437 + REGULATOR_LINEAR_RANGE(860000, 2, 50, 10000), 438 + REGULATOR_LINEAR_RANGE(1360000, 51, 55, 20000), 439 + REGULATOR_LINEAR_RANGE(900000, 56, 63, 0), 440 + }; 441 + 442 + /* DCDC group IOSR1: supported voltages in microvolts */ 443 + static const struct linear_range bcm59056_dcdc_iosr1_ranges[] = { 444 + REGULATOR_LINEAR_RANGE(860000, 2, 51, 10000), 445 + REGULATOR_LINEAR_RANGE(1500000, 52, 52, 0), 446 + REGULATOR_LINEAR_RANGE(1800000, 53, 53, 0), 447 + REGULATOR_LINEAR_RANGE(900000, 54, 63, 0), 448 + }; 449 + 450 + /* DCDC group SDSR1: supported voltages in microvolts */ 451 + static const struct linear_range bcm59056_dcdc_sdsr1_ranges[] = { 452 + REGULATOR_LINEAR_RANGE(860000, 2, 50, 10000), 453 + REGULATOR_LINEAR_RANGE(1340000, 51, 51, 0), 454 + REGULATOR_LINEAR_RANGE(900000, 52, 63, 0), 455 + }; 456 + 457 + static const struct bcm590xx_reg_data bcm59056_regs[BCM59056_NUM_REGS] = { 458 + { 459 + .type = BCM590XX_REG_TYPE_LDO, 460 + .regmap = BCM590XX_REGMAP_PRI, 461 + .desc = { 462 + BCM59056_LDO_DESC(RFLDO, rfldo, ldo_a_table), 463 + }, 464 + }, 465 + 466 + { 467 + .type = BCM590XX_REG_TYPE_LDO, 468 + .regmap = BCM590XX_REGMAP_PRI, 469 + .desc = { 470 + BCM59056_LDO_DESC(CAMLDO1, camldo1, ldo_c_table), 471 + }, 472 + }, 473 + 474 + { 475 + .type = BCM590XX_REG_TYPE_LDO, 476 + .regmap = BCM590XX_REGMAP_PRI, 477 + .desc = { 478 + BCM59056_LDO_DESC(CAMLDO2, camldo2, ldo_c_table), 479 + }, 480 + }, 481 + 482 + { 483 + .type = BCM590XX_REG_TYPE_LDO, 484 + .regmap = BCM590XX_REGMAP_PRI, 485 + .desc = { 486 + BCM59056_LDO_DESC(SIMLDO1, simldo1, ldo_a_table), 487 + }, 488 + }, 489 + 490 + { 491 + .type = BCM590XX_REG_TYPE_LDO, 492 + .regmap = BCM590XX_REGMAP_PRI, 493 + .desc = { 494 + BCM59056_LDO_DESC(SIMLDO2, simldo2, ldo_a_table), 495 + }, 496 + }, 497 + 498 + { 499 + .type = BCM590XX_REG_TYPE_LDO, 500 + .regmap = BCM590XX_REGMAP_PRI, 501 + .desc = { 502 + BCM59056_LDO_DESC(SDLDO, sdldo, ldo_c_table), 503 + }, 504 + }, 505 + 506 + { 507 + .type = BCM590XX_REG_TYPE_LDO, 508 + .regmap = BCM590XX_REGMAP_PRI, 509 + .desc = { 510 + BCM59056_LDO_DESC(SDXLDO, sdxldo, ldo_a_table), 511 + }, 512 + }, 513 + 514 + { 515 + .type = BCM590XX_REG_TYPE_LDO, 516 + .regmap = BCM590XX_REGMAP_PRI, 517 + .desc = { 518 + BCM59056_LDO_DESC(MMCLDO1, mmcldo1, ldo_a_table), 519 + }, 520 + }, 521 + 522 + { 523 + .type = BCM590XX_REG_TYPE_LDO, 524 + .regmap = BCM590XX_REGMAP_PRI, 525 + .desc = { 526 + BCM59056_LDO_DESC(MMCLDO2, mmcldo2, ldo_a_table), 527 + }, 528 + }, 529 + 530 + { 531 + .type = BCM590XX_REG_TYPE_LDO, 532 + .regmap = BCM590XX_REGMAP_PRI, 533 + .desc = { 534 + BCM59056_LDO_DESC(AUDLDO, audldo, ldo_a_table), 535 + }, 536 + }, 537 + 538 + { 539 + .type = BCM590XX_REG_TYPE_LDO, 540 + .regmap = BCM590XX_REGMAP_PRI, 541 + .desc = { 542 + BCM59056_LDO_DESC(MICLDO, micldo, ldo_a_table), 543 + }, 544 + }, 545 + 546 + { 547 + .type = BCM590XX_REG_TYPE_LDO, 548 + .regmap = BCM590XX_REGMAP_PRI, 549 + .desc = { 550 + BCM59056_LDO_DESC(USBLDO, usbldo, ldo_a_table), 551 + }, 552 + }, 553 + 554 + { 555 + .type = BCM590XX_REG_TYPE_LDO, 556 + .regmap = BCM590XX_REGMAP_PRI, 557 + .desc = { 558 + BCM59056_LDO_DESC(VIBLDO, vibldo, ldo_c_table), 559 + }, 560 + }, 561 + 562 + { 563 + .type = BCM590XX_REG_TYPE_SR, 564 + .regmap = BCM590XX_REGMAP_PRI, 565 + .desc = { 566 + BCM59056_SR_DESC(CSR, csr, dcdc_csr_ranges), 567 + }, 568 + }, 569 + 570 + { 571 + .type = BCM590XX_REG_TYPE_SR, 572 + .regmap = BCM590XX_REGMAP_PRI, 573 + .desc = { 574 + BCM59056_SR_DESC(IOSR1, iosr1, dcdc_iosr1_ranges), 575 + }, 576 + }, 577 + 578 + { 579 + .type = BCM590XX_REG_TYPE_SR, 580 + .regmap = BCM590XX_REGMAP_PRI, 581 + .desc = { 582 + BCM59056_SR_DESC(IOSR2, iosr2, dcdc_iosr1_ranges), 583 + }, 584 + }, 585 + 586 + { 587 + .type = BCM590XX_REG_TYPE_SR, 588 + .regmap = BCM590XX_REGMAP_PRI, 589 + .desc = { 590 + BCM59056_SR_DESC(MSR, msr, dcdc_iosr1_ranges), 591 + }, 592 + }, 593 + 594 + { 595 + .type = BCM590XX_REG_TYPE_SR, 596 + .regmap = BCM590XX_REGMAP_PRI, 597 + .desc = { 598 + BCM59056_SR_DESC(SDSR1, sdsr1, dcdc_sdsr1_ranges), 599 + }, 600 + }, 601 + 602 + { 603 + .type = BCM590XX_REG_TYPE_SR, 604 + .regmap = BCM590XX_REGMAP_PRI, 605 + .desc = { 606 + BCM59056_SR_DESC(SDSR2, sdsr2, dcdc_iosr1_ranges), 607 + }, 608 + }, 609 + 610 + { 611 + .type = BCM590XX_REG_TYPE_SR, 612 + .regmap = BCM590XX_REGMAP_PRI, 613 + .desc = { 614 + BCM59056_SR_DESC(VSR, vsr, dcdc_iosr1_ranges), 615 + }, 616 + }, 617 + 618 + { 619 + .type = BCM590XX_REG_TYPE_GPLDO, 620 + .regmap = BCM590XX_REGMAP_SEC, 621 + .desc = { 622 + BCM59056_LDO_DESC(GPLDO1, gpldo1, ldo_a_table), 623 + }, 624 + }, 625 + 626 + { 627 + .type = BCM590XX_REG_TYPE_GPLDO, 628 + .regmap = BCM590XX_REGMAP_SEC, 629 + .desc = { 630 + BCM59056_LDO_DESC(GPLDO2, gpldo2, ldo_a_table), 631 + }, 632 + }, 633 + 634 + { 635 + .type = BCM590XX_REG_TYPE_GPLDO, 636 + .regmap = BCM590XX_REGMAP_SEC, 637 + .desc = { 638 + BCM59056_LDO_DESC(GPLDO3, gpldo3, ldo_a_table), 639 + }, 640 + }, 641 + 642 + { 643 + .type = BCM590XX_REG_TYPE_GPLDO, 644 + .regmap = BCM590XX_REGMAP_SEC, 645 + .desc = { 646 + BCM59056_LDO_DESC(GPLDO4, gpldo4, ldo_a_table), 647 + }, 648 + }, 649 + 650 + { 651 + .type = BCM590XX_REG_TYPE_GPLDO, 652 + .regmap = BCM590XX_REGMAP_SEC, 653 + .desc = { 654 + BCM59056_LDO_DESC(GPLDO5, gpldo5, ldo_a_table), 655 + }, 656 + }, 657 + 658 + { 659 + .type = BCM590XX_REG_TYPE_GPLDO, 660 + .regmap = BCM590XX_REGMAP_SEC, 661 + .desc = { 662 + BCM59056_LDO_DESC(GPLDO6, gpldo6, ldo_a_table), 663 + }, 664 + }, 665 + 666 + { 667 + .type = BCM590XX_REG_TYPE_VBUS, 668 + .regmap = BCM590XX_REGMAP_SEC, 669 + .desc = { 670 + BCM59056_REG_DESC(VBUS, vbus), 671 + .ops = &bcm590xx_ops_vbus, 672 + .n_voltages = 1, 673 + .fixed_uV = 5000000, 674 + .enable_reg = BCM59056_OTG_CTRL, 675 + .enable_mask = BCM590XX_VBUS_ENABLE, 676 + }, 677 + }, 678 + }; 679 + 680 + /* BCM59054 data */ 681 + 682 + /* I2C slave 0 registers */ 683 + #define BCM59054_RFLDOPMCTRL1 0x60 684 + #define BCM59054_CAMLDO1PMCTRL1 0x62 685 + #define BCM59054_CAMLDO2PMCTRL1 0x64 686 + #define BCM59054_SIMLDO1PMCTRL1 0x66 687 + #define BCM59054_SIMLDO2PMCTRL1 0x68 688 + #define BCM59054_SDLDOPMCTRL1 0x6a 689 + #define BCM59054_SDXLDOPMCTRL1 0x6c 690 + #define BCM59054_MMCLDO1PMCTRL1 0x6e 691 + #define BCM59054_MMCLDO2PMCTRL1 0x70 692 + #define BCM59054_AUDLDOPMCTRL1 0x72 693 + #define BCM59054_MICLDOPMCTRL1 0x74 694 + #define BCM59054_USBLDOPMCTRL1 0x76 695 + #define BCM59054_VIBLDOPMCTRL1 0x78 696 + #define BCM59054_IOSR1PMCTRL1 0x7a 697 + #define BCM59054_IOSR2PMCTRL1 0x7c 698 + #define BCM59054_CSRPMCTRL1 0x7e 699 + #define BCM59054_SDSR1PMCTRL1 0x82 700 + #define BCM59054_SDSR2PMCTRL1 0x86 701 + #define BCM59054_MMSRPMCTRL1 0x8a 702 + #define BCM59054_VSRPMCTRL1 0x8e 703 + #define BCM59054_RFLDOCTRL 0x96 704 + #define BCM59054_CAMLDO1CTRL 0x97 705 + #define BCM59054_CAMLDO2CTRL 0x98 706 + #define BCM59054_SIMLDO1CTRL 0x99 707 + #define BCM59054_SIMLDO2CTRL 0x9a 708 + #define BCM59054_SDLDOCTRL 0x9b 709 + #define BCM59054_SDXLDOCTRL 0x9c 710 + #define BCM59054_MMCLDO1CTRL 0x9d 711 + #define BCM59054_MMCLDO2CTRL 0x9e 712 + #define BCM59054_AUDLDOCTRL 0x9f 713 + #define BCM59054_MICLDOCTRL 0xa0 714 + #define BCM59054_USBLDOCTRL 0xa1 715 + #define BCM59054_VIBLDOCTRL 0xa2 716 + #define BCM59054_CSRVOUT1 0xc0 717 + #define BCM59054_IOSR1VOUT1 0xc3 718 + #define BCM59054_IOSR2VOUT1 0xc6 719 + #define BCM59054_MMSRVOUT1 0xc9 720 + #define BCM59054_SDSR1VOUT1 0xcc 721 + #define BCM59054_SDSR2VOUT1 0xcf 722 + #define BCM59054_VSRVOUT1 0xd2 723 + 724 + /* I2C slave 1 registers */ 725 + #define BCM59054_LVLDO1PMCTRL1 0x16 726 + #define BCM59054_LVLDO2PMCTRL1 0x18 727 + #define BCM59054_GPLDO1CTRL 0x1a 728 + #define BCM59054_GPLDO2CTRL 0x1b 729 + #define BCM59054_GPLDO3CTRL 0x1c 730 + #define BCM59054_TCXLDOCTRL 0x1d 731 + #define BCM59054_LVLDO1CTRL 0x1e 732 + #define BCM59054_LVLDO2CTRL 0x1f 733 + #define BCM59054_OTG_CTRL 0x40 734 + #define BCM59054_GPLDO1PMCTRL1 0x57 735 + #define BCM59054_GPLDO2PMCTRL1 0x59 736 + #define BCM59054_GPLDO3PMCTRL1 0x5b 737 + #define BCM59054_TCXLDOPMCTRL1 0x5d 738 + 739 + /* 740 + * RFLDO to VSR regulators are 741 + * accessed via I2C slave 0 742 + */ 743 + 744 + /* LDO regulator IDs */ 745 + #define BCM59054_REG_RFLDO 0 746 + #define BCM59054_REG_CAMLDO1 1 747 + #define BCM59054_REG_CAMLDO2 2 748 + #define BCM59054_REG_SIMLDO1 3 749 + #define BCM59054_REG_SIMLDO2 4 750 + #define BCM59054_REG_SDLDO 5 751 + #define BCM59054_REG_SDXLDO 6 752 + #define BCM59054_REG_MMCLDO1 7 753 + #define BCM59054_REG_MMCLDO2 8 754 + #define BCM59054_REG_AUDLDO 9 755 + #define BCM59054_REG_MICLDO 10 756 + #define BCM59054_REG_USBLDO 11 757 + #define BCM59054_REG_VIBLDO 12 758 + 759 + /* DCDC regulator IDs */ 760 + #define BCM59054_REG_CSR 13 761 + #define BCM59054_REG_IOSR1 14 762 + #define BCM59054_REG_IOSR2 15 763 + #define BCM59054_REG_MMSR 16 764 + #define BCM59054_REG_SDSR1 17 765 + #define BCM59054_REG_SDSR2 18 766 + #define BCM59054_REG_VSR 19 767 + 768 + /* 769 + * GPLDO1 to VBUS regulators are 770 + * accessed via I2C slave 1 771 + */ 772 + 773 + #define BCM59054_REG_GPLDO1 20 774 + #define BCM59054_REG_GPLDO2 21 775 + #define BCM59054_REG_GPLDO3 22 776 + #define BCM59054_REG_TCXLDO 23 777 + #define BCM59054_REG_LVLDO1 24 778 + #define BCM59054_REG_LVLDO2 25 779 + #define BCM59054_REG_VBUS 26 780 + 781 + #define BCM59054_NUM_REGS 27 782 + 783 + /* LDO group 1: supported voltages in microvolts */ 784 + static const unsigned int bcm59054_ldo_1_table[] = { 785 + 1200000, 1800000, 2500000, 2700000, 2800000, 786 + 2900000, 3000000, 3300000, 787 + }; 788 + 789 + /* LDO group 2: supported voltages in microvolts */ 790 + static const unsigned int bcm59054_ldo_2_table[] = { 791 + 3100000, 1800000, 2500000, 2700000, 2800000, 792 + 2900000, 3000000, 3300000, 793 + }; 794 + 795 + /* LDO group 3: supported voltages in microvolts */ 796 + static const unsigned int bcm59054_ldo_3_table[] = { 797 + 1000000, 1107000, 1143000, 1214000, 1250000, 798 + 1464000, 1500000, 1786000, 799 + }; 800 + 801 + /* DCDC group SR: supported voltages in microvolts */ 802 + static const struct linear_range bcm59054_dcdc_sr_ranges[] = { 803 + REGULATOR_LINEAR_RANGE(0, 0, 1, 0), 804 + REGULATOR_LINEAR_RANGE(860000, 2, 60, 10000), 805 + REGULATOR_LINEAR_RANGE(1500000, 61, 61, 0), 806 + REGULATOR_LINEAR_RANGE(1800000, 62, 62, 0), 807 + REGULATOR_LINEAR_RANGE(900000, 63, 63, 0), 808 + }; 809 + 810 + /* DCDC group VSR (BCM59054A1): supported voltages in microvolts */ 811 + static const struct linear_range bcm59054_dcdc_vsr_a1_ranges[] = { 812 + REGULATOR_LINEAR_RANGE(0, 0, 1, 0), 813 + REGULATOR_LINEAR_RANGE(860000, 2, 59, 10000), 814 + REGULATOR_LINEAR_RANGE(1700000, 60, 60, 0), 815 + REGULATOR_LINEAR_RANGE(1500000, 61, 61, 0), 816 + REGULATOR_LINEAR_RANGE(1800000, 62, 62, 0), 817 + REGULATOR_LINEAR_RANGE(1600000, 63, 63, 0), 818 + }; 819 + 820 + /* DCDC group CSR: supported voltages in microvolts */ 821 + static const struct linear_range bcm59054_dcdc_csr_ranges[] = { 822 + REGULATOR_LINEAR_RANGE(700000, 0, 1, 100000), 823 + REGULATOR_LINEAR_RANGE(860000, 2, 60, 10000), 824 + REGULATOR_LINEAR_RANGE(900000, 61, 63, 0), 825 + }; 826 + 827 + static const struct bcm590xx_reg_data bcm59054_regs[BCM59054_NUM_REGS] = { 828 + { 829 + .type = BCM590XX_REG_TYPE_LDO, 830 + .regmap = BCM590XX_REGMAP_PRI, 831 + .desc = { 832 + BCM59054_LDO_DESC(RFLDO, rfldo, ldo_1_table), 833 + }, 834 + }, 835 + 836 + { 837 + .type = BCM590XX_REG_TYPE_LDO, 838 + .regmap = BCM590XX_REGMAP_PRI, 839 + .desc = { 840 + BCM59054_LDO_DESC(CAMLDO1, camldo1, ldo_2_table), 841 + }, 842 + }, 843 + 844 + { 845 + .type = BCM590XX_REG_TYPE_LDO, 846 + .regmap = BCM590XX_REGMAP_PRI, 847 + .desc = { 848 + BCM59054_LDO_DESC(CAMLDO2, camldo2, ldo_2_table), 849 + }, 850 + }, 851 + 852 + { 853 + .type = BCM590XX_REG_TYPE_LDO, 854 + .regmap = BCM590XX_REGMAP_PRI, 855 + .desc = { 856 + BCM59054_LDO_DESC(SIMLDO1, simldo1, ldo_1_table), 857 + }, 858 + }, 859 + 860 + { 861 + .type = BCM590XX_REG_TYPE_LDO, 862 + .regmap = BCM590XX_REGMAP_PRI, 863 + .desc = { 864 + BCM59054_LDO_DESC(SIMLDO2, simldo2, ldo_1_table), 865 + }, 866 + }, 867 + 868 + { 869 + .type = BCM590XX_REG_TYPE_LDO, 870 + .regmap = BCM590XX_REGMAP_PRI, 871 + .desc = { 872 + BCM59054_LDO_DESC(SDLDO, sdldo, ldo_2_table), 873 + }, 874 + }, 875 + 876 + { 877 + .type = BCM590XX_REG_TYPE_LDO, 878 + .regmap = BCM590XX_REGMAP_PRI, 879 + .desc = { 880 + BCM59054_LDO_DESC(SDXLDO, sdxldo, ldo_1_table), 881 + }, 882 + }, 883 + 884 + { 885 + .type = BCM590XX_REG_TYPE_LDO, 886 + .regmap = BCM590XX_REGMAP_PRI, 887 + .desc = { 888 + BCM59054_LDO_DESC(MMCLDO1, mmcldo1, ldo_1_table), 889 + }, 890 + }, 891 + 892 + { 893 + .type = BCM590XX_REG_TYPE_LDO, 894 + .regmap = BCM590XX_REGMAP_PRI, 895 + .desc = { 896 + BCM59054_LDO_DESC(MMCLDO2, mmcldo2, ldo_1_table), 897 + }, 898 + }, 899 + 900 + { 901 + .type = BCM590XX_REG_TYPE_LDO, 902 + .regmap = BCM590XX_REGMAP_PRI, 903 + .desc = { 904 + BCM59054_LDO_DESC(AUDLDO, audldo, ldo_1_table), 905 + }, 906 + }, 907 + 908 + { 909 + .type = BCM590XX_REG_TYPE_LDO, 910 + .regmap = BCM590XX_REGMAP_PRI, 911 + .desc = { 912 + BCM59054_REG_DESC(MICLDO, micldo), 913 + .ops = &bcm590xx_ops_ldo_novolt, 914 + /* MICLDO is locked at 1.8V */ 915 + .n_voltages = 1, 916 + .fixed_uV = 1800000, 917 + .enable_reg = BCM59054_MICLDOPMCTRL1, 918 + .enable_mask = BCM590XX_REG_ENABLE, 919 + .enable_is_inverted = true, 920 + }, 921 + }, 922 + 923 + { 924 + .type = BCM590XX_REG_TYPE_LDO, 925 + .regmap = BCM590XX_REGMAP_PRI, 926 + .desc = { 927 + BCM59054_LDO_DESC(USBLDO, usbldo, ldo_1_table), 928 + }, 929 + }, 930 + 931 + { 932 + .type = BCM590XX_REG_TYPE_LDO, 933 + .regmap = BCM590XX_REGMAP_PRI, 934 + .desc = { 935 + BCM59054_LDO_DESC(VIBLDO, vibldo, ldo_2_table), 936 + }, 937 + }, 938 + 939 + { 940 + .type = BCM590XX_REG_TYPE_SR, 941 + .regmap = BCM590XX_REGMAP_PRI, 942 + .desc = { 943 + BCM59054_SR_DESC(CSR, csr, dcdc_csr_ranges), 944 + }, 945 + }, 946 + 947 + { 948 + .type = BCM590XX_REG_TYPE_SR, 949 + .regmap = BCM590XX_REGMAP_PRI, 950 + .desc = { 951 + BCM59054_SR_DESC(IOSR1, iosr1, dcdc_sr_ranges), 952 + }, 953 + }, 954 + 955 + { 956 + .type = BCM590XX_REG_TYPE_SR, 957 + .regmap = BCM590XX_REGMAP_PRI, 958 + .desc = { 959 + BCM59054_SR_DESC(IOSR2, iosr2, dcdc_sr_ranges), 960 + }, 961 + }, 962 + 963 + { 964 + .type = BCM590XX_REG_TYPE_SR, 965 + .regmap = BCM590XX_REGMAP_PRI, 966 + .desc = { 967 + BCM59054_SR_DESC(MMSR, mmsr, dcdc_sr_ranges), 968 + }, 969 + }, 970 + 971 + { 972 + .type = BCM590XX_REG_TYPE_SR, 973 + .regmap = BCM590XX_REGMAP_PRI, 974 + .desc = { 975 + BCM59054_SR_DESC(SDSR1, sdsr1, dcdc_sr_ranges), 976 + }, 977 + }, 978 + 979 + { 980 + .type = BCM590XX_REG_TYPE_SR, 981 + .regmap = BCM590XX_REGMAP_PRI, 982 + .desc = { 983 + BCM59054_SR_DESC(SDSR2, sdsr2, dcdc_sr_ranges), 984 + }, 985 + }, 986 + 987 + { 988 + .type = BCM590XX_REG_TYPE_SR, 989 + .regmap = BCM590XX_REGMAP_PRI, 990 + .desc = { 991 + BCM59054_SR_DESC(VSR, vsr, dcdc_sr_ranges), 992 + }, 993 + }, 994 + 995 + { 996 + .type = BCM590XX_REG_TYPE_GPLDO, 997 + .regmap = BCM590XX_REGMAP_SEC, 998 + .desc = { 999 + BCM59054_LDO_DESC(GPLDO1, gpldo1, ldo_1_table), 1000 + }, 1001 + }, 1002 + 1003 + { 1004 + .type = BCM590XX_REG_TYPE_GPLDO, 1005 + .regmap = BCM590XX_REGMAP_SEC, 1006 + .desc = { 1007 + BCM59054_LDO_DESC(GPLDO2, gpldo2, ldo_1_table), 1008 + }, 1009 + }, 1010 + 1011 + { 1012 + .type = BCM590XX_REG_TYPE_GPLDO, 1013 + .regmap = BCM590XX_REGMAP_SEC, 1014 + .desc = { 1015 + BCM59054_LDO_DESC(GPLDO3, gpldo3, ldo_1_table), 1016 + }, 1017 + }, 1018 + 1019 + { 1020 + .type = BCM590XX_REG_TYPE_GPLDO, 1021 + .regmap = BCM590XX_REGMAP_SEC, 1022 + .desc = { 1023 + BCM59054_LDO_DESC(TCXLDO, tcxldo, ldo_1_table), 1024 + }, 1025 + }, 1026 + 1027 + { 1028 + .type = BCM590XX_REG_TYPE_GPLDO, 1029 + .regmap = BCM590XX_REGMAP_SEC, 1030 + .desc = { 1031 + BCM59054_LDO_DESC(LVLDO1, lvldo1, ldo_3_table), 1032 + }, 1033 + }, 1034 + 1035 + { 1036 + .type = BCM590XX_REG_TYPE_GPLDO, 1037 + .regmap = BCM590XX_REGMAP_SEC, 1038 + .desc = { 1039 + BCM59054_LDO_DESC(LVLDO2, lvldo2, ldo_3_table), 1040 + }, 1041 + }, 1042 + 1043 + { 1044 + .type = BCM590XX_REG_TYPE_VBUS, 1045 + .regmap = BCM590XX_REGMAP_SEC, 1046 + .desc = { 1047 + BCM59054_REG_DESC(VBUS, vbus), 1048 + .ops = &bcm590xx_ops_vbus, 1049 + .n_voltages = 1, 1050 + .fixed_uV = 5000000, 1051 + .enable_reg = BCM59054_OTG_CTRL, 1052 + .enable_mask = BCM590XX_VBUS_ENABLE, 1053 + }, 1054 + }, 1055 + }; 1056 + 1057 + /* 1058 + * BCM59054A1 regulators; same as previous revision, but with different 1059 + * VSR voltage table. 1060 + */ 1061 + static const struct bcm590xx_reg_data bcm59054_a1_regs[BCM59054_NUM_REGS] = { 1062 + { 1063 + .type = BCM590XX_REG_TYPE_LDO, 1064 + .regmap = BCM590XX_REGMAP_PRI, 1065 + .desc = { 1066 + BCM59054_LDO_DESC(RFLDO, rfldo, ldo_1_table), 1067 + }, 1068 + }, 1069 + 1070 + { 1071 + .type = BCM590XX_REG_TYPE_LDO, 1072 + .regmap = BCM590XX_REGMAP_PRI, 1073 + .desc = { 1074 + BCM59054_LDO_DESC(CAMLDO1, camldo1, ldo_2_table), 1075 + }, 1076 + }, 1077 + 1078 + { 1079 + .type = BCM590XX_REG_TYPE_LDO, 1080 + .regmap = BCM590XX_REGMAP_PRI, 1081 + .desc = { 1082 + BCM59054_LDO_DESC(CAMLDO2, camldo2, ldo_2_table), 1083 + }, 1084 + }, 1085 + 1086 + { 1087 + .type = BCM590XX_REG_TYPE_LDO, 1088 + .regmap = BCM590XX_REGMAP_PRI, 1089 + .desc = { 1090 + BCM59054_LDO_DESC(SIMLDO1, simldo1, ldo_1_table), 1091 + }, 1092 + }, 1093 + 1094 + { 1095 + .type = BCM590XX_REG_TYPE_LDO, 1096 + .regmap = BCM590XX_REGMAP_PRI, 1097 + .desc = { 1098 + BCM59054_LDO_DESC(SIMLDO2, simldo2, ldo_1_table), 1099 + }, 1100 + }, 1101 + 1102 + { 1103 + .type = BCM590XX_REG_TYPE_LDO, 1104 + .regmap = BCM590XX_REGMAP_PRI, 1105 + .desc = { 1106 + BCM59054_LDO_DESC(SDLDO, sdldo, ldo_2_table), 1107 + }, 1108 + }, 1109 + 1110 + { 1111 + .type = BCM590XX_REG_TYPE_LDO, 1112 + .regmap = BCM590XX_REGMAP_PRI, 1113 + .desc = { 1114 + BCM59054_LDO_DESC(SDXLDO, sdxldo, ldo_1_table), 1115 + }, 1116 + }, 1117 + 1118 + { 1119 + .type = BCM590XX_REG_TYPE_LDO, 1120 + .regmap = BCM590XX_REGMAP_PRI, 1121 + .desc = { 1122 + BCM59054_LDO_DESC(MMCLDO1, mmcldo1, ldo_1_table), 1123 + }, 1124 + }, 1125 + 1126 + { 1127 + .type = BCM590XX_REG_TYPE_LDO, 1128 + .regmap = BCM590XX_REGMAP_PRI, 1129 + .desc = { 1130 + BCM59054_LDO_DESC(MMCLDO2, mmcldo2, ldo_1_table), 1131 + }, 1132 + }, 1133 + 1134 + { 1135 + .type = BCM590XX_REG_TYPE_LDO, 1136 + .regmap = BCM590XX_REGMAP_PRI, 1137 + .desc = { 1138 + BCM59054_LDO_DESC(AUDLDO, audldo, ldo_1_table), 1139 + }, 1140 + }, 1141 + 1142 + { 1143 + .type = BCM590XX_REG_TYPE_LDO, 1144 + .regmap = BCM590XX_REGMAP_PRI, 1145 + .desc = { 1146 + BCM59054_REG_DESC(MICLDO, micldo), 1147 + .ops = &bcm590xx_ops_ldo_novolt, 1148 + /* MICLDO is locked at 1.8V */ 1149 + .n_voltages = 1, 1150 + .fixed_uV = 1800000, 1151 + .enable_reg = BCM59054_MICLDOPMCTRL1, 1152 + .enable_mask = BCM590XX_REG_ENABLE, 1153 + .enable_is_inverted = true, 1154 + }, 1155 + }, 1156 + 1157 + { 1158 + .type = BCM590XX_REG_TYPE_LDO, 1159 + .regmap = BCM590XX_REGMAP_PRI, 1160 + .desc = { 1161 + BCM59054_LDO_DESC(USBLDO, usbldo, ldo_1_table), 1162 + }, 1163 + }, 1164 + 1165 + { 1166 + .type = BCM590XX_REG_TYPE_LDO, 1167 + .regmap = BCM590XX_REGMAP_PRI, 1168 + .desc = { 1169 + BCM59054_LDO_DESC(VIBLDO, vibldo, ldo_2_table), 1170 + }, 1171 + }, 1172 + 1173 + { 1174 + .type = BCM590XX_REG_TYPE_SR, 1175 + .regmap = BCM590XX_REGMAP_PRI, 1176 + .desc = { 1177 + BCM59054_SR_DESC(CSR, csr, dcdc_csr_ranges), 1178 + }, 1179 + }, 1180 + 1181 + { 1182 + .type = BCM590XX_REG_TYPE_SR, 1183 + .regmap = BCM590XX_REGMAP_PRI, 1184 + .desc = { 1185 + BCM59054_SR_DESC(IOSR1, iosr1, dcdc_sr_ranges), 1186 + }, 1187 + }, 1188 + 1189 + { 1190 + .type = BCM590XX_REG_TYPE_SR, 1191 + .regmap = BCM590XX_REGMAP_PRI, 1192 + .desc = { 1193 + BCM59054_SR_DESC(IOSR2, iosr2, dcdc_sr_ranges), 1194 + }, 1195 + }, 1196 + 1197 + { 1198 + .type = BCM590XX_REG_TYPE_SR, 1199 + .regmap = BCM590XX_REGMAP_PRI, 1200 + .desc = { 1201 + BCM59054_SR_DESC(MMSR, mmsr, dcdc_sr_ranges), 1202 + }, 1203 + }, 1204 + 1205 + { 1206 + .type = BCM590XX_REG_TYPE_SR, 1207 + .regmap = BCM590XX_REGMAP_PRI, 1208 + .desc = { 1209 + BCM59054_SR_DESC(SDSR1, sdsr1, dcdc_sr_ranges), 1210 + }, 1211 + }, 1212 + 1213 + { 1214 + .type = BCM590XX_REG_TYPE_SR, 1215 + .regmap = BCM590XX_REGMAP_PRI, 1216 + .desc = { 1217 + BCM59054_SR_DESC(SDSR2, sdsr2, dcdc_sr_ranges), 1218 + }, 1219 + }, 1220 + 1221 + { 1222 + .type = BCM590XX_REG_TYPE_SR, 1223 + .regmap = BCM590XX_REGMAP_PRI, 1224 + .desc = { 1225 + BCM59054_SR_DESC(VSR, vsr, dcdc_vsr_a1_ranges), 1226 + }, 1227 + }, 1228 + 1229 + { 1230 + .type = BCM590XX_REG_TYPE_GPLDO, 1231 + .regmap = BCM590XX_REGMAP_SEC, 1232 + .desc = { 1233 + BCM59054_LDO_DESC(GPLDO1, gpldo1, ldo_1_table), 1234 + }, 1235 + }, 1236 + 1237 + { 1238 + .type = BCM590XX_REG_TYPE_GPLDO, 1239 + .regmap = BCM590XX_REGMAP_SEC, 1240 + .desc = { 1241 + BCM59054_LDO_DESC(GPLDO2, gpldo2, ldo_1_table), 1242 + }, 1243 + }, 1244 + 1245 + { 1246 + .type = BCM590XX_REG_TYPE_GPLDO, 1247 + .regmap = BCM590XX_REGMAP_SEC, 1248 + .desc = { 1249 + BCM59054_LDO_DESC(GPLDO3, gpldo3, ldo_1_table), 1250 + }, 1251 + }, 1252 + 1253 + { 1254 + .type = BCM590XX_REG_TYPE_GPLDO, 1255 + .regmap = BCM590XX_REGMAP_SEC, 1256 + .desc = { 1257 + BCM59054_LDO_DESC(TCXLDO, tcxldo, ldo_1_table), 1258 + }, 1259 + }, 1260 + 1261 + { 1262 + .type = BCM590XX_REG_TYPE_GPLDO, 1263 + .regmap = BCM590XX_REGMAP_SEC, 1264 + .desc = { 1265 + BCM59054_LDO_DESC(LVLDO1, lvldo1, ldo_3_table), 1266 + }, 1267 + }, 1268 + 1269 + { 1270 + .type = BCM590XX_REG_TYPE_GPLDO, 1271 + .regmap = BCM590XX_REGMAP_SEC, 1272 + .desc = { 1273 + BCM59054_LDO_DESC(LVLDO2, lvldo2, ldo_3_table), 1274 + }, 1275 + }, 1276 + 1277 + { 1278 + .type = BCM590XX_REG_TYPE_VBUS, 1279 + .regmap = BCM590XX_REGMAP_SEC, 1280 + .desc = { 1281 + BCM59054_REG_DESC(VBUS, vbus), 1282 + .ops = &bcm590xx_ops_vbus, 1283 + .n_voltages = 1, 1284 + .fixed_uV = 5000000, 1285 + .enable_reg = BCM59054_OTG_CTRL, 1286 + .enable_mask = BCM590XX_VBUS_ENABLE, 1287 + }, 1288 + }, 1289 + }; 1290 + 82 1291 static int bcm590xx_probe(struct platform_device *pdev) 83 1292 { 84 1293 struct bcm590xx *bcm590xx = dev_get_drvdata(pdev->dev.parent); 85 1294 struct bcm590xx_reg *pmu; 1295 + const struct bcm590xx_reg_data *info; 86 1296 struct regulator_config config = { }; 87 - struct bcm590xx_info *info; 88 1297 struct regulator_dev *rdev; 89 - int i; 1298 + unsigned int i; 90 1299 91 1300 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); 92 1301 if (!pmu) ··· 1110 287 1111 288 pmu->mfd = bcm590xx; 1112 289 290 + switch (pmu->mfd->pmu_id) { 291 + case BCM590XX_PMUID_BCM59054: 292 + pmu->n_regulators = BCM59054_NUM_REGS; 293 + if (pmu->mfd->rev_analog == BCM59054_REV_ANALOG_A1) 294 + pmu->regs = bcm59054_a1_regs; 295 + else 296 + pmu->regs = bcm59054_regs; 297 + break; 298 + case BCM590XX_PMUID_BCM59056: 299 + pmu->n_regulators = BCM59056_NUM_REGS; 300 + pmu->regs = bcm59056_regs; 301 + break; 302 + default: 303 + dev_err(bcm590xx->dev, 304 + "unknown device type, could not initialize\n"); 305 + return -EINVAL; 306 + } 307 + 1113 308 platform_set_drvdata(pdev, pmu); 1114 309 1115 - pmu->desc = devm_kcalloc(&pdev->dev, 1116 - BCM590XX_NUM_REGS, 1117 - sizeof(struct regulator_desc), 1118 - GFP_KERNEL); 1119 - if (!pmu->desc) 1120 - return -ENOMEM; 1121 - 1122 - info = bcm590xx_regs; 1123 - 1124 - for (i = 0; i < BCM590XX_NUM_REGS; i++, info++) { 1125 - /* Register the regulators */ 1126 - pmu->desc[i].name = info->name; 1127 - pmu->desc[i].of_match = of_match_ptr(info->name); 1128 - pmu->desc[i].regulators_node = of_match_ptr("regulators"); 1129 - pmu->desc[i].supply_name = info->vin_name; 1130 - pmu->desc[i].id = i; 1131 - pmu->desc[i].volt_table = info->volt_table; 1132 - pmu->desc[i].n_voltages = info->n_voltages; 1133 - pmu->desc[i].linear_ranges = info->linear_ranges; 1134 - pmu->desc[i].n_linear_ranges = info->n_linear_ranges; 1135 - 1136 - if ((BCM590XX_REG_IS_LDO(i)) || (BCM590XX_REG_IS_GPLDO(i))) { 1137 - pmu->desc[i].ops = &bcm590xx_ops_ldo; 1138 - pmu->desc[i].vsel_mask = BCM590XX_LDO_VSEL_MASK; 1139 - } else if (BCM590XX_REG_IS_VBUS(i)) 1140 - pmu->desc[i].ops = &bcm590xx_ops_vbus; 1141 - else { 1142 - pmu->desc[i].ops = &bcm590xx_ops_dcdc; 1143 - pmu->desc[i].vsel_mask = BCM590XX_SR_VSEL_MASK; 1144 - } 1145 - 1146 - if (BCM590XX_REG_IS_VBUS(i)) 1147 - pmu->desc[i].enable_mask = BCM590XX_VBUS_ENABLE; 1148 - else { 1149 - pmu->desc[i].vsel_reg = bcm590xx_get_vsel_register(i); 1150 - pmu->desc[i].enable_is_inverted = true; 1151 - pmu->desc[i].enable_mask = BCM590XX_REG_ENABLE; 1152 - } 1153 - pmu->desc[i].enable_reg = bcm590xx_get_enable_register(i); 1154 - pmu->desc[i].type = REGULATOR_VOLTAGE; 1155 - pmu->desc[i].owner = THIS_MODULE; 310 + /* Register the regulators */ 311 + for (i = 0; i < pmu->n_regulators; i++) { 312 + info = &pmu->regs[i]; 1156 313 1157 314 config.dev = bcm590xx->dev; 1158 315 config.driver_data = pmu; 1159 - if (BCM590XX_REG_IS_GPLDO(i) || BCM590XX_REG_IS_VBUS(i)) 1160 - config.regmap = bcm590xx->regmap_sec; 1161 - else 1162 - config.regmap = bcm590xx->regmap_pri; 1163 316 1164 - rdev = devm_regulator_register(&pdev->dev, &pmu->desc[i], 1165 - &config); 1166 - if (IS_ERR(rdev)) { 317 + switch (info->regmap) { 318 + case BCM590XX_REGMAP_PRI: 319 + config.regmap = bcm590xx->regmap_pri; 320 + break; 321 + case BCM590XX_REGMAP_SEC: 322 + config.regmap = bcm590xx->regmap_sec; 323 + break; 324 + default: 1167 325 dev_err(bcm590xx->dev, 1168 - "failed to register %s regulator\n", 326 + "invalid regmap for %s regulator; this is a driver bug\n", 1169 327 pdev->name); 1170 - return PTR_ERR(rdev); 328 + return -EINVAL; 1171 329 } 330 + 331 + rdev = devm_regulator_register(&pdev->dev, &info->desc, 332 + &config); 333 + if (IS_ERR(rdev)) 334 + return dev_err_probe(bcm590xx->dev, PTR_ERR(rdev), 335 + "failed to register %s regulator\n", 336 + pdev->name); 1172 337 } 1173 338 1174 339 return 0;
+403 -52
drivers/regulator/bd96801-regulator.c
··· 83 83 #define BD96801_LDO6_VSEL_REG 0x26 84 84 #define BD96801_LDO7_VSEL_REG 0x27 85 85 #define BD96801_BUCK_VSEL_MASK 0x1F 86 + #define BD96805_BUCK_VSEL_MASK 0x3f 86 87 #define BD96801_LDO_VSEL_MASK 0xff 87 88 88 89 #define BD96801_MASK_RAMP_DELAY 0xc0 ··· 91 90 #define BD96801_BUCK_INT_VOUT_MASK 0xff 92 91 93 92 #define BD96801_BUCK_VOLTS 256 93 + #define BD96805_BUCK_VOLTS 64 94 94 #define BD96801_LDO_VOLTS 256 95 95 96 96 #define BD96801_OVP_MASK 0x03 ··· 162 160 REGULATOR_LINEAR_RANGE(3300000 - 150000, 0xed, 0xff, 0), 163 161 }; 164 162 163 + /* BD96802 uses same voltage ranges for bucks as BD96801 */ 164 + #define bd96802_tune_volts bd96801_tune_volts 165 + #define bd96802_buck_init_volts bd96801_buck_init_volts 166 + 167 + /* 168 + * On BD96805 we have similar "negative tuning range" as on BD96801, except 169 + * that the max tuning is -310 ... +310 mV (instead of the 150mV). We use same 170 + * approach as with the BD96801 ranges. 171 + */ 172 + static const struct linear_range bd96805_tune_volts[] = { 173 + REGULATOR_LINEAR_RANGE(310000, 0x00, 0x1F, 10000), 174 + REGULATOR_LINEAR_RANGE(0, 0x20, 0x3F, 10000), 175 + }; 176 + 177 + static const struct linear_range bd96805_buck_init_volts[] = { 178 + REGULATOR_LINEAR_RANGE(500000 - 310000, 0x00, 0xc8, 5000), 179 + REGULATOR_LINEAR_RANGE(1550000 - 310000, 0xc9, 0xec, 50000), 180 + REGULATOR_LINEAR_RANGE(3300000 - 310000, 0xed, 0xff, 0), 181 + }; 182 + 183 + /* BD96806 uses same voltage ranges for bucks as BD96805 */ 184 + #define bd96806_tune_volts bd96805_tune_volts 185 + #define bd96806_buck_init_volts bd96805_buck_init_volts 186 + 165 187 static const struct linear_range bd96801_ldo_int_volts[] = { 166 188 REGULATOR_LINEAR_RANGE(300000, 0x00, 0x78, 25000), 167 189 REGULATOR_LINEAR_RANGE(3300000, 0x79, 0xff, 0), ··· 224 198 225 199 static const struct bd96801_irqinfo buck1_irqinfo[] = { 226 200 BD96801_IRQINFO(BD96801_PROT_OCP, "buck1-over-curr-h", 500, 227 - "bd96801-buck1-overcurr-h"), 201 + "buck1-overcurr-h"), 228 202 BD96801_IRQINFO(BD96801_PROT_OCP, "buck1-over-curr-l", 500, 229 - "bd96801-buck1-overcurr-l"), 203 + "buck1-overcurr-l"), 230 204 BD96801_IRQINFO(BD96801_PROT_OCP, "buck1-over-curr-n", 500, 231 - "bd96801-buck1-overcurr-n"), 205 + "buck1-overcurr-n"), 232 206 BD96801_IRQINFO(BD96801_PROT_OVP, "buck1-over-voltage", 500, 233 - "bd96801-buck1-overvolt"), 207 + "buck1-overvolt"), 234 208 BD96801_IRQINFO(BD96801_PROT_UVP, "buck1-under-voltage", 500, 235 - "bd96801-buck1-undervolt"), 209 + "buck1-undervolt"), 236 210 BD96801_IRQINFO(BD96801_PROT_TEMP, "buck1-over-temp", 500, 237 - "bd96801-buck1-thermal") 211 + "buck1-thermal") 238 212 }; 239 213 240 214 static const struct bd96801_irqinfo buck2_irqinfo[] = { 241 215 BD96801_IRQINFO(BD96801_PROT_OCP, "buck2-over-curr-h", 500, 242 - "bd96801-buck2-overcurr-h"), 216 + "buck2-overcurr-h"), 243 217 BD96801_IRQINFO(BD96801_PROT_OCP, "buck2-over-curr-l", 500, 244 - "bd96801-buck2-overcurr-l"), 218 + "buck2-overcurr-l"), 245 219 BD96801_IRQINFO(BD96801_PROT_OCP, "buck2-over-curr-n", 500, 246 - "bd96801-buck2-overcurr-n"), 220 + "buck2-overcurr-n"), 247 221 BD96801_IRQINFO(BD96801_PROT_OVP, "buck2-over-voltage", 500, 248 - "bd96801-buck2-overvolt"), 222 + "buck2-overvolt"), 249 223 BD96801_IRQINFO(BD96801_PROT_UVP, "buck2-under-voltage", 500, 250 - "bd96801-buck2-undervolt"), 224 + "buck2-undervolt"), 251 225 BD96801_IRQINFO(BD96801_PROT_TEMP, "buck2-over-temp", 500, 252 - "bd96801-buck2-thermal") 226 + "buck2-thermal") 253 227 }; 254 228 255 229 static const struct bd96801_irqinfo buck3_irqinfo[] = { 256 230 BD96801_IRQINFO(BD96801_PROT_OCP, "buck3-over-curr-h", 500, 257 - "bd96801-buck3-overcurr-h"), 231 + "buck3-overcurr-h"), 258 232 BD96801_IRQINFO(BD96801_PROT_OCP, "buck3-over-curr-l", 500, 259 - "bd96801-buck3-overcurr-l"), 233 + "buck3-overcurr-l"), 260 234 BD96801_IRQINFO(BD96801_PROT_OCP, "buck3-over-curr-n", 500, 261 - "bd96801-buck3-overcurr-n"), 235 + "buck3-overcurr-n"), 262 236 BD96801_IRQINFO(BD96801_PROT_OVP, "buck3-over-voltage", 500, 263 - "bd96801-buck3-overvolt"), 237 + "buck3-overvolt"), 264 238 BD96801_IRQINFO(BD96801_PROT_UVP, "buck3-under-voltage", 500, 265 - "bd96801-buck3-undervolt"), 239 + "buck3-undervolt"), 266 240 BD96801_IRQINFO(BD96801_PROT_TEMP, "buck3-over-temp", 500, 267 - "bd96801-buck3-thermal") 241 + "buck3-thermal") 268 242 }; 269 243 270 244 static const struct bd96801_irqinfo buck4_irqinfo[] = { 271 245 BD96801_IRQINFO(BD96801_PROT_OCP, "buck4-over-curr-h", 500, 272 - "bd96801-buck4-overcurr-h"), 246 + "buck4-overcurr-h"), 273 247 BD96801_IRQINFO(BD96801_PROT_OCP, "buck4-over-curr-l", 500, 274 - "bd96801-buck4-overcurr-l"), 248 + "buck4-overcurr-l"), 275 249 BD96801_IRQINFO(BD96801_PROT_OCP, "buck4-over-curr-n", 500, 276 - "bd96801-buck4-overcurr-n"), 250 + "buck4-overcurr-n"), 277 251 BD96801_IRQINFO(BD96801_PROT_OVP, "buck4-over-voltage", 500, 278 - "bd96801-buck4-overvolt"), 252 + "buck4-overvolt"), 279 253 BD96801_IRQINFO(BD96801_PROT_UVP, "buck4-under-voltage", 500, 280 - "bd96801-buck4-undervolt"), 254 + "buck4-undervolt"), 281 255 BD96801_IRQINFO(BD96801_PROT_TEMP, "buck4-over-temp", 500, 282 - "bd96801-buck4-thermal") 256 + "buck4-thermal") 283 257 }; 284 258 285 259 static const struct bd96801_irqinfo ldo5_irqinfo[] = { 286 260 BD96801_IRQINFO(BD96801_PROT_OCP, "ldo5-overcurr", 500, 287 - "bd96801-ldo5-overcurr"), 261 + "ldo5-overcurr"), 288 262 BD96801_IRQINFO(BD96801_PROT_OVP, "ldo5-over-voltage", 500, 289 - "bd96801-ldo5-overvolt"), 263 + "ldo5-overvolt"), 290 264 BD96801_IRQINFO(BD96801_PROT_UVP, "ldo5-under-voltage", 500, 291 - "bd96801-ldo5-undervolt"), 265 + "ldo5-undervolt"), 292 266 }; 293 267 294 268 static const struct bd96801_irqinfo ldo6_irqinfo[] = { 295 269 BD96801_IRQINFO(BD96801_PROT_OCP, "ldo6-overcurr", 500, 296 - "bd96801-ldo6-overcurr"), 270 + "ldo6-overcurr"), 297 271 BD96801_IRQINFO(BD96801_PROT_OVP, "ldo6-over-voltage", 500, 298 - "bd96801-ldo6-overvolt"), 272 + "ldo6-overvolt"), 299 273 BD96801_IRQINFO(BD96801_PROT_UVP, "ldo6-under-voltage", 500, 300 - "bd96801-ldo6-undervolt"), 274 + "ldo6-undervolt"), 301 275 }; 302 276 303 277 static const struct bd96801_irqinfo ldo7_irqinfo[] = { 304 278 BD96801_IRQINFO(BD96801_PROT_OCP, "ldo7-overcurr", 500, 305 - "bd96801-ldo7-overcurr"), 279 + "ldo7-overcurr"), 306 280 BD96801_IRQINFO(BD96801_PROT_OVP, "ldo7-over-voltage", 500, 307 - "bd96801-ldo7-overvolt"), 281 + "ldo7-overvolt"), 308 282 BD96801_IRQINFO(BD96801_PROT_UVP, "ldo7-under-voltage", 500, 309 - "bd96801-ldo7-undervolt"), 283 + "ldo7-undervolt"), 310 284 }; 311 285 312 286 struct bd96801_irq_desc { ··· 328 302 struct bd96801_regulator_data regulator_data[BD96801_NUM_REGULATORS]; 329 303 struct regmap *regmap; 330 304 int fatal_ind; 305 + int num_regulators; 331 306 }; 332 307 333 308 static int ldo_map_notif(int irq, struct regulator_irq_data *rid, ··· 530 503 * case later. What we can easly do for preparing is to not use static global 531 504 * data for regulators though. 532 505 */ 506 + static const struct bd96801_pmic_data bd96802_data = { 507 + .regulator_data = { 508 + { 509 + .desc = { 510 + .name = "buck1", 511 + .of_match = of_match_ptr("buck1"), 512 + .regulators_node = of_match_ptr("regulators"), 513 + .id = BD96801_BUCK1, 514 + .ops = &bd96801_buck_ops, 515 + .type = REGULATOR_VOLTAGE, 516 + .linear_ranges = bd96802_tune_volts, 517 + .n_linear_ranges = ARRAY_SIZE(bd96802_tune_volts), 518 + .n_voltages = BD96801_BUCK_VOLTS, 519 + .enable_reg = BD96801_REG_ENABLE, 520 + .enable_mask = BD96801_BUCK1_EN_MASK, 521 + .enable_is_inverted = true, 522 + .vsel_reg = BD96801_BUCK1_VSEL_REG, 523 + .vsel_mask = BD96801_BUCK_VSEL_MASK, 524 + .ramp_reg = BD96801_BUCK1_VSEL_REG, 525 + .ramp_mask = BD96801_MASK_RAMP_DELAY, 526 + .ramp_delay_table = &buck_ramp_table[0], 527 + .n_ramp_values = ARRAY_SIZE(buck_ramp_table), 528 + .owner = THIS_MODULE, 529 + }, 530 + .init_ranges = bd96802_buck_init_volts, 531 + .num_ranges = ARRAY_SIZE(bd96802_buck_init_volts), 532 + .irq_desc = { 533 + .irqinfo = (struct bd96801_irqinfo *)&buck1_irqinfo[0], 534 + .num_irqs = ARRAY_SIZE(buck1_irqinfo), 535 + }, 536 + }, 537 + { 538 + .desc = { 539 + .name = "buck2", 540 + .of_match = of_match_ptr("buck2"), 541 + .regulators_node = of_match_ptr("regulators"), 542 + .id = BD96801_BUCK2, 543 + .ops = &bd96801_buck_ops, 544 + .type = REGULATOR_VOLTAGE, 545 + .linear_ranges = bd96802_tune_volts, 546 + .n_linear_ranges = ARRAY_SIZE(bd96802_tune_volts), 547 + .n_voltages = BD96801_BUCK_VOLTS, 548 + .enable_reg = BD96801_REG_ENABLE, 549 + .enable_mask = BD96801_BUCK2_EN_MASK, 550 + .enable_is_inverted = true, 551 + .vsel_reg = BD96801_BUCK2_VSEL_REG, 552 + .vsel_mask = BD96801_BUCK_VSEL_MASK, 553 + .ramp_reg = BD96801_BUCK2_VSEL_REG, 554 + .ramp_mask = BD96801_MASK_RAMP_DELAY, 555 + .ramp_delay_table = &buck_ramp_table[0], 556 + .n_ramp_values = ARRAY_SIZE(buck_ramp_table), 557 + .owner = THIS_MODULE, 558 + }, 559 + .irq_desc = { 560 + .irqinfo = (struct bd96801_irqinfo *)&buck2_irqinfo[0], 561 + .num_irqs = ARRAY_SIZE(buck2_irqinfo), 562 + }, 563 + .init_ranges = bd96802_buck_init_volts, 564 + .num_ranges = ARRAY_SIZE(bd96802_buck_init_volts), 565 + }, 566 + }, 567 + .num_regulators = 2, 568 + }; 569 + 533 570 static const struct bd96801_pmic_data bd96801_data = { 534 571 .regulator_data = { 535 572 { ··· 779 688 .ldo_vol_lvl = BD96801_LDO7_VOL_LVL_REG, 780 689 }, 781 690 }, 691 + .num_regulators = 7, 782 692 }; 783 693 784 - static int initialize_pmic_data(struct device *dev, 694 + static const struct bd96801_pmic_data bd96805_data = { 695 + .regulator_data = { 696 + { 697 + .desc = { 698 + .name = "buck1", 699 + .of_match = of_match_ptr("buck1"), 700 + .regulators_node = of_match_ptr("regulators"), 701 + .id = BD96801_BUCK1, 702 + .ops = &bd96801_buck_ops, 703 + .type = REGULATOR_VOLTAGE, 704 + .linear_ranges = bd96805_tune_volts, 705 + .n_linear_ranges = ARRAY_SIZE(bd96805_tune_volts), 706 + .n_voltages = BD96805_BUCK_VOLTS, 707 + .enable_reg = BD96801_REG_ENABLE, 708 + .enable_mask = BD96801_BUCK1_EN_MASK, 709 + .enable_is_inverted = true, 710 + .vsel_reg = BD96801_BUCK1_VSEL_REG, 711 + .vsel_mask = BD96805_BUCK_VSEL_MASK, 712 + .ramp_reg = BD96801_BUCK1_VSEL_REG, 713 + .ramp_mask = BD96801_MASK_RAMP_DELAY, 714 + .ramp_delay_table = &buck_ramp_table[0], 715 + .n_ramp_values = ARRAY_SIZE(buck_ramp_table), 716 + .owner = THIS_MODULE, 717 + }, 718 + .init_ranges = bd96805_buck_init_volts, 719 + .num_ranges = ARRAY_SIZE(bd96805_buck_init_volts), 720 + .irq_desc = { 721 + .irqinfo = (struct bd96801_irqinfo *)&buck1_irqinfo[0], 722 + .num_irqs = ARRAY_SIZE(buck1_irqinfo), 723 + }, 724 + }, { 725 + .desc = { 726 + .name = "buck2", 727 + .of_match = of_match_ptr("buck2"), 728 + .regulators_node = of_match_ptr("regulators"), 729 + .id = BD96801_BUCK2, 730 + .ops = &bd96801_buck_ops, 731 + .type = REGULATOR_VOLTAGE, 732 + .linear_ranges = bd96805_tune_volts, 733 + .n_linear_ranges = ARRAY_SIZE(bd96805_tune_volts), 734 + .n_voltages = BD96805_BUCK_VOLTS, 735 + .enable_reg = BD96801_REG_ENABLE, 736 + .enable_mask = BD96801_BUCK2_EN_MASK, 737 + .enable_is_inverted = true, 738 + .vsel_reg = BD96801_BUCK2_VSEL_REG, 739 + .vsel_mask = BD96805_BUCK_VSEL_MASK, 740 + .ramp_reg = BD96801_BUCK2_VSEL_REG, 741 + .ramp_mask = BD96801_MASK_RAMP_DELAY, 742 + .ramp_delay_table = &buck_ramp_table[0], 743 + .n_ramp_values = ARRAY_SIZE(buck_ramp_table), 744 + .owner = THIS_MODULE, 745 + }, 746 + .irq_desc = { 747 + .irqinfo = (struct bd96801_irqinfo *)&buck2_irqinfo[0], 748 + .num_irqs = ARRAY_SIZE(buck2_irqinfo), 749 + }, 750 + .init_ranges = bd96805_buck_init_volts, 751 + .num_ranges = ARRAY_SIZE(bd96805_buck_init_volts), 752 + }, { 753 + .desc = { 754 + .name = "buck3", 755 + .of_match = of_match_ptr("buck3"), 756 + .regulators_node = of_match_ptr("regulators"), 757 + .id = BD96801_BUCK3, 758 + .ops = &bd96801_buck_ops, 759 + .type = REGULATOR_VOLTAGE, 760 + .linear_ranges = bd96805_tune_volts, 761 + .n_linear_ranges = ARRAY_SIZE(bd96805_tune_volts), 762 + .n_voltages = BD96805_BUCK_VOLTS, 763 + .enable_reg = BD96801_REG_ENABLE, 764 + .enable_mask = BD96801_BUCK3_EN_MASK, 765 + .enable_is_inverted = true, 766 + .vsel_reg = BD96801_BUCK3_VSEL_REG, 767 + .vsel_mask = BD96805_BUCK_VSEL_MASK, 768 + .ramp_reg = BD96801_BUCK3_VSEL_REG, 769 + .ramp_mask = BD96801_MASK_RAMP_DELAY, 770 + .ramp_delay_table = &buck_ramp_table[0], 771 + .n_ramp_values = ARRAY_SIZE(buck_ramp_table), 772 + .owner = THIS_MODULE, 773 + }, 774 + .irq_desc = { 775 + .irqinfo = (struct bd96801_irqinfo *)&buck3_irqinfo[0], 776 + .num_irqs = ARRAY_SIZE(buck3_irqinfo), 777 + }, 778 + .init_ranges = bd96805_buck_init_volts, 779 + .num_ranges = ARRAY_SIZE(bd96805_buck_init_volts), 780 + }, { 781 + .desc = { 782 + .name = "buck4", 783 + .of_match = of_match_ptr("buck4"), 784 + .regulators_node = of_match_ptr("regulators"), 785 + .id = BD96801_BUCK4, 786 + .ops = &bd96801_buck_ops, 787 + .type = REGULATOR_VOLTAGE, 788 + .linear_ranges = bd96805_tune_volts, 789 + .n_linear_ranges = ARRAY_SIZE(bd96805_tune_volts), 790 + .n_voltages = BD96805_BUCK_VOLTS, 791 + .enable_reg = BD96801_REG_ENABLE, 792 + .enable_mask = BD96801_BUCK4_EN_MASK, 793 + .enable_is_inverted = true, 794 + .vsel_reg = BD96801_BUCK4_VSEL_REG, 795 + .vsel_mask = BD96805_BUCK_VSEL_MASK, 796 + .ramp_reg = BD96801_BUCK4_VSEL_REG, 797 + .ramp_mask = BD96801_MASK_RAMP_DELAY, 798 + .ramp_delay_table = &buck_ramp_table[0], 799 + .n_ramp_values = ARRAY_SIZE(buck_ramp_table), 800 + .owner = THIS_MODULE, 801 + }, 802 + .irq_desc = { 803 + .irqinfo = (struct bd96801_irqinfo *)&buck4_irqinfo[0], 804 + .num_irqs = ARRAY_SIZE(buck4_irqinfo), 805 + }, 806 + .init_ranges = bd96805_buck_init_volts, 807 + .num_ranges = ARRAY_SIZE(bd96805_buck_init_volts), 808 + }, { 809 + .desc = { 810 + .name = "ldo5", 811 + .of_match = of_match_ptr("ldo5"), 812 + .regulators_node = of_match_ptr("regulators"), 813 + .id = BD96801_LDO5, 814 + .ops = &bd96801_ldo_ops, 815 + .type = REGULATOR_VOLTAGE, 816 + .linear_ranges = bd96801_ldo_int_volts, 817 + .n_linear_ranges = ARRAY_SIZE(bd96801_ldo_int_volts), 818 + .n_voltages = BD96801_LDO_VOLTS, 819 + .enable_reg = BD96801_REG_ENABLE, 820 + .enable_mask = BD96801_LDO5_EN_MASK, 821 + .enable_is_inverted = true, 822 + .vsel_reg = BD96801_LDO5_VSEL_REG, 823 + .vsel_mask = BD96801_LDO_VSEL_MASK, 824 + .owner = THIS_MODULE, 825 + }, 826 + .irq_desc = { 827 + .irqinfo = (struct bd96801_irqinfo *)&ldo5_irqinfo[0], 828 + .num_irqs = ARRAY_SIZE(ldo5_irqinfo), 829 + }, 830 + .ldo_vol_lvl = BD96801_LDO5_VOL_LVL_REG, 831 + }, { 832 + .desc = { 833 + .name = "ldo6", 834 + .of_match = of_match_ptr("ldo6"), 835 + .regulators_node = of_match_ptr("regulators"), 836 + .id = BD96801_LDO6, 837 + .ops = &bd96801_ldo_ops, 838 + .type = REGULATOR_VOLTAGE, 839 + .linear_ranges = bd96801_ldo_int_volts, 840 + .n_linear_ranges = ARRAY_SIZE(bd96801_ldo_int_volts), 841 + .n_voltages = BD96801_LDO_VOLTS, 842 + .enable_reg = BD96801_REG_ENABLE, 843 + .enable_mask = BD96801_LDO6_EN_MASK, 844 + .enable_is_inverted = true, 845 + .vsel_reg = BD96801_LDO6_VSEL_REG, 846 + .vsel_mask = BD96801_LDO_VSEL_MASK, 847 + .owner = THIS_MODULE, 848 + }, 849 + .irq_desc = { 850 + .irqinfo = (struct bd96801_irqinfo *)&ldo6_irqinfo[0], 851 + .num_irqs = ARRAY_SIZE(ldo6_irqinfo), 852 + }, 853 + .ldo_vol_lvl = BD96801_LDO6_VOL_LVL_REG, 854 + }, { 855 + .desc = { 856 + .name = "ldo7", 857 + .of_match = of_match_ptr("ldo7"), 858 + .regulators_node = of_match_ptr("regulators"), 859 + .id = BD96801_LDO7, 860 + .ops = &bd96801_ldo_ops, 861 + .type = REGULATOR_VOLTAGE, 862 + .linear_ranges = bd96801_ldo_int_volts, 863 + .n_linear_ranges = ARRAY_SIZE(bd96801_ldo_int_volts), 864 + .n_voltages = BD96801_LDO_VOLTS, 865 + .enable_reg = BD96801_REG_ENABLE, 866 + .enable_mask = BD96801_LDO7_EN_MASK, 867 + .enable_is_inverted = true, 868 + .vsel_reg = BD96801_LDO7_VSEL_REG, 869 + .vsel_mask = BD96801_LDO_VSEL_MASK, 870 + .owner = THIS_MODULE, 871 + }, 872 + .irq_desc = { 873 + .irqinfo = (struct bd96801_irqinfo *)&ldo7_irqinfo[0], 874 + .num_irqs = ARRAY_SIZE(ldo7_irqinfo), 875 + }, 876 + .ldo_vol_lvl = BD96801_LDO7_VOL_LVL_REG, 877 + }, 878 + }, 879 + .num_regulators = 7, 880 + }; 881 + 882 + static const struct bd96801_pmic_data bd96806_data = { 883 + .regulator_data = { 884 + { 885 + .desc = { 886 + .name = "buck1", 887 + .of_match = of_match_ptr("buck1"), 888 + .regulators_node = of_match_ptr("regulators"), 889 + .id = BD96801_BUCK1, 890 + .ops = &bd96801_buck_ops, 891 + .type = REGULATOR_VOLTAGE, 892 + .linear_ranges = bd96806_tune_volts, 893 + .n_linear_ranges = ARRAY_SIZE(bd96806_tune_volts), 894 + .n_voltages = BD96805_BUCK_VOLTS, 895 + .enable_reg = BD96801_REG_ENABLE, 896 + .enable_mask = BD96801_BUCK1_EN_MASK, 897 + .enable_is_inverted = true, 898 + .vsel_reg = BD96801_BUCK1_VSEL_REG, 899 + .vsel_mask = BD96805_BUCK_VSEL_MASK, 900 + .ramp_reg = BD96801_BUCK1_VSEL_REG, 901 + .ramp_mask = BD96801_MASK_RAMP_DELAY, 902 + .ramp_delay_table = &buck_ramp_table[0], 903 + .n_ramp_values = ARRAY_SIZE(buck_ramp_table), 904 + .owner = THIS_MODULE, 905 + }, 906 + .init_ranges = bd96806_buck_init_volts, 907 + .num_ranges = ARRAY_SIZE(bd96806_buck_init_volts), 908 + .irq_desc = { 909 + .irqinfo = (struct bd96801_irqinfo *)&buck1_irqinfo[0], 910 + .num_irqs = ARRAY_SIZE(buck1_irqinfo), 911 + }, 912 + }, 913 + { 914 + .desc = { 915 + .name = "buck2", 916 + .of_match = of_match_ptr("buck2"), 917 + .regulators_node = of_match_ptr("regulators"), 918 + .id = BD96801_BUCK2, 919 + .ops = &bd96801_buck_ops, 920 + .type = REGULATOR_VOLTAGE, 921 + .linear_ranges = bd96806_tune_volts, 922 + .n_linear_ranges = ARRAY_SIZE(bd96806_tune_volts), 923 + .n_voltages = BD96805_BUCK_VOLTS, 924 + .enable_reg = BD96801_REG_ENABLE, 925 + .enable_mask = BD96801_BUCK2_EN_MASK, 926 + .enable_is_inverted = true, 927 + .vsel_reg = BD96801_BUCK2_VSEL_REG, 928 + .vsel_mask = BD96805_BUCK_VSEL_MASK, 929 + .ramp_reg = BD96801_BUCK2_VSEL_REG, 930 + .ramp_mask = BD96801_MASK_RAMP_DELAY, 931 + .ramp_delay_table = &buck_ramp_table[0], 932 + .n_ramp_values = ARRAY_SIZE(buck_ramp_table), 933 + .owner = THIS_MODULE, 934 + }, 935 + .irq_desc = { 936 + .irqinfo = (struct bd96801_irqinfo *)&buck2_irqinfo[0], 937 + .num_irqs = ARRAY_SIZE(buck2_irqinfo), 938 + }, 939 + .init_ranges = bd96806_buck_init_volts, 940 + .num_ranges = ARRAY_SIZE(bd96806_buck_init_volts), 941 + }, 942 + }, 943 + .num_regulators = 2, 944 + }; 945 + 946 + static int initialize_pmic_data(struct platform_device *pdev, 785 947 struct bd96801_pmic_data *pdata) 786 948 { 949 + struct device *dev = &pdev->dev; 787 950 int r, i; 788 951 789 952 /* ··· 1045 700 * wish to modify IRQ information independently for each driver 1046 701 * instance. 1047 702 */ 1048 - for (r = 0; r < BD96801_NUM_REGULATORS; r++) { 703 + for (r = 0; r < pdata->num_regulators; r++) { 1049 704 const struct bd96801_irqinfo *template; 1050 705 struct bd96801_irqinfo *new; 1051 706 int num_infos; ··· 1086 741 int i; 1087 742 void *retp; 1088 743 static const char * const single_out_errb_irqs[] = { 1089 - "bd96801-%s-pvin-err", "bd96801-%s-ovp-err", 1090 - "bd96801-%s-uvp-err", "bd96801-%s-shdn-err", 744 + "%s-pvin-err", "%s-ovp-err", "%s-uvp-err", "%s-shdn-err", 1091 745 }; 1092 746 1093 747 for (i = 0; i < ARRAY_SIZE(single_out_errb_irqs); i++) { ··· 1123 779 int i, num_irqs; 1124 780 void *retp; 1125 781 static const char * const global_errb_irqs[] = { 1126 - "bd96801-otp-err", "bd96801-dbist-err", "bd96801-eep-err", 1127 - "bd96801-abist-err", "bd96801-prstb-err", "bd96801-drmoserr1", 1128 - "bd96801-drmoserr2", "bd96801-slave-err", "bd96801-vref-err", 1129 - "bd96801-tsd", "bd96801-uvlo-err", "bd96801-ovlo-err", 1130 - "bd96801-osc-err", "bd96801-pon-err", "bd96801-poff-err", 1131 - "bd96801-cmd-shdn-err", "bd96801-int-shdn-err" 782 + "otp-err", "dbist-err", "eep-err", "abist-err", "prstb-err", 783 + "drmoserr1", "drmoserr2", "slave-err", "vref-err", "tsd", 784 + "uvlo-err", "ovlo-err", "osc-err", "pon-err", "poff-err", 785 + "cmd-shdn-err", "int-shdn-err" 1132 786 }; 1133 787 1134 788 num_irqs = ARRAY_SIZE(global_errb_irqs); ··· 1211 869 { 1212 870 struct regulator_dev *ldo_errs_rdev_arr[BD96801_NUM_LDOS]; 1213 871 struct regulator_dev *all_rdevs[BD96801_NUM_REGULATORS]; 872 + struct bd96801_pmic_data *pdata_template; 1214 873 struct bd96801_regulator_data *rdesc; 1215 874 struct regulator_config config = {}; 1216 875 int ldo_errs_arr[BD96801_NUM_LDOS]; ··· 1224 881 1225 882 parent = pdev->dev.parent; 1226 883 1227 - pdata = devm_kmemdup(&pdev->dev, &bd96801_data, sizeof(bd96801_data), 884 + pdata_template = (struct bd96801_pmic_data *)platform_get_device_id(pdev)->driver_data; 885 + if (!pdata_template) 886 + return -ENODEV; 887 + 888 + pdata = devm_kmemdup(&pdev->dev, pdata_template, sizeof(bd96801_data), 1228 889 GFP_KERNEL); 1229 890 if (!pdata) 1230 891 return -ENOMEM; 1231 892 1232 - if (initialize_pmic_data(&pdev->dev, pdata)) 893 + if (initialize_pmic_data(pdev, pdata)) 1233 894 return -ENOMEM; 1234 895 1235 896 pdata->regmap = dev_get_regmap(parent, NULL); ··· 1256 909 use_errb = true; 1257 910 1258 911 ret = bd96801_walk_regulator_dt(&pdev->dev, pdata->regmap, rdesc, 1259 - BD96801_NUM_REGULATORS); 912 + pdata->num_regulators); 1260 913 if (ret) 1261 914 return ret; 1262 915 1263 - for (i = 0; i < ARRAY_SIZE(pdata->regulator_data); i++) { 916 + for (i = 0; i < pdata->num_regulators; i++) { 1264 917 struct regulator_dev *rdev; 1265 918 struct bd96801_irq_desc *idesc = &rdesc[i].irq_desc; 1266 919 int j; ··· 1273 926 rdesc[i].desc.name); 1274 927 return PTR_ERR(rdev); 1275 928 } 929 + 1276 930 all_rdevs[i] = rdev; 1277 931 /* 1278 932 * LDOs don't have own temperature monitoring. If temperature ··· 1304 956 if (temp_notif_ldos) { 1305 957 int irq; 1306 958 struct regulator_irq_desc tw_desc = { 1307 - .name = "bd96801-core-thermal", 959 + .name = "core-thermal", 1308 960 .irq_off_ms = 500, 1309 961 .map_event = ldo_map_notif, 1310 962 }; 1311 963 1312 - irq = platform_get_irq_byname(pdev, "bd96801-core-thermal"); 964 + irq = platform_get_irq_byname(pdev, "core-thermal"); 1313 965 if (irq < 0) 1314 966 return irq; 1315 967 ··· 1323 975 1324 976 if (use_errb) 1325 977 return bd96801_global_errb_irqs(pdev, all_rdevs, 1326 - ARRAY_SIZE(all_rdevs)); 978 + pdata->num_regulators); 1327 979 1328 980 return 0; 1329 981 } 1330 982 1331 983 static const struct platform_device_id bd96801_pmic_id[] = { 1332 - { "bd96801-regulator", }, 1333 - { } 984 + { "bd96801-regulator", (kernel_ulong_t)&bd96801_data }, 985 + { "bd96802-regulator", (kernel_ulong_t)&bd96802_data }, 986 + { "bd96805-regulator", (kernel_ulong_t)&bd96805_data }, 987 + { "bd96806-regulator", (kernel_ulong_t)&bd96806_data }, 988 + { }, 1334 989 }; 1335 990 MODULE_DEVICE_TABLE(platform, bd96801_pmic_id); 1336 991
-3
include/linux/mfd/aat2870.h
··· 133 133 int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val); 134 134 int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val); 135 135 int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val); 136 - 137 - /* for debugfs */ 138 - struct dentry *dentry_root; 139 136 }; 140 137 141 138 struct aat2870_subdev_info {
+27 -1
include/linux/mfd/bcm590xx.h
··· 13 13 #include <linux/i2c.h> 14 14 #include <linux/regmap.h> 15 15 16 + /* PMU ID register values; also used as device type */ 17 + #define BCM590XX_PMUID_BCM59054 0x54 18 + #define BCM590XX_PMUID_BCM59056 0x56 19 + 20 + /* Known chip revision IDs */ 21 + #define BCM59054_REV_DIGITAL_A1 1 22 + #define BCM59054_REV_ANALOG_A1 2 23 + 24 + #define BCM59056_REV_DIGITAL_A0 1 25 + #define BCM59056_REV_ANALOG_A0 1 26 + 27 + #define BCM59056_REV_DIGITAL_B0 2 28 + #define BCM59056_REV_ANALOG_B0 2 29 + 30 + /* regmap types */ 31 + enum bcm590xx_regmap_type { 32 + BCM590XX_REGMAP_PRI, 33 + BCM590XX_REGMAP_SEC, 34 + }; 35 + 16 36 /* max register address */ 17 37 #define BCM590XX_MAX_REGISTER_PRI 0xe7 18 38 #define BCM590XX_MAX_REGISTER_SEC 0xf0 ··· 43 23 struct i2c_client *i2c_sec; 44 24 struct regmap *regmap_pri; 45 25 struct regmap *regmap_sec; 46 - unsigned int id; 26 + 27 + /* PMU ID value; also used as device type */ 28 + u8 pmu_id; 29 + 30 + /* Chip revision, read from PMUREV reg */ 31 + u8 rev_digital; 32 + u8 rev_analog; 47 33 }; 48 34 49 35 #endif /* __LINUX_MFD_BCM590XX_H */
+1 -1
include/linux/mfd/max14577-private.h
··· 2 2 /* 3 3 * max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip 4 4 * 5 - * Copyright (C) 2014 Samsung Electrnoics 5 + * Copyright (C) 2014 Samsung Electronics 6 6 * Chanwoo Choi <cw00.choi@samsung.com> 7 7 * Krzysztof Kozlowski <krzk@kernel.org> 8 8 */
+1 -1
include/linux/mfd/max14577.h
··· 2 2 /* 3 3 * max14577.h - Driver for the Maxim 14577/77836 4 4 * 5 - * Copyright (C) 2014 Samsung Electrnoics 5 + * Copyright (C) 2014 Samsung Electronics 6 6 * Chanwoo Choi <cw00.choi@samsung.com> 7 7 * Krzysztof Kozlowski <krzk@kernel.org> 8 8 *
+1 -1
include/linux/mfd/max77686-private.h
··· 2 2 /* 3 3 * max77686-private.h - Voltage regulator driver for the Maxim 77686/802 4 4 * 5 - * Copyright (C) 2012 Samsung Electrnoics 5 + * Copyright (C) 2012 Samsung Electronics 6 6 * Chiwoong Byun <woong.byun@samsung.com> 7 7 */ 8 8
+1 -1
include/linux/mfd/max77686.h
··· 2 2 /* 3 3 * max77686.h - Driver for the Maxim 77686/802 4 4 * 5 - * Copyright (C) 2012 Samsung Electrnoics 5 + * Copyright (C) 2012 Samsung Electronics 6 6 * Chiwoong Byun <woong.byun@samsung.com> 7 7 * 8 8 * This driver is based on max8997.h
+1 -1
include/linux/mfd/max77693-private.h
··· 2 2 /* 3 3 * max77693-private.h - Voltage regulator driver for the Maxim 77693 4 4 * 5 - * Copyright (C) 2012 Samsung Electrnoics 5 + * Copyright (C) 2012 Samsung Electronics 6 6 * SangYoung Son <hello.son@samsung.com> 7 7 * 8 8 * This program is not provided / owned by Maxim Integrated Products.
+1 -1
include/linux/mfd/max77693.h
··· 2 2 /* 3 3 * max77693.h - Driver for the Maxim 77693 4 4 * 5 - * Copyright (C) 2012 Samsung Electrnoics 5 + * Copyright (C) 2012 Samsung Electronics 6 6 * SangYoung Son <hello.son@samsung.com> 7 7 * 8 8 * This program is not provided / owned by Maxim Integrated Products.
+1 -1
include/linux/mfd/max8997-private.h
··· 2 2 /* 3 3 * max8997-private.h - Voltage regulator driver for the Maxim 8997 4 4 * 5 - * Copyright (C) 2010 Samsung Electrnoics 5 + * Copyright (C) 2010 Samsung Electronics 6 6 * MyungJoo Ham <myungjoo.ham@samsung.com> 7 7 */ 8 8
+1 -1
include/linux/mfd/max8997.h
··· 2 2 /* 3 3 * max8997.h - Driver for the Maxim 8997/8966 4 4 * 5 - * Copyright (C) 2009-2010 Samsung Electrnoics 5 + * Copyright (C) 2009-2010 Samsung Electronics 6 6 * MyungJoo Ham <myungjoo.ham@samsung.com> 7 7 * 8 8 * This driver is based on max8998.h
+1 -1
include/linux/mfd/max8998-private.h
··· 2 2 /* 3 3 * max8998-private.h - Voltage regulator driver for the Maxim 8998 4 4 * 5 - * Copyright (C) 2009-2010 Samsung Electrnoics 5 + * Copyright (C) 2009-2010 Samsung Electronics 6 6 * Kyungmin Park <kyungmin.park@samsung.com> 7 7 * Marek Szyprowski <m.szyprowski@samsung.com> 8 8 */
+1 -1
include/linux/mfd/max8998.h
··· 2 2 /* 3 3 * max8998.h - Voltage regulator driver for the Maxim 8998 4 4 * 5 - * Copyright (C) 2009-2010 Samsung Electrnoics 5 + * Copyright (C) 2009-2010 Samsung Electronics 6 6 * Kyungmin Park <kyungmin.park@samsung.com> 7 7 * Marek Szyprowski <m.szyprowski@samsung.com> 8 8 */
+2
include/linux/mfd/rohm-bd96801.h
··· 40 40 * INTB status registers are at range 0x5c ... 0x63 41 41 */ 42 42 #define BD96801_REG_INT_SYS_ERRB1 0x52 43 + #define BD96801_REG_INT_BUCK2_ERRB 0x56 43 44 #define BD96801_REG_INT_SYS_INTB 0x5c 45 + #define BD96801_REG_INT_BUCK2_INTB 0x5e 44 46 #define BD96801_REG_INT_LDO7_INTB 0x63 45 47 46 48 /* MASK registers */
+74
include/linux/mfd/rohm-bd96802.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2025 ROHM Semiconductors 4 + * 5 + * The digital interface of trhe BD96802 PMIC is a reduced version of the 6 + * BD96801. Hence the BD96801 definitions are used for registers and masks 7 + * while this header only holds the IRQ definitions - mainly to avoid gaps in 8 + * IRQ numbers caused by the lack of some BUCKs / LDOs and their respective 9 + * IRQs. 10 + */ 11 + 12 + #ifndef __LINUX_MFD_BD96802_H__ 13 + #define __LINUX_MFD_BD96802_H__ 14 + 15 + /* ERRB IRQs */ 16 + enum { 17 + /* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */ 18 + BD96802_OTP_ERR_STAT, 19 + BD96802_DBIST_ERR_STAT, 20 + BD96802_EEP_ERR_STAT, 21 + BD96802_ABIST_ERR_STAT, 22 + BD96802_PRSTB_ERR_STAT, 23 + BD96802_DRMOS1_ERR_STAT, 24 + BD96802_DRMOS2_ERR_STAT, 25 + BD96802_SLAVE_ERR_STAT, 26 + BD96802_VREF_ERR_STAT, 27 + BD96802_TSD_ERR_STAT, 28 + BD96802_UVLO_ERR_STAT, 29 + BD96802_OVLO_ERR_STAT, 30 + BD96802_OSC_ERR_STAT, 31 + BD96802_PON_ERR_STAT, 32 + BD96802_POFF_ERR_STAT, 33 + BD96802_CMD_SHDN_ERR_STAT, 34 + BD96802_INT_SHDN_ERR_STAT, 35 + 36 + /* Reg 0x55 BUCK1 ERR IRQs */ 37 + BD96802_BUCK1_PVIN_ERR_STAT, 38 + BD96802_BUCK1_OVP_ERR_STAT, 39 + BD96802_BUCK1_UVP_ERR_STAT, 40 + BD96802_BUCK1_SHDN_ERR_STAT, 41 + 42 + /* Reg 0x56 BUCK2 ERR IRQs */ 43 + BD96802_BUCK2_PVIN_ERR_STAT, 44 + BD96802_BUCK2_OVP_ERR_STAT, 45 + BD96802_BUCK2_UVP_ERR_STAT, 46 + BD96802_BUCK2_SHDN_ERR_STAT, 47 + }; 48 + 49 + /* INTB IRQs */ 50 + enum { 51 + /* Reg 0x5c (System INTB) */ 52 + BD96802_TW_STAT, 53 + BD96802_WDT_ERR_STAT, 54 + BD96802_I2C_ERR_STAT, 55 + BD96802_CHIP_IF_ERR_STAT, 56 + 57 + /* Reg 0x5d (BUCK1 INTB) */ 58 + BD96802_BUCK1_OCPH_STAT, 59 + BD96802_BUCK1_OCPL_STAT, 60 + BD96802_BUCK1_OCPN_STAT, 61 + BD96802_BUCK1_OVD_STAT, 62 + BD96802_BUCK1_UVD_STAT, 63 + BD96802_BUCK1_TW_CH_STAT, 64 + 65 + /* Reg 0x5e (BUCK2 INTB) */ 66 + BD96802_BUCK2_OCPH_STAT, 67 + BD96802_BUCK2_OCPL_STAT, 68 + BD96802_BUCK2_OCPN_STAT, 69 + BD96802_BUCK2_OVD_STAT, 70 + BD96802_BUCK2_UVD_STAT, 71 + BD96802_BUCK2_TW_CH_STAT, 72 + }; 73 + 74 + #endif
+3
include/linux/mfd/rohm-generic.h
··· 17 17 ROHM_CHIP_TYPE_BD71837, 18 18 ROHM_CHIP_TYPE_BD71847, 19 19 ROHM_CHIP_TYPE_BD96801, 20 + ROHM_CHIP_TYPE_BD96802, 21 + ROHM_CHIP_TYPE_BD96805, 22 + ROHM_CHIP_TYPE_BD96806, 20 23 ROHM_CHIP_TYPE_AMOUNT 21 24 }; 22 25
+2 -5
include/linux/mfd/samsung/core.h
··· 39 39 S5M8767X, 40 40 S2DOS05, 41 41 S2MPA01, 42 + S2MPG10, 42 43 S2MPS11X, 43 44 S2MPS13X, 44 45 S2MPS14X, ··· 67 66 struct regmap *regmap_pmic; 68 67 struct i2c_client *i2c; 69 68 70 - unsigned long device_type; 69 + int device_type; 71 70 int irq; 72 71 struct regmap_irq_chip_data *irq_data; 73 72 }; 74 - 75 - int sec_irq_init(struct sec_pmic_dev *sec_pmic); 76 - void sec_irq_exit(struct sec_pmic_dev *sec_pmic); 77 - int sec_irq_resume(struct sec_pmic_dev *sec_pmic); 78 73 79 74 struct sec_platform_data { 80 75 struct sec_regulator_data *regulators;
+103
include/linux/mfd/samsung/irq.h
··· 57 57 #define S2MPA01_IRQ_B24_TSD_MASK (1 << 4) 58 58 #define S2MPA01_IRQ_B35_TSD_MASK (1 << 5) 59 59 60 + enum s2mpg10_irq { 61 + /* PMIC */ 62 + S2MPG10_IRQ_PWRONF, 63 + S2MPG10_IRQ_PWRONR, 64 + S2MPG10_IRQ_JIGONBF, 65 + S2MPG10_IRQ_JIGONBR, 66 + S2MPG10_IRQ_ACOKBF, 67 + S2MPG10_IRQ_ACOKBR, 68 + S2MPG10_IRQ_PWRON1S, 69 + S2MPG10_IRQ_MRB, 70 + #define S2MPG10_IRQ_PWRONF_MASK BIT(0) 71 + #define S2MPG10_IRQ_PWRONR_MASK BIT(1) 72 + #define S2MPG10_IRQ_JIGONBF_MASK BIT(2) 73 + #define S2MPG10_IRQ_JIGONBR_MASK BIT(3) 74 + #define S2MPG10_IRQ_ACOKBF_MASK BIT(4) 75 + #define S2MPG10_IRQ_ACOKBR_MASK BIT(5) 76 + #define S2MPG10_IRQ_PWRON1S_MASK BIT(6) 77 + #define S2MPG10_IRQ_MRB_MASK BIT(7) 78 + 79 + S2MPG10_IRQ_RTC60S, 80 + S2MPG10_IRQ_RTCA1, 81 + S2MPG10_IRQ_RTCA0, 82 + S2MPG10_IRQ_RTC1S, 83 + S2MPG10_IRQ_WTSR_COLDRST, 84 + S2MPG10_IRQ_WTSR, 85 + S2MPG10_IRQ_WRST, 86 + S2MPG10_IRQ_SMPL, 87 + #define S2MPG10_IRQ_RTC60S_MASK BIT(0) 88 + #define S2MPG10_IRQ_RTCA1_MASK BIT(1) 89 + #define S2MPG10_IRQ_RTCA0_MASK BIT(2) 90 + #define S2MPG10_IRQ_RTC1S_MASK BIT(3) 91 + #define S2MPG10_IRQ_WTSR_COLDRST_MASK BIT(4) 92 + #define S2MPG10_IRQ_WTSR_MASK BIT(5) 93 + #define S2MPG10_IRQ_WRST_MASK BIT(6) 94 + #define S2MPG10_IRQ_SMPL_MASK BIT(7) 95 + 96 + S2MPG10_IRQ_120C, 97 + S2MPG10_IRQ_140C, 98 + S2MPG10_IRQ_TSD, 99 + S2MPG10_IRQ_PIF_TIMEOUT1, 100 + S2MPG10_IRQ_PIF_TIMEOUT2, 101 + S2MPG10_IRQ_SPD_PARITY_ERR, 102 + S2MPG10_IRQ_SPD_ABNORMAL_STOP, 103 + S2MPG10_IRQ_PMETER_OVERF, 104 + #define S2MPG10_IRQ_INT120C_MASK BIT(0) 105 + #define S2MPG10_IRQ_INT140C_MASK BIT(1) 106 + #define S2MPG10_IRQ_TSD_MASK BIT(2) 107 + #define S2MPG10_IRQ_PIF_TIMEOUT1_MASK BIT(3) 108 + #define S2MPG10_IRQ_PIF_TIMEOUT2_MASK BIT(4) 109 + #define S2MPG10_IRQ_SPD_PARITY_ERR_MASK BIT(5) 110 + #define S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6) 111 + #define S2MPG10_IRQ_PMETER_OVERF_MASK BIT(7) 112 + 113 + S2MPG10_IRQ_OCP_B1M, 114 + S2MPG10_IRQ_OCP_B2M, 115 + S2MPG10_IRQ_OCP_B3M, 116 + S2MPG10_IRQ_OCP_B4M, 117 + S2MPG10_IRQ_OCP_B5M, 118 + S2MPG10_IRQ_OCP_B6M, 119 + S2MPG10_IRQ_OCP_B7M, 120 + S2MPG10_IRQ_OCP_B8M, 121 + #define S2MPG10_IRQ_OCP_B1M_MASK BIT(0) 122 + #define S2MPG10_IRQ_OCP_B2M_MASK BIT(1) 123 + #define S2MPG10_IRQ_OCP_B3M_MASK BIT(2) 124 + #define S2MPG10_IRQ_OCP_B4M_MASK BIT(3) 125 + #define S2MPG10_IRQ_OCP_B5M_MASK BIT(4) 126 + #define S2MPG10_IRQ_OCP_B6M_MASK BIT(5) 127 + #define S2MPG10_IRQ_OCP_B7M_MASK BIT(6) 128 + #define S2MPG10_IRQ_OCP_B8M_MASK BIT(7) 129 + 130 + S2MPG10_IRQ_OCP_B9M, 131 + S2MPG10_IRQ_OCP_B10M, 132 + S2MPG10_IRQ_WLWP_ACC, 133 + S2MPG10_IRQ_SMPL_TIMEOUT, 134 + S2MPG10_IRQ_WTSR_TIMEOUT, 135 + S2MPG10_IRQ_SPD_SRP_PKT_RST, 136 + #define S2MPG10_IRQ_OCP_B9M_MASK BIT(0) 137 + #define S2MPG10_IRQ_OCP_B10M_MASK BIT(1) 138 + #define S2MPG10_IRQ_WLWP_ACC_MASK BIT(2) 139 + #define S2MPG10_IRQ_SMPL_TIMEOUT_MASK BIT(5) 140 + #define S2MPG10_IRQ_WTSR_TIMEOUT_MASK BIT(6) 141 + #define S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK BIT(7) 142 + 143 + S2MPG10_IRQ_PWR_WARN_CH0, 144 + S2MPG10_IRQ_PWR_WARN_CH1, 145 + S2MPG10_IRQ_PWR_WARN_CH2, 146 + S2MPG10_IRQ_PWR_WARN_CH3, 147 + S2MPG10_IRQ_PWR_WARN_CH4, 148 + S2MPG10_IRQ_PWR_WARN_CH5, 149 + S2MPG10_IRQ_PWR_WARN_CH6, 150 + S2MPG10_IRQ_PWR_WARN_CH7, 151 + #define S2MPG10_IRQ_PWR_WARN_CH0_MASK BIT(0) 152 + #define S2MPG10_IRQ_PWR_WARN_CH1_MASK BIT(1) 153 + #define S2MPG10_IRQ_PWR_WARN_CH2_MASK BIT(2) 154 + #define S2MPG10_IRQ_PWR_WARN_CH3_MASK BIT(3) 155 + #define S2MPG10_IRQ_PWR_WARN_CH4_MASK BIT(4) 156 + #define S2MPG10_IRQ_PWR_WARN_CH5_MASK BIT(5) 157 + #define S2MPG10_IRQ_PWR_WARN_CH6_MASK BIT(6) 158 + #define S2MPG10_IRQ_PWR_WARN_CH7_MASK BIT(7) 159 + 160 + S2MPG10_IRQ_NR, 161 + }; 162 + 60 163 enum s2mps11_irq { 61 164 S2MPS11_IRQ_PWRONF, 62 165 S2MPS11_IRQ_PWRONR,
+37
include/linux/mfd/samsung/rtc.h
··· 72 72 S2MPS_RTC_REG_MAX, 73 73 }; 74 74 75 + enum s2mpg10_rtc_reg { 76 + S2MPG10_RTC_CTRL, 77 + S2MPG10_RTC_UPDATE, 78 + S2MPG10_RTC_SMPL, 79 + S2MPG10_RTC_WTSR, 80 + S2MPG10_RTC_CAP_SEL, 81 + S2MPG10_RTC_MSEC, 82 + S2MPG10_RTC_SEC, 83 + S2MPG10_RTC_MIN, 84 + S2MPG10_RTC_HOUR, 85 + S2MPG10_RTC_WEEK, 86 + S2MPG10_RTC_DAY, 87 + S2MPG10_RTC_MON, 88 + S2MPG10_RTC_YEAR, 89 + S2MPG10_RTC_A0SEC, 90 + S2MPG10_RTC_A0MIN, 91 + S2MPG10_RTC_A0HOUR, 92 + S2MPG10_RTC_A0WEEK, 93 + S2MPG10_RTC_A0DAY, 94 + S2MPG10_RTC_A0MON, 95 + S2MPG10_RTC_A0YEAR, 96 + S2MPG10_RTC_A1SEC, 97 + S2MPG10_RTC_A1MIN, 98 + S2MPG10_RTC_A1HOUR, 99 + S2MPG10_RTC_A1WEEK, 100 + S2MPG10_RTC_A1DAY, 101 + S2MPG10_RTC_A1MON, 102 + S2MPG10_RTC_A1YEAR, 103 + S2MPG10_RTC_OSC_CTRL, 104 + }; 105 + 75 106 #define RTC_I2C_ADDR (0x0C >> 1) 76 107 77 108 #define HOUR_12 (1 << 7) ··· 155 124 #define ALARM_ENABLE_SHIFT 7 156 125 #define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT) 157 126 127 + /* WTSR & SMPL registers */ 158 128 #define SMPL_ENABLE_SHIFT 7 159 129 #define SMPL_ENABLE_MASK (1 << SMPL_ENABLE_SHIFT) 160 130 161 131 #define WTSR_ENABLE_SHIFT 6 162 132 #define WTSR_ENABLE_MASK (1 << WTSR_ENABLE_SHIFT) 133 + 134 + #define S2MPG10_WTSR_COLDTIMER GENMASK(6, 5) 135 + #define S2MPG10_WTSR_COLDRST BIT(4) 136 + #define S2MPG10_WTSR_WTSRT GENMASK(3, 1) 137 + #define S2MPG10_WTSR_WTSR_EN BIT(0) 163 138 164 139 #endif /* __LINUX_MFD_SEC_RTC_H */
+454
include/linux/mfd/samsung/s2mpg10.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0+ */ 2 + /* 3 + * Copyright 2015 Samsung Electronics 4 + * Copyright 2020 Google Inc 5 + * Copyright 2025 Linaro Ltd. 6 + */ 7 + 8 + #ifndef __LINUX_MFD_S2MPG10_H 9 + #define __LINUX_MFD_S2MPG10_H 10 + 11 + /* Common registers (type 0x000) */ 12 + enum s2mpg10_common_reg { 13 + S2MPG10_COMMON_CHIPID, 14 + S2MPG10_COMMON_INT, 15 + S2MPG10_COMMON_INT_MASK, 16 + S2MPG10_COMMON_SPD_CTRL1 = 0x0a, 17 + S2MPG10_COMMON_SPD_CTRL2, 18 + S2MPG10_COMMON_SPD_CTRL3, 19 + S2MPG10_COMMON_MON1SEL = 0x1a, 20 + S2MPG10_COMMON_MON2SEL, 21 + S2MPG10_COMMON_MONR, 22 + S2MPG10_COMMON_DEBUG_CTRL1, 23 + S2MPG10_COMMON_DEBUG_CTRL2, 24 + S2MPG10_COMMON_DEBUG_CTRL3, 25 + S2MPG10_COMMON_DEBUG_CTRL4, 26 + S2MPG10_COMMON_DEBUG_CTRL5, 27 + S2MPG10_COMMON_DEBUG_CTRL6, 28 + S2MPG10_COMMON_DEBUG_CTRL7, 29 + S2MPG10_COMMON_DEBUG_CTRL8, 30 + S2MPG10_COMMON_TEST_MODE1, 31 + S2MPG10_COMMON_TEST_MODE2, 32 + S2MPG10_COMMON_SPD_DEBUG1, 33 + S2MPG10_COMMON_SPD_DEBUG2, 34 + S2MPG10_COMMON_SPD_DEBUG3, 35 + S2MPG10_COMMON_SPD_DEBUG4, 36 + }; 37 + 38 + /* For S2MPG10_COMMON_INT and S2MPG10_COMMON_INT_MASK */ 39 + #define S2MPG10_COMMON_INT_SRC GENMASK(7, 0) 40 + #define S2MPG10_COMMON_INT_SRC_PMIC BIT(0) 41 + 42 + /* PMIC registers (type 0x100) */ 43 + enum s2mpg10_pmic_reg { 44 + S2MPG10_PMIC_INT1, 45 + S2MPG10_PMIC_INT2, 46 + S2MPG10_PMIC_INT3, 47 + S2MPG10_PMIC_INT4, 48 + S2MPG10_PMIC_INT5, 49 + S2MPG10_PMIC_INT6, 50 + S2MPG10_PMIC_INT1M, 51 + S2MPG10_PMIC_INT2M, 52 + S2MPG10_PMIC_INT3M, 53 + S2MPG10_PMIC_INT4M, 54 + S2MPG10_PMIC_INT5M, 55 + S2MPG10_PMIC_INT6M, 56 + S2MPG10_PMIC_STATUS1, 57 + S2MPG10_PMIC_STATUS2, 58 + S2MPG10_PMIC_PWRONSRC, 59 + S2MPG10_PMIC_OFFSRC, 60 + S2MPG10_PMIC_BU_CHG, 61 + S2MPG10_PMIC_RTCBUF, 62 + S2MPG10_PMIC_COMMON_CTRL1, 63 + S2MPG10_PMIC_COMMON_CTRL2, 64 + S2MPG10_PMIC_COMMON_CTRL3, 65 + S2MPG10_PMIC_COMMON_CTRL4, 66 + S2MPG10_PMIC_SMPL_WARN_CTRL, 67 + S2MPG10_PMIC_MIMICKING_CTRL, 68 + S2MPG10_PMIC_B1M_CTRL, 69 + S2MPG10_PMIC_B1M_OUT1, 70 + S2MPG10_PMIC_B1M_OUT2, 71 + S2MPG10_PMIC_B2M_CTRL, 72 + S2MPG10_PMIC_B2M_OUT1, 73 + S2MPG10_PMIC_B2M_OUT2, 74 + S2MPG10_PMIC_B3M_CTRL, 75 + S2MPG10_PMIC_B3M_OUT1, 76 + S2MPG10_PMIC_B3M_OUT2, 77 + S2MPG10_PMIC_B4M_CTRL, 78 + S2MPG10_PMIC_B4M_OUT1, 79 + S2MPG10_PMIC_B4M_OUT2, 80 + S2MPG10_PMIC_B5M_CTRL, 81 + S2MPG10_PMIC_B5M_OUT1, 82 + S2MPG10_PMIC_B5M_OUT2, 83 + S2MPG10_PMIC_B6M_CTRL, 84 + S2MPG10_PMIC_B6M_OUT1, 85 + S2MPG10_PMIC_B6M_OUT2, 86 + S2MPG10_PMIC_B7M_CTRL, 87 + S2MPG10_PMIC_B7M_OUT1, 88 + S2MPG10_PMIC_B7M_OUT2, 89 + S2MPG10_PMIC_B8M_CTRL, 90 + S2MPG10_PMIC_B8M_OUT1, 91 + S2MPG10_PMIC_B8M_OUT2, 92 + S2MPG10_PMIC_B9M_CTRL, 93 + S2MPG10_PMIC_B9M_OUT1, 94 + S2MPG10_PMIC_B9M_OUT2, 95 + S2MPG10_PMIC_B10M_CTRL, 96 + S2MPG10_PMIC_B10M_OUT1, 97 + S2MPG10_PMIC_B10M_OUT2, 98 + S2MPG10_PMIC_BUCK1M_USONIC, 99 + S2MPG10_PMIC_BUCK2M_USONIC, 100 + S2MPG10_PMIC_BUCK3M_USONIC, 101 + S2MPG10_PMIC_BUCK4M_USONIC, 102 + S2MPG10_PMIC_BUCK5M_USONIC, 103 + S2MPG10_PMIC_BUCK6M_USONIC, 104 + S2MPG10_PMIC_BUCK7M_USONIC, 105 + S2MPG10_PMIC_BUCK8M_USONIC, 106 + S2MPG10_PMIC_BUCK9M_USONIC, 107 + S2MPG10_PMIC_BUCK10M_USONIC, 108 + S2MPG10_PMIC_L1M_CTRL, 109 + S2MPG10_PMIC_L2M_CTRL, 110 + S2MPG10_PMIC_L3M_CTRL, 111 + S2MPG10_PMIC_L4M_CTRL, 112 + S2MPG10_PMIC_L5M_CTRL, 113 + S2MPG10_PMIC_L6M_CTRL, 114 + S2MPG10_PMIC_L7M_CTRL, 115 + S2MPG10_PMIC_L8M_CTRL, 116 + S2MPG10_PMIC_L9M_CTRL, 117 + S2MPG10_PMIC_L10M_CTRL, 118 + S2MPG10_PMIC_L11M_CTRL1, 119 + S2MPG10_PMIC_L11M_CTRL2, 120 + S2MPG10_PMIC_L12M_CTRL1, 121 + S2MPG10_PMIC_L12M_CTRL2, 122 + S2MPG10_PMIC_L13M_CTRL1, 123 + S2MPG10_PMIC_L13M_CTRL2, 124 + S2MPG10_PMIC_L14M_CTRL, 125 + S2MPG10_PMIC_L15M_CTRL1, 126 + S2MPG10_PMIC_L15M_CTRL2, 127 + S2MPG10_PMIC_L16M_CTRL, 128 + S2MPG10_PMIC_L17M_CTRL, 129 + S2MPG10_PMIC_L18M_CTRL, 130 + S2MPG10_PMIC_L19M_CTRL, 131 + S2MPG10_PMIC_L20M_CTRL, 132 + S2MPG10_PMIC_L21M_CTRL, 133 + S2MPG10_PMIC_L22M_CTRL, 134 + S2MPG10_PMIC_L23M_CTRL, 135 + S2MPG10_PMIC_L24M_CTRL, 136 + S2MPG10_PMIC_L25M_CTRL, 137 + S2MPG10_PMIC_L26M_CTRL, 138 + S2MPG10_PMIC_L27M_CTRL, 139 + S2MPG10_PMIC_L28M_CTRL, 140 + S2MPG10_PMIC_L29M_CTRL, 141 + S2MPG10_PMIC_L30M_CTRL, 142 + S2MPG10_PMIC_L31M_CTRL, 143 + S2MPG10_PMIC_LDO_CTRL1, 144 + S2MPG10_PMIC_LDO_CTRL2, 145 + S2MPG10_PMIC_LDO_DSCH1, 146 + S2MPG10_PMIC_LDO_DSCH2, 147 + S2MPG10_PMIC_LDO_DSCH3, 148 + S2MPG10_PMIC_LDO_DSCH4, 149 + S2MPG10_PMIC_LDO_BUCK7M_HLIMIT, 150 + S2MPG10_PMIC_LDO_BUCK7M_LLIMIT, 151 + S2MPG10_PMIC_LDO_LDO21M_HLIMIT, 152 + S2MPG10_PMIC_LDO_LDO21M_LLIMIT, 153 + S2MPG10_PMIC_LDO_LDO11M_HLIMIT, 154 + S2MPG10_PMIC_DVS_RAMP1, 155 + S2MPG10_PMIC_DVS_RAMP2, 156 + S2MPG10_PMIC_DVS_RAMP3, 157 + S2MPG10_PMIC_DVS_RAMP4, 158 + S2MPG10_PMIC_DVS_RAMP5, 159 + S2MPG10_PMIC_DVS_RAMP6, 160 + S2MPG10_PMIC_DVS_SYNC_CTRL1, 161 + S2MPG10_PMIC_DVS_SYNC_CTRL2, 162 + S2MPG10_PMIC_DVS_SYNC_CTRL3, 163 + S2MPG10_PMIC_DVS_SYNC_CTRL4, 164 + S2MPG10_PMIC_DVS_SYNC_CTRL5, 165 + S2MPG10_PMIC_DVS_SYNC_CTRL6, 166 + S2MPG10_PMIC_OFF_CTRL1, 167 + S2MPG10_PMIC_OFF_CTRL2, 168 + S2MPG10_PMIC_OFF_CTRL3, 169 + S2MPG10_PMIC_OFF_CTRL4, 170 + S2MPG10_PMIC_SEQ_CTRL1, 171 + S2MPG10_PMIC_SEQ_CTRL2, 172 + S2MPG10_PMIC_SEQ_CTRL3, 173 + S2MPG10_PMIC_SEQ_CTRL4, 174 + S2MPG10_PMIC_SEQ_CTRL5, 175 + S2MPG10_PMIC_SEQ_CTRL6, 176 + S2MPG10_PMIC_SEQ_CTRL7, 177 + S2MPG10_PMIC_SEQ_CTRL8, 178 + S2MPG10_PMIC_SEQ_CTRL9, 179 + S2MPG10_PMIC_SEQ_CTRL10, 180 + S2MPG10_PMIC_SEQ_CTRL11, 181 + S2MPG10_PMIC_SEQ_CTRL12, 182 + S2MPG10_PMIC_SEQ_CTRL13, 183 + S2MPG10_PMIC_SEQ_CTRL14, 184 + S2MPG10_PMIC_SEQ_CTRL15, 185 + S2MPG10_PMIC_SEQ_CTRL16, 186 + S2MPG10_PMIC_SEQ_CTRL17, 187 + S2MPG10_PMIC_SEQ_CTRL18, 188 + S2MPG10_PMIC_SEQ_CTRL19, 189 + S2MPG10_PMIC_SEQ_CTRL20, 190 + S2MPG10_PMIC_SEQ_CTRL21, 191 + S2MPG10_PMIC_SEQ_CTRL22, 192 + S2MPG10_PMIC_SEQ_CTRL23, 193 + S2MPG10_PMIC_SEQ_CTRL24, 194 + S2MPG10_PMIC_SEQ_CTRL25, 195 + S2MPG10_PMIC_SEQ_CTRL26, 196 + S2MPG10_PMIC_SEQ_CTRL27, 197 + S2MPG10_PMIC_SEQ_CTRL28, 198 + S2MPG10_PMIC_SEQ_CTRL29, 199 + S2MPG10_PMIC_SEQ_CTRL30, 200 + S2MPG10_PMIC_SEQ_CTRL31, 201 + S2MPG10_PMIC_SEQ_CTRL32, 202 + S2MPG10_PMIC_SEQ_CTRL33, 203 + S2MPG10_PMIC_SEQ_CTRL34, 204 + S2MPG10_PMIC_SEQ_CTRL35, 205 + S2MPG10_PMIC_OFF_SEQ_CTRL1, 206 + S2MPG10_PMIC_OFF_SEQ_CTRL2, 207 + S2MPG10_PMIC_OFF_SEQ_CTRL3, 208 + S2MPG10_PMIC_OFF_SEQ_CTRL4, 209 + S2MPG10_PMIC_OFF_SEQ_CTRL5, 210 + S2MPG10_PMIC_OFF_SEQ_CTRL6, 211 + S2MPG10_PMIC_OFF_SEQ_CTRL7, 212 + S2MPG10_PMIC_OFF_SEQ_CTRL8, 213 + S2MPG10_PMIC_OFF_SEQ_CTRL9, 214 + S2MPG10_PMIC_OFF_SEQ_CTRL10, 215 + S2MPG10_PMIC_OFF_SEQ_CTRL11, 216 + S2MPG10_PMIC_OFF_SEQ_CTRL12, 217 + S2MPG10_PMIC_OFF_SEQ_CTRL13, 218 + S2MPG10_PMIC_OFF_SEQ_CTRL14, 219 + S2MPG10_PMIC_OFF_SEQ_CTRL15, 220 + S2MPG10_PMIC_OFF_SEQ_CTRL16, 221 + S2MPG10_PMIC_OFF_SEQ_CTRL17, 222 + S2MPG10_PMIC_OFF_SEQ_CTRL18, 223 + S2MPG10_PMIC_PCTRLSEL1, 224 + S2MPG10_PMIC_PCTRLSEL2, 225 + S2MPG10_PMIC_PCTRLSEL3, 226 + S2MPG10_PMIC_PCTRLSEL4, 227 + S2MPG10_PMIC_PCTRLSEL5, 228 + S2MPG10_PMIC_PCTRLSEL6, 229 + S2MPG10_PMIC_PCTRLSEL7, 230 + S2MPG10_PMIC_PCTRLSEL8, 231 + S2MPG10_PMIC_PCTRLSEL9, 232 + S2MPG10_PMIC_PCTRLSEL10, 233 + S2MPG10_PMIC_PCTRLSEL11, 234 + S2MPG10_PMIC_PCTRLSEL12, 235 + S2MPG10_PMIC_PCTRLSEL13, 236 + S2MPG10_PMIC_DCTRLSEL1, 237 + S2MPG10_PMIC_DCTRLSEL2, 238 + S2MPG10_PMIC_DCTRLSEL3, 239 + S2MPG10_PMIC_DCTRLSEL4, 240 + S2MPG10_PMIC_DCTRLSEL5, 241 + S2MPG10_PMIC_DCTRLSEL6, 242 + S2MPG10_PMIC_DCTRLSEL7, 243 + S2MPG10_PMIC_GPIO_CTRL1, 244 + S2MPG10_PMIC_GPIO_CTRL2, 245 + S2MPG10_PMIC_GPIO_CTRL3, 246 + S2MPG10_PMIC_GPIO_CTRL4, 247 + S2MPG10_PMIC_GPIO_CTRL5, 248 + S2MPG10_PMIC_GPIO_CTRL6, 249 + S2MPG10_PMIC_GPIO_CTRL7, 250 + S2MPG10_PMIC_B2M_OCP_WARN, 251 + S2MPG10_PMIC_B2M_OCP_WARN_X, 252 + S2MPG10_PMIC_B2M_OCP_WARN_Y, 253 + S2MPG10_PMIC_B2M_OCP_WARN_Z, 254 + S2MPG10_PMIC_B3M_OCP_WARN, 255 + S2MPG10_PMIC_B3M_OCP_WARN_X, 256 + S2MPG10_PMIC_B3M_OCP_WARN_Y, 257 + S2MPG10_PMIC_B3M_OCP_WARN_Z, 258 + S2MPG10_PMIC_B10M_OCP_WARN, 259 + S2MPG10_PMIC_B10M_OCP_WARN_X, 260 + S2MPG10_PMIC_B10M_OCP_WARN_Y, 261 + S2MPG10_PMIC_B10M_OCP_WARN_Z, 262 + S2MPG10_PMIC_B2M_SOFT_OCP_WARN, 263 + S2MPG10_PMIC_B2M_SOFT_OCP_WARN_X, 264 + S2MPG10_PMIC_B2M_SOFT_OCP_WARN_Y, 265 + S2MPG10_PMIC_B2M_SOFT_OCP_WARN_Z, 266 + S2MPG10_PMIC_B3M_SOFT_OCP_WARN, 267 + S2MPG10_PMIC_B3M_SOFT_OCP_WARN_X, 268 + S2MPG10_PMIC_B3M_SOFT_OCP_WARN_Y, 269 + S2MPG10_PMIC_B3M_SOFT_OCP_WARN_Z, 270 + S2MPG10_PMIC_B10M_SOFT_OCP_WARN, 271 + S2MPG10_PMIC_B10M_SOFT_OCP_WARN_X, 272 + S2MPG10_PMIC_B10M_SOFT_OCP_WARN_Y, 273 + S2MPG10_PMIC_B10M_SOFT_OCP_WARN_Z, 274 + S2MPG10_PMIC_BUCK_OCP_EN1, 275 + S2MPG10_PMIC_BUCK_OCP_EN2, 276 + S2MPG10_PMIC_BUCK_OCP_PD_EN1, 277 + S2MPG10_PMIC_BUCK_OCP_PD_EN2, 278 + S2MPG10_PMIC_BUCK_OCP_CTRL1, 279 + S2MPG10_PMIC_BUCK_OCP_CTRL2, 280 + S2MPG10_PMIC_BUCK_OCP_CTRL3, 281 + S2MPG10_PMIC_BUCK_OCP_CTRL4, 282 + S2MPG10_PMIC_BUCK_OCP_CTRL5, 283 + S2MPG10_PMIC_PIF_CTRL, 284 + S2MPG10_PMIC_BUCK_HR_MODE1, 285 + S2MPG10_PMIC_BUCK_HR_MODE2, 286 + S2MPG10_PMIC_FAULTOUT_CTRL, 287 + S2MPG10_PMIC_LDO_SENSE1, 288 + S2MPG10_PMIC_LDO_SENSE2, 289 + S2MPG10_PMIC_LDO_SENSE3, 290 + S2MPG10_PMIC_LDO_SENSE4, 291 + }; 292 + 293 + /* Meter registers (type 0xa00) */ 294 + enum s2mpg10_meter_reg { 295 + S2MPG10_METER_CTRL1, 296 + S2MPG10_METER_CTRL2, 297 + S2MPG10_METER_CTRL3, 298 + S2MPG10_METER_CTRL4, 299 + S2MPG10_METER_BUCKEN1, 300 + S2MPG10_METER_BUCKEN2, 301 + S2MPG10_METER_MUXSEL0, 302 + S2MPG10_METER_MUXSEL1, 303 + S2MPG10_METER_MUXSEL2, 304 + S2MPG10_METER_MUXSEL3, 305 + S2MPG10_METER_MUXSEL4, 306 + S2MPG10_METER_MUXSEL5, 307 + S2MPG10_METER_MUXSEL6, 308 + S2MPG10_METER_MUXSEL7, 309 + S2MPG10_METER_LPF_C0_0, 310 + S2MPG10_METER_LPF_C0_1, 311 + S2MPG10_METER_LPF_C0_2, 312 + S2MPG10_METER_LPF_C0_3, 313 + S2MPG10_METER_LPF_C0_4, 314 + S2MPG10_METER_LPF_C0_5, 315 + S2MPG10_METER_LPF_C0_6, 316 + S2MPG10_METER_LPF_C0_7, 317 + S2MPG10_METER_PWR_WARN0, 318 + S2MPG10_METER_PWR_WARN1, 319 + S2MPG10_METER_PWR_WARN2, 320 + S2MPG10_METER_PWR_WARN3, 321 + S2MPG10_METER_PWR_WARN4, 322 + S2MPG10_METER_PWR_WARN5, 323 + S2MPG10_METER_PWR_WARN6, 324 + S2MPG10_METER_PWR_WARN7, 325 + S2MPG10_METER_PWR_HYS1, 326 + S2MPG10_METER_PWR_HYS2, 327 + S2MPG10_METER_PWR_HYS3, 328 + S2MPG10_METER_PWR_HYS4, 329 + S2MPG10_METER_ACC_DATA_CH0_1 = 0x40, 330 + S2MPG10_METER_ACC_DATA_CH0_2, 331 + S2MPG10_METER_ACC_DATA_CH0_3, 332 + S2MPG10_METER_ACC_DATA_CH0_4, 333 + S2MPG10_METER_ACC_DATA_CH0_5, 334 + S2MPG10_METER_ACC_DATA_CH0_6, 335 + S2MPG10_METER_ACC_DATA_CH1_1, 336 + S2MPG10_METER_ACC_DATA_CH1_2, 337 + S2MPG10_METER_ACC_DATA_CH1_3, 338 + S2MPG10_METER_ACC_DATA_CH1_4, 339 + S2MPG10_METER_ACC_DATA_CH1_5, 340 + S2MPG10_METER_ACC_DATA_CH1_6, 341 + S2MPG10_METER_ACC_DATA_CH2_1, 342 + S2MPG10_METER_ACC_DATA_CH2_2, 343 + S2MPG10_METER_ACC_DATA_CH2_3, 344 + S2MPG10_METER_ACC_DATA_CH2_4, 345 + S2MPG10_METER_ACC_DATA_CH2_5, 346 + S2MPG10_METER_ACC_DATA_CH2_6, 347 + S2MPG10_METER_ACC_DATA_CH3_1, 348 + S2MPG10_METER_ACC_DATA_CH3_2, 349 + S2MPG10_METER_ACC_DATA_CH3_3, 350 + S2MPG10_METER_ACC_DATA_CH3_4, 351 + S2MPG10_METER_ACC_DATA_CH3_5, 352 + S2MPG10_METER_ACC_DATA_CH3_6, 353 + S2MPG10_METER_ACC_DATA_CH4_1, 354 + S2MPG10_METER_ACC_DATA_CH4_2, 355 + S2MPG10_METER_ACC_DATA_CH4_3, 356 + S2MPG10_METER_ACC_DATA_CH4_4, 357 + S2MPG10_METER_ACC_DATA_CH4_5, 358 + S2MPG10_METER_ACC_DATA_CH4_6, 359 + S2MPG10_METER_ACC_DATA_CH5_1, 360 + S2MPG10_METER_ACC_DATA_CH5_2, 361 + S2MPG10_METER_ACC_DATA_CH5_3, 362 + S2MPG10_METER_ACC_DATA_CH5_4, 363 + S2MPG10_METER_ACC_DATA_CH5_5, 364 + S2MPG10_METER_ACC_DATA_CH5_6, 365 + S2MPG10_METER_ACC_DATA_CH6_1, 366 + S2MPG10_METER_ACC_DATA_CH6_2, 367 + S2MPG10_METER_ACC_DATA_CH6_3, 368 + S2MPG10_METER_ACC_DATA_CH6_4, 369 + S2MPG10_METER_ACC_DATA_CH6_5, 370 + S2MPG10_METER_ACC_DATA_CH6_6, 371 + S2MPG10_METER_ACC_DATA_CH7_1, 372 + S2MPG10_METER_ACC_DATA_CH7_2, 373 + S2MPG10_METER_ACC_DATA_CH7_3, 374 + S2MPG10_METER_ACC_DATA_CH7_4, 375 + S2MPG10_METER_ACC_DATA_CH7_5, 376 + S2MPG10_METER_ACC_DATA_CH7_6, 377 + S2MPG10_METER_ACC_COUNT_1, 378 + S2MPG10_METER_ACC_COUNT_2, 379 + S2MPG10_METER_ACC_COUNT_3, 380 + S2MPG10_METER_LPF_DATA_CH0_1, 381 + S2MPG10_METER_LPF_DATA_CH0_2, 382 + S2MPG10_METER_LPF_DATA_CH0_3, 383 + S2MPG10_METER_LPF_DATA_CH1_1, 384 + S2MPG10_METER_LPF_DATA_CH1_2, 385 + S2MPG10_METER_LPF_DATA_CH1_3, 386 + S2MPG10_METER_LPF_DATA_CH2_1, 387 + S2MPG10_METER_LPF_DATA_CH2_2, 388 + S2MPG10_METER_LPF_DATA_CH2_3, 389 + S2MPG10_METER_LPF_DATA_CH3_1, 390 + S2MPG10_METER_LPF_DATA_CH3_2, 391 + S2MPG10_METER_LPF_DATA_CH3_3, 392 + S2MPG10_METER_LPF_DATA_CH4_1, 393 + S2MPG10_METER_LPF_DATA_CH4_2, 394 + S2MPG10_METER_LPF_DATA_CH4_3, 395 + S2MPG10_METER_LPF_DATA_CH5_1, 396 + S2MPG10_METER_LPF_DATA_CH5_2, 397 + S2MPG10_METER_LPF_DATA_CH5_3, 398 + S2MPG10_METER_LPF_DATA_CH6_1, 399 + S2MPG10_METER_LPF_DATA_CH6_2, 400 + S2MPG10_METER_LPF_DATA_CH6_3, 401 + S2MPG10_METER_LPF_DATA_CH7_1, 402 + S2MPG10_METER_LPF_DATA_CH7_2, 403 + S2MPG10_METER_LPF_DATA_CH7_3, 404 + S2MPG10_METER_DSM_TRIM_OFFSET = 0xee, 405 + S2MPG10_METER_BUCK_METER_TRIM3 = 0xf1, 406 + }; 407 + 408 + /* S2MPG10 regulator IDs */ 409 + enum s2mpg10_regulators { 410 + S2MPG10_LDO1, 411 + S2MPG10_LDO2, 412 + S2MPG10_LDO3, 413 + S2MPG10_LDO4, 414 + S2MPG10_LDO5, 415 + S2MPG10_LDO6, 416 + S2MPG10_LDO7, 417 + S2MPG10_LDO8, 418 + S2MPG10_LDO9, 419 + S2MPG10_LDO10, 420 + S2MPG10_LDO11, 421 + S2MPG10_LDO12, 422 + S2MPG10_LDO13, 423 + S2MPG10_LDO14, 424 + S2MPG10_LDO15, 425 + S2MPG10_LDO16, 426 + S2MPG10_LDO17, 427 + S2MPG10_LDO18, 428 + S2MPG10_LDO19, 429 + S2MPG10_LDO20, 430 + S2MPG10_LDO21, 431 + S2MPG10_LDO22, 432 + S2MPG10_LDO23, 433 + S2MPG10_LDO24, 434 + S2MPG10_LDO25, 435 + S2MPG10_LDO26, 436 + S2MPG10_LDO27, 437 + S2MPG10_LDO28, 438 + S2MPG10_LDO29, 439 + S2MPG10_LDO30, 440 + S2MPG10_LDO31, 441 + S2MPG10_BUCK1, 442 + S2MPG10_BUCK2, 443 + S2MPG10_BUCK3, 444 + S2MPG10_BUCK4, 445 + S2MPG10_BUCK5, 446 + S2MPG10_BUCK6, 447 + S2MPG10_BUCK7, 448 + S2MPG10_BUCK8, 449 + S2MPG10_BUCK9, 450 + S2MPG10_BUCK10, 451 + S2MPG10_REGULATOR_MAX, 452 + }; 453 + 454 + #endif /* __LINUX_MFD_S2MPG10_H */
+34 -3
include/linux/mfd/stm32-lptimer.h
··· 17 17 #define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */ 18 18 #define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */ 19 19 #define STM32_LPTIM_CR 0x10 /* Control Reg */ 20 - #define STM32_LPTIM_CMP 0x14 /* Compare Reg */ 20 + #define STM32_LPTIM_CMP 0x14 /* Compare Reg (MP25 CCR1) */ 21 21 #define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */ 22 22 #define STM32_LPTIM_CNT 0x1C /* Counter Reg */ 23 + #define STM32_LPTIM_CCMR1 0x2C /* Capture/Compare Mode MP25 */ 24 + #define STM32_LPTIM_CCR2 0x34 /* Compare Reg2 MP25 */ 25 + 26 + #define STM32_LPTIM_HWCFGR2 0x3EC /* Hardware configuration register 2 - MP25 */ 27 + #define STM32_LPTIM_HWCFGR1 0x3F0 /* Hardware configuration register 1 - MP15 */ 28 + #define STM32_LPTIM_VERR 0x3F4 /* Version identification register - MP15 */ 23 29 24 30 /* STM32_LPTIM_ISR - bit fields */ 31 + #define STM32_LPTIM_DIEROK_ARROK (BIT(24) | BIT(4)) /* MP25 */ 32 + #define STM32_LPTIM_CMP2_ARROK (BIT(19) | BIT(4)) 25 33 #define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3) 26 34 #define STM32_LPTIM_ARROK BIT(4) 27 35 #define STM32_LPTIM_CMPOK BIT(3) 28 36 29 37 /* STM32_LPTIM_ICR - bit fields */ 30 - #define STM32_LPTIM_ARRMCF BIT(1) 38 + #define STM32_LPTIM_DIEROKCF_ARROKCF (BIT(24) | BIT(4)) /* MP25 */ 39 + #define STM32_LPTIM_CMP2OKCF_ARROKCF (BIT(19) | BIT(4)) 31 40 #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) 41 + #define STM32_LPTIM_ARRMCF BIT(1) 32 42 33 - /* STM32_LPTIM_IER - bit flieds */ 43 + /* STM32_LPTIM_IER - bit fields */ 34 44 #define STM32_LPTIM_ARRMIE BIT(1) 35 45 36 46 /* STM32_LPTIM_CR - bit fields */ ··· 63 53 /* STM32_LPTIM_ARR */ 64 54 #define STM32_LPTIM_MAX_ARR 0xFFFF 65 55 56 + /* STM32_LPTIM_CCMR1 */ 57 + #define STM32_LPTIM_CC2P GENMASK(19, 18) 58 + #define STM32_LPTIM_CC2E BIT(17) 59 + #define STM32_LPTIM_CC2SEL BIT(16) 60 + #define STM32_LPTIM_CC1P GENMASK(3, 2) 61 + #define STM32_LPTIM_CC1E BIT(1) 62 + #define STM32_LPTIM_CC1SEL BIT(0) 63 + 64 + /* STM32_LPTIM_HWCFGR1 */ 65 + #define STM32_LPTIM_HWCFGR1_ENCODER BIT(16) 66 + 67 + /* STM32_LPTIM_HWCFGR2 */ 68 + #define STM32_LPTIM_HWCFGR2_CHAN_NUM GENMASK(3, 0) 69 + 70 + /* STM32_LPTIM_VERR */ 71 + #define STM32_LPTIM_VERR_23 0x23 /* STM32MP25 */ 72 + 66 73 /** 67 74 * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device 68 75 * @clk: clock reference for this instance 69 76 * @regmap: register map reference for this instance 70 77 * @has_encoder: indicates this Low-Power Timer supports encoder mode 78 + * @num_cc_chans: indicates the number of capture/compare channels 79 + * @version: indicates the major and minor revision of the controller 71 80 */ 72 81 struct stm32_lptimer { 73 82 struct clk *clk; 74 83 struct regmap *regmap; 75 84 bool has_encoder; 85 + unsigned int num_cc_chans; 86 + u32 version; 76 87 }; 77 88 78 89 #endif
-3
include/linux/sm501.h
··· 12 12 extern unsigned long sm501_set_clock(struct device *dev, 13 13 int clksrc, unsigned long freq); 14 14 15 - extern unsigned long sm501_find_clock(struct device *dev, 16 - int clksrc, unsigned long req_freq); 17 - 18 15 /* sm501_misc_control 19 16 * 20 17 * Modify the SM501's MISC_CONTROL register