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drm/tidss: Restructure dispc_vp_prepare() and dispc_vp_enable()

tidss_crtc.c calls dispc_vp_prepare() and dispc_vp_enable() in that
order, next to each other. dispc_vp_prepare() does preparations for
enabling the crtc, by writing some registers, and dispc_vp_enable() does
more preparations. As the last thing, dispc_vp_enable() enables the CRTC
by writing the enable bit.

There might have been a reason at some point in the history for this
split, but I can't find any point to it. They also do a bit of
overlapping work: both call dispc_vp_find_bus_fmt(). They could as well
be a single function.

But instead of combining them, this patch moves everything from
dispc_vp_enable() to dispc_vp_prepare(), except the actual CRTC enable
bit write. The reason for this is that unlike all the preparatory
register writes, CRTC enable has an immediate effect, starting the
timing generator and the CRTC as a whole. Thus it may be important to
time the enable just right (as we do in the next patch).

No functional changes.

Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://patch.msgid.link/20250905-tidss-fix-timestamp-v1-1-c2aedf31e2c9@ideasonboard.com
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

Tomi Valkeinen 6939508c 975ca62a

+8 -19
+1 -1
drivers/gpu/drm/tidss/tidss_crtc.c
··· 243 243 244 244 dispc_vp_prepare(tidss->dispc, tcrtc->hw_videoport, crtc->state); 245 245 246 - dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport, crtc->state); 246 + dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport); 247 247 248 248 spin_lock_irqsave(&ddev->event_lock, flags); 249 249
+6 -16
drivers/gpu/drm/tidss/tidss_dispc.c
··· 1164 1164 { 1165 1165 const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); 1166 1166 const struct dispc_bus_format *fmt; 1167 + const struct drm_display_mode *mode = &state->adjusted_mode; 1168 + bool align, onoff, rf, ieo, ipc, ihs, ivs; 1169 + u32 hsw, hfp, hbp, vsw, vfp, vbp; 1167 1170 1168 1171 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, 1169 1172 tstate->bus_flags); ··· 1179 1176 1180 1177 dispc_enable_am65x_oldi(dispc, hw_videoport, fmt); 1181 1178 } 1182 - } 1183 - 1184 - void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, 1185 - const struct drm_crtc_state *state) 1186 - { 1187 - const struct drm_display_mode *mode = &state->adjusted_mode; 1188 - const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); 1189 - bool align, onoff, rf, ieo, ipc, ihs, ivs; 1190 - const struct dispc_bus_format *fmt; 1191 - u32 hsw, hfp, hbp, vsw, vfp, vbp; 1192 - 1193 - fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, 1194 - tstate->bus_flags); 1195 - 1196 - if (WARN_ON(!fmt)) 1197 - return; 1198 1179 1199 1180 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); 1200 1181 ··· 1234 1247 mode->crtc_hdisplay - 1) | 1235 1248 FIELD_PREP(DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK, 1236 1249 mode->crtc_vdisplay - 1)); 1250 + } 1237 1251 1252 + void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport) 1253 + { 1238 1254 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 1239 1255 DISPC_VP_CONTROL_ENABLE_MASK); 1240 1256 }
+1 -2
drivers/gpu/drm/tidss/tidss_dispc.h
··· 119 119 120 120 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, 121 121 const struct drm_crtc_state *state); 122 - void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, 123 - const struct drm_crtc_state *state); 122 + void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport); 124 123 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport); 125 124 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport); 126 125 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);