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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dmaengine: stm32-mdma: add support to be triggered by STM32 DMA
STM32 MDMA can be triggered by STM32 DMA channels transfer complete.
In case of non-null struct dma_slave_config .peripheral_size, it means the
DMA client wants the DMA to trigger the MDMA.
stm32-mdma driver gets the request id, the mask_addr, and the mask_data in
struct stm32_mdma_dma_config passed by DMA with struct dma_slave_config
.peripheral_config/.peripheral_size.
Then, as DMA is configured in Double-Buffer mode, and MDMA channel will
transfer data from/to SRAM to/from DDR, then bursts are optimized.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20220829154646.29867-7-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Amelie Delaunay
and committed by
Vinod Koul
69687432
72379517
+69
-1
+69
-1
drivers/dma/stm32-mdma.c
+69
-1
drivers/dma/stm32-mdma.c
···
199
199
u32 transfer_config;
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200
u32 mask_addr;
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u32 mask_data;
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+
bool m2m_hw; /* True when MDMA is triggered by STM32 DMA */
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};
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struct stm32_mdma_hwdesc {
···
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bool cyclic;
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u32 count;
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struct stm32_mdma_desc_node node[];
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+
};
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+
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struct stm32_mdma_dma_config {
231
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u32 request; /* STM32 DMA channel stream id, triggering MDMA */
232
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u32 cmar; /* STM32 DMA interrupt flag clear register address */
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+
u32 cmdr; /* STM32 DMA Transfer Complete flag */
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};
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struct stm32_mdma_chan {
···
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dst_addr = chan->dma_config.dst_addr;
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541
/* Set device data size */
542
+
if (chan_config->m2m_hw)
543
+
dst_addr_width = stm32_mdma_get_max_width(dst_addr, buf_len,
544
+
STM32_MDMA_MAX_BUF_LEN);
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dst_bus_width = stm32_mdma_get_width(chan, dst_addr_width);
550
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if (dst_bus_width < 0)
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return dst_bus_width;
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ctcr &= ~STM32_MDMA_CTCR_DSIZE_MASK;
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ctcr |= STM32_MDMA_CTCR_DSIZE(dst_bus_width);
550
+
if (chan_config->m2m_hw) {
551
+
ctcr &= ~STM32_MDMA_CTCR_DINCOS_MASK;
552
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ctcr |= STM32_MDMA_CTCR_DINCOS(dst_bus_width);
553
+
}
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555
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/* Set device burst value */
556
+
if (chan_config->m2m_hw)
557
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dst_maxburst = STM32_MDMA_MAX_BUF_LEN / dst_addr_width;
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+
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dst_best_burst = stm32_mdma_get_best_burst(buf_len, tlen,
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dst_maxburst,
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dst_addr_width);
···
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src_addr = chan->dma_config.src_addr;
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/* Set device data size */
591
+
if (chan_config->m2m_hw)
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+
src_addr_width = stm32_mdma_get_max_width(src_addr, buf_len,
593
+
STM32_MDMA_MAX_BUF_LEN);
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+
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src_bus_width = stm32_mdma_get_width(chan, src_addr_width);
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if (src_bus_width < 0)
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return src_bus_width;
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ctcr &= ~STM32_MDMA_CTCR_SSIZE_MASK;
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ctcr |= STM32_MDMA_CTCR_SSIZE(src_bus_width);
600
+
if (chan_config->m2m_hw) {
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ctcr &= ~STM32_MDMA_CTCR_SINCOS_MASK;
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ctcr |= STM32_MDMA_CTCR_SINCOS(src_bus_width);
603
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}
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/* Set device burst value */
606
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if (chan_config->m2m_hw)
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src_maxburst = STM32_MDMA_MAX_BUF_LEN / src_addr_width;
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src_best_burst = stm32_mdma_get_best_burst(buf_len, tlen,
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src_maxburst,
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src_addr_width);
···
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{
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struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
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struct dma_slave_config *dma_config = &chan->dma_config;
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+
struct stm32_mdma_chan_config *chan_config = &chan->chan_config;
733
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struct scatterlist *sg;
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dma_addr_t src_addr, dst_addr;
735
-
u32 ccr, ctcr, ctbr;
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u32 m2m_hw_period, ccr, ctcr, ctbr;
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int i, ret = 0;
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if (chan_config->m2m_hw)
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m2m_hw_period = sg_dma_len(sgl);
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for_each_sg(sgl, sg, sg_len, i) {
739
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if (sg_dma_len(sg) > STM32_MDMA_MAX_BLOCK_LEN) {
···
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if (direction == DMA_MEM_TO_DEV) {
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src_addr = sg_dma_address(sg);
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dst_addr = dma_config->dst_addr;
719
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if (chan_config->m2m_hw && (i & 1))
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dst_addr += m2m_hw_period;
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ret = stm32_mdma_set_xfer_param(chan, direction, &ccr,
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&ctcr, &ctbr, src_addr,
753
723
sg_dma_len(sg));
···
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src_addr);
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} else {
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src_addr = dma_config->src_addr;
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if (chan_config->m2m_hw && (i & 1))
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src_addr += m2m_hw_period;
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dst_addr = sg_dma_address(sg);
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ret = stm32_mdma_set_xfer_param(chan, direction, &ccr,
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&ctcr, &ctbr, dst_addr,
···
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unsigned long flags, void *context)
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{
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struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
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struct stm32_mdma_chan_config *chan_config = &chan->chan_config;
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struct stm32_mdma_desc *desc;
795
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int i, ret;
796
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···
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if (ret < 0)
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goto xfer_setup_err;
816
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+
/*
781
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* In case of M2M HW transfer triggered by STM32 DMA, we do not have to clear the
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* transfer complete flag by hardware in order to let the CPU rearm the STM32 DMA
783
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* with the next sg element and update some data in dmaengine framework.
784
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*/
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if (chan_config->m2m_hw && direction == DMA_MEM_TO_DEV) {
786
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struct stm32_mdma_hwdesc *hwdesc;
787
+
788
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for (i = 0; i < sg_len; i++) {
789
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hwdesc = desc->node[i].hwdesc;
790
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hwdesc->cmar = 0;
791
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hwdesc->cmdr = 0;
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}
793
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}
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+
817
795
desc->cyclic = false;
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
···
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struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
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struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
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struct dma_slave_config *dma_config = &chan->dma_config;
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+
struct stm32_mdma_chan_config *chan_config = &chan->chan_config;
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802
struct stm32_mdma_desc *desc;
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dma_addr_t src_addr, dst_addr;
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u32 ccr, ctcr, ctbr, count;
···
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if (direction == DMA_MEM_TO_DEV) {
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src_addr = buf_addr + i * period_len;
913
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dst_addr = dma_config->dst_addr;
861
+
if (chan_config->m2m_hw && (i & 1))
862
+
dst_addr += period_len;
914
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} else {
915
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src_addr = dma_config->src_addr;
865
+
if (chan_config->m2m_hw && (i & 1))
866
+
src_addr += period_len;
916
867
dst_addr = buf_addr + i * period_len;
917
868
}
918
869
···
1300
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struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
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memcpy(&chan->dma_config, config, sizeof(*config));
1246
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1247
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/* Check if user is requesting STM32 DMA to trigger MDMA */
1248
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if (config->peripheral_size) {
1249
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struct stm32_mdma_dma_config *mdma_config;
1250
+
1251
+
mdma_config = (struct stm32_mdma_dma_config *)chan->dma_config.peripheral_config;
1252
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chan->chan_config.request = mdma_config->request;
1253
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chan->chan_config.mask_addr = mdma_config->cmar;
1254
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chan->chan_config.mask_data = mdma_config->cmdr;
1255
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chan->chan_config.m2m_hw = true;
1256
+
}
1303
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1304
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return 0;
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}