tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
"This is a rather unpleasantly large set of bug fixes for arm-soc, Most
of them because of cross-tree dependencies for Exynos where we should
have figured out the right path to merge things before the merge
window, and then the maintainer being unable to sort things out in
time during a business trip.

The other changes contained here are the usual collection:

MAINTAINERS file updates
- Gregory Clement is now a co-maintainer for the legacy Marvell EBU
platforms
- A MAINTAINERS entry for the Freescale Vybrid platform that was
added last year
- Matt Porter no longer works as a maintainer on Broadcom SoCs

Build-time issues
- A compile-time error for at91
- Several minor DT fixes on at91, imx, exynos, socfpga, and omap
- The new digicolor platform was not correctly enabled at all

Configuration issues
- Two defconfig fix for regressions using USB on versatile express
and on OMAP3
- Enabling all 8 CPUs on Allwinner/SUNxi
- Enabling the new STiH410 platform to be usable

Bug fixes in platform code
- A missing barrier for socfpga
- Fixing LPDDR1 self-refresh mode on at91
- Fixing RTC interrupt numbers on Exynos3250
- Fixing a cache-coherency issues in CPU power-down on Exynos5
- Multiple small OMAP power management fixes"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (69 commits)
MAINTAINERS: Add myself as co-maintainer to the legacy support of the mvebu SoCs
ARM: at91: pm_slowclock: fix the compilation error
ARM: at91/dt: fix USB high-speed clock to select UTMI
ARM: at91/dt: fix at91 udc compatible strings
ARM: at91/dt: declare matrix node as a syscon device
ARM: vexpress: update CONFIG_USB_ISP1760 option
ARM: digicolor: add the machine directory to Makefile
ARM: STi: Add STiH410 SoC support
MAINTAINERS: add Freescale Vybrid SoC
MAINTAINERS: Remove self as ARM mach-bcm co-maintainer
ARM: imx6sl-evk: set swbst_reg as vbus's parent reg
ARM: imx6qdl-sabresd: set swbst_reg as vbus's parent reg
ARM: at91/dt: at91sam9261: fix clocks and clock-names in udc definition
ARM: OMAP2+: Fix wl12xx on dm3730-evm with mainline u-boot
ARM: OMAP: enable TWL4030_USB in omap2plus_defconfig
ARM: dts: dra7x-evm: avoid possible contention while muxing on CAN lines
ARM: dts: dra7x-evm: Don't use dcan1_rx.gpio1_15 in DCAN pinctrl
ARM: dts: am43xx: fix SLEWCTRL_FAST pinctrl binding
ARM: dts: am33xx: fix SLEWCTRL_FAST pinctrl binding
ARM: dts: OMAP5: fix polling intervals for thermal zones
...

Linus Torvalds 6981e2af 71c87bd0

+882 -225
+2
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
··· 22 22 - pclkN, clkN: Pairs of parent of input clock and input clock to the 23 23 devices in this power domain. Maximum of 4 pairs (N = 0 to 3) 24 24 are supported currently. 25 + - power-domains: phandle pointing to the parent power domain, for more details 26 + see Documentation/devicetree/bindings/power/power_domain.txt 25 27 26 28 Node of a device using power domains must have a power-domains property 27 29 defined with a phandle to respective power domain.
+4
Documentation/devicetree/bindings/arm/sti.txt
··· 13 13 Required root node property: 14 14 compatible = "st,stih407"; 15 15 16 + Boards with the ST STiH410 SoC shall have the following properties: 17 + Required root node property: 18 + compatible = "st,stih410"; 19 + 16 20 Boards with the ST STiH418 SoC shall have the following properties: 17 21 Required root node property: 18 22 compatible = "st,stih418";
+29
Documentation/devicetree/bindings/power/power_domain.txt
··· 19 19 providing multiple PM domains (e.g. power controllers), but can be any value 20 20 as specified by device tree binding documentation of particular provider. 21 21 22 + Optional properties: 23 + - power-domains : A phandle and PM domain specifier as defined by bindings of 24 + the power controller specified by phandle. 25 + Some power domains might be powered from another power domain (or have 26 + other hardware specific dependencies). For representing such dependency 27 + a standard PM domain consumer binding is used. When provided, all domains 28 + created by the given provider should be subdomains of the domain 29 + specified by this binding. More details about power domain specifier are 30 + available in the next section. 31 + 22 32 Example: 23 33 24 34 power: power-controller@12340000 { ··· 39 29 40 30 The node above defines a power controller that is a PM domain provider and 41 31 expects one cell as its phandle argument. 32 + 33 + Example 2: 34 + 35 + parent: power-controller@12340000 { 36 + compatible = "foo,power-controller"; 37 + reg = <0x12340000 0x1000>; 38 + #power-domain-cells = <1>; 39 + }; 40 + 41 + child: power-controller@12340000 { 42 + compatible = "foo,power-controller"; 43 + reg = <0x12341000 0x1000>; 44 + power-domains = <&parent 0>; 45 + #power-domain-cells = <1>; 46 + }; 47 + 48 + The nodes above define two power controllers: 'parent' and 'child'. 49 + Domains created by the 'child' power controller are subdomains of '0' power 50 + domain provided by the 'parent' power controller. 42 51 43 52 ==PM domain consumers== 44 53
+5
Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
··· 26 26 - atmel,disable : Should be present if you want to disable the watchdog. 27 27 - atmel,idle-halt : Should be present if you want to stop the watchdog when 28 28 entering idle state. 29 + CAUTION: This property should be used with care, it actually makes the 30 + watchdog not counting when the CPU is in idle state, therefore the 31 + watchdog reset time depends on mean CPU usage and will not reset at all 32 + if the CPU stop working while it is in idle state, which is probably 33 + not what you want. 29 34 - atmel,dbg-halt : Should be present if you want to stop the watchdog when 30 35 entering debug state. 31 36
+11 -1
MAINTAINERS
··· 1030 1030 F: arch/arm/boot/dts/imx* 1031 1031 F: arch/arm/configs/imx*_defconfig 1032 1032 1033 + ARM/FREESCALE VYBRID ARM ARCHITECTURE 1034 + M: Shawn Guo <shawn.guo@linaro.org> 1035 + M: Sascha Hauer <kernel@pengutronix.de> 1036 + R: Stefan Agner <stefan@agner.ch> 1037 + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1038 + S: Maintained 1039 + T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git 1040 + F: arch/arm/mach-imx/*vf610* 1041 + F: arch/arm/boot/dts/vf* 1042 + 1033 1043 ARM/GLOMATION GESBC9312SX MACHINE SUPPORT 1034 1044 M: Lennert Buytenhek <kernel@wantstofly.org> 1035 1045 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) ··· 1198 1188 M: Jason Cooper <jason@lakedaemon.net> 1199 1189 M: Andrew Lunn <andrew@lunn.ch> 1200 1190 M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 1191 + M: Gregory Clement <gregory.clement@free-electrons.com> 1201 1192 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1202 1193 S: Maintained 1203 1194 F: arch/arm/mach-dove/ ··· 2118 2107 2119 2108 BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE 2120 2109 M: Christian Daudt <bcm@fixthebug.org> 2121 - M: Matt Porter <mporter@linaro.org> 2122 2110 M: Florian Fainelli <f.fainelli@gmail.com> 2123 2111 L: bcm-kernel-feedback-list@broadcom.com 2124 2112 T: git git://github.com/broadcom/mach-bcm
+1
arch/arm/Makefile
··· 150 150 machine-$(CONFIG_ARCH_CLPS711X) += clps711x 151 151 machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx 152 152 machine-$(CONFIG_ARCH_DAVINCI) += davinci 153 + machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor 153 154 machine-$(CONFIG_ARCH_DOVE) += dove 154 155 machine-$(CONFIG_ARCH_EBSA110) += ebsa110 155 156 machine-$(CONFIG_ARCH_EFM32) += efm32
+8
arch/arm/boot/dts/am335x-bone-common.dtsi
··· 301 301 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 302 302 cd-inverted; 303 303 }; 304 + 305 + &aes { 306 + status = "okay"; 307 + }; 308 + 309 + &sham { 310 + status = "okay"; 311 + };
-8
arch/arm/boot/dts/am335x-bone.dts
··· 24 24 &mmc1 { 25 25 vmmc-supply = <&ldo3_reg>; 26 26 }; 27 - 28 - &sham { 29 - status = "okay"; 30 - }; 31 - 32 - &aes { 33 - status = "okay"; 34 - };
+4
arch/arm/boot/dts/am335x-lxm.dts
··· 328 328 dual_emac_res_vlan = <3>; 329 329 }; 330 330 331 + &phy_sel { 332 + rmii-clock-ext; 333 + }; 334 + 331 335 &mac { 332 336 pinctrl-names = "default", "sleep"; 333 337 pinctrl-0 = <&cpsw_default>;
+3 -3
arch/arm/boot/dts/am33xx-clocks.dtsi
··· 99 99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { 100 100 #clock-cells = <0>; 101 101 compatible = "ti,gate-clock"; 102 - clocks = <&dpll_per_m2_ck>; 102 + clocks = <&l4ls_gclk>; 103 103 ti,bit-shift = <0>; 104 104 reg = <0x0664>; 105 105 }; ··· 107 107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { 108 108 #clock-cells = <0>; 109 109 compatible = "ti,gate-clock"; 110 - clocks = <&dpll_per_m2_ck>; 110 + clocks = <&l4ls_gclk>; 111 111 ti,bit-shift = <1>; 112 112 reg = <0x0664>; 113 113 }; ··· 115 115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { 116 116 #clock-cells = <0>; 117 117 compatible = "ti,gate-clock"; 118 - clocks = <&dpll_per_m2_ck>; 118 + clocks = <&l4ls_gclk>; 119 119 ti,bit-shift = <2>; 120 120 reg = <0x0664>; 121 121 };
+6 -6
arch/arm/boot/dts/am43xx-clocks.dtsi
··· 107 107 ehrpwm0_tbclk: ehrpwm0_tbclk { 108 108 #clock-cells = <0>; 109 109 compatible = "ti,gate-clock"; 110 - clocks = <&dpll_per_m2_ck>; 110 + clocks = <&l4ls_gclk>; 111 111 ti,bit-shift = <0>; 112 112 reg = <0x0664>; 113 113 }; ··· 115 115 ehrpwm1_tbclk: ehrpwm1_tbclk { 116 116 #clock-cells = <0>; 117 117 compatible = "ti,gate-clock"; 118 - clocks = <&dpll_per_m2_ck>; 118 + clocks = <&l4ls_gclk>; 119 119 ti,bit-shift = <1>; 120 120 reg = <0x0664>; 121 121 }; ··· 123 123 ehrpwm2_tbclk: ehrpwm2_tbclk { 124 124 #clock-cells = <0>; 125 125 compatible = "ti,gate-clock"; 126 - clocks = <&dpll_per_m2_ck>; 126 + clocks = <&l4ls_gclk>; 127 127 ti,bit-shift = <2>; 128 128 reg = <0x0664>; 129 129 }; ··· 131 131 ehrpwm3_tbclk: ehrpwm3_tbclk { 132 132 #clock-cells = <0>; 133 133 compatible = "ti,gate-clock"; 134 - clocks = <&dpll_per_m2_ck>; 134 + clocks = <&l4ls_gclk>; 135 135 ti,bit-shift = <4>; 136 136 reg = <0x0664>; 137 137 }; ··· 139 139 ehrpwm4_tbclk: ehrpwm4_tbclk { 140 140 #clock-cells = <0>; 141 141 compatible = "ti,gate-clock"; 142 - clocks = <&dpll_per_m2_ck>; 142 + clocks = <&l4ls_gclk>; 143 143 ti,bit-shift = <5>; 144 144 reg = <0x0664>; 145 145 }; ··· 147 147 ehrpwm5_tbclk: ehrpwm5_tbclk { 148 148 #clock-cells = <0>; 149 149 compatible = "ti,gate-clock"; 150 - clocks = <&dpll_per_m2_ck>; 150 + clocks = <&l4ls_gclk>; 151 151 ti,bit-shift = <6>; 152 152 reg = <0x0664>; 153 153 };
+3 -4
arch/arm/boot/dts/at91sam9260.dtsi
··· 494 494 495 495 pinctrl_usart3_rts: usart3_rts-0 { 496 496 atmel,pins = 497 - <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ 497 + <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 498 498 }; 499 499 500 500 pinctrl_usart3_cts: usart3_cts-0 { 501 501 atmel,pins = 502 - <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ 502 + <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 503 503 }; 504 504 }; 505 505 ··· 853 853 }; 854 854 855 855 usb1: gadget@fffa4000 { 856 - compatible = "atmel,at91rm9200-udc"; 856 + compatible = "atmel,at91sam9260-udc"; 857 857 reg = <0xfffa4000 0x4000>; 858 858 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 859 859 clocks = <&udc_clk>, <&udpck>; ··· 976 976 atmel,watchdog-type = "hardware"; 977 977 atmel,reset-type = "all"; 978 978 atmel,dbg-halt; 979 - atmel,idle-halt; 980 979 status = "disabled"; 981 980 }; 982 981
+5 -4
arch/arm/boot/dts/at91sam9261.dtsi
··· 124 124 }; 125 125 126 126 usb1: gadget@fffa4000 { 127 - compatible = "atmel,at91rm9200-udc"; 127 + compatible = "atmel,at91sam9261-udc"; 128 128 reg = <0xfffa4000 0x4000>; 129 129 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 130 - clocks = <&usb>, <&udc_clk>, <&udpck>; 131 - clock-names = "usb_clk", "udc_clk", "udpck"; 130 + clocks = <&udc_clk>, <&udpck>; 131 + clock-names = "pclk", "hclk"; 132 + atmel,matrix = <&matrix>; 132 133 status = "disabled"; 133 134 }; 134 135 ··· 263 262 }; 264 263 265 264 matrix: matrix@ffffee00 { 266 - compatible = "atmel,at91sam9260-bus-matrix"; 265 + compatible = "atmel,at91sam9260-bus-matrix", "syscon"; 267 266 reg = <0xffffee00 0x200>; 268 267 }; 269 268
+2 -3
arch/arm/boot/dts/at91sam9263.dtsi
··· 69 69 70 70 sram1: sram@00500000 { 71 71 compatible = "mmio-sram"; 72 - reg = <0x00300000 0x4000>; 72 + reg = <0x00500000 0x4000>; 73 73 }; 74 74 75 75 ahb { ··· 856 856 }; 857 857 858 858 usb1: gadget@fff78000 { 859 - compatible = "atmel,at91rm9200-udc"; 859 + compatible = "atmel,at91sam9263-udc"; 860 860 reg = <0xfff78000 0x4000>; 861 861 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; 862 862 clocks = <&udc_clk>, <&udpck>; ··· 905 905 atmel,watchdog-type = "hardware"; 906 906 atmel,reset-type = "all"; 907 907 atmel,dbg-halt; 908 - atmel,idle-halt; 909 908 status = "disabled"; 910 909 }; 911 910
+1 -2
arch/arm/boot/dts/at91sam9g45.dtsi
··· 1116 1116 atmel,watchdog-type = "hardware"; 1117 1117 atmel,reset-type = "all"; 1118 1118 atmel,dbg-halt; 1119 - atmel,idle-halt; 1120 1119 status = "disabled"; 1121 1120 }; 1122 1121 ··· 1300 1301 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1301 1302 reg = <0x00800000 0x100000>; 1302 1303 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1303 - clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1304 + clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1304 1305 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck"; 1305 1306 status = "disabled"; 1306 1307 };
-1
arch/arm/boot/dts/at91sam9n12.dtsi
··· 894 894 atmel,watchdog-type = "hardware"; 895 895 atmel,reset-type = "all"; 896 896 atmel,dbg-halt; 897 - atmel,idle-halt; 898 897 status = "disabled"; 899 898 }; 900 899
+2 -3
arch/arm/boot/dts/at91sam9x5.dtsi
··· 1066 1066 reg = <0x00500000 0x80000 1067 1067 0xf803c000 0x400>; 1068 1068 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 1069 - clocks = <&usb>, <&udphs_clk>; 1069 + clocks = <&utmi>, <&udphs_clk>; 1070 1070 clock-names = "hclk", "pclk"; 1071 1071 status = "disabled"; 1072 1072 ··· 1130 1130 atmel,watchdog-type = "hardware"; 1131 1131 atmel,reset-type = "all"; 1132 1132 atmel,dbg-halt; 1133 - atmel,idle-halt; 1134 1133 status = "disabled"; 1135 1134 }; 1136 1135 ··· 1185 1186 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1186 1187 reg = <0x00700000 0x100000>; 1187 1188 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1188 - clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1189 + clocks = <&utmi>, <&uhphs_clk>, <&uhpck>; 1189 1190 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1190 1191 status = "disabled"; 1191 1192 };
+4 -6
arch/arm/boot/dts/dra7-evm.dts
··· 263 263 264 264 dcan1_pins_default: dcan1_pins_default { 265 265 pinctrl-single,pins = < 266 - 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ 267 - 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 268 - 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */ 266 + 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 267 + 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 269 268 >; 270 269 }; 271 270 272 271 dcan1_pins_sleep: dcan1_pins_sleep { 273 272 pinctrl-single,pins = < 274 - 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ 275 - 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 276 - 0x418 (MUX_MODE15) /* wakeup0.off */ 273 + 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 274 + 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ 277 275 >; 278 276 }; 279 277 };
+4 -6
arch/arm/boot/dts/dra72-evm.dts
··· 119 119 120 120 dcan1_pins_default: dcan1_pins_default { 121 121 pinctrl-single,pins = < 122 - 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ 123 - 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 124 - 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */ 122 + 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 123 + 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 125 124 >; 126 125 }; 127 126 128 127 dcan1_pins_sleep: dcan1_pins_sleep { 129 128 pinctrl-single,pins = < 130 - 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ 131 - 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 132 - 0x418 (MUX_MODE15) /* wakeup0.off */ 129 + 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 130 + 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ 133 131 >; 134 132 }; 135 133
+81 -9
arch/arm/boot/dts/dra7xx-clocks.dtsi
··· 243 243 ti,invert-autoidle-bit; 244 244 }; 245 245 246 + dpll_core_byp_mux: dpll_core_byp_mux { 247 + #clock-cells = <0>; 248 + compatible = "ti,mux-clock"; 249 + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 250 + ti,bit-shift = <23>; 251 + reg = <0x012c>; 252 + }; 253 + 246 254 dpll_core_ck: dpll_core_ck { 247 255 #clock-cells = <0>; 248 256 compatible = "ti,omap4-dpll-core-clock"; 249 - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 257 + clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; 250 258 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 251 259 }; 252 260 ··· 317 309 clock-div = <1>; 318 310 }; 319 311 312 + dpll_dsp_byp_mux: dpll_dsp_byp_mux { 313 + #clock-cells = <0>; 314 + compatible = "ti,mux-clock"; 315 + clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; 316 + ti,bit-shift = <23>; 317 + reg = <0x0240>; 318 + }; 319 + 320 320 dpll_dsp_ck: dpll_dsp_ck { 321 321 #clock-cells = <0>; 322 322 compatible = "ti,omap4-dpll-clock"; 323 - clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; 323 + clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; 324 324 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; 325 325 }; 326 326 ··· 351 335 clock-div = <1>; 352 336 }; 353 337 338 + dpll_iva_byp_mux: dpll_iva_byp_mux { 339 + #clock-cells = <0>; 340 + compatible = "ti,mux-clock"; 341 + clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; 342 + ti,bit-shift = <23>; 343 + reg = <0x01ac>; 344 + }; 345 + 354 346 dpll_iva_ck: dpll_iva_ck { 355 347 #clock-cells = <0>; 356 348 compatible = "ti,omap4-dpll-clock"; 357 - clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; 349 + clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; 358 350 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 359 351 }; 360 352 ··· 385 361 clock-div = <1>; 386 362 }; 387 363 364 + dpll_gpu_byp_mux: dpll_gpu_byp_mux { 365 + #clock-cells = <0>; 366 + compatible = "ti,mux-clock"; 367 + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 368 + ti,bit-shift = <23>; 369 + reg = <0x02e4>; 370 + }; 371 + 388 372 dpll_gpu_ck: dpll_gpu_ck { 389 373 #clock-cells = <0>; 390 374 compatible = "ti,omap4-dpll-clock"; 391 - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 375 + clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; 392 376 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; 393 377 }; 394 378 ··· 430 398 clock-div = <1>; 431 399 }; 432 400 401 + dpll_ddr_byp_mux: dpll_ddr_byp_mux { 402 + #clock-cells = <0>; 403 + compatible = "ti,mux-clock"; 404 + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 405 + ti,bit-shift = <23>; 406 + reg = <0x021c>; 407 + }; 408 + 433 409 dpll_ddr_ck: dpll_ddr_ck { 434 410 #clock-cells = <0>; 435 411 compatible = "ti,omap4-dpll-clock"; 436 - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 412 + clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; 437 413 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; 438 414 }; 439 415 ··· 456 416 ti,invert-autoidle-bit; 457 417 }; 458 418 419 + dpll_gmac_byp_mux: dpll_gmac_byp_mux { 420 + #clock-cells = <0>; 421 + compatible = "ti,mux-clock"; 422 + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 423 + ti,bit-shift = <23>; 424 + reg = <0x02b4>; 425 + }; 426 + 459 427 dpll_gmac_ck: dpll_gmac_ck { 460 428 #clock-cells = <0>; 461 429 compatible = "ti,omap4-dpll-clock"; 462 - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 430 + clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; 463 431 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; 464 432 }; 465 433 ··· 530 482 clock-div = <1>; 531 483 }; 532 484 485 + dpll_eve_byp_mux: dpll_eve_byp_mux { 486 + #clock-cells = <0>; 487 + compatible = "ti,mux-clock"; 488 + clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; 489 + ti,bit-shift = <23>; 490 + reg = <0x0290>; 491 + }; 492 + 533 493 dpll_eve_ck: dpll_eve_ck { 534 494 #clock-cells = <0>; 535 495 compatible = "ti,omap4-dpll-clock"; 536 - clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; 496 + clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; 537 497 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; 538 498 }; 539 499 ··· 1305 1249 clock-div = <1>; 1306 1250 }; 1307 1251 1252 + dpll_per_byp_mux: dpll_per_byp_mux { 1253 + #clock-cells = <0>; 1254 + compatible = "ti,mux-clock"; 1255 + clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; 1256 + ti,bit-shift = <23>; 1257 + reg = <0x014c>; 1258 + }; 1259 + 1308 1260 dpll_per_ck: dpll_per_ck { 1309 1261 #clock-cells = <0>; 1310 1262 compatible = "ti,omap4-dpll-clock"; 1311 - clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; 1263 + clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; 1312 1264 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 1313 1265 }; 1314 1266 ··· 1339 1275 clock-div = <1>; 1340 1276 }; 1341 1277 1278 + dpll_usb_byp_mux: dpll_usb_byp_mux { 1279 + #clock-cells = <0>; 1280 + compatible = "ti,mux-clock"; 1281 + clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; 1282 + ti,bit-shift = <23>; 1283 + reg = <0x018c>; 1284 + }; 1285 + 1342 1286 dpll_usb_ck: dpll_usb_ck { 1343 1287 #clock-cells = <0>; 1344 1288 compatible = "ti,omap4-dpll-j-type-clock"; 1345 - clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; 1289 + clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; 1346 1290 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 1347 1291 }; 1348 1292
+2
arch/arm/boot/dts/exynos3250.dtsi
··· 18 18 */ 19 19 20 20 #include "skeleton.dtsi" 21 + #include "exynos4-cpu-thermal.dtsi" 21 22 #include <dt-bindings/clock/exynos3250.h> 22 23 23 24 / { ··· 194 193 interrupts = <0 216 0>; 195 194 clocks = <&cmu CLK_TMU_APBIF>; 196 195 clock-names = "tmu_apbif"; 196 + #include "exynos4412-tmu-sensor-conf.dtsi" 197 197 status = "disabled"; 198 198 }; 199 199
+52
arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
··· 1 + /* 2 + * Device tree sources for Exynos4 thermal zone 3 + * 4 + * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> 5 + * 6 + * This program is free software; you can redistribute it and/or modify 7 + * it under the terms of the GNU General Public License version 2 as 8 + * published by the Free Software Foundation. 9 + * 10 + */ 11 + 12 + #include <dt-bindings/thermal/thermal.h> 13 + 14 + / { 15 + thermal-zones { 16 + cpu_thermal: cpu-thermal { 17 + thermal-sensors = <&tmu 0>; 18 + polling-delay-passive = <0>; 19 + polling-delay = <0>; 20 + trips { 21 + cpu_alert0: cpu-alert-0 { 22 + temperature = <70000>; /* millicelsius */ 23 + hysteresis = <10000>; /* millicelsius */ 24 + type = "active"; 25 + }; 26 + cpu_alert1: cpu-alert-1 { 27 + temperature = <95000>; /* millicelsius */ 28 + hysteresis = <10000>; /* millicelsius */ 29 + type = "active"; 30 + }; 31 + cpu_alert2: cpu-alert-2 { 32 + temperature = <110000>; /* millicelsius */ 33 + hysteresis = <10000>; /* millicelsius */ 34 + type = "active"; 35 + }; 36 + cpu_crit0: cpu-crit-0 { 37 + temperature = <120000>; /* millicelsius */ 38 + hysteresis = <0>; /* millicelsius */ 39 + type = "critical"; 40 + }; 41 + }; 42 + cooling-maps { 43 + map0 { 44 + trip = <&cpu_alert0>; 45 + }; 46 + map1 { 47 + trip = <&cpu_alert1>; 48 + }; 49 + }; 50 + }; 51 + }; 52 + };
+45
arch/arm/boot/dts/exynos4.dtsi
··· 38 38 i2c5 = &i2c_5; 39 39 i2c6 = &i2c_6; 40 40 i2c7 = &i2c_7; 41 + i2c8 = &i2c_8; 41 42 csis0 = &csis_0; 42 43 csis1 = &csis_1; 43 44 fimc0 = &fimc_0; ··· 105 104 compatible = "samsung,exynos4210-pd"; 106 105 reg = <0x10023C20 0x20>; 107 106 #power-domain-cells = <0>; 107 + power-domains = <&pd_lcd0>; 108 108 }; 109 109 110 110 pd_cam: cam-power-domain@10023C00 { ··· 556 554 status = "disabled"; 557 555 }; 558 556 557 + i2c_8: i2c@138E0000 { 558 + #address-cells = <1>; 559 + #size-cells = <0>; 560 + compatible = "samsung,s3c2440-hdmiphy-i2c"; 561 + reg = <0x138E0000 0x100>; 562 + interrupts = <0 93 0>; 563 + clocks = <&clock CLK_I2C_HDMI>; 564 + clock-names = "i2c"; 565 + status = "disabled"; 566 + 567 + hdmi_i2c_phy: hdmiphy@38 { 568 + compatible = "exynos4210-hdmiphy"; 569 + reg = <0x38>; 570 + }; 571 + }; 572 + 559 573 spi_0: spi@13920000 { 560 574 compatible = "samsung,exynos4210-spi"; 561 575 reg = <0x13920000 0x100>; ··· 678 660 clock-names = "sclk_fimd", "fimd"; 679 661 power-domains = <&pd_lcd0>; 680 662 samsung,sysreg = <&sys_reg>; 663 + status = "disabled"; 664 + }; 665 + 666 + tmu: tmu@100C0000 { 667 + #include "exynos4412-tmu-sensor-conf.dtsi" 668 + }; 669 + 670 + hdmi: hdmi@12D00000 { 671 + compatible = "samsung,exynos4210-hdmi"; 672 + reg = <0x12D00000 0x70000>; 673 + interrupts = <0 92 0>; 674 + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", 675 + "mout_hdmi"; 676 + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 677 + <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 678 + <&clock CLK_MOUT_HDMI>; 679 + phy = <&hdmi_i2c_phy>; 680 + power-domains = <&pd_tv>; 681 + samsung,syscon-phandle = <&pmu_system_controller>; 682 + status = "disabled"; 683 + }; 684 + 685 + mixer: mixer@12C10000 { 686 + compatible = "samsung,exynos4210-mixer"; 687 + interrupts = <0 91 0>; 688 + reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; 689 + power-domains = <&pd_tv>; 681 690 status = "disabled"; 682 691 }; 683 692
+19
arch/arm/boot/dts/exynos4210-trats.dts
··· 426 426 status = "okay"; 427 427 }; 428 428 429 + tmu@100C0000 { 430 + status = "okay"; 431 + }; 432 + 433 + thermal-zones { 434 + cpu_thermal: cpu-thermal { 435 + cooling-maps { 436 + map0 { 437 + /* Corresponds to 800MHz at freq_table */ 438 + cooling-device = <&cpu0 2 2>; 439 + }; 440 + map1 { 441 + /* Corresponds to 200MHz at freq_table */ 442 + cooling-device = <&cpu0 4 4>; 443 + }; 444 + }; 445 + }; 446 + }; 447 + 429 448 camera { 430 449 pinctrl-names = "default"; 431 450 pinctrl-0 = <>;
+57
arch/arm/boot/dts/exynos4210-universal_c210.dts
··· 505 505 assigned-clock-rates = <0>, <160000000>; 506 506 }; 507 507 }; 508 + 509 + hdmi_en: voltage-regulator-hdmi-5v { 510 + compatible = "regulator-fixed"; 511 + regulator-name = "HDMI_5V"; 512 + regulator-min-microvolt = <5000000>; 513 + regulator-max-microvolt = <5000000>; 514 + gpio = <&gpe0 1 0>; 515 + enable-active-high; 516 + }; 517 + 518 + hdmi_ddc: i2c-ddc { 519 + compatible = "i2c-gpio"; 520 + gpios = <&gpe4 2 0 &gpe4 3 0>; 521 + i2c-gpio,delay-us = <100>; 522 + #address-cells = <1>; 523 + #size-cells = <0>; 524 + 525 + pinctrl-0 = <&i2c_ddc_bus>; 526 + pinctrl-names = "default"; 527 + status = "okay"; 528 + }; 529 + 530 + mixer@12C10000 { 531 + status = "okay"; 532 + }; 533 + 534 + hdmi@12D00000 { 535 + hpd-gpio = <&gpx3 7 0>; 536 + pinctrl-names = "default"; 537 + pinctrl-0 = <&hdmi_hpd>; 538 + hdmi-en-supply = <&hdmi_en>; 539 + vdd-supply = <&ldo3_reg>; 540 + vdd_osc-supply = <&ldo4_reg>; 541 + vdd_pll-supply = <&ldo3_reg>; 542 + ddc = <&hdmi_ddc>; 543 + status = "okay"; 544 + }; 545 + 546 + i2c@138E0000 { 547 + status = "okay"; 548 + }; 549 + }; 550 + 551 + &pinctrl_1 { 552 + hdmi_hpd: hdmi-hpd { 553 + samsung,pins = "gpx3-7"; 554 + samsung,pin-pud = <0>; 555 + }; 556 + }; 557 + 558 + &pinctrl_0 { 559 + i2c_ddc_bus: i2c-ddc-bus { 560 + samsung,pins = "gpe4-2", "gpe4-3"; 561 + samsung,pin-function = <2>; 562 + samsung,pin-pud = <3>; 563 + samsung,pin-drv = <0>; 564 + }; 508 565 }; 509 566 510 567 &mdma1 {
+36 -2
arch/arm/boot/dts/exynos4210.dtsi
··· 21 21 22 22 #include "exynos4.dtsi" 23 23 #include "exynos4210-pinctrl.dtsi" 24 + #include "exynos4-cpu-thermal.dtsi" 24 25 25 26 / { 26 27 compatible = "samsung,exynos4210", "samsung,exynos4"; ··· 36 35 #address-cells = <1>; 37 36 #size-cells = <0>; 38 37 39 - cpu@900 { 38 + cpu0: cpu@900 { 40 39 device_type = "cpu"; 41 40 compatible = "arm,cortex-a9"; 42 41 reg = <0x900>; 42 + cooling-min-level = <4>; 43 + cooling-max-level = <2>; 44 + #cooling-cells = <2>; /* min followed by max */ 43 45 }; 44 46 45 47 cpu@901 { ··· 157 153 reg = <0x03860000 0x1000>; 158 154 }; 159 155 160 - tmu@100C0000 { 156 + tmu: tmu@100C0000 { 161 157 compatible = "samsung,exynos4210-tmu"; 162 158 interrupt-parent = <&combiner>; 163 159 reg = <0x100C0000 0x100>; 164 160 interrupts = <2 4>; 165 161 clocks = <&clock CLK_TMU_APBIF>; 166 162 clock-names = "tmu_apbif"; 163 + samsung,tmu_gain = <15>; 164 + samsung,tmu_reference_voltage = <7>; 167 165 status = "disabled"; 166 + }; 167 + 168 + thermal-zones { 169 + cpu_thermal: cpu-thermal { 170 + polling-delay-passive = <0>; 171 + polling-delay = <0>; 172 + thermal-sensors = <&tmu 0>; 173 + 174 + trips { 175 + cpu_alert0: cpu-alert-0 { 176 + temperature = <85000>; /* millicelsius */ 177 + }; 178 + cpu_alert1: cpu-alert-1 { 179 + temperature = <100000>; /* millicelsius */ 180 + }; 181 + cpu_alert2: cpu-alert-2 { 182 + temperature = <110000>; /* millicelsius */ 183 + }; 184 + }; 185 + }; 168 186 }; 169 187 170 188 g2d@12800000 { ··· 227 201 samsung,mainscaler-ext; 228 202 samsung,lcd-wb; 229 203 }; 204 + }; 205 + 206 + mixer: mixer@12C10000 { 207 + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", 208 + "sclk_mixer"; 209 + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 210 + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, 211 + <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; 230 212 }; 231 213 232 214 ppmu_lcd1: ppmu_lcd1@12240000 {
+4 -1
arch/arm/boot/dts/exynos4212.dtsi
··· 26 26 #address-cells = <1>; 27 27 #size-cells = <0>; 28 28 29 - cpu@A00 { 29 + cpu0: cpu@A00 { 30 30 device_type = "cpu"; 31 31 compatible = "arm,cortex-a9"; 32 32 reg = <0xA00>; 33 + cooling-min-level = <13>; 34 + cooling-max-level = <7>; 35 + #cooling-cells = <2>; /* min followed by max */ 33 36 }; 34 37 35 38 cpu@A01 {
+64
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
··· 249 249 regulator-always-on; 250 250 }; 251 251 252 + ldo8_reg: ldo@8 { 253 + regulator-compatible = "LDO8"; 254 + regulator-name = "VDD10_HDMI_1.0V"; 255 + regulator-min-microvolt = <1000000>; 256 + regulator-max-microvolt = <1000000>; 257 + }; 258 + 259 + ldo10_reg: ldo@10 { 260 + regulator-compatible = "LDO10"; 261 + regulator-name = "VDDQ_MIPIHSI_1.8V"; 262 + regulator-min-microvolt = <1800000>; 263 + regulator-max-microvolt = <1800000>; 264 + }; 265 + 252 266 ldo11_reg: LDO11 { 253 267 regulator-name = "VDD18_ABB1_1.8V"; 254 268 regulator-min-microvolt = <1800000>; ··· 425 411 ehci: ehci@12580000 { 426 412 status = "okay"; 427 413 }; 414 + 415 + tmu@100C0000 { 416 + vtmu-supply = <&ldo10_reg>; 417 + status = "okay"; 418 + }; 419 + 420 + thermal-zones { 421 + cpu_thermal: cpu-thermal { 422 + cooling-maps { 423 + map0 { 424 + /* Corresponds to 800MHz at freq_table */ 425 + cooling-device = <&cpu0 7 7>; 426 + }; 427 + map1 { 428 + /* Corresponds to 200MHz at freq_table */ 429 + cooling-device = <&cpu0 13 13>; 430 + }; 431 + }; 432 + }; 433 + }; 434 + 435 + mixer: mixer@12C10000 { 436 + status = "okay"; 437 + }; 438 + 439 + hdmi@12D00000 { 440 + hpd-gpio = <&gpx3 7 0>; 441 + pinctrl-names = "default"; 442 + pinctrl-0 = <&hdmi_hpd>; 443 + vdd-supply = <&ldo8_reg>; 444 + vdd_osc-supply = <&ldo10_reg>; 445 + vdd_pll-supply = <&ldo8_reg>; 446 + ddc = <&hdmi_ddc>; 447 + status = "okay"; 448 + }; 449 + 450 + hdmi_ddc: i2c@13880000 { 451 + status = "okay"; 452 + pinctrl-names = "default"; 453 + pinctrl-0 = <&i2c2_bus>; 454 + }; 455 + 456 + i2c@138E0000 { 457 + status = "okay"; 458 + }; 428 459 }; 429 460 430 461 &pinctrl_1 { ··· 483 424 samsung,pin-function = <0>; 484 425 samsung,pin-pud = <0>; 485 426 samsung,pin-drv = <0>; 427 + }; 428 + 429 + hdmi_hpd: hdmi-hpd { 430 + samsung,pins = "gpx3-7"; 431 + samsung,pin-pud = <1>; 486 432 }; 487 433 };
+24
arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
··· 1 + /* 2 + * Device tree sources for Exynos4412 TMU sensor configuration 3 + * 4 + * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> 5 + * 6 + * This program is free software; you can redistribute it and/or modify 7 + * it under the terms of the GNU General Public License version 2 as 8 + * published by the Free Software Foundation. 9 + * 10 + */ 11 + 12 + #include <dt-bindings/thermal/thermal_exynos.h> 13 + 14 + #thermal-sensor-cells = <0>; 15 + samsung,tmu_gain = <8>; 16 + samsung,tmu_reference_voltage = <16>; 17 + samsung,tmu_noise_cancel_mode = <4>; 18 + samsung,tmu_efuse_value = <55>; 19 + samsung,tmu_min_efuse_value = <40>; 20 + samsung,tmu_max_efuse_value = <100>; 21 + samsung,tmu_first_point_trim = <25>; 22 + samsung,tmu_second_point_trim = <85>; 23 + samsung,tmu_default_temp_offset = <50>; 24 + samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
+15
arch/arm/boot/dts/exynos4412-trats2.dts
··· 927 927 pulldown-ohm = <100000>; /* 100K */ 928 928 io-channels = <&adc 2>; /* Battery temperature */ 929 929 }; 930 + 931 + thermal-zones { 932 + cpu_thermal: cpu-thermal { 933 + cooling-maps { 934 + map0 { 935 + /* Corresponds to 800MHz at freq_table */ 936 + cooling-device = <&cpu0 7 7>; 937 + }; 938 + map1 { 939 + /* Corresponds to 200MHz at freq_table */ 940 + cooling-device = <&cpu0 13 13>; 941 + }; 942 + }; 943 + }; 944 + }; 930 945 }; 931 946 932 947 &pmu_system_controller {
+4 -1
arch/arm/boot/dts/exynos4412.dtsi
··· 26 26 #address-cells = <1>; 27 27 #size-cells = <0>; 28 28 29 - cpu@A00 { 29 + cpu0: cpu@A00 { 30 30 device_type = "cpu"; 31 31 compatible = "arm,cortex-a9"; 32 32 reg = <0xA00>; 33 + cooling-min-level = <13>; 34 + cooling-max-level = <7>; 35 + #cooling-cells = <2>; /* min followed by max */ 33 36 }; 34 37 35 38 cpu@A01 {
+12
arch/arm/boot/dts/exynos4x12.dtsi
··· 19 19 20 20 #include "exynos4.dtsi" 21 21 #include "exynos4x12-pinctrl.dtsi" 22 + #include "exynos4-cpu-thermal.dtsi" 22 23 23 24 / { 24 25 aliases { ··· 297 296 clocks = <&clock 383>; 298 297 clock-names = "tmu_apbif"; 299 298 status = "disabled"; 299 + }; 300 + 301 + hdmi: hdmi@12D00000 { 302 + compatible = "samsung,exynos4212-hdmi"; 303 + }; 304 + 305 + mixer: mixer@12C10000 { 306 + compatible = "samsung,exynos4212-mixer"; 307 + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; 308 + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 309 + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; 300 310 }; 301 311 };
+39 -5
arch/arm/boot/dts/exynos5250.dtsi
··· 20 20 #include <dt-bindings/clock/exynos5250.h> 21 21 #include "exynos5.dtsi" 22 22 #include "exynos5250-pinctrl.dtsi" 23 - 23 + #include "exynos4-cpu-thermal.dtsi" 24 24 #include <dt-bindings/clock/exynos-audss-clk.h> 25 25 26 26 / { ··· 58 58 #address-cells = <1>; 59 59 #size-cells = <0>; 60 60 61 - cpu@0 { 61 + cpu0: cpu@0 { 62 62 device_type = "cpu"; 63 63 compatible = "arm,cortex-a15"; 64 64 reg = <0>; 65 65 clock-frequency = <1700000000>; 66 + cooling-min-level = <15>; 67 + cooling-max-level = <9>; 68 + #cooling-cells = <2>; /* min followed by max */ 66 69 }; 67 70 cpu@1 { 68 71 device_type = "cpu"; ··· 102 99 pd_mfc: mfc-power-domain@10044040 { 103 100 compatible = "samsung,exynos4210-pd"; 104 101 reg = <0x10044040 0x20>; 102 + #power-domain-cells = <0>; 103 + }; 104 + 105 + pd_disp1: disp1-power-domain@100440A0 { 106 + compatible = "samsung,exynos4210-pd"; 107 + reg = <0x100440A0 0x20>; 105 108 #power-domain-cells = <0>; 106 109 }; 107 110 ··· 244 235 status = "disabled"; 245 236 }; 246 237 247 - tmu@10060000 { 238 + tmu: tmu@10060000 { 248 239 compatible = "samsung,exynos5250-tmu"; 249 240 reg = <0x10060000 0x100>; 250 241 interrupts = <0 65 0>; 251 242 clocks = <&clock CLK_TMU>; 252 243 clock-names = "tmu_apbif"; 244 + #include "exynos4412-tmu-sensor-conf.dtsi" 245 + }; 246 + 247 + thermal-zones { 248 + cpu_thermal: cpu-thermal { 249 + polling-delay-passive = <0>; 250 + polling-delay = <0>; 251 + thermal-sensors = <&tmu 0>; 252 + 253 + cooling-maps { 254 + map0 { 255 + /* Corresponds to 800MHz at freq_table */ 256 + cooling-device = <&cpu0 9 9>; 257 + }; 258 + map1 { 259 + /* Corresponds to 200MHz at freq_table */ 260 + cooling-device = <&cpu0 15 15>; 261 + }; 262 + }; 263 + }; 253 264 }; 254 265 255 266 serial@12C00000 { ··· 748 719 hdmi: hdmi { 749 720 compatible = "samsung,exynos4212-hdmi"; 750 721 reg = <0x14530000 0x70000>; 722 + power-domains = <&pd_disp1>; 751 723 interrupts = <0 95 0>; 752 724 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 753 725 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, ··· 761 731 mixer { 762 732 compatible = "samsung,exynos5250-mixer"; 763 733 reg = <0x14450000 0x10000>; 734 + power-domains = <&pd_disp1>; 764 735 interrupts = <0 94 0>; 765 - clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 766 - clock-names = "mixer", "sclk_hdmi"; 736 + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 737 + <&clock CLK_SCLK_HDMI>; 738 + clock-names = "mixer", "hdmi", "sclk_hdmi"; 767 739 }; 768 740 769 741 dp_phy: video-phy@10040720 { ··· 775 743 }; 776 744 777 745 dp: dp-controller@145B0000 { 746 + power-domains = <&pd_disp1>; 778 747 clocks = <&clock CLK_DP>; 779 748 clock-names = "dp"; 780 749 phys = <&dp_phy>; ··· 783 750 }; 784 751 785 752 fimd: fimd@14400000 { 753 + power-domains = <&pd_disp1>; 786 754 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 787 755 clock-names = "sclk_fimd", "fimd"; 788 756 };
+35
arch/arm/boot/dts/exynos5420-trip-points.dtsi
··· 1 + /* 2 + * Device tree sources for default Exynos5420 thermal zone definition 3 + * 4 + * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> 5 + * 6 + * This program is free software; you can redistribute it and/or modify 7 + * it under the terms of the GNU General Public License version 2 as 8 + * published by the Free Software Foundation. 9 + * 10 + */ 11 + 12 + polling-delay-passive = <0>; 13 + polling-delay = <0>; 14 + trips { 15 + cpu-alert-0 { 16 + temperature = <85000>; /* millicelsius */ 17 + hysteresis = <10000>; /* millicelsius */ 18 + type = "active"; 19 + }; 20 + cpu-alert-1 { 21 + temperature = <103000>; /* millicelsius */ 22 + hysteresis = <10000>; /* millicelsius */ 23 + type = "active"; 24 + }; 25 + cpu-alert-2 { 26 + temperature = <110000>; /* millicelsius */ 27 + hysteresis = <10000>; /* millicelsius */ 28 + type = "active"; 29 + }; 30 + cpu-crit-0 { 31 + temperature = <1200000>; /* millicelsius */ 32 + hysteresis = <0>; /* millicelsius */ 33 + type = "critical"; 34 + }; 35 + };
+31 -2
arch/arm/boot/dts/exynos5420.dtsi
··· 740 740 compatible = "samsung,exynos5420-mixer"; 741 741 reg = <0x14450000 0x10000>; 742 742 interrupts = <0 94 0>; 743 - clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 744 - clock-names = "mixer", "sclk_hdmi"; 743 + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 744 + <&clock CLK_SCLK_HDMI>; 745 + clock-names = "mixer", "hdmi", "sclk_hdmi"; 745 746 power-domains = <&disp_pd>; 746 747 }; 747 748 ··· 783 782 interrupts = <0 65 0>; 784 783 clocks = <&clock CLK_TMU>; 785 784 clock-names = "tmu_apbif"; 785 + #include "exynos4412-tmu-sensor-conf.dtsi" 786 786 }; 787 787 788 788 tmu_cpu1: tmu@10064000 { ··· 792 790 interrupts = <0 183 0>; 793 791 clocks = <&clock CLK_TMU>; 794 792 clock-names = "tmu_apbif"; 793 + #include "exynos4412-tmu-sensor-conf.dtsi" 795 794 }; 796 795 797 796 tmu_cpu2: tmu@10068000 { ··· 801 798 interrupts = <0 184 0>; 802 799 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 803 800 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 801 + #include "exynos4412-tmu-sensor-conf.dtsi" 804 802 }; 805 803 806 804 tmu_cpu3: tmu@1006c000 { ··· 810 806 interrupts = <0 185 0>; 811 807 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 812 808 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 809 + #include "exynos4412-tmu-sensor-conf.dtsi" 813 810 }; 814 811 815 812 tmu_gpu: tmu@100a0000 { ··· 819 814 interrupts = <0 215 0>; 820 815 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 821 816 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 817 + #include "exynos4412-tmu-sensor-conf.dtsi" 818 + }; 819 + 820 + thermal-zones { 821 + cpu0_thermal: cpu0-thermal { 822 + thermal-sensors = <&tmu_cpu0>; 823 + #include "exynos5420-trip-points.dtsi" 824 + }; 825 + cpu1_thermal: cpu1-thermal { 826 + thermal-sensors = <&tmu_cpu1>; 827 + #include "exynos5420-trip-points.dtsi" 828 + }; 829 + cpu2_thermal: cpu2-thermal { 830 + thermal-sensors = <&tmu_cpu2>; 831 + #include "exynos5420-trip-points.dtsi" 832 + }; 833 + cpu3_thermal: cpu3-thermal { 834 + thermal-sensors = <&tmu_cpu3>; 835 + #include "exynos5420-trip-points.dtsi" 836 + }; 837 + gpu_thermal: gpu-thermal { 838 + thermal-sensors = <&tmu_gpu>; 839 + #include "exynos5420-trip-points.dtsi" 840 + }; 822 841 }; 823 842 824 843 watchdog: watchdog@101D0000 {
+24
arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi
··· 1 + /* 2 + * Device tree sources for Exynos5440 TMU sensor configuration 3 + * 4 + * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> 5 + * 6 + * This program is free software; you can redistribute it and/or modify 7 + * it under the terms of the GNU General Public License version 2 as 8 + * published by the Free Software Foundation. 9 + * 10 + */ 11 + 12 + #include <dt-bindings/thermal/thermal_exynos.h> 13 + 14 + #thermal-sensor-cells = <0>; 15 + samsung,tmu_gain = <5>; 16 + samsung,tmu_reference_voltage = <16>; 17 + samsung,tmu_noise_cancel_mode = <4>; 18 + samsung,tmu_efuse_value = <0x5d2d>; 19 + samsung,tmu_min_efuse_value = <16>; 20 + samsung,tmu_max_efuse_value = <76>; 21 + samsung,tmu_first_point_trim = <25>; 22 + samsung,tmu_second_point_trim = <70>; 23 + samsung,tmu_default_temp_offset = <25>; 24 + samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
+25
arch/arm/boot/dts/exynos5440-trip-points.dtsi
··· 1 + /* 2 + * Device tree sources for default Exynos5440 thermal zone definition 3 + * 4 + * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> 5 + * 6 + * This program is free software; you can redistribute it and/or modify 7 + * it under the terms of the GNU General Public License version 2 as 8 + * published by the Free Software Foundation. 9 + * 10 + */ 11 + 12 + polling-delay-passive = <0>; 13 + polling-delay = <0>; 14 + trips { 15 + cpu-alert-0 { 16 + temperature = <100000>; /* millicelsius */ 17 + hysteresis = <0>; /* millicelsius */ 18 + type = "active"; 19 + }; 20 + cpu-crit-0 { 21 + temperature = <1050000>; /* millicelsius */ 22 + hysteresis = <0>; /* millicelsius */ 23 + type = "critical"; 24 + }; 25 + };
+18
arch/arm/boot/dts/exynos5440.dtsi
··· 219 219 interrupts = <0 58 0>; 220 220 clocks = <&clock CLK_B_125>; 221 221 clock-names = "tmu_apbif"; 222 + #include "exynos5440-tmu-sensor-conf.dtsi" 222 223 }; 223 224 224 225 tmuctrl_1: tmuctrl@16011C { ··· 228 227 interrupts = <0 58 0>; 229 228 clocks = <&clock CLK_B_125>; 230 229 clock-names = "tmu_apbif"; 230 + #include "exynos5440-tmu-sensor-conf.dtsi" 231 231 }; 232 232 233 233 tmuctrl_2: tmuctrl@160120 { ··· 237 235 interrupts = <0 58 0>; 238 236 clocks = <&clock CLK_B_125>; 239 237 clock-names = "tmu_apbif"; 238 + #include "exynos5440-tmu-sensor-conf.dtsi" 239 + }; 240 + 241 + thermal-zones { 242 + cpu0_thermal: cpu0-thermal { 243 + thermal-sensors = <&tmuctrl_0>; 244 + #include "exynos5440-trip-points.dtsi" 245 + }; 246 + cpu1_thermal: cpu1-thermal { 247 + thermal-sensors = <&tmuctrl_1>; 248 + #include "exynos5440-trip-points.dtsi" 249 + }; 250 + cpu2_thermal: cpu2-thermal { 251 + thermal-sensors = <&tmuctrl_2>; 252 + #include "exynos5440-trip-points.dtsi" 253 + }; 240 254 }; 241 255 242 256 sata@210000 {
+2
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
··· 35 35 regulator-max-microvolt = <5000000>; 36 36 gpio = <&gpio3 22 0>; 37 37 enable-active-high; 38 + vin-supply = <&swbst_reg>; 38 39 }; 39 40 40 41 reg_usb_h1_vbus: regulator@1 { ··· 46 45 regulator-max-microvolt = <5000000>; 47 46 gpio = <&gpio1 29 0>; 48 47 enable-active-high; 48 + vin-supply = <&swbst_reg>; 49 49 }; 50 50 51 51 reg_audio: regulator@2 {
+2
arch/arm/boot/dts/imx6sl-evk.dts
··· 52 52 regulator-max-microvolt = <5000000>; 53 53 gpio = <&gpio4 0 0>; 54 54 enable-active-high; 55 + vin-supply = <&swbst_reg>; 55 56 }; 56 57 57 58 reg_usb_otg2_vbus: regulator@1 { ··· 63 62 regulator-max-microvolt = <5000000>; 64 63 gpio = <&gpio4 2 0>; 65 64 enable-active-high; 65 + vin-supply = <&swbst_reg>; 66 66 }; 67 67 68 68 reg_aud3v: regulator@2 {
+1 -1
arch/arm/boot/dts/omap5-core-thermal.dtsi
··· 13 13 14 14 core_thermal: core_thermal { 15 15 polling-delay-passive = <250>; /* milliseconds */ 16 - polling-delay = <1000>; /* milliseconds */ 16 + polling-delay = <500>; /* milliseconds */ 17 17 18 18 /* sensor ID */ 19 19 thermal-sensors = <&bandgap 2>;
+1 -1
arch/arm/boot/dts/omap5-gpu-thermal.dtsi
··· 13 13 14 14 gpu_thermal: gpu_thermal { 15 15 polling-delay-passive = <250>; /* milliseconds */ 16 - polling-delay = <1000>; /* milliseconds */ 16 + polling-delay = <500>; /* milliseconds */ 17 17 18 18 /* sensor ID */ 19 19 thermal-sensors = <&bandgap 1>;
+4
arch/arm/boot/dts/omap5.dtsi
··· 1079 1079 }; 1080 1080 }; 1081 1081 1082 + &cpu_thermal { 1083 + polling-delay = <500>; /* milliseconds */ 1084 + }; 1085 + 1082 1086 /include/ "omap54xx-clocks.dtsi"
+37 -4
arch/arm/boot/dts/omap54xx-clocks.dtsi
··· 167 167 ti,index-starts-at-one; 168 168 }; 169 169 170 + dpll_core_byp_mux: dpll_core_byp_mux { 171 + #clock-cells = <0>; 172 + compatible = "ti,mux-clock"; 173 + clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; 174 + ti,bit-shift = <23>; 175 + reg = <0x012c>; 176 + }; 177 + 170 178 dpll_core_ck: dpll_core_ck { 171 179 #clock-cells = <0>; 172 180 compatible = "ti,omap4-dpll-core-clock"; 173 - clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; 181 + clocks = <&sys_clkin>, <&dpll_core_byp_mux>; 174 182 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 175 183 }; 176 184 ··· 302 294 clock-div = <1>; 303 295 }; 304 296 297 + dpll_iva_byp_mux: dpll_iva_byp_mux { 298 + #clock-cells = <0>; 299 + compatible = "ti,mux-clock"; 300 + clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; 301 + ti,bit-shift = <23>; 302 + reg = <0x01ac>; 303 + }; 304 + 305 305 dpll_iva_ck: dpll_iva_ck { 306 306 #clock-cells = <0>; 307 307 compatible = "ti,omap4-dpll-clock"; 308 - clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; 308 + clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; 309 309 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 310 310 }; 311 311 ··· 615 599 }; 616 600 }; 617 601 &cm_core_clocks { 602 + 603 + dpll_per_byp_mux: dpll_per_byp_mux { 604 + #clock-cells = <0>; 605 + compatible = "ti,mux-clock"; 606 + clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; 607 + ti,bit-shift = <23>; 608 + reg = <0x014c>; 609 + }; 610 + 618 611 dpll_per_ck: dpll_per_ck { 619 612 #clock-cells = <0>; 620 613 compatible = "ti,omap4-dpll-clock"; 621 - clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; 614 + clocks = <&sys_clkin>, <&dpll_per_byp_mux>; 622 615 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 623 616 }; 624 617 ··· 739 714 ti,index-starts-at-one; 740 715 }; 741 716 717 + dpll_usb_byp_mux: dpll_usb_byp_mux { 718 + #clock-cells = <0>; 719 + compatible = "ti,mux-clock"; 720 + clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; 721 + ti,bit-shift = <23>; 722 + reg = <0x018c>; 723 + }; 724 + 742 725 dpll_usb_ck: dpll_usb_ck { 743 726 #clock-cells = <0>; 744 727 compatible = "ti,omap4-dpll-j-type-clock"; 745 - clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; 728 + clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; 746 729 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 747 730 }; 748 731
+1 -2
arch/arm/boot/dts/sama5d3.dtsi
··· 1248 1248 atmel,watchdog-type = "hardware"; 1249 1249 atmel,reset-type = "all"; 1250 1250 atmel,dbg-halt; 1251 - atmel,idle-halt; 1252 1251 status = "disabled"; 1253 1252 }; 1254 1253 ··· 1415 1416 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1416 1417 reg = <0x00700000 0x100000>; 1417 1418 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1418 - clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1419 + clocks = <&utmi>, <&uhphs_clk>, <&uhpck>; 1419 1420 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1420 1421 status = "disabled"; 1421 1422 };
+5 -4
arch/arm/boot/dts/sama5d4.dtsi
··· 66 66 gpio4 = &pioE; 67 67 tcb0 = &tcb0; 68 68 tcb1 = &tcb1; 69 + i2c0 = &i2c0; 69 70 i2c2 = &i2c2; 70 71 }; 71 72 cpus { ··· 260 259 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 261 260 reg = <0x00600000 0x100000>; 262 261 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 263 - clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 262 + clocks = <&utmi>, <&uhphs_clk>, <&uhpck>; 264 263 clock-names = "usb_clk", "ehci_clk", "uhpck"; 265 264 status = "disabled"; 266 265 }; ··· 462 461 463 462 lcdck: lcdck { 464 463 #clock-cells = <0>; 465 - reg = <4>; 466 - clocks = <&smd>; 464 + reg = <3>; 465 + clocks = <&mck>; 467 466 }; 468 467 469 468 smdck: smdck { ··· 771 770 reg = <50>; 772 771 }; 773 772 774 - lcd_clk: lcd_clk { 773 + lcdc_clk: lcdc_clk { 775 774 #clock-cells = <0>; 776 775 reg = <51>; 777 776 };
+6
arch/arm/boot/dts/socfpga.dtsi
··· 713 713 reg-shift = <2>; 714 714 reg-io-width = <4>; 715 715 clocks = <&l4_sp_clk>; 716 + dmas = <&pdma 28>, 717 + <&pdma 29>; 718 + dma-names = "tx", "rx"; 716 719 }; 717 720 718 721 uart1: serial1@ffc03000 { ··· 725 722 reg-shift = <2>; 726 723 reg-io-width = <4>; 727 724 clocks = <&l4_sp_clk>; 725 + dmas = <&pdma 30>, 726 + <&pdma 31>; 727 + dma-names = "tx", "rx"; 728 728 }; 729 729 730 730 rst: rstmgr@ffd05000 {
+1
arch/arm/configs/at91_dt_defconfig
··· 70 70 CONFIG_BLK_DEV_SD=y 71 71 # CONFIG_SCSI_LOWLEVEL is not set 72 72 CONFIG_NETDEVICES=y 73 + CONFIG_ARM_AT91_ETHER=y 73 74 CONFIG_MACB=y 74 75 # CONFIG_NET_VENDOR_BROADCOM is not set 75 76 CONFIG_DM9000=y
+1 -1
arch/arm/configs/multi_v7_defconfig
··· 99 99 CONFIG_PCI_RCAR_GEN2_PCIE=y 100 100 CONFIG_PCIEPORTBUS=y 101 101 CONFIG_SMP=y 102 - CONFIG_NR_CPUS=8 102 + CONFIG_NR_CPUS=16 103 103 CONFIG_HIGHPTE=y 104 104 CONFIG_CMA=y 105 105 CONFIG_ARM_APPENDED_DTB=y
+1
arch/arm/configs/omap2plus_defconfig
··· 377 377 CONFIG_PWM_TWL_LED=m 378 378 CONFIG_OMAP_USB2=m 379 379 CONFIG_TI_PIPE3=y 380 + CONFIG_TWL4030_USB=m 380 381 CONFIG_EXT2_FS=y 381 382 CONFIG_EXT3_FS=y 382 383 # CONFIG_EXT3_FS_XATTR is not set
-2
arch/arm/configs/sama5_defconfig
··· 3 3 CONFIG_SYSVIPC=y 4 4 CONFIG_IRQ_DOMAIN_DEBUG=y 5 5 CONFIG_LOG_BUF_SHIFT=14 6 - CONFIG_SYSFS_DEPRECATED=y 7 - CONFIG_SYSFS_DEPRECATED_V2=y 8 6 CONFIG_BLK_DEV_INITRD=y 9 7 CONFIG_EMBEDDED=y 10 8 CONFIG_SLAB=y
+1
arch/arm/configs/sunxi_defconfig
··· 4 4 CONFIG_PERF_EVENTS=y 5 5 CONFIG_ARCH_SUNXI=y 6 6 CONFIG_SMP=y 7 + CONFIG_NR_CPUS=8 7 8 CONFIG_AEABI=y 8 9 CONFIG_HIGHMEM=y 9 10 CONFIG_HIGHPTE=y
+1 -1
arch/arm/configs/vexpress_defconfig
··· 118 118 CONFIG_USB=y 119 119 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 120 120 CONFIG_USB_MON=y 121 - CONFIG_USB_ISP1760_HCD=y 122 121 CONFIG_USB_STORAGE=y 122 + CONFIG_USB_ISP1760=y 123 123 CONFIG_MMC=y 124 124 CONFIG_MMC_ARMMMCI=y 125 125 CONFIG_NEW_LEDS=y
+4 -1
arch/arm/include/debug/at91.S
··· 18 18 #define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */ 19 19 #endif 20 20 21 - /* Keep in sync with mach-at91/include/mach/hardware.h */ 21 + #ifdef CONFIG_MMU 22 22 #define AT91_IO_P2V(x) ((x) - 0x01000000) 23 + #else 24 + #define AT91_IO_P2V(x) (x) 25 + #endif 23 26 24 27 #define AT91_DBGU_SR (0x14) /* Status Register */ 25 28 #define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
+10 -12
arch/arm/mach-at91/pm.c
··· 270 270 phys_addr_t sram_pbase; 271 271 unsigned long sram_base; 272 272 struct device_node *node; 273 - struct platform_device *pdev; 273 + struct platform_device *pdev = NULL; 274 274 275 - node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 276 - if (!node) { 277 - pr_warn("%s: failed to find sram node!\n", __func__); 278 - return; 275 + for_each_compatible_node(node, NULL, "mmio-sram") { 276 + pdev = of_find_device_by_node(node); 277 + if (pdev) { 278 + of_node_put(node); 279 + break; 280 + } 279 281 } 280 282 281 - pdev = of_find_device_by_node(node); 282 283 if (!pdev) { 283 284 pr_warn("%s: failed to find sram device!\n", __func__); 284 - goto put_node; 285 + return; 285 286 } 286 287 287 288 sram_pool = dev_get_gen_pool(&pdev->dev); 288 289 if (!sram_pool) { 289 290 pr_warn("%s: sram pool unavailable!\n", __func__); 290 - goto put_node; 291 + return; 291 292 } 292 293 293 294 sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz); 294 295 if (!sram_base) { 295 296 pr_warn("%s: unable to alloc ocram!\n", __func__); 296 - goto put_node; 297 + return; 297 298 } 298 299 299 300 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 300 301 slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false); 301 - 302 - put_node: 303 - of_node_put(node); 304 302 } 305 303 #endif 306 304
+1 -1
arch/arm/mach-at91/pm.h
··· 44 44 " mcr p15, 0, %0, c7, c0, 4\n\t" 45 45 " str %5, [%1, %2]" 46 46 : 47 - : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR), 47 + : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), 48 48 "r" (1), "r" (AT91RM9200_SDRAMC_SRR), 49 49 "r" (lpr)); 50 50 }
+46 -34
arch/arm/mach-at91/pm_slowclock.S
··· 25 25 */ 26 26 #undef SLOWDOWN_MASTER_CLOCK 27 27 28 - #define MCKRDY_TIMEOUT 1000 29 - #define MOSCRDY_TIMEOUT 1000 30 - #define PLLALOCK_TIMEOUT 1000 31 - #define PLLBLOCK_TIMEOUT 1000 32 - 33 28 pmc .req r0 34 29 sdramc .req r1 35 30 ramc1 .req r2 ··· 36 41 * Wait until master clock is ready (after switching master clock source) 37 42 */ 38 43 .macro wait_mckrdy 39 - mov tmp2, #MCKRDY_TIMEOUT 40 - 1: sub tmp2, tmp2, #1 41 - cmp tmp2, #0 42 - beq 2f 43 - ldr tmp1, [pmc, #AT91_PMC_SR] 44 + 1: ldr tmp1, [pmc, #AT91_PMC_SR] 44 45 tst tmp1, #AT91_PMC_MCKRDY 45 46 beq 1b 46 - 2: 47 47 .endm 48 48 49 49 /* 50 50 * Wait until master oscillator has stabilized. 51 51 */ 52 52 .macro wait_moscrdy 53 - mov tmp2, #MOSCRDY_TIMEOUT 54 - 1: sub tmp2, tmp2, #1 55 - cmp tmp2, #0 56 - beq 2f 57 - ldr tmp1, [pmc, #AT91_PMC_SR] 53 + 1: ldr tmp1, [pmc, #AT91_PMC_SR] 58 54 tst tmp1, #AT91_PMC_MOSCS 59 55 beq 1b 60 - 2: 61 56 .endm 62 57 63 58 /* 64 59 * Wait until PLLA has locked. 65 60 */ 66 61 .macro wait_pllalock 67 - mov tmp2, #PLLALOCK_TIMEOUT 68 - 1: sub tmp2, tmp2, #1 69 - cmp tmp2, #0 70 - beq 2f 71 - ldr tmp1, [pmc, #AT91_PMC_SR] 62 + 1: ldr tmp1, [pmc, #AT91_PMC_SR] 72 63 tst tmp1, #AT91_PMC_LOCKA 73 64 beq 1b 74 - 2: 75 65 .endm 76 66 77 67 /* 78 68 * Wait until PLLB has locked. 79 69 */ 80 70 .macro wait_pllblock 81 - mov tmp2, #PLLBLOCK_TIMEOUT 82 - 1: sub tmp2, tmp2, #1 83 - cmp tmp2, #0 84 - beq 2f 85 - ldr tmp1, [pmc, #AT91_PMC_SR] 71 + 1: ldr tmp1, [pmc, #AT91_PMC_SR] 86 72 tst tmp1, #AT91_PMC_LOCKB 87 73 beq 1b 88 - 2: 89 74 .endm 90 75 91 76 .text 77 + 78 + .arm 92 79 93 80 /* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, 94 81 * void __iomem *ramc1, int memctrl) ··· 111 134 cmp memctrl, #AT91_MEMCTRL_DDRSDR 112 135 bne sdr_sr_enable 113 136 137 + /* LPDDR1 --> force DDR2 mode during self-refresh */ 138 + ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR] 139 + str tmp1, .saved_sam9_mdr 140 + bic tmp1, tmp1, #~AT91_DDRSDRC_MD 141 + cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR 142 + ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR] 143 + biceq tmp1, tmp1, #AT91_DDRSDRC_MD 144 + orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2 145 + streq tmp1, [sdramc, #AT91_DDRSDRC_MDR] 146 + 114 147 /* prepare for DDRAM self-refresh mode */ 115 148 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] 116 149 str tmp1, .saved_sam9_lpr ··· 129 142 130 143 /* figure out if we use the second ram controller */ 131 144 cmp ramc1, #0 132 - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR] 133 - strne tmp2, .saved_sam9_lpr1 134 - bicne tmp2, #AT91_DDRSDRC_LPCB 135 - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH 145 + beq ddr_no_2nd_ctrl 146 + 147 + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR] 148 + str tmp2, .saved_sam9_mdr1 149 + bic tmp2, tmp2, #~AT91_DDRSDRC_MD 150 + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR 151 + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR] 152 + biceq tmp2, tmp2, #AT91_DDRSDRC_MD 153 + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2 154 + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR] 155 + 156 + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR] 157 + str tmp2, .saved_sam9_lpr1 158 + bic tmp2, #AT91_DDRSDRC_LPCB 159 + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH 136 160 137 161 /* Enable DDRAM self-refresh mode */ 162 + str tmp2, [ramc1, #AT91_DDRSDRC_LPR] 163 + ddr_no_2nd_ctrl: 138 164 str tmp1, [sdramc, #AT91_DDRSDRC_LPR] 139 - strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] 140 165 141 166 b sdr_sr_done 142 167 ··· 207 208 /* Turn off the main oscillator */ 208 209 ldr tmp1, [pmc, #AT91_CKGR_MOR] 209 210 bic tmp1, tmp1, #AT91_PMC_MOSCEN 211 + orr tmp1, tmp1, #AT91_PMC_KEY 210 212 str tmp1, [pmc, #AT91_CKGR_MOR] 211 213 212 214 /* Wait for interrupt */ ··· 216 216 /* Turn on the main oscillator */ 217 217 ldr tmp1, [pmc, #AT91_CKGR_MOR] 218 218 orr tmp1, tmp1, #AT91_PMC_MOSCEN 219 + orr tmp1, tmp1, #AT91_PMC_KEY 219 220 str tmp1, [pmc, #AT91_CKGR_MOR] 220 221 221 222 wait_moscrdy ··· 281 280 */ 282 281 cmp memctrl, #AT91_MEMCTRL_DDRSDR 283 282 bne sdr_en_restore 283 + /* Restore MDR in case of LPDDR1 */ 284 + ldr tmp1, .saved_sam9_mdr 285 + str tmp1, [sdramc, #AT91_DDRSDRC_MDR] 284 286 /* Restore LPR on AT91 with DDRAM */ 285 287 ldr tmp1, .saved_sam9_lpr 286 288 str tmp1, [sdramc, #AT91_DDRSDRC_LPR] 287 289 288 290 /* if we use the second ram controller */ 289 291 cmp ramc1, #0 292 + ldrne tmp2, .saved_sam9_mdr1 293 + strne tmp2, [ramc1, #AT91_DDRSDRC_MDR] 290 294 ldrne tmp2, .saved_sam9_lpr1 291 295 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] 292 296 ··· 323 317 .word 0 324 318 325 319 .saved_sam9_lpr1: 320 + .word 0 321 + 322 + .saved_sam9_mdr: 323 + .word 0 324 + 325 + .saved_sam9_mdr1: 326 326 .word 0 327 327 328 328 ENTRY(at91_slow_clock_sz)
+1 -2
arch/arm/mach-exynos/platsmp.c
··· 126 126 */ 127 127 void exynos_cpu_power_down(int cpu) 128 128 { 129 - if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") || 130 - of_machine_is_compatible("samsung,exynos5800"))) { 129 + if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) { 131 130 /* 132 131 * Bypass power down for CPU0 during suspend. Check for 133 132 * the SYS_PWR_REG value to decide if we are suspending
+28
arch/arm/mach-exynos/pm_domains.c
··· 161 161 of_genpd_add_provider_simple(np, &pd->pd); 162 162 } 163 163 164 + /* Assign the child power domains to their parents */ 165 + for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { 166 + struct generic_pm_domain *child_domain, *parent_domain; 167 + struct of_phandle_args args; 168 + 169 + args.np = np; 170 + args.args_count = 0; 171 + child_domain = of_genpd_get_from_provider(&args); 172 + if (!child_domain) 173 + continue; 174 + 175 + if (of_parse_phandle_with_args(np, "power-domains", 176 + "#power-domain-cells", 0, &args) != 0) 177 + continue; 178 + 179 + parent_domain = of_genpd_get_from_provider(&args); 180 + if (!parent_domain) 181 + continue; 182 + 183 + if (pm_genpd_add_subdomain(parent_domain, child_domain)) 184 + pr_warn("%s failed to add subdomain: %s\n", 185 + parent_domain->name, child_domain->name); 186 + else 187 + pr_info("%s has as child subdomain: %s.\n", 188 + parent_domain->name, child_domain->name); 189 + of_node_put(np); 190 + } 191 + 164 192 return 0; 165 193 } 166 194 arch_initcall(exynos4_pm_init_power_domain);
+2 -2
arch/arm/mach-exynos/suspend.c
··· 87 87 static u32 exynos_irqwake_intmask = 0xffffffff; 88 88 89 89 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { 90 - { 73, BIT(1) }, /* RTC alarm */ 91 - { 74, BIT(2) }, /* RTC tick */ 90 + { 105, BIT(1) }, /* RTC alarm */ 91 + { 106, BIT(2) }, /* RTC tick */ 92 92 { /* sentinel */ }, 93 93 }; 94 94
+5 -5
arch/arm/mach-omap2/omap_hwmod.c
··· 1692 1692 if (ret == -EBUSY) 1693 1693 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); 1694 1694 1695 - if (!ret) { 1695 + if (oh->clkdm) { 1696 1696 /* 1697 1697 * Set the clockdomain to HW_AUTO, assuming that the 1698 1698 * previous state was HW_AUTO. 1699 1699 */ 1700 - if (oh->clkdm && hwsup) 1700 + if (hwsup) 1701 1701 clkdm_allow_idle(oh->clkdm); 1702 - } else { 1703 - if (oh->clkdm) 1704 - clkdm_hwmod_disable(oh->clkdm, oh); 1702 + 1703 + clkdm_hwmod_disable(oh->clkdm, oh); 1705 1704 } 1706 1705 1707 1706 return ret; ··· 2697 2698 INIT_LIST_HEAD(&oh->master_ports); 2698 2699 INIT_LIST_HEAD(&oh->slave_ports); 2699 2700 spin_lock_init(&oh->_lock); 2701 + lockdep_set_class(&oh->_lock, &oh->hwmod_key); 2700 2702 2701 2703 oh->_state = _HWMOD_STATE_REGISTERED; 2702 2704
+1
arch/arm/mach-omap2/omap_hwmod.h
··· 674 674 u32 _sysc_cache; 675 675 void __iomem *_mpu_rt_va; 676 676 spinlock_t _lock; 677 + struct lock_class_key hwmod_key; /* unique lock class */ 677 678 struct list_head node; 678 679 struct omap_hwmod_ocp_if *_mpu_port; 679 680 unsigned int (*xlate_irq)(unsigned int);
+24 -79
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
··· 1466 1466 * 1467 1467 */ 1468 1468 1469 - static struct omap_hwmod_class dra7xx_pcie_hwmod_class = { 1469 + static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { 1470 1470 .name = "pcie", 1471 1471 }; 1472 1472 1473 1473 /* pcie1 */ 1474 - static struct omap_hwmod dra7xx_pcie1_hwmod = { 1474 + static struct omap_hwmod dra7xx_pciess1_hwmod = { 1475 1475 .name = "pcie1", 1476 - .class = &dra7xx_pcie_hwmod_class, 1476 + .class = &dra7xx_pciess_hwmod_class, 1477 1477 .clkdm_name = "pcie_clkdm", 1478 - .main_clk = "l4_root_clk_div", 1479 - .prcm = { 1480 - .omap4 = { 1481 - .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET, 1482 - .modulemode = MODULEMODE_SWCTRL, 1483 - }, 1484 - }, 1485 - }; 1486 - 1487 - /* pcie2 */ 1488 - static struct omap_hwmod dra7xx_pcie2_hwmod = { 1489 - .name = "pcie2", 1490 - .class = &dra7xx_pcie_hwmod_class, 1491 - .clkdm_name = "pcie_clkdm", 1492 - .main_clk = "l4_root_clk_div", 1493 - .prcm = { 1494 - .omap4 = { 1495 - .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET, 1496 - .modulemode = MODULEMODE_SWCTRL, 1497 - }, 1498 - }, 1499 - }; 1500 - 1501 - /* 1502 - * 'PCIE PHY' class 1503 - * 1504 - */ 1505 - 1506 - static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = { 1507 - .name = "pcie-phy", 1508 - }; 1509 - 1510 - /* pcie1 phy */ 1511 - static struct omap_hwmod dra7xx_pcie1_phy_hwmod = { 1512 - .name = "pcie1-phy", 1513 - .class = &dra7xx_pcie_phy_hwmod_class, 1514 - .clkdm_name = "l3init_clkdm", 1515 1478 .main_clk = "l4_root_clk_div", 1516 1479 .prcm = { 1517 1480 .omap4 = { ··· 1485 1522 }, 1486 1523 }; 1487 1524 1488 - /* pcie2 phy */ 1489 - static struct omap_hwmod dra7xx_pcie2_phy_hwmod = { 1490 - .name = "pcie2-phy", 1491 - .class = &dra7xx_pcie_phy_hwmod_class, 1492 - .clkdm_name = "l3init_clkdm", 1525 + /* pcie2 */ 1526 + static struct omap_hwmod dra7xx_pciess2_hwmod = { 1527 + .name = "pcie2", 1528 + .class = &dra7xx_pciess_hwmod_class, 1529 + .clkdm_name = "pcie_clkdm", 1493 1530 .main_clk = "l4_root_clk_div", 1494 1531 .prcm = { 1495 1532 .omap4 = { ··· 2840 2877 .user = OCP_USER_MPU | OCP_USER_SDMA, 2841 2878 }; 2842 2879 2843 - /* l3_main_1 -> pcie1 */ 2844 - static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = { 2880 + /* l3_main_1 -> pciess1 */ 2881 + static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = { 2845 2882 .master = &dra7xx_l3_main_1_hwmod, 2846 - .slave = &dra7xx_pcie1_hwmod, 2883 + .slave = &dra7xx_pciess1_hwmod, 2847 2884 .clk = "l3_iclk_div", 2848 2885 .user = OCP_USER_MPU | OCP_USER_SDMA, 2849 2886 }; 2850 2887 2851 - /* l4_cfg -> pcie1 */ 2852 - static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = { 2888 + /* l4_cfg -> pciess1 */ 2889 + static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = { 2853 2890 .master = &dra7xx_l4_cfg_hwmod, 2854 - .slave = &dra7xx_pcie1_hwmod, 2891 + .slave = &dra7xx_pciess1_hwmod, 2855 2892 .clk = "l4_root_clk_div", 2856 2893 .user = OCP_USER_MPU | OCP_USER_SDMA, 2857 2894 }; 2858 2895 2859 - /* l3_main_1 -> pcie2 */ 2860 - static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = { 2896 + /* l3_main_1 -> pciess2 */ 2897 + static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = { 2861 2898 .master = &dra7xx_l3_main_1_hwmod, 2862 - .slave = &dra7xx_pcie2_hwmod, 2899 + .slave = &dra7xx_pciess2_hwmod, 2863 2900 .clk = "l3_iclk_div", 2864 2901 .user = OCP_USER_MPU | OCP_USER_SDMA, 2865 2902 }; 2866 2903 2867 - /* l4_cfg -> pcie2 */ 2868 - static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = { 2904 + /* l4_cfg -> pciess2 */ 2905 + static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = { 2869 2906 .master = &dra7xx_l4_cfg_hwmod, 2870 - .slave = &dra7xx_pcie2_hwmod, 2871 - .clk = "l4_root_clk_div", 2872 - .user = OCP_USER_MPU | OCP_USER_SDMA, 2873 - }; 2874 - 2875 - /* l4_cfg -> pcie1 phy */ 2876 - static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = { 2877 - .master = &dra7xx_l4_cfg_hwmod, 2878 - .slave = &dra7xx_pcie1_phy_hwmod, 2879 - .clk = "l4_root_clk_div", 2880 - .user = OCP_USER_MPU | OCP_USER_SDMA, 2881 - }; 2882 - 2883 - /* l4_cfg -> pcie2 phy */ 2884 - static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = { 2885 - .master = &dra7xx_l4_cfg_hwmod, 2886 - .slave = &dra7xx_pcie2_phy_hwmod, 2907 + .slave = &dra7xx_pciess2_hwmod, 2887 2908 .clk = "l4_root_clk_div", 2888 2909 .user = OCP_USER_MPU | OCP_USER_SDMA, 2889 2910 }; ··· 3274 3327 &dra7xx_l4_cfg__mpu, 3275 3328 &dra7xx_l4_cfg__ocp2scp1, 3276 3329 &dra7xx_l4_cfg__ocp2scp3, 3277 - &dra7xx_l3_main_1__pcie1, 3278 - &dra7xx_l4_cfg__pcie1, 3279 - &dra7xx_l3_main_1__pcie2, 3280 - &dra7xx_l4_cfg__pcie2, 3281 - &dra7xx_l4_cfg__pcie1_phy, 3282 - &dra7xx_l4_cfg__pcie2_phy, 3330 + &dra7xx_l3_main_1__pciess1, 3331 + &dra7xx_l4_cfg__pciess1, 3332 + &dra7xx_l3_main_1__pciess2, 3333 + &dra7xx_l4_cfg__pciess2, 3283 3334 &dra7xx_l3_main_1__qspi, 3284 3335 &dra7xx_l4_per3__rtcss, 3285 3336 &dra7xx_l4_cfg__sata,
+1
arch/arm/mach-omap2/pdata-quirks.c
··· 173 173 174 174 static void __init omap3_evm_legacy_init(void) 175 175 { 176 + hsmmc2_internal_input_clk(); 176 177 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149); 177 178 } 178 179
+2 -2
arch/arm/mach-omap2/prm44xx.c
··· 252 252 { 253 253 saved_mask[0] = 254 254 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 255 - OMAP4_PRM_IRQSTATUS_MPU_OFFSET); 255 + OMAP4_PRM_IRQENABLE_MPU_OFFSET); 256 256 saved_mask[1] = 257 257 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 258 - OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); 258 + OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); 259 259 260 260 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, 261 261 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
+1 -1
arch/arm/mach-socfpga/core.h
··· 45 45 46 46 extern unsigned long socfpga_cpu1start_addr; 47 47 48 - #define SOCFPGA_SCU_VIRT_BASE 0xfffec000 48 + #define SOCFPGA_SCU_VIRT_BASE 0xfee00000 49 49 50 50 #endif
+5
arch/arm/mach-socfpga/socfpga.c
··· 23 23 #include <asm/hardware/cache-l2x0.h> 24 24 #include <asm/mach/arch.h> 25 25 #include <asm/mach/map.h> 26 + #include <asm/cacheflush.h> 26 27 27 28 #include "core.h" 28 29 ··· 73 72 if (of_property_read_u32(np, "cpu1-start-addr", 74 73 (u32 *) &socfpga_cpu1start_addr)) 75 74 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); 75 + 76 + /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */ 77 + smp_wmb(); 78 + sync_cache_w(&socfpga_cpu1start_addr); 76 79 77 80 sys_manager_base_addr = of_iomap(np, 0); 78 81
+1
arch/arm/mach-sti/board-dt.c
··· 18 18 "st,stih415", 19 19 "st,stih416", 20 20 "st,stih407", 21 + "st,stih410", 21 22 "st,stih418", 22 23 NULL 23 24 };
+2 -1
include/dt-bindings/pinctrl/am33xx.h
··· 13 13 14 14 #define PULL_DISABLE (1 << 3) 15 15 #define INPUT_EN (1 << 5) 16 - #define SLEWCTRL_FAST (1 << 6) 16 + #define SLEWCTRL_SLOW (1 << 6) 17 + #define SLEWCTRL_FAST 0 17 18 18 19 /* update macro depending on INPUT_EN and PULL_ENA */ 19 20 #undef PIN_OUTPUT
+2 -1
include/dt-bindings/pinctrl/am43xx.h
··· 18 18 #define PULL_DISABLE (1 << 16) 19 19 #define PULL_UP (1 << 17) 20 20 #define INPUT_EN (1 << 18) 21 - #define SLEWCTRL_FAST (1 << 19) 21 + #define SLEWCTRL_SLOW (1 << 19) 22 + #define SLEWCTRL_FAST 0 22 23 #define DS0_PULL_UP_DOWN_EN (1 << 27) 23 24 24 25 #define PIN_OUTPUT (PULL_DISABLE)
+1 -1
include/soc/at91/at91sam9_ddrsdr.h
··· 92 92 #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 93 93 94 94 #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 95 - #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 95 + #define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */ 96 96 #define AT91_DDRSDRC_MD_SDR 0 97 97 #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 98 98 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3