tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk driver fixes from Stephen Boyd:
"Clk driver fixes for critical issues found in the past few weeks:

- Select gdsc config so qcom sm6350 driver probes

- Fix a register offset in qcom gcc-sm6115 so the correct clk is
controlled

- Fix inverted logic in Renesas RZ/G2L .is_enabled()

- Mark some more clks critical in Renesas clk driver

- Remove a duplicate clk in the agilex driver"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: add select QCOM_GDSC for SM6350
clk: qcom: gcc-sm6115: Fix offset for hlos1_vote_turing_mmu_tbu0_gdsc
clk: socfpga: agilex: fix duplicate s2f_user0_clk
clk: renesas: rzg2l: Fix clk status function
clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical

Linus Torvalds 6985c40a dcd61984

+5 -11
+1
drivers/clk/qcom/Kconfig
··· 564 564 565 565 config SM_GCC_6350 566 566 tristate "SM6350 Global Clock Controller" 567 + select QCOM_GDSC 567 568 help 568 569 Support for the global clock controller on SM6350 devices. 569 570 Say Y if you want to use peripheral devices such as UART,
+1 -1
drivers/clk/qcom/gcc-sm6115.c
··· 3242 3242 }; 3243 3243 3244 3244 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3245 - .gdscr = 0x7d060, 3245 + .gdscr = 0x7d07c, 3246 3246 .pd = { 3247 3247 .name = "hlos1_vote_turing_mmu_tbu0", 3248 3248 },
+2
drivers/clk/renesas/r9a07g044-cpg.c
··· 186 186 187 187 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 188 188 MOD_CLK_BASE + R9A07G044_GIC600_GICCLK, 189 + MOD_CLK_BASE + R9A07G044_IA55_CLK, 190 + MOD_CLK_BASE + R9A07G044_DMAC_ACLK, 189 191 }; 190 192 191 193 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
+1 -1
drivers/clk/renesas/rzg2l-cpg.c
··· 391 391 392 392 value = readl(priv->base + CLK_MON_R(clock->off)); 393 393 394 - return !(value & bitmask); 394 + return value & bitmask; 395 395 } 396 396 397 397 static const struct clk_ops rzg2l_mod_clock_ops = {
-9
drivers/clk/socfpga/clk-agilex.c
··· 165 165 .name = "boot_clk", }, 166 166 }; 167 167 168 - static const struct clk_parent_data s2f_usr0_mux[] = { 169 - { .fw_name = "f2s-free-clk", 170 - .name = "f2s-free-clk", }, 171 - { .fw_name = "boot_clk", 172 - .name = "boot_clk", }, 173 - }; 174 - 175 168 static const struct clk_parent_data emac_mux[] = { 176 169 { .fw_name = "emaca_free_clk", 177 170 .name = "emaca_free_clk", }, ··· 305 312 4, 0x44, 28, 1, 0, 0, 0}, 306 313 { AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, 307 314 5, 0, 0, 0, 0x30, 1, 0}, 308 - { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24, 309 - 6, 0, 0, 0, 0, 0, 0}, 310 315 { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C, 311 316 0, 0, 0, 0, 0x94, 26, 0}, 312 317 { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,