Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-fixes', 'clk-renesas', 'clk-rpi', 'clk-eswin' and 'clk-mediatek' into clk-next
- ESWIN eic700 SoC clk support
- Econet EN751221 SoC clock/reset support
* clk-fixes:
clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()
clk: microchip: mpfs-ccc: fix out of bounds access during output registration
clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source
* clk-renesas:
clk: renesas: Add support for RZ/G3L SoC
dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
clk: renesas: rzg2l: Re-enable critical module clocks during resume
clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()
clk: renesas: rzg2l: Add helper for mod clock enable/disable
clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries
clk: renesas: rzg2l: Add support for critical resets
clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}
clk: renesas: r9a06g032: Enable watchdog reset sources
clk: renesas: cpg-mssr: Use struct_size() helper
clk: renesas: r9a09g047: Add PCIe clocks and reset
clk: renesas: r9a09g057: Add PCIe clocks and reset
clk: renesas: r9a09g056: Add PCIe clocks and reset
clk: renesas: r9a09g047: Add entries for the RSPIs
clk: renesas: r9a09g056: Add clock and reset entries for RTC
clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}
clk: renesas: r9a09g056: Fix ordering of module clocks array
clk: renesas: r9a09g057: Fix ordering of module clocks array
* clk-rpi:
clk: bcm: rpi: Manage clock rate in prepare/unprepare callbacks
* clk-eswin:
MAINTAINERS: Add entry for ESWIN EIC7700 clock driver
clk: eswin: Add eic7700 clock driver
clk: divider: Add devm_clk_hw_register_divider_parent_data
dt-bindings: clock: eswin: Documentation for eic7700 SoC
* clk-mediatek:
clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
dt-bindings: clock, reset: Add econet EN751221
+3751
-104
+5
-1
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
+5
-1
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
···
32
32
- enum:
33
33
- airoha,en7523-scu
34
34
- airoha,en7581-scu
35
+
- econet,en751221-scu
35
36
36
37
reg:
37
38
items:
···
68
67
- if:
69
68
properties:
70
69
compatible:
71
-
const: airoha,en7581-scu
70
+
enum:
71
+
- airoha,en7581-scu
72
+
- econet,en751221-scu
72
73
then:
73
74
properties:
74
75
reg:
···
101
98
#reset-cells = <1>;
102
99
};
103
100
};
101
+
+46
Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
+46
Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Eswin EIC7700 SoC clock controller
8
+
9
+
maintainers:
10
+
- Yifeng Huang <huangyifeng@eswincomputing.com>
11
+
- Xuyang Dong <dongxuyang@eswincomputing.com>
12
+
13
+
description:
14
+
The clock controller generates and supplies clock to all the modules
15
+
for eic7700 SoC.
16
+
17
+
properties:
18
+
compatible:
19
+
const: eswin,eic7700-clock
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
items:
26
+
- description: External 24MHz oscillator clock
27
+
28
+
'#clock-cells':
29
+
const: 1
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
- clocks
35
+
- '#clock-cells'
36
+
37
+
additionalProperties: false
38
+
39
+
examples:
40
+
- |
41
+
clock-controller@51828000 {
42
+
compatible = "eswin,eic7700-clock";
43
+
reg = <0x51828000 0x300>;
44
+
clocks = <&xtal24m>;
45
+
#clock-cells = <1>;
46
+
};
+35
-5
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+35
-5
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
···
28
28
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
29
29
- renesas,r9a07g054-cpg # RZ/V2L
30
30
- renesas,r9a08g045-cpg # RZ/G3S
31
+
- renesas,r9a08g046-cpg # RZ/G3L
31
32
- renesas,r9a09g011-cpg # RZ/V2M
32
33
33
34
reg:
34
35
maxItems: 1
35
36
36
37
clocks:
37
-
maxItems: 1
38
+
minItems: 1
39
+
items:
40
+
- description: Clock source to CPG can be either from external clock
41
+
input (EXCLK) or crystal oscillator (XIN/XOUT).
42
+
- description: ETH0 TXC clock input
43
+
- description: ETH0 RXC clock input
44
+
- description: ETH1 TXC clock input
45
+
- description: ETH1 RXC clock input
38
46
39
47
clock-names:
40
-
description:
41
-
Clock source to CPG can be either from external clock input (EXCLK) or
42
-
crystal oscillator (XIN/XOUT).
43
-
const: extal
48
+
minItems: 1
49
+
items:
50
+
- const: extal
51
+
- const: eth0_txc_tx_clk
52
+
- const: eth0_rxc_rx_clk
53
+
- const: eth1_txc_tx_clk
54
+
- const: eth1_rxc_rx_clk
44
55
45
56
'#clock-cells':
46
57
description: |
···
84
73
- '#clock-cells'
85
74
- '#power-domain-cells'
86
75
- '#reset-cells'
76
+
77
+
allOf:
78
+
- if:
79
+
properties:
80
+
compatible:
81
+
contains:
82
+
const: renesas,r9a08g046-cpg
83
+
then:
84
+
properties:
85
+
clocks:
86
+
minItems: 5
87
+
clock-names:
88
+
minItems: 5
89
+
else:
90
+
properties:
91
+
clocks:
92
+
maxItems: 1
93
+
clock-names:
94
+
maxItems: 1
87
95
88
96
additionalProperties: false
89
97
+2
Documentation/devicetree/bindings/mfd/syscon.yaml
+2
Documentation/devicetree/bindings/mfd/syscon.yaml
···
61
61
- cirrus,ep7209-syscon2
62
62
- cirrus,ep7209-syscon3
63
63
- cnxt,cx92755-uc
64
+
- econet,en751221-chip-scu
64
65
- freecom,fsg-cs2-system-controller
65
66
- fsl,imx93-aonmix-ns-syscfg
66
67
- fsl,imx93-wakeupmix-syscfg
···
174
173
- cirrus,ep7209-syscon2
175
174
- cirrus,ep7209-syscon3
176
175
- cnxt,cx92755-uc
176
+
- econet,en751221-chip-scu
177
177
- freecom,fsg-cs2-system-controller
178
178
- fsl,imx93-aonmix-ns-syscfg
179
179
- fsl,imx93-wakeupmix-syscfg
+10
MAINTAINERS
+10
MAINTAINERS
···
9096
9096
F: arch/mips/econet/
9097
9097
F: drivers/clocksource/timer-econet-en751221.c
9098
9098
F: drivers/irqchip/irq-econet-en751221.c
9099
+
F: include/dt-bindings/clock/econet,en751221-scu.h
9100
+
F: include/dt-bindings/reset/econet,en751221-scu.h
9099
9101
9100
9102
ECRYPT FILE SYSTEM
9101
9103
M: Tyler Hicks <code@tyhicks.com>
···
9496
9494
T: git https://github.com/eswincomputing/linux-next.git
9497
9495
F: Documentation/devicetree/bindings/riscv/eswin.yaml
9498
9496
F: arch/riscv/boot/dts/eswin/
9497
+
9498
+
ESWIN EIC7700 CLOCK DRIVER
9499
+
M: Yifeng Huang <huangyifeng@eswincomputing.com>
9500
+
M: Xuyang Dong <dongxuyang@eswincomputing.com>
9501
+
S: Maintained
9502
+
F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
9503
+
F: drivers/clk/eswin/
9504
+
F: include/dt-bindings/clock/eswin,eic7700-clock.h
9499
9505
9500
9506
ET131X NETWORK DRIVER
9501
9507
M: Mark Einon <mark.einon@gmail.com>
+4
-3
drivers/clk/Kconfig
+4
-3
drivers/clk/Kconfig
···
218
218
If you say yes here you get support for the CS2000 clock multiplier.
219
219
220
220
config COMMON_CLK_EN7523
221
-
bool "Clock driver for Airoha EN7523 SoC system clocks"
221
+
bool "Clock driver for Airoha/EcoNet SoC system clocks"
222
222
depends on OF
223
-
depends on ARCH_AIROHA || COMPILE_TEST
223
+
depends on ARCH_AIROHA || ECONET || COMPILE_TEST
224
224
default ARCH_AIROHA
225
225
help
226
226
This driver provides the fixed clocks and gates present on Airoha
227
-
ARM silicon.
227
+
and EcoNet silicon.
228
228
229
229
config COMMON_CLK_EP93XX
230
230
tristate "Clock driver for Cirrus Logic ep93xx SoC"
···
504
504
source "drivers/clk/aspeed/Kconfig"
505
505
source "drivers/clk/baikal-t1/Kconfig"
506
506
source "drivers/clk/bcm/Kconfig"
507
+
source "drivers/clk/eswin/Kconfig"
507
508
source "drivers/clk/hisilicon/Kconfig"
508
509
source "drivers/clk/imgtec/Kconfig"
509
510
source "drivers/clk/imx/Kconfig"
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
+34
-4
drivers/clk/bcm/clk-raspberrypi.c
+34
-4
drivers/clk/bcm/clk-raspberrypi.c
···
289
289
static int raspberrypi_fw_prepare(struct clk_hw *hw)
290
290
{
291
291
const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
292
+
struct raspberrypi_clk_variant *variant = data->variant;
292
293
struct raspberrypi_clk *rpi = data->rpi;
293
294
u32 state = RPI_FIRMWARE_STATE_ENABLE_BIT;
294
295
int ret;
295
296
296
297
ret = raspberrypi_clock_property(rpi->firmware, data,
297
298
RPI_FIRMWARE_SET_CLOCK_STATE, &state);
298
-
if (ret)
299
+
if (ret) {
299
300
dev_err_ratelimited(rpi->dev,
300
301
"Failed to set clock %s state to on: %d\n",
301
302
clk_hw_get_name(hw), ret);
303
+
return ret;
304
+
}
305
+
306
+
/*
307
+
* For clocks marked with 'maximize', restore the rate to the
308
+
* maximum after enabling. This compensates for the rate being
309
+
* set to minimum during unprepare (see raspberrypi_fw_unprepare).
310
+
*/
311
+
if (variant->maximize) {
312
+
unsigned long min_rate, max_rate;
313
+
314
+
clk_hw_get_rate_range(hw, &min_rate, &max_rate);
315
+
ret = raspberrypi_fw_set_rate(hw, max_rate, 0);
316
+
}
302
317
303
318
return ret;
304
319
}
···
322
307
{
323
308
const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
324
309
struct raspberrypi_clk *rpi = data->rpi;
310
+
unsigned long min_rate, max_rate;
325
311
u32 state = 0;
326
312
int ret;
313
+
314
+
clk_hw_get_rate_range(hw, &min_rate, &max_rate);
315
+
316
+
/*
317
+
* Setting the rate in unprepare is a deviation from the usual CCF
318
+
* behavior, where unprepare only gates the clock. However, this is
319
+
* needed, as RPI_FIRMWARE_SET_CLOCK_STATE doesn't actually power off
320
+
* the clock on current firmware versions. Setting the rate to minimum
321
+
* before disabling the clock is the only way to achieve meaningful
322
+
* power savings.
323
+
*
324
+
* This is safe because no consumer should rely on the rate of an
325
+
* unprepared clock. Any consumer must call clk_prepare() before use,
326
+
* at which point the rate is either restored to maximum (for clocks
327
+
* with the 'maximize' flag) or re-established by the consumer.
328
+
*/
329
+
raspberrypi_fw_set_rate(hw, min_rate, 0);
327
330
328
331
ret = raspberrypi_clock_property(rpi->firmware, data,
329
332
RPI_FIRMWARE_SET_CLOCK_STATE, &state);
···
419
386
return ERR_PTR(ret);
420
387
}
421
388
}
422
-
423
-
if (variant->maximize)
424
-
variant->min_rate = max_rate;
425
389
426
390
if (variant->min_rate) {
427
391
unsigned long rate;
+218
-5
drivers/clk/clk-en7523.c
+218
-5
drivers/clk/clk-en7523.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
3
+
#include <linux/bitfield.h>
3
4
#include <linux/delay.h>
4
5
#include <linux/clk-provider.h>
5
6
#include <linux/io.h>
···
12
11
#include <dt-bindings/clock/en7523-clk.h>
13
12
#include <dt-bindings/reset/airoha,en7523-reset.h>
14
13
#include <dt-bindings/reset/airoha,en7581-reset.h>
14
+
#include <dt-bindings/clock/econet,en751221-scu.h>
15
+
#include <dt-bindings/reset/econet,en751221-scu.h>
15
16
16
17
#define RST_NR_PER_BANK 32
17
18
···
36
33
#define REG_RESET_CONTROL_PCIEHB BIT(29)
37
34
#define REG_RESET_CONTROL_PCIE1 BIT(27)
38
35
#define REG_RESET_CONTROL_PCIE2 BIT(26)
36
+
#define REG_HIR 0x064
37
+
#define REG_HIR_MASK GENMASK(31, 16)
39
38
/* EN7581 */
40
39
#define REG_NP_SCU_PCIC 0x88
41
40
#define REG_NP_SCU_SSTR 0x9c
42
41
#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
43
42
#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
44
43
#define REG_CRYPTO_CLKSRC2 0x20c
44
+
/* EN751221 */
45
+
#define EN751221_REG_SPI_DIV 0x0cc
46
+
#define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8)
47
+
#define EN751221_SPI_BASE 500000000
48
+
#define EN751221_SPI_BASE_EN7526C 400000000
49
+
#define EN751221_SPI_DIV_DEFAULT 40
50
+
#define EN751221_REG_BUS 0x284
51
+
#define EN751221_REG_BUS_MASK GENMASK(21, 12)
52
+
#define EN751221_REG_SSR3 0x094
53
+
#define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8)
45
54
46
55
#define REG_RST_CTRL2 0x830
47
56
#define REG_RST_CTRL1 0x834
57
+
#define EN751221_REG_RST_DMT 0x84
58
+
#define EN751221_REG_RST_USB 0xec
59
+
60
+
#define EN751221_MAX_CLKS 5
61
+
62
+
enum en_hir {
63
+
HIR_UNKNOWN = -1,
64
+
HIR_TC3169 = 0,
65
+
HIR_TC3182 = 1,
66
+
HIR_RT65168 = 2,
67
+
HIR_RT63165 = 3,
68
+
HIR_RT63365 = 4,
69
+
HIR_MT751020 = 5,
70
+
HIR_MT7505 = 6,
71
+
HIR_EN751221 = 7,
72
+
HIR_EN7526C = 8,
73
+
HIR_EN751627 = 9,
74
+
HIR_EN7580 = 10,
75
+
HIR_EN7528 = 11,
76
+
HIR_EN7523 = 12,
77
+
HIR_EN7581 = 13,
78
+
HIR_MAX = 14,
79
+
};
48
80
49
81
struct en_clk_desc {
50
82
int id;
···
131
93
static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
132
94
static const u32 crypto_base[] = { 540000000, 480000000 };
133
95
static const u32 emmc7581_base[] = { 200000000, 150000000 };
96
+
/* EN751221 */
97
+
static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
134
98
135
99
static const struct en_clk_desc en7523_base_clks[] = {
136
100
{
···
340
300
REG_RST_CTRL1,
341
301
};
342
302
303
+
static const u16 en751221_rst_ofs[] = {
304
+
REG_RST_CTRL2,
305
+
REG_RST_CTRL1,
306
+
EN751221_REG_RST_DMT,
307
+
EN751221_REG_RST_USB,
308
+
};
309
+
343
310
static const u16 en7523_rst_map[] = {
344
311
/* RST_CTRL2 */
345
312
[EN7523_XPON_PHY_RST] = 0,
···
452
405
[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
453
406
};
454
407
408
+
static const u16 en751221_rst_map[] = {
409
+
/* RST_CTRL2 */
410
+
[EN751221_XPON_PHY_RST] = 0,
411
+
[EN751221_GFAST_RST] = 1,
412
+
[EN751221_CPU_TIMER2_RST] = 2,
413
+
[EN751221_UART3_RST] = 3,
414
+
[EN751221_UART4_RST] = 4,
415
+
[EN751221_UART5_RST] = 5,
416
+
[EN751221_I2C2_RST] = 6,
417
+
[EN751221_XSI_MAC_RST] = 7,
418
+
[EN751221_XSI_PHY_RST] = 8,
419
+
420
+
/* RST_CTRL1 */
421
+
[EN751221_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
422
+
[EN751221_FE_QDMA1_RST] = RST_NR_PER_BANK + 1,
423
+
[EN751221_FE_QDMA2_RST] = RST_NR_PER_BANK + 2,
424
+
[EN751221_FE_UNZIP_RST] = RST_NR_PER_BANK + 3,
425
+
[EN751221_PCM2_RST] = RST_NR_PER_BANK + 4,
426
+
[EN751221_PTM_MAC_RST] = RST_NR_PER_BANK + 5,
427
+
[EN751221_CRYPTO_RST] = RST_NR_PER_BANK + 6,
428
+
[EN751221_SAR_RST] = RST_NR_PER_BANK + 7,
429
+
[EN751221_TIMER_RST] = RST_NR_PER_BANK + 8,
430
+
[EN751221_INTC_RST] = RST_NR_PER_BANK + 9,
431
+
[EN751221_BONDING_RST] = RST_NR_PER_BANK + 10,
432
+
[EN751221_PCM1_RST] = RST_NR_PER_BANK + 11,
433
+
[EN751221_UART_RST] = RST_NR_PER_BANK + 12,
434
+
[EN751221_GPIO_RST] = RST_NR_PER_BANK + 13,
435
+
[EN751221_GDMA_RST] = RST_NR_PER_BANK + 14,
436
+
[EN751221_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
437
+
[EN751221_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
438
+
[EN751221_SFC_RST] = RST_NR_PER_BANK + 18,
439
+
[EN751221_UART2_RST] = RST_NR_PER_BANK + 19,
440
+
[EN751221_GDMP_RST] = RST_NR_PER_BANK + 20,
441
+
[EN751221_FE_RST] = RST_NR_PER_BANK + 21,
442
+
[EN751221_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
443
+
[EN751221_GSW_RST] = RST_NR_PER_BANK + 23,
444
+
[EN751221_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
445
+
[EN751221_PCIE0_RST] = RST_NR_PER_BANK + 26,
446
+
[EN751221_PCIE1_RST] = RST_NR_PER_BANK + 27,
447
+
[EN751221_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
448
+
[EN751221_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
449
+
[EN751221_SIMIF_RST] = RST_NR_PER_BANK + 30,
450
+
[EN751221_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
451
+
452
+
/* RST_DMT */
453
+
[EN751221_DMT_RST] = 2 * RST_NR_PER_BANK + 0,
454
+
455
+
/* RST_USB */
456
+
[EN751221_USB_PHY_P0_RST] = 3 * RST_NR_PER_BANK + 6,
457
+
[EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7,
458
+
};
459
+
455
460
static int en7581_reset_register(struct device *dev, void __iomem *base,
456
-
const u16 *rst_map, int nr_resets);
461
+
const u16 *rst_map, int nr_resets,
462
+
const u16 *rst_reg_ofs);
457
463
458
464
static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val)
459
465
{
···
704
604
en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
705
605
706
606
return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map,
707
-
ARRAY_SIZE(en7523_rst_map));
607
+
ARRAY_SIZE(en7523_rst_map),
608
+
en7581_rst_ofs);
708
609
}
709
610
710
611
static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
···
806
705
};
807
706
808
707
static int en7581_reset_register(struct device *dev, void __iomem *base,
809
-
const u16 *rst_map, int nr_resets)
708
+
const u16 *rst_map, int nr_resets,
709
+
const u16 *rst_reg_ofs)
810
710
{
811
711
struct en_rst_data *rst_data;
812
712
···
815
713
if (!rst_data)
816
714
return -ENOMEM;
817
715
818
-
rst_data->bank_ofs = en7581_rst_ofs;
716
+
rst_data->bank_ofs = rst_reg_ofs;
819
717
rst_data->idx_map = rst_map;
820
718
rst_data->base = base;
821
719
···
854
752
writel(val | 3, base + REG_NP_SCU_PCIC);
855
753
856
754
return en7581_reset_register(&pdev->dev, base, en7581_rst_map,
857
-
ARRAY_SIZE(en7581_rst_map));
755
+
ARRAY_SIZE(en7581_rst_map),
756
+
en7581_rst_ofs);
757
+
}
758
+
759
+
static enum en_hir get_hw_id(void __iomem *np_base)
760
+
{
761
+
u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));
762
+
763
+
if (val < HIR_MAX)
764
+
return (enum en_hir)val;
765
+
766
+
pr_warn("Unable to determine EcoNet SoC\n");
767
+
768
+
return HIR_UNKNOWN;
769
+
}
770
+
771
+
static void en751221_try_register_clk(struct device *dev, int key,
772
+
struct clk_hw_onecell_data *clk_data,
773
+
const char *name, u32 rate)
774
+
{
775
+
struct clk_hw *hw;
776
+
777
+
if (WARN_ON_ONCE(key >= EN751221_MAX_CLKS))
778
+
return;
779
+
780
+
hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
781
+
if (IS_ERR(hw))
782
+
pr_err("Failed to register clk %s: %pe\n", name, hw);
783
+
else
784
+
clk_data->hws[key] = hw;
785
+
}
786
+
787
+
static void en751221_register_clocks(struct device *dev,
788
+
struct clk_hw_onecell_data *clk_data,
789
+
struct regmap *map, void __iomem *np_base)
790
+
{
791
+
enum en_hir hid = get_hw_id(np_base);
792
+
struct clk_hw *hw;
793
+
u32 rate;
794
+
u32 div;
795
+
int err;
796
+
797
+
/* PCI */
798
+
hw = en7523_register_pcie_clk(dev, np_base);
799
+
clk_data->hws[EN751221_CLK_PCIE] = hw;
800
+
801
+
/* SPI */
802
+
rate = EN751221_SPI_BASE;
803
+
if (hid == HIR_EN7526C)
804
+
rate = EN751221_SPI_BASE_EN7526C;
805
+
806
+
err = regmap_read(map, EN751221_REG_SPI_DIV, &div);
807
+
if (err) {
808
+
pr_err("Failed reading fixed clk div %s: %d\n",
809
+
"spi", err);
810
+
} else {
811
+
div = FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2;
812
+
if (!div)
813
+
div = EN751221_SPI_DIV_DEFAULT;
814
+
815
+
en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data,
816
+
"spi", rate / div);
817
+
}
818
+
819
+
/* BUS */
820
+
rate = FIELD_GET(EN751221_REG_BUS_MASK,
821
+
readl(np_base + EN751221_REG_BUS));
822
+
rate *= 1000000;
823
+
en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus",
824
+
rate);
825
+
826
+
/* CPU */
827
+
en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu",
828
+
rate * 4);
829
+
830
+
/* GSW */
831
+
rate = FIELD_GET(EN751221_REG_SSR3_GSW_MASK,
832
+
readl(np_base + EN751221_REG_SSR3));
833
+
en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw",
834
+
gsw751221_base[rate]);
835
+
}
836
+
837
+
static int en751221_clk_hw_init(struct platform_device *pdev,
838
+
struct clk_hw_onecell_data *clk_data)
839
+
{
840
+
struct regmap *map;
841
+
void __iomem *base;
842
+
843
+
map = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu");
844
+
if (IS_ERR(map))
845
+
return PTR_ERR(map);
846
+
847
+
base = devm_platform_ioremap_resource(pdev, 0);
848
+
if (IS_ERR(base))
849
+
return PTR_ERR(base);
850
+
851
+
en751221_register_clocks(&pdev->dev, clk_data, map, base);
852
+
853
+
return en7581_reset_register(&pdev->dev, base, en751221_rst_map,
854
+
ARRAY_SIZE(en751221_rst_map),
855
+
en751221_rst_ofs);
858
856
}
859
857
860
858
static int en7523_clk_probe(struct platform_device *pdev)
···
1001
799
.hw_init = en7581_clk_hw_init,
1002
800
};
1003
801
802
+
static const struct en_clk_soc_data en751221_data = {
803
+
.num_clocks = EN751221_MAX_CLKS,
804
+
.pcie_ops = {
805
+
.is_enabled = en7523_pci_is_enabled,
806
+
.prepare = en7523_pci_prepare,
807
+
.unprepare = en7523_pci_unprepare,
808
+
},
809
+
.hw_init = en751221_clk_hw_init,
810
+
};
811
+
1004
812
static const struct of_device_id of_match_clk_en7523[] = {
1005
813
{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
1006
814
{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
815
+
{ .compatible = "econet,en751221-scu", .data = &en751221_data },
1007
816
{ /* sentinel */ }
1008
817
};
1009
818
+15
drivers/clk/eswin/Kconfig
+15
drivers/clk/eswin/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
3
+
config COMMON_CLK_ESWIN
4
+
bool
5
+
6
+
config COMMON_CLK_EIC7700
7
+
tristate "EIC7700 Clock Driver"
8
+
depends on ARCH_ESWIN || COMPILE_TEST
9
+
select COMMON_CLK_ESWIN
10
+
default ARCH_ESWIN
11
+
help
12
+
This driver provides support for clock controller on ESWIN EIC7700
13
+
SoC. The clock controller generates and supplies clocks to various
14
+
peripherals within the SoC.
15
+
Say yes here to support the clock controller on the EIC7700 SoC.
+8
drivers/clk/eswin/Makefile
+8
drivers/clk/eswin/Makefile
+1376
drivers/clk/eswin/clk-eic7700.c
+1376
drivers/clk/eswin/clk-eic7700.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
4
+
* All rights reserved.
5
+
*
6
+
* ESWIN EIC7700 Clk Provider Driver
7
+
*
8
+
* Authors:
9
+
* Yifeng Huang <huangyifeng@eswincomputing.com>
10
+
* Xuyang Dong <dongxuyang@eswincomputing.com>
11
+
*/
12
+
13
+
#include <linux/clk.h>
14
+
#include <linux/clk-provider.h>
15
+
#include <linux/platform_device.h>
16
+
17
+
#include <dt-bindings/clock/eswin,eic7700-clock.h>
18
+
19
+
#include "common.h"
20
+
21
+
/* REG OFFSET OF SYS-CRG */
22
+
#define EIC7700_REG_OFFSET_SPLL0_CFG_0 0x0
23
+
#define EIC7700_REG_OFFSET_SPLL0_CFG_1 0x4
24
+
#define EIC7700_REG_OFFSET_SPLL0_CFG_2 0x8
25
+
#define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL 0xC
26
+
#define EIC7700_REG_OFFSET_SPLL0_SSC 0x10
27
+
#define EIC7700_REG_OFFSET_SPLL1_CFG_0 0x14
28
+
#define EIC7700_REG_OFFSET_SPLL1_CFG_1 0x18
29
+
#define EIC7700_REG_OFFSET_SPLL1_CFG_2 0x1C
30
+
#define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL 0x20
31
+
#define EIC7700_REG_OFFSET_SPLL1_SSC 0x24
32
+
#define EIC7700_REG_OFFSET_SPLL2_CFG_0 0x28
33
+
#define EIC7700_REG_OFFSET_SPLL2_CFG_1 0x2C
34
+
#define EIC7700_REG_OFFSET_SPLL2_CFG_2 0x30
35
+
#define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL 0x34
36
+
#define EIC7700_REG_OFFSET_SPLL2_SSC 0x38
37
+
#define EIC7700_REG_OFFSET_VPLL_CFG_0 0x3C
38
+
#define EIC7700_REG_OFFSET_VPLL_CFG_1 0x40
39
+
#define EIC7700_REG_OFFSET_VPLL_CFG_2 0x44
40
+
#define EIC7700_REG_OFFSET_VPLL_DSKEWCAL 0x48
41
+
#define EIC7700_REG_OFFSET_VPLL_SSC 0x4C
42
+
#define EIC7700_REG_OFFSET_APLL_CFG_0 0x50
43
+
#define EIC7700_REG_OFFSET_APLL_CFG_1 0x54
44
+
#define EIC7700_REG_OFFSET_APLL_CFG_2 0x58
45
+
#define EIC7700_REG_OFFSET_APLL_DSKEWCAL 0x5C
46
+
#define EIC7700_REG_OFFSET_APLL_SSC 0x60
47
+
#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0 0x64
48
+
#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1 0x68
49
+
#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2 0x6C
50
+
#define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL 0x70
51
+
#define EIC7700_REG_OFFSET_MCPUT_PLL_SSC 0x74
52
+
#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0 0x78
53
+
#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1 0x7C
54
+
#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2 0x80
55
+
#define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL 0x84
56
+
#define EIC7700_REG_OFFSET_DDRT_PLL_SSC 0x88
57
+
#define EIC7700_REG_OFFSET_PLL_STATUS 0xA4
58
+
#define EIC7700_REG_OFFSET_NOC 0x100
59
+
#define EIC7700_REG_OFFSET_BOOTSPI 0x104
60
+
#define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK 0x108
61
+
#define EIC7700_REG_OFFSET_SCPU_CORE 0x10C
62
+
#define EIC7700_REG_OFFSET_SCPU_BUSCLK 0x110
63
+
#define EIC7700_REG_OFFSET_LPCPU_CORE 0x114
64
+
#define EIC7700_REG_OFFSET_LPCPU_BUSCLK 0x118
65
+
#define EIC7700_REG_OFFSET_TCU_ACLK 0x11C
66
+
#define EIC7700_REG_OFFSET_TCU_CFG 0x120
67
+
#define EIC7700_REG_OFFSET_DDR 0x124
68
+
#define EIC7700_REG_OFFSET_DDR1 0x128
69
+
#define EIC7700_REG_OFFSET_GPU_ACLK 0x12C
70
+
#define EIC7700_REG_OFFSET_GPU_CFG 0x130
71
+
#define EIC7700_REG_OFFSET_GPU_GRAY 0x134
72
+
#define EIC7700_REG_OFFSET_DSP_ACLK 0x138
73
+
#define EIC7700_REG_OFFSET_DSP_CFG 0x13C
74
+
#define EIC7700_REG_OFFSET_D2D_ACLK 0x140
75
+
#define EIC7700_REG_OFFSET_D2D_CFG 0x144
76
+
#define EIC7700_REG_OFFSET_HSP_ACLK 0x148
77
+
#define EIC7700_REG_OFFSET_HSP_CFG 0x14C
78
+
#define EIC7700_REG_OFFSET_SATA_RBC 0x150
79
+
#define EIC7700_REG_OFFSET_SATA_OOB 0x154
80
+
#define EIC7700_REG_OFFSET_ETH0 0x158
81
+
#define EIC7700_REG_OFFSET_ETH1 0x15C
82
+
#define EIC7700_REG_OFFSET_MSHC0_CORE 0x160
83
+
#define EIC7700_REG_OFFSET_MSHC1_CORE 0x164
84
+
#define EIC7700_REG_OFFSET_MSHC2_CORE 0x168
85
+
#define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK 0x16C
86
+
#define EIC7700_REG_OFFSET_PCIE_ACLK 0x170
87
+
#define EIC7700_REG_OFFSET_PCIE_CFG 0x174
88
+
#define EIC7700_REG_OFFSET_NPU_ACLK 0x178
89
+
#define EIC7700_REG_OFFSET_NPU_LLC 0x17C
90
+
#define EIC7700_REG_OFFSET_NPU_CORE 0x180
91
+
#define EIC7700_REG_OFFSET_VI_DWCLK 0x184
92
+
#define EIC7700_REG_OFFSET_VI_ACLK 0x188
93
+
#define EIC7700_REG_OFFSET_VI_DIG_ISP 0x18C
94
+
#define EIC7700_REG_OFFSET_VI_DVP 0x190
95
+
#define EIC7700_REG_OFFSET_VI_SHUTTER0 0x194
96
+
#define EIC7700_REG_OFFSET_VI_SHUTTER1 0x198
97
+
#define EIC7700_REG_OFFSET_VI_SHUTTER2 0x19C
98
+
#define EIC7700_REG_OFFSET_VI_SHUTTER3 0x1A0
99
+
#define EIC7700_REG_OFFSET_VI_SHUTTER4 0x1A4
100
+
#define EIC7700_REG_OFFSET_VI_SHUTTER5 0x1A8
101
+
#define EIC7700_REG_OFFSET_VI_PHY 0x1AC
102
+
#define EIC7700_REG_OFFSET_VO_ACLK 0x1B0
103
+
#define EIC7700_REG_OFFSET_VO_IESMCLK 0x1B4
104
+
#define EIC7700_REG_OFFSET_VO_PIXEL 0x1B8
105
+
#define EIC7700_REG_OFFSET_VO_MCLK 0x1BC
106
+
#define EIC7700_REG_OFFSET_VO_PHY_CLK 0x1C0
107
+
#define EIC7700_REG_OFFSET_VC_ACLK 0x1C4
108
+
#define EIC7700_REG_OFFSET_VCDEC_ROOT 0x1C8
109
+
#define EIC7700_REG_OFFSET_G2D 0x1CC
110
+
#define EIC7700_REG_OFFSET_VC_CLKEN 0x1D0
111
+
#define EIC7700_REG_OFFSET_JE 0x1D4
112
+
#define EIC7700_REG_OFFSET_JD 0x1D8
113
+
#define EIC7700_REG_OFFSET_VD 0x1DC
114
+
#define EIC7700_REG_OFFSET_VE 0x1E0
115
+
#define EIC7700_REG_OFFSET_AON_DMA 0x1E4
116
+
#define EIC7700_REG_OFFSET_TIMER 0x1E8
117
+
#define EIC7700_REG_OFFSET_RTC 0x1EC
118
+
#define EIC7700_REG_OFFSET_PKA 0x1F0
119
+
#define EIC7700_REG_OFFSET_SPACC 0x1F4
120
+
#define EIC7700_REG_OFFSET_TRNG 0x1F8
121
+
#define EIC7700_REG_OFFSET_OTP 0x1FC
122
+
#define EIC7700_REG_OFFSET_LSP_EN0 0x200
123
+
#define EIC7700_REG_OFFSET_LSP_EN1 0x204
124
+
#define EIC7700_REG_OFFSET_U84 0x208
125
+
#define EIC7700_REG_OFFSET_SYSCFG 0x20C
126
+
#define EIC7700_REG_OFFSET_I2C0 0x210
127
+
#define EIC7700_REG_OFFSET_I2C1 0x214
128
+
129
+
#define EIC7700_NR_CLKS (EIC7700_CLK_GATE_NOC_WDREF + 1)
130
+
131
+
/*
132
+
* The 24 MHz oscillator, the root of most of the clock tree.
133
+
*/
134
+
static const struct clk_parent_data xtal24M[] = {
135
+
{ .index = 0, }
136
+
};
137
+
138
+
/* fixed rate clocks */
139
+
static struct eswin_fixed_rate_clock eic7700_fixed_rate_clks[] = {
140
+
ESWIN_FIXED(EIC7700_CLK_XTAL_32K, "fixed_rate_clk_xtal_32k", 0, 32768),
141
+
ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT1, "fixed_rate_clk_spll0_fout1", 0,
142
+
1600000000),
143
+
ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT2, "fixed_rate_clk_spll0_fout2", 0,
144
+
800000000),
145
+
ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT3, "fixed_rate_clk_spll0_fout3", 0,
146
+
400000000),
147
+
ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT1, "fixed_rate_clk_spll1_fout1", 0,
148
+
1500000000),
149
+
ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT2, "fixed_rate_clk_spll1_fout2", 0,
150
+
300000000),
151
+
ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT3, "fixed_rate_clk_spll1_fout3", 0,
152
+
250000000),
153
+
ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT1, "fixed_rate_clk_spll2_fout1", 0,
154
+
2080000000),
155
+
ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT2, "fixed_rate_clk_spll2_fout2", 0,
156
+
1040000000),
157
+
ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT3, "fixed_rate_clk_spll2_fout3", 0,
158
+
416000000),
159
+
ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT1, "fixed_rate_clk_vpll_fout1", 0,
160
+
1188000000),
161
+
ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT2, "fixed_rate_clk_vpll_fout2", 0,
162
+
594000000),
163
+
ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT3, "fixed_rate_clk_vpll_fout3", 0,
164
+
49500000),
165
+
ESWIN_FIXED(EIC7700_CLK_APLL_FOUT2, "fixed_rate_clk_apll_fout2", 0, 0),
166
+
ESWIN_FIXED(EIC7700_CLK_APLL_FOUT3, "fixed_rate_clk_apll_fout3", 0, 0),
167
+
ESWIN_FIXED(EIC7700_CLK_EXT_MCLK, "fixed_rate_ext_mclk", 0, 0),
168
+
ESWIN_FIXED(EIC7700_CLK_LPDDR_REF_BAK, "fixed_rate_lpddr_ref_bak", 0,
169
+
50000000),
170
+
};
171
+
172
+
/* pll clocks */
173
+
static struct eswin_pll_clock eic7700_pll_clks[] = {
174
+
ESWIN_PLL(EIC7700_CLK_APLL_FOUT1, "clk_apll_fout1", xtal24M,
175
+
EIC7700_REG_OFFSET_APLL_CFG_0, 20,
176
+
EIC7700_REG_OFFSET_APLL_CFG_1, 4,
177
+
EIC7700_REG_OFFSET_APLL_CFG_2, EIC7700_REG_OFFSET_PLL_STATUS,
178
+
4, 1, APLL_HIGH_FREQ, APLL_LOW_FREQ),
179
+
ESWIN_PLL(EIC7700_CLK_PLL_CPU, "clk_pll_cpu", xtal24M,
180
+
EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0, 20,
181
+
EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1, 4,
182
+
EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2,
183
+
EIC7700_REG_OFFSET_PLL_STATUS, 5, 1, PLL_HIGH_FREQ,
184
+
PLL_LOW_FREQ),
185
+
};
186
+
187
+
/* fixed factor clocks */
188
+
static struct eswin_fixed_factor_clock eic7700_factor_clks[] = {
189
+
ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24,
190
+
"fixed_factor_clk_1m_div24", xtal24M, 1, 24, 0),
191
+
ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_PVT_DIV20,
192
+
"fixed_factor_pvt_div20", xtal24M, 1, 20, 0),
193
+
};
194
+
195
+
/* divider clocks */
196
+
static struct eswin_divider_clock eic7700_div_clks[] = {
197
+
ESWIN_DIV(EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM,
198
+
"divider_u84_rtc_toggle_dynm", xtal24M, 0,
199
+
EIC7700_REG_OFFSET_RTC, 16, 5,
200
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
201
+
ESWIN_DIV(EIC7700_CLK_DIV_NOC_WDREF_DYNM, "divider_noc_wdref_dynm",
202
+
xtal24M, 0, EIC7700_REG_OFFSET_NOC, 4, 16,
203
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
204
+
};
205
+
206
+
/* gate clocks */
207
+
static struct eswin_gate_clock eic7700_gate_clks[] = {
208
+
ESWIN_GATE(EIC7700_CLK_GATE_GPU_GRAY_CLK, "gate_gpu_gray_clk", xtal24M,
209
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_GRAY, 31, 0),
210
+
ESWIN_GATE(EIC7700_CLK_GATE_VI_PHY_CFG, "gate_vi_phy_cfg", xtal24M,
211
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 1, 0),
212
+
ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_0, "gate_time_clk_0", xtal24M,
213
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 0, 0),
214
+
ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_1, "gate_time_clk_1", xtal24M,
215
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 1, 0),
216
+
ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_2, "gate_time_clk_2", xtal24M,
217
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 2, 0),
218
+
ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_3, "gate_time_clk_3", xtal24M,
219
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 3, 0),
220
+
};
221
+
222
+
/* Define the early clocks as the parent clocks of the mux clocks. */
223
+
static struct eswin_clk_info eic7700_early_clks[] = {
224
+
ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6,
225
+
"fixed_factor_hsp_rmii_ref_div6",
226
+
EIC7700_CLK_SPLL1_FOUT2, 1, 6, 0),
227
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM,
228
+
"divider_npu_llc_src0_div_dynm",
229
+
EIC7700_CLK_SPLL0_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC,
230
+
4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
231
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM,
232
+
"divider_npu_llc_src1_div_dynm",
233
+
EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC,
234
+
8, 4, 0, ESWIN_PRIV_DIV_MIN_2),
235
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPLL0_FOUT2, "gate_clk_spll0_fout2",
236
+
EIC7700_CLK_SPLL0_FOUT2,
237
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
238
+
EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0),
239
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm",
240
+
EIC7700_CLK_GATE_SPLL0_FOUT2, 0,
241
+
EIC7700_REG_OFFSET_BOOTSPI, 4, 6, 0,
242
+
ESWIN_PRIV_DIV_MIN_2),
243
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SCPU_CORE_DYNM,
244
+
"divider_scpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
245
+
EIC7700_REG_OFFSET_SCPU_CORE, 4, 4, 0,
246
+
ESWIN_PRIV_DIV_MIN_2),
247
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_LPCPU_CORE_DYNM,
248
+
"divider_lpcpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1,
249
+
0, EIC7700_REG_OFFSET_LPCPU_CORE, 4, 4, 0,
250
+
ESWIN_PRIV_DIV_MIN_2),
251
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_MCLK_DYNM, "divider_vo_mclk_div_dynm",
252
+
EIC7700_CLK_APLL_FOUT1, 0, EIC7700_REG_OFFSET_VO_MCLK, 4,
253
+
8, 0, ESWIN_PRIV_DIV_MIN_2),
254
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AONDMA_AXI_DYNM,
255
+
"divider_aondma_axi_div_dynm", EIC7700_CLK_SPLL0_FOUT1,
256
+
0, EIC7700_REG_OFFSET_AON_DMA, 4, 4, 0,
257
+
ESWIN_PRIV_DIV_MIN_2),
258
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SATA_PHY_REF_DYNM,
259
+
"divider_sata_phy_ref_div_dynm",
260
+
EIC7700_CLK_SPLL1_FOUT2, 0, EIC7700_REG_OFFSET_SATA_OOB,
261
+
0, 4, 0, ESWIN_PRIV_DIV_MIN_2),
262
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm",
263
+
EIC7700_CLK_SPLL0_FOUT3, 0, EIC7700_REG_OFFSET_SYSCFG, 4,
264
+
3, 0, ESWIN_PRIV_DIV_MIN_2),
265
+
ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2,
266
+
"fixed_factor_u84_core_lp_div2",
267
+
EIC7700_CLK_GATE_SPLL0_FOUT2, 1, 2, 0),
268
+
};
269
+
270
+
static const struct clk_parent_data dsp_aclk_root_2mux1_gfree_mux_p[] = {
271
+
{ .hw = &eic7700_fixed_rate_clks[7].hw },
272
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
273
+
};
274
+
275
+
static const struct clk_parent_data d2d_aclk_root_2mux1_gfree_mux_p[] = {
276
+
{ .hw = &eic7700_fixed_rate_clks[7].hw },
277
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
278
+
};
279
+
280
+
static const struct clk_parent_data ddr_aclk_root_2mux1_gfree_mux_p[] = {
281
+
{ .hw = &eic7700_fixed_rate_clks[7].hw },
282
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
283
+
};
284
+
285
+
static const struct clk_parent_data mshcore_root_3mux1_0_mux_p[] = {
286
+
{ .hw = &eic7700_fixed_rate_clks[3].hw },
287
+
{ .hw = &eic7700_fixed_rate_clks[9].hw },
288
+
};
289
+
290
+
static const struct clk_parent_data mshcore_root_3mux1_1_mux_p[] = {
291
+
{ .hw = &eic7700_fixed_rate_clks[3].hw },
292
+
{ .hw = &eic7700_fixed_rate_clks[9].hw },
293
+
};
294
+
295
+
static const struct clk_parent_data mshcore_root_3mux1_2_mux_p[] = {
296
+
{ .hw = &eic7700_fixed_rate_clks[3].hw },
297
+
{ .hw = &eic7700_fixed_rate_clks[9].hw },
298
+
};
299
+
300
+
static const struct clk_parent_data npu_core_3mux1_gfree_mux_p[] = {
301
+
{ .hw = &eic7700_fixed_rate_clks[4].hw },
302
+
{ .hw = &eic7700_fixed_rate_clks[10].hw },
303
+
{ .hw = &eic7700_fixed_rate_clks[8].hw },
304
+
};
305
+
306
+
static const struct clk_parent_data npu_e31_3mux1_gfree_mux_p[] = {
307
+
{ .hw = &eic7700_fixed_rate_clks[4].hw },
308
+
{ .hw = &eic7700_fixed_rate_clks[10].hw },
309
+
{ .hw = &eic7700_fixed_rate_clks[8].hw },
310
+
};
311
+
312
+
static const struct clk_parent_data vi_aclk_root_2mux1_gfree_mux_p[] = {
313
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
314
+
{ .hw = &eic7700_fixed_rate_clks[7].hw },
315
+
};
316
+
317
+
static const struct clk_parent_data mux_vi_dw_root_2mux1_p[] = {
318
+
{ .hw = &eic7700_fixed_rate_clks[10].hw },
319
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
320
+
};
321
+
322
+
static const struct clk_parent_data mux_vi_dvp_root_2mux1_gfree_p[] = {
323
+
{ .hw = &eic7700_fixed_rate_clks[10].hw },
324
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
325
+
};
326
+
327
+
static const struct clk_parent_data mux_vi_dig_isp_root_2mux1_gfree_p[] = {
328
+
{ .hw = &eic7700_fixed_rate_clks[10].hw },
329
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
330
+
};
331
+
332
+
static const struct clk_parent_data mux_vo_aclk_root_2mux1_gfree_p[] = {
333
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
334
+
{ .hw = &eic7700_fixed_rate_clks[7].hw },
335
+
};
336
+
337
+
static const struct clk_parent_data mux_vo_pixel_root_2mux1_p[] = {
338
+
{ .hw = &eic7700_fixed_rate_clks[10].hw },
339
+
{ .hw = &eic7700_fixed_rate_clks[8].hw },
340
+
};
341
+
342
+
static const struct clk_parent_data mux_vcdec_root_2mux1_gfree_p[] = {
343
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
344
+
{ .hw = &eic7700_fixed_rate_clks[7].hw },
345
+
};
346
+
347
+
static const struct clk_parent_data mux_vcaclk_root_2mux1_gfree_p[] = {
348
+
{ .hw = &eic7700_fixed_rate_clks[1].hw },
349
+
{ .hw = &eic7700_fixed_rate_clks[7].hw },
350
+
};
351
+
352
+
static const struct clk_parent_data npu_llclk_3mux1_gfree_mux_p[] = {
353
+
{ .hw = &eic7700_early_clks[1].hw },
354
+
{ .hw = &eic7700_early_clks[2].hw },
355
+
{ .hw = &eic7700_fixed_rate_clks[10].hw },
356
+
};
357
+
358
+
static const struct clk_parent_data mux_bootspi_clk_2mux1_gfree_p[] = {
359
+
{ .hw = &eic7700_early_clks[4].hw },
360
+
{ .index = 0 },
361
+
};
362
+
363
+
static const struct clk_parent_data mux_scpu_core_clk_2mux1_gfree_p[] = {
364
+
{ .hw = &eic7700_early_clks[5].hw },
365
+
{ .index = 0 },
366
+
};
367
+
368
+
static const struct clk_parent_data mux_lpcpu_core_clk_2mux1_gfree_p[] = {
369
+
{ .hw = &eic7700_early_clks[6].hw },
370
+
{ .index = 0 },
371
+
};
372
+
373
+
static const struct clk_parent_data mux_vo_mclk_2mux_ext_mclk_p[] = {
374
+
{ .hw = &eic7700_early_clks[7].hw },
375
+
{ .hw = &eic7700_fixed_rate_clks[15].hw },
376
+
};
377
+
378
+
static const struct clk_parent_data mux_aondma_axi2mux1_gfree_p[] = {
379
+
{ .hw = &eic7700_early_clks[8].hw },
380
+
{ .index = 0 },
381
+
};
382
+
383
+
static const struct clk_parent_data mux_rmii_ref_2mux1_p[] = {
384
+
{ .hw = &eic7700_early_clks[0].hw },
385
+
{ .hw = &eic7700_fixed_rate_clks[16].hw },
386
+
};
387
+
388
+
static const struct clk_parent_data mux_eth_core_2mux1_p[] = {
389
+
{ .hw = &eic7700_fixed_rate_clks[6].hw },
390
+
{ .hw = &eic7700_fixed_rate_clks[16].hw },
391
+
};
392
+
393
+
static const struct clk_parent_data mux_sata_phy_2mux1_p[] = {
394
+
{ .hw = &eic7700_early_clks[9].hw },
395
+
{ .hw = &eic7700_fixed_rate_clks[16].hw },
396
+
};
397
+
398
+
static const struct clk_parent_data mux_syscfg_clk_root_2mux1_gfree_p[] = {
399
+
{ .hw = &eic7700_early_clks[10].hw },
400
+
{ .index = 0 },
401
+
};
402
+
403
+
static const struct clk_parent_data mux_cpu_root_3mux1_gfree_p[] = {
404
+
{ .hw = &eic7700_pll_clks[1].hw },
405
+
{ .hw = &eic7700_early_clks[11].hw },
406
+
{ .index = 0 },
407
+
};
408
+
409
+
static struct eswin_mux_clock eic7700_mux_clks[] = {
410
+
ESWIN_MUX(EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
411
+
"mux_cpu_root_3mux1_gfree", mux_cpu_root_3mux1_gfree_p,
412
+
ARRAY_SIZE(mux_cpu_root_3mux1_gfree_p),
413
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 0, 2,
414
+
CLK_MUX_ROUND_CLOSEST),
415
+
ESWIN_MUX(EIC7700_CLK_MUX_RMII_REF_2MUX, "mux_rmii_ref_2mux1",
416
+
mux_rmii_ref_2mux1_p, ARRAY_SIZE(mux_rmii_ref_2mux1_p),
417
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 2, 1,
418
+
CLK_MUX_ROUND_CLOSEST),
419
+
ESWIN_MUX(EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE,
420
+
"mux_dsp_aclk_root_2mux1_gfree",
421
+
dsp_aclk_root_2mux1_gfree_mux_p,
422
+
ARRAY_SIZE(dsp_aclk_root_2mux1_gfree_mux_p),
423
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_ACLK, 0, 1,
424
+
CLK_MUX_ROUND_CLOSEST),
425
+
ESWIN_MUX(EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE,
426
+
"mux_d2d_aclk_root_2mux1_gfree",
427
+
d2d_aclk_root_2mux1_gfree_mux_p,
428
+
ARRAY_SIZE(d2d_aclk_root_2mux1_gfree_mux_p),
429
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_ACLK, 0, 1,
430
+
CLK_MUX_ROUND_CLOSEST),
431
+
ESWIN_MUX(EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE,
432
+
"mux_ddr_aclk_root_2mux1_gfree",
433
+
ddr_aclk_root_2mux1_gfree_mux_p,
434
+
ARRAY_SIZE(ddr_aclk_root_2mux1_gfree_mux_p),
435
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 16, 1,
436
+
CLK_MUX_ROUND_CLOSEST),
437
+
ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0,
438
+
"mux_mshcore_root_3mux1_0", mshcore_root_3mux1_0_mux_p,
439
+
ARRAY_SIZE(mshcore_root_3mux1_0_mux_p), CLK_SET_RATE_PARENT,
440
+
EIC7700_REG_OFFSET_MSHC0_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
441
+
ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1,
442
+
"mux_mshcore_root_3mux1_1", mshcore_root_3mux1_1_mux_p,
443
+
ARRAY_SIZE(mshcore_root_3mux1_1_mux_p), CLK_SET_RATE_PARENT,
444
+
EIC7700_REG_OFFSET_MSHC1_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
445
+
ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2,
446
+
"mux_mshcore_root_3mux1_2", mshcore_root_3mux1_2_mux_p,
447
+
ARRAY_SIZE(mshcore_root_3mux1_2_mux_p), CLK_SET_RATE_PARENT,
448
+
EIC7700_REG_OFFSET_MSHC2_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
449
+
ESWIN_MUX(EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE,
450
+
"mux_npu_llclk_3mux1_gfree", npu_llclk_3mux1_gfree_mux_p,
451
+
ARRAY_SIZE(npu_llclk_3mux1_gfree_mux_p),
452
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 0, 2,
453
+
CLK_MUX_ROUND_CLOSEST),
454
+
ESWIN_MUX(EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE,
455
+
"mux_npu_core_3mux1_gfree", npu_core_3mux1_gfree_mux_p,
456
+
ARRAY_SIZE(npu_core_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT,
457
+
EIC7700_REG_OFFSET_NPU_CORE, 0, 2, CLK_MUX_ROUND_CLOSEST),
458
+
ESWIN_MUX(EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE,
459
+
"mux_npu_e31_3mux1_gfree", npu_e31_3mux1_gfree_mux_p,
460
+
ARRAY_SIZE(npu_e31_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT,
461
+
EIC7700_REG_OFFSET_NPU_CORE, 8, 2, CLK_MUX_ROUND_CLOSEST),
462
+
ESWIN_MUX(EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE,
463
+
"mux_vi_aclk_root_2mux1_gfree",
464
+
vi_aclk_root_2mux1_gfree_mux_p,
465
+
ARRAY_SIZE(vi_aclk_root_2mux1_gfree_mux_p),
466
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 0, 1,
467
+
CLK_MUX_ROUND_CLOSEST),
468
+
ESWIN_MUX(EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, "mux_vi_dw_root_2mux1",
469
+
mux_vi_dw_root_2mux1_p, ARRAY_SIZE(mux_vi_dw_root_2mux1_p),
470
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DWCLK, 0, 1,
471
+
CLK_MUX_ROUND_CLOSEST),
472
+
ESWIN_MUX(EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE,
473
+
"mux_vi_dvp_root_2mux1_gfree",
474
+
mux_vi_dvp_root_2mux1_gfree_p,
475
+
ARRAY_SIZE(mux_vi_dvp_root_2mux1_gfree_p),
476
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DVP, 0, 1,
477
+
CLK_MUX_ROUND_CLOSEST),
478
+
ESWIN_MUX(EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE,
479
+
"mux_vi_dig_isp_root_2mux1_gfree",
480
+
mux_vi_dig_isp_root_2mux1_gfree_p,
481
+
ARRAY_SIZE(mux_vi_dig_isp_root_2mux1_gfree_p),
482
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DIG_ISP, 0, 1,
483
+
CLK_MUX_ROUND_CLOSEST),
484
+
ESWIN_MUX(EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE,
485
+
"mux_vo_aclk_root_2mux1_gfree",
486
+
mux_vo_aclk_root_2mux1_gfree_p,
487
+
ARRAY_SIZE(mux_vo_aclk_root_2mux1_gfree_p),
488
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 0, 1,
489
+
CLK_MUX_ROUND_CLOSEST),
490
+
ESWIN_MUX(EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1,
491
+
"mux_vo_pixel_root_2mux1", mux_vo_pixel_root_2mux1_p,
492
+
ARRAY_SIZE(mux_vo_pixel_root_2mux1_p), CLK_SET_RATE_PARENT,
493
+
EIC7700_REG_OFFSET_VO_PIXEL, 0, 1, CLK_MUX_ROUND_CLOSEST),
494
+
ESWIN_MUX(EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE,
495
+
"mux_vcdec_root_2mux1_gfree", mux_vcdec_root_2mux1_gfree_p,
496
+
ARRAY_SIZE(mux_vcdec_root_2mux1_gfree_p),
497
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VCDEC_ROOT, 0, 1,
498
+
CLK_MUX_ROUND_CLOSEST),
499
+
ESWIN_MUX(EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE,
500
+
"mux_vcaclk_root_2mux1_gfree",
501
+
mux_vcaclk_root_2mux1_gfree_p,
502
+
ARRAY_SIZE(mux_vcaclk_root_2mux1_gfree_p),
503
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_ACLK, 0, 1,
504
+
CLK_MUX_ROUND_CLOSEST),
505
+
ESWIN_MUX(EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
506
+
"mux_syscfg_clk_root_2mux1_gfree",
507
+
mux_syscfg_clk_root_2mux1_gfree_p,
508
+
ARRAY_SIZE(mux_syscfg_clk_root_2mux1_gfree_p),
509
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SYSCFG, 0, 1,
510
+
CLK_MUX_ROUND_CLOSEST),
511
+
ESWIN_MUX(EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE,
512
+
"mux_bootspi_clk_2mux1_gfree",
513
+
mux_bootspi_clk_2mux1_gfree_p,
514
+
ARRAY_SIZE(mux_bootspi_clk_2mux1_gfree_p),
515
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 0, 1,
516
+
CLK_MUX_ROUND_CLOSEST),
517
+
ESWIN_MUX(EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE,
518
+
"mux_scpu_core_clk_2mux1_gfree",
519
+
mux_scpu_core_clk_2mux1_gfree_p,
520
+
ARRAY_SIZE(mux_scpu_core_clk_2mux1_gfree_p),
521
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 0, 1,
522
+
CLK_MUX_ROUND_CLOSEST),
523
+
ESWIN_MUX(EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE,
524
+
"mux_lpcpu_core_clk_2mux1_gfree",
525
+
mux_lpcpu_core_clk_2mux1_gfree_p,
526
+
ARRAY_SIZE(mux_lpcpu_core_clk_2mux1_gfree_p),
527
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 0, 1,
528
+
CLK_MUX_ROUND_CLOSEST),
529
+
ESWIN_MUX(EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK,
530
+
"mux_vo_mclk_2mux_ext_mclk", mux_vo_mclk_2mux_ext_mclk_p,
531
+
ARRAY_SIZE(mux_vo_mclk_2mux_ext_mclk_p),
532
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 0, 1,
533
+
CLK_MUX_ROUND_CLOSEST),
534
+
ESWIN_MUX(EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
535
+
"mux_aondma_axi2mux1_gfree", mux_aondma_axi2mux1_gfree_p,
536
+
ARRAY_SIZE(mux_aondma_axi2mux1_gfree_p),
537
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 0, 1,
538
+
CLK_MUX_ROUND_CLOSEST),
539
+
ESWIN_MUX(EIC7700_CLK_MUX_ETH_CORE_2MUX1, "mux_eth_core_2mux1",
540
+
mux_eth_core_2mux1_p, ARRAY_SIZE(mux_eth_core_2mux1_p),
541
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 1, 1,
542
+
CLK_MUX_ROUND_CLOSEST),
543
+
ESWIN_MUX(EIC7700_CLK_MUX_SATA_PHY_2MUX1, "mux_sata_phy_2mux1",
544
+
mux_sata_phy_2mux1_p, ARRAY_SIZE(mux_sata_phy_2mux1_p),
545
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 9, 1,
546
+
CLK_MUX_ROUND_CLOSEST),
547
+
};
548
+
549
+
static const struct clk_parent_data mux_cpu_aclk_2mux1_gfree_p[] = {
550
+
{ .hw = &eic7700_mux_clks[1].hw },
551
+
{ .hw = &eic7700_mux_clks[0].hw },
552
+
};
553
+
554
+
static struct eswin_clk_info eic7700_clks[] = {
555
+
ESWIN_MUX_TYPE(EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE,
556
+
"mux_cpu_aclk_2mux1_gfree", mux_cpu_aclk_2mux1_gfree_p,
557
+
ARRAY_SIZE(mux_cpu_aclk_2mux1_gfree_p),
558
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 20, 1,
559
+
CLK_MUX_ROUND_CLOSEST, NULL),
560
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_COM_CLK,
561
+
"gate_clk_cpu_trace_com_clk",
562
+
EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE,
563
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 23, 0),
564
+
ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_CPU_DIV2,
565
+
"fixed_factor_cpu_div2",
566
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 1, 2, 0),
567
+
ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
568
+
"fixed_factor_mipi_txesc_div10",
569
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 10,
570
+
0),
571
+
ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2,
572
+
"fixed_factor_scpu_bus_div2",
573
+
EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0),
574
+
ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2,
575
+
"fixed_factor_lpcpu_bus_div2",
576
+
EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0),
577
+
ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2,
578
+
"fixed_factor_pcie_cr_div2",
579
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 2, 0),
580
+
ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4,
581
+
"fixed_factor_pcie_aux_div4",
582
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 4, 0),
583
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_D2D_ACLK_DYNM,
584
+
"divider_d2d_aclk_div_dynm",
585
+
EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, 0,
586
+
EIC7700_REG_OFFSET_D2D_ACLK, 4, 4, 0,
587
+
ESWIN_PRIV_DIV_MIN_2),
588
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_ACLK_DYNM,
589
+
"divider_dsp_aclk_div_dynm",
590
+
EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0,
591
+
EIC7700_REG_OFFSET_DSP_ACLK, 4, 4, 0,
592
+
ESWIN_PRIV_DIV_MIN_2),
593
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DDR_ACLK_DYNM,
594
+
"divider_ddr_aclk_div_dynm",
595
+
EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, 0,
596
+
EIC7700_REG_OFFSET_DDR, 20, 4, 0, ESWIN_PRIV_DIV_MIN_2),
597
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0,
598
+
"divider_eth_txclk_div_dynm_0",
599
+
EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0,
600
+
EIC7700_REG_OFFSET_ETH0, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2),
601
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1,
602
+
"divider_eth_txclk_div_dynm_1",
603
+
EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0,
604
+
EIC7700_REG_OFFSET_ETH1, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2),
605
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_0,
606
+
"divider_mshc_core_div_dynm_0",
607
+
EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0,
608
+
0, EIC7700_REG_OFFSET_MSHC0_CORE, 4, 12,
609
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
610
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_1,
611
+
"divider_mshc_core_div_dynm_1",
612
+
EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1,
613
+
0, EIC7700_REG_OFFSET_MSHC1_CORE, 4, 12,
614
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
615
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_2,
616
+
"divider_mshc_core_div_dynm_2",
617
+
EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2,
618
+
0, EIC7700_REG_OFFSET_MSHC2_CORE, 4, 12,
619
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
620
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_CORECLK_DYNM,
621
+
"divider_npu_coreclk_div_dynm",
622
+
EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE,
623
+
0, EIC7700_REG_OFFSET_NPU_CORE, 4, 4,
624
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
625
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_E31_DYNM, "divider_npu_e31_div_dynm",
626
+
EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, 0,
627
+
EIC7700_REG_OFFSET_NPU_CORE, 12, 4,
628
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0),
629
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_ACLK_DYNM, "divider_vi_aclk_div_dynm",
630
+
EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, 0,
631
+
EIC7700_REG_OFFSET_VI_ACLK, 4, 4, 0,
632
+
ESWIN_PRIV_DIV_MIN_2),
633
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DW_DYNM, "divider_vi_dw_div_dynm",
634
+
EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, 0,
635
+
EIC7700_REG_OFFSET_VI_DWCLK, 4, 4, 0,
636
+
ESWIN_PRIV_DIV_MIN_2),
637
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DVP_DYNM, "divider_vi_dvp_div_dynm",
638
+
EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, 0,
639
+
EIC7700_REG_OFFSET_VI_DVP, 4, 4, 0,
640
+
ESWIN_PRIV_DIV_MIN_2),
641
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DIG_ISP_DYNM,
642
+
"divider_vi_dig_isp_div_dynm",
643
+
EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, 0,
644
+
EIC7700_REG_OFFSET_VI_DIG_ISP, 4, 4, 0,
645
+
ESWIN_PRIV_DIV_MIN_2),
646
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_ACLK_DYNM, "divider_vo_aclk_div_dynm",
647
+
EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, 0,
648
+
EIC7700_REG_OFFSET_VO_ACLK, 4, 4, 0,
649
+
ESWIN_PRIV_DIV_MIN_2),
650
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_PIXEL_DYNM,
651
+
"divider_vo_pixel_div_dynm",
652
+
EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, 0,
653
+
EIC7700_REG_OFFSET_VO_PIXEL, 4, 6, 0,
654
+
ESWIN_PRIV_DIV_MIN_2),
655
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VC_ACLK_DYNM, "divider_vc_aclk_div_dynm",
656
+
EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, 0,
657
+
EIC7700_REG_OFFSET_VC_ACLK, 4, 4, 0,
658
+
ESWIN_PRIV_DIV_MIN_2),
659
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JD_DYNM, "divider_jd_div_dynm",
660
+
EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
661
+
EIC7700_REG_OFFSET_JD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
662
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JE_DYNM, "divider_je_div_dynm",
663
+
EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
664
+
EIC7700_REG_OFFSET_JE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
665
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VE_DYNM, "divider_ve_div_dynm",
666
+
EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
667
+
EIC7700_REG_OFFSET_VE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
668
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VD_DYNM, "divider_vd_div_dynm",
669
+
EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
670
+
EIC7700_REG_OFFSET_VD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
671
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_G2D_DYNM, "divider_g2d_div_dynm",
672
+
EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0,
673
+
EIC7700_REG_OFFSET_G2D, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
674
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm",
675
+
EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NOC, 0, 3,
676
+
0, ESWIN_PRIV_DIV_MIN_2),
677
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_GPU_ACLK_DYNM,
678
+
"divider_gpu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
679
+
EIC7700_REG_OFFSET_GPU_ACLK, 4, 4, 0,
680
+
ESWIN_PRIV_DIV_MIN_2),
681
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_HSP_ACLK_DYNM,
682
+
"divider_hsp_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
683
+
EIC7700_REG_OFFSET_HSP_ACLK, 4, 4, 0,
684
+
ESWIN_PRIV_DIV_MIN_2),
685
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_PCIE_ACLK_DYNM,
686
+
"divider_pcie_aclk_div_dynm", EIC7700_CLK_SPLL2_FOUT2, 0,
687
+
EIC7700_REG_OFFSET_PCIE_ACLK, 4, 4, 0,
688
+
ESWIN_PRIV_DIV_MIN_2),
689
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_ACLK_DYNM,
690
+
"divider_npu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
691
+
EIC7700_REG_OFFSET_NPU_ACLK, 4, 4, 0,
692
+
ESWIN_PRIV_DIV_MIN_2),
693
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0,
694
+
"divider_vi_shutter_div_dynm_0",
695
+
EIC7700_CLK_VPLL_FOUT2, 0,
696
+
EIC7700_REG_OFFSET_VI_SHUTTER0, 4, 7, 0,
697
+
ESWIN_PRIV_DIV_MIN_2),
698
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1,
699
+
"divider_vi_shutter_div_dynm_1",
700
+
EIC7700_CLK_VPLL_FOUT2, 0,
701
+
EIC7700_REG_OFFSET_VI_SHUTTER1, 4, 7, 0,
702
+
ESWIN_PRIV_DIV_MIN_2),
703
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2,
704
+
"divider_vi_shutter_div_dynm_2",
705
+
EIC7700_CLK_VPLL_FOUT2, 0,
706
+
EIC7700_REG_OFFSET_VI_SHUTTER2, 4, 7, 0,
707
+
ESWIN_PRIV_DIV_MIN_2),
708
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3,
709
+
"divider_vi_shutter_div_dynm_3",
710
+
EIC7700_CLK_VPLL_FOUT2, 0,
711
+
EIC7700_REG_OFFSET_VI_SHUTTER3, 4, 7, 0,
712
+
ESWIN_PRIV_DIV_MIN_2),
713
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4,
714
+
"divider_vi_shutter_div_dynm_4",
715
+
EIC7700_CLK_VPLL_FOUT2, 0,
716
+
EIC7700_REG_OFFSET_VI_SHUTTER4, 4, 7, 0,
717
+
ESWIN_PRIV_DIV_MIN_2),
718
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5,
719
+
"divider_vi_shutter_div_dynm_5",
720
+
EIC7700_CLK_VPLL_FOUT2, 0,
721
+
EIC7700_REG_OFFSET_VI_SHUTTER5, 4, 7, 0,
722
+
ESWIN_PRIV_DIV_MIN_2),
723
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_IESMCLK_DYNM, "divider_iesmclk_div_dynm",
724
+
EIC7700_CLK_SPLL0_FOUT3, 0,
725
+
EIC7700_REG_OFFSET_VO_IESMCLK, 4, 4, 0,
726
+
ESWIN_PRIV_DIV_MIN_2),
727
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_CEC_DYNM, "divider_vo_cec_div_dynm",
728
+
EIC7700_CLK_VPLL_FOUT2, 0,
729
+
EIC7700_REG_OFFSET_VO_PHY_CLK, 16, 16, 0,
730
+
ESWIN_PRIV_DIV_MIN_2),
731
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_CRYPTO_DYNM, "divider_crypto_div_dynm",
732
+
EIC7700_CLK_SPLL0_FOUT1, 0,
733
+
EIC7700_REG_OFFSET_SPACC, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
734
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AON_RTC_DYNM, "divider_aon_rtc_div_dynm",
735
+
EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, 0,
736
+
EIC7700_REG_OFFSET_RTC, 21, 11, 0,
737
+
ESWIN_PRIV_DIV_MIN_2),
738
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_ACLK, "gate_dspt_aclk",
739
+
EIC7700_CLK_DIV_DSP_ACLK_DYNM, CLK_SET_RATE_PARENT,
740
+
EIC7700_REG_OFFSET_DSP_ACLK, 31, 0),
741
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_0_ACLK_DYNM,
742
+
"divider_dsp_0_aclk_div_dynm",
743
+
EIC7700_CLK_GATE_DSPT_ACLK, 0,
744
+
EIC7700_REG_OFFSET_DSP_CFG, 19, 1, 0, 0),
745
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_1_ACLK_DYNM,
746
+
"divider_dsp_1_aclk_div_dynm",
747
+
EIC7700_CLK_GATE_DSPT_ACLK, 0,
748
+
EIC7700_REG_OFFSET_DSP_CFG, 20, 1, 0, 0),
749
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_2_ACLK_DYNM,
750
+
"divider_dsp_2_aclk_div_dynm",
751
+
EIC7700_CLK_GATE_DSPT_ACLK, 0,
752
+
EIC7700_REG_OFFSET_DSP_CFG, 21, 1, 0, 0),
753
+
ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_3_ACLK_DYNM,
754
+
"divider_dsp_3_aclk_div_dynm",
755
+
EIC7700_CLK_GATE_DSPT_ACLK, 0,
756
+
EIC7700_REG_OFFSET_DSP_CFG, 22, 1, 0, 0),
757
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0,
758
+
"gate_clk_cpu_ext_src_core_clk_0",
759
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
760
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
761
+
EIC7700_REG_OFFSET_U84, 28, 0),
762
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1,
763
+
"gate_clk_cpu_ext_src_core_clk_1",
764
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
765
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
766
+
EIC7700_REG_OFFSET_U84, 29, 0),
767
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2,
768
+
"gate_clk_cpu_ext_src_core_clk_2",
769
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
770
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
771
+
EIC7700_REG_OFFSET_U84, 30, 0),
772
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3,
773
+
"gate_clk_cpu_ext_src_core_clk_3",
774
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
775
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
776
+
EIC7700_REG_OFFSET_U84, 31, 0),
777
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_0,
778
+
"gate_clk_cpu_trace_clk_0",
779
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
780
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 24, 0),
781
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_1,
782
+
"gate_clk_cpu_trace_clk_1",
783
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
784
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 25, 0),
785
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_2,
786
+
"gate_clk_cpu_trace_clk_2",
787
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
788
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 26, 0),
789
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_3,
790
+
"gate_clk_cpu_trace_clk_3",
791
+
EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
792
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 27, 0),
793
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_NSP_CLK, "gate_noc_nsp_clk",
794
+
EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT,
795
+
EIC7700_REG_OFFSET_NOC, 31, 0),
796
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI, "gate_clk_bootspi",
797
+
EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE,
798
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 31, 0),
799
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI_CFG, "gate_clk_bootspi_cfg",
800
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
801
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI_CFGCLK,
802
+
31, 0),
803
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_CORE, "gate_clk_scpu_core",
804
+
EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE,
805
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 31,
806
+
0),
807
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_BUS, "gate_clk_scpu_bus",
808
+
EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2,
809
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_BUSCLK, 31,
810
+
0),
811
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_CORE, "gate_clk_lpcpu_core",
812
+
EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE,
813
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 31,
814
+
0),
815
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_BUS, "gate_clk_lpcpu_bus",
816
+
EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2,
817
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_BUSCLK,
818
+
31, 0),
819
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_ACLK, "gate_gpu_aclk",
820
+
EIC7700_CLK_DIV_GPU_ACLK_DYNM, CLK_SET_RATE_PARENT,
821
+
EIC7700_REG_OFFSET_GPU_ACLK, 31, 0),
822
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_CFG_CLK, "gate_gpu_cfg_clk",
823
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
824
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_CFG, 31, 0),
825
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_CFG_CLK, "gate_dspt_cfg_clk",
826
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
827
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_CFG, 31, 0),
828
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_ACLK, "gate_d2d_aclk",
829
+
EIC7700_CLK_DIV_D2D_ACLK_DYNM, CLK_SET_RATE_PARENT,
830
+
EIC7700_REG_OFFSET_D2D_ACLK, 31, 0),
831
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_CFG_CLK, "gate_d2d_cfg_clk",
832
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
833
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_CFG, 31, 0),
834
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_ACLK, "gate_tcu_aclk",
835
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
836
+
EIC7700_REG_OFFSET_TCU_ACLK, 31, 0),
837
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_CFG_CLK, "gate_tcu_cfg_clk",
838
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
839
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TCU_CFG, 31, 0),
840
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT_CFG_CLK, "gate_ddrt_cfg_clk",
841
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
842
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 9, 0),
843
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P0_ACLK, "gate_ddrt0_p0_aclk",
844
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
845
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
846
+
EIC7700_REG_OFFSET_DDR, 4, 0),
847
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P1_ACLK, "gate_ddrt0_p1_aclk",
848
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
849
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
850
+
EIC7700_REG_OFFSET_DDR, 5, 0),
851
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P2_ACLK, "gate_ddrt0_p2_aclk",
852
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
853
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
854
+
EIC7700_REG_OFFSET_DDR, 6, 0),
855
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P3_ACLK, "gate_ddrt0_p3_aclk",
856
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
857
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
858
+
EIC7700_REG_OFFSET_DDR, 7, 0),
859
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P4_ACLK, "gate_ddrt0_p4_aclk",
860
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
861
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
862
+
EIC7700_REG_OFFSET_DDR, 8, 0),
863
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P0_ACLK, "gate_ddrt1_p0_aclk",
864
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
865
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
866
+
EIC7700_REG_OFFSET_DDR1, 4, 0),
867
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P1_ACLK, "gate_ddrt1_p1_aclk",
868
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
869
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
870
+
EIC7700_REG_OFFSET_DDR1, 5, 0),
871
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P2_ACLK, "gate_ddrt1_p2_aclk",
872
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
873
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
874
+
EIC7700_REG_OFFSET_DDR1, 6, 0),
875
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P3_ACLK, "gate_ddrt1_p3_aclk",
876
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
877
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
878
+
EIC7700_REG_OFFSET_DDR1, 7, 0),
879
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P4_ACLK, "gate_ddrt1_p4_aclk",
880
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM,
881
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
882
+
EIC7700_REG_OFFSET_DDR1, 8, 0),
883
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ACLK, "gate_clk_hsp_aclk",
884
+
EIC7700_CLK_DIV_HSP_ACLK_DYNM, CLK_SET_RATE_PARENT,
885
+
EIC7700_REG_OFFSET_HSP_ACLK, 31, 0),
886
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_CFG_CLK, "gate_clk_hsp_cfg_clk",
887
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
888
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_CFG, 31, 0),
889
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_ACLK, "gate_pciet_aclk",
890
+
EIC7700_CLK_DIV_PCIE_ACLK_DYNM, CLK_SET_RATE_PARENT,
891
+
EIC7700_REG_OFFSET_PCIE_ACLK, 31, 0),
892
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CFG_CLK, "gate_pciet_cfg_clk",
893
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
894
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 31,
895
+
0),
896
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CR_CLK, "gate_pciet_cr_clk",
897
+
EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2,
898
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 0, 0),
899
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_AUX_CLK, "gate_pciet_aux_clk",
900
+
EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4,
901
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 1, 0),
902
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_ACLK, "gate_npu_aclk",
903
+
EIC7700_CLK_DIV_NPU_ACLK_DYNM, CLK_SET_RATE_PARENT,
904
+
EIC7700_REG_OFFSET_NPU_ACLK, 31, 0),
905
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CFG_CLK, "gate_npu_cfg_clk",
906
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
907
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_ACLK, 30,
908
+
0),
909
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_LLC_ACLK, "gate_npu_llc_aclk",
910
+
EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE,
911
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 31, 0),
912
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CLK, "gate_npu_clk",
913
+
EIC7700_CLK_DIV_NPU_CORECLK_DYNM, CLK_SET_RATE_PARENT,
914
+
EIC7700_REG_OFFSET_NPU_CORE, 31, 0),
915
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_E31_CLK, "gate_npu_e31_clk",
916
+
EIC7700_CLK_DIV_NPU_E31_DYNM, CLK_SET_RATE_PARENT,
917
+
EIC7700_REG_OFFSET_NPU_CORE, 30, 0),
918
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_ACLK, "gate_vi_aclk",
919
+
EIC7700_CLK_DIV_VI_ACLK_DYNM, CLK_SET_RATE_PARENT,
920
+
EIC7700_REG_OFFSET_VI_ACLK, 31, 0),
921
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_CFG_CLK, "gate_vi_cfg_clk",
922
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
923
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 30, 0),
924
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_DW_CLK, "gate_vi_dig_dw_clk",
925
+
EIC7700_CLK_DIV_VI_DW_DYNM, CLK_SET_RATE_PARENT,
926
+
EIC7700_REG_OFFSET_VI_DWCLK, 31, 0),
927
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DVP_CLK, "gate_vi_dvp_clk",
928
+
EIC7700_CLK_DIV_VI_DVP_DYNM, CLK_SET_RATE_PARENT,
929
+
EIC7700_REG_OFFSET_VI_DVP, 31, 0),
930
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_ISP_CLK, "gate_vi_dig_isp_clk",
931
+
EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, CLK_SET_RATE_PARENT,
932
+
EIC7700_REG_OFFSET_VI_DIG_ISP, 31, 0),
933
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_0, "gate_vi_shutter_0",
934
+
EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, CLK_SET_RATE_PARENT,
935
+
EIC7700_REG_OFFSET_VI_SHUTTER0, 31, 0),
936
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_1, "gate_vi_shutter_1",
937
+
EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, CLK_SET_RATE_PARENT,
938
+
EIC7700_REG_OFFSET_VI_SHUTTER1, 31, 0),
939
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_2, "gate_vi_shutter_2",
940
+
EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, CLK_SET_RATE_PARENT,
941
+
EIC7700_REG_OFFSET_VI_SHUTTER2, 31, 0),
942
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_3, "gate_vi_shutter_3",
943
+
EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, CLK_SET_RATE_PARENT,
944
+
EIC7700_REG_OFFSET_VI_SHUTTER3, 31, 0),
945
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_4, "gate_vi_shutter_4",
946
+
EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, CLK_SET_RATE_PARENT,
947
+
EIC7700_REG_OFFSET_VI_SHUTTER4, 31, 0),
948
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_5, "gate_vi_shutter_5",
949
+
EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, CLK_SET_RATE_PARENT,
950
+
EIC7700_REG_OFFSET_VI_SHUTTER5, 31, 0),
951
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_PHY_TXCLKESC,
952
+
"gate_vi_phy_txclkesc",
953
+
EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
954
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 0, 0),
955
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_ACLK, "gate_vo_aclk",
956
+
EIC7700_CLK_DIV_VO_ACLK_DYNM, CLK_SET_RATE_PARENT,
957
+
EIC7700_REG_OFFSET_VO_ACLK, 31, 0),
958
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CFG_CLK, "gate_vo_cfg_clk",
959
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
960
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 30, 0),
961
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_HDMI_IESMCLK,
962
+
"gate_vo_hdmi_iesmclk", EIC7700_CLK_DIV_IESMCLK_DYNM,
963
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_IESMCLK, 31,
964
+
0),
965
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_PIXEL_CLK, "gate_vo_pixel_clk",
966
+
EIC7700_CLK_DIV_VO_PIXEL_DYNM, CLK_SET_RATE_PARENT,
967
+
EIC7700_REG_OFFSET_VO_PIXEL, 31, 0),
968
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_I2S_MCLK, "gate_vo_i2s_mclk",
969
+
EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK,
970
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 31, 0),
971
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CR_CLK, "gate_vo_cr_clk",
972
+
EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
973
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_PHY_CLK, 1,
974
+
0),
975
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_ACLK, "gate_vc_aclk",
976
+
EIC7700_CLK_DIV_VC_ACLK_DYNM, CLK_SET_RATE_PARENT,
977
+
EIC7700_REG_OFFSET_VC_ACLK, 31, 0),
978
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_CFG_CLK, "gate_vc_cfg_clk",
979
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
980
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 0, 0),
981
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_CLK, "gate_vc_je_clk",
982
+
EIC7700_CLK_DIV_JE_DYNM, CLK_SET_RATE_PARENT,
983
+
EIC7700_REG_OFFSET_JE, 31, 0),
984
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_CLK, "gate_vc_jd_clk",
985
+
EIC7700_CLK_DIV_JD_DYNM, CLK_SET_RATE_PARENT,
986
+
EIC7700_REG_OFFSET_JD, 31, 0),
987
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_CLK, "gate_vc_ve_clk",
988
+
EIC7700_CLK_DIV_VE_DYNM, CLK_SET_RATE_PARENT,
989
+
EIC7700_REG_OFFSET_VE, 31, 0),
990
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_CLK, "gate_vc_vd_clk",
991
+
EIC7700_CLK_DIV_VD_DYNM, CLK_SET_RATE_PARENT,
992
+
EIC7700_REG_OFFSET_VD, 31, 0),
993
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CFG_CLK, "gate_g2d_cfg_clk",
994
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
995
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_G2D, 28, 0),
996
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CLK, "gate_g2d_clk",
997
+
EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT,
998
+
EIC7700_REG_OFFSET_G2D, 30, 0),
999
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_ACLK, "gate_g2d_aclk",
1000
+
EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT,
1001
+
EIC7700_REG_OFFSET_G2D, 31, 0),
1002
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_CFG, "gate_clk_aondma_cfg",
1003
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1004
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 30, 0),
1005
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_ACLK, "gate_aondma_aclk",
1006
+
EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
1007
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 31, 0),
1008
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_ACLK, "gate_aon_aclk",
1009
+
EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
1010
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 29, 0),
1011
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_0, "gate_timer_pclk_0",
1012
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1013
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 4, 0),
1014
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_1, "gate_timer_pclk_1",
1015
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1016
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 5, 0),
1017
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_2, "gate_timer_pclk_2",
1018
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1019
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 6, 0),
1020
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_3, "gate_timer_pclk_3",
1021
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1022
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 7, 0),
1023
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER3_CLK8, "gate_timer3_clk8",
1024
+
EIC7700_CLK_VPLL_FOUT3, CLK_SET_RATE_PARENT,
1025
+
EIC7700_REG_OFFSET_TIMER, 8, 0),
1026
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC_CFG, "gate_clk_rtc_cfg",
1027
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1028
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_RTC, 2, 0),
1029
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC, "gate_clk_rtc",
1030
+
EIC7700_CLK_DIV_AON_RTC_DYNM, CLK_SET_RATE_PARENT,
1031
+
EIC7700_REG_OFFSET_RTC, 1, 0),
1032
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_0, "gate_hsp_rmii_ref_0",
1033
+
EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT,
1034
+
EIC7700_REG_OFFSET_ETH0, 31, 0),
1035
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_1, "gate_hsp_rmii_ref_1",
1036
+
EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT,
1037
+
EIC7700_REG_OFFSET_ETH1, 31, 0),
1038
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PKA_CFG, "gate_clk_pka_cfg",
1039
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1040
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PKA, 31, 0),
1041
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPACC_CFG, "gate_clk_spacc_cfg",
1042
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1043
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SPACC, 31, 0),
1044
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CRYPTO, "gate_clk_crypto",
1045
+
EIC7700_CLK_DIV_CRYPTO_DYNM, CLK_SET_RATE_PARENT,
1046
+
EIC7700_REG_OFFSET_SPACC, 30, 0),
1047
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TRNG_CFG, "gate_clk_trng_cfg",
1048
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1049
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TRNG, 31, 0),
1050
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_OTP_CFG, "gate_clk_otp_cfg",
1051
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1052
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_OTP, 31, 0),
1053
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_0, "gate_clk_mailbox_0",
1054
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1055
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 0, 0),
1056
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_1, "gate_clk_mailbox_1",
1057
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1058
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 1, 0),
1059
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_2, "gate_clk_mailbox_2",
1060
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1061
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 2, 0),
1062
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_3, "gate_clk_mailbox_3",
1063
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1064
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 3, 0),
1065
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_4, "gate_clk_mailbox_4",
1066
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1067
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 4, 0),
1068
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_5, "gate_clk_mailbox_5",
1069
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1070
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 5, 0),
1071
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_6, "gate_clk_mailbox_6",
1072
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1073
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 6, 0),
1074
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_7, "gate_clk_mailbox_7",
1075
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1076
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 7, 0),
1077
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_8, "gate_clk_mailbox_8",
1078
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1079
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 8, 0),
1080
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_9, "gate_clk_mailbox_9",
1081
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1082
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 9, 0),
1083
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_10, "gate_clk_mailbox_10",
1084
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1085
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 10, 0),
1086
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_11, "gate_clk_mailbox_11",
1087
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1088
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 11, 0),
1089
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_12, "gate_clk_mailbox_12",
1090
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1091
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 12, 0),
1092
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_13, "gate_clk_mailbox_13",
1093
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1094
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 13, 0),
1095
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_14, "gate_clk_mailbox_14",
1096
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1097
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 14, 0),
1098
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_15, "gate_clk_mailbox_15",
1099
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1100
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 15, 0),
1101
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C0_PCLK, "gate_i2c0_pclk",
1102
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1103
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 7, 0),
1104
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C1_PCLK, "gate_i2c1_pclk",
1105
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1106
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 8, 0),
1107
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C2_PCLK, "gate_i2c2_pclk",
1108
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1109
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 9, 0),
1110
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C3_PCLK, "gate_i2c3_pclk",
1111
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1112
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 10, 0),
1113
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C4_PCLK, "gate_i2c4_pclk",
1114
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1115
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 11, 0),
1116
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C5_PCLK, "gate_i2c5_pclk",
1117
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1118
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 12, 0),
1119
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C6_PCLK, "gate_i2c6_pclk",
1120
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1121
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 13, 0),
1122
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C7_PCLK, "gate_i2c7_pclk",
1123
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1124
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 14, 0),
1125
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C8_PCLK, "gate_i2c8_pclk",
1126
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1127
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 15, 0),
1128
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C9_PCLK, "gate_i2c9_pclk",
1129
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1130
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 16, 0),
1131
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT0_PCLK, "gate_lsp_wdt0_pclk",
1132
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1133
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 28, 0),
1134
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT1_PCLK, "gate_lsp_wdt1_pclk",
1135
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1136
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 29, 0),
1137
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT2_PCLK, "gate_lsp_wdt2_pclk",
1138
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1139
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 30, 0),
1140
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT3_PCLK, "gate_lsp_wdt3_pclk",
1141
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1142
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 31, 0),
1143
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI0_PCLK, "gate_lsp_ssi0_pclk",
1144
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1145
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 26, 0),
1146
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI1_PCLK, "gate_lsp_ssi1_pclk",
1147
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1148
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 27, 0),
1149
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART0_PCLK, "gate_lsp_uart0_pclk",
1150
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1151
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1152
+
EIC7700_REG_OFFSET_LSP_EN0, 17, 0),
1153
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART1_PCLK, "gate_lsp_uart1_pclk",
1154
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1155
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 18, 0),
1156
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART2_PCLK, "gate_lsp_uart2_pclk",
1157
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1158
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1159
+
EIC7700_REG_OFFSET_LSP_EN0, 19, 0),
1160
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART3_PCLK, "gate_lsp_uart3_pclk",
1161
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1162
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 20, 0),
1163
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART4_PCLK, "gate_lsp_uart4_pclk",
1164
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1165
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 21, 0),
1166
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_TIMER_PCLK, "gate_lsp_timer_pclk",
1167
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1168
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1169
+
EIC7700_REG_OFFSET_LSP_EN0, 25, 0),
1170
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_FAN_PCLK, "gate_lsp_fan_pclk",
1171
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1172
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 0, 0),
1173
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT_PCLK, "gate_lsp_pvt_pclk",
1174
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1175
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 1, 0),
1176
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT0_CLK, "gate_pvt0_clk",
1177
+
EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT,
1178
+
EIC7700_REG_OFFSET_LSP_EN1, 16, 0),
1179
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT1_CLK, "gate_pvt1_clk",
1180
+
EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT,
1181
+
EIC7700_REG_OFFSET_LSP_EN1, 17, 0),
1182
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_PCLK, "gate_vc_je_pclk",
1183
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1184
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 2, 0),
1185
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_PCLK, "gate_vc_jd_pclk",
1186
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1187
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 1, 0),
1188
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_PCLK, "gate_vc_ve_pclk",
1189
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1190
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 5, 0),
1191
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_PCLK, "gate_vc_vd_pclk",
1192
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1193
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 4, 0),
1194
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_MON_PCLK, "gate_vc_mon_pclk",
1195
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1196
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 3, 0),
1197
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK,
1198
+
"gate_hsp_mshc0_core_clk",
1199
+
EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, CLK_SET_RATE_PARENT,
1200
+
EIC7700_REG_OFFSET_MSHC0_CORE, 16, 0),
1201
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK,
1202
+
"gate_hsp_mshc1_core_clk",
1203
+
EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, CLK_SET_RATE_PARENT,
1204
+
EIC7700_REG_OFFSET_MSHC1_CORE, 16, 0),
1205
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK,
1206
+
"gate_hsp_mshc2_core_clk",
1207
+
EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, CLK_SET_RATE_PARENT,
1208
+
EIC7700_REG_OFFSET_MSHC2_CORE, 16, 0),
1209
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_RBC_CLK,
1210
+
"gate_hsp_sata_rbc_clk", EIC7700_CLK_SPLL1_FOUT2,
1211
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_RBC,
1212
+
0, 0),
1213
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_OOB_CLK,
1214
+
"gate_hsp_sata_oob_clk", EIC7700_CLK_MUX_SATA_PHY_2MUX1,
1215
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 31,
1216
+
0),
1217
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST,
1218
+
"gate_hsp_dma0_clk_test", EIC7700_CLK_GATE_HSP_ACLK,
1219
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_ACLK, 1, 0),
1220
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK, "gate_hsp_dma0_clk",
1221
+
EIC7700_CLK_GATE_HSP_ACLK, CLK_SET_RATE_PARENT,
1222
+
EIC7700_REG_OFFSET_HSP_ACLK, 0, 0),
1223
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK,
1224
+
"gate_hsp_eth0_core_clk",
1225
+
EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, CLK_SET_RATE_PARENT,
1226
+
EIC7700_REG_OFFSET_ETH0, 0, 0),
1227
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK,
1228
+
"gate_hsp_eth1_core_clk",
1229
+
EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, CLK_SET_RATE_PARENT,
1230
+
EIC7700_REG_OFFSET_ETH1, 0, 0),
1231
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C0_PCLK, "gate_aon_i2c0_pclk",
1232
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1233
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C0, 31, 0),
1234
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C1_PCLK, "gate_aon_i2c1_pclk",
1235
+
EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
1236
+
CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C1, 31, 0),
1237
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR0_TRACE, "gate_ddr0_trace",
1238
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
1239
+
EIC7700_REG_OFFSET_DDR, 0, 0),
1240
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR1_TRACE, "gate_ddr1_trace",
1241
+
EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
1242
+
EIC7700_REG_OFFSET_DDR1, 0, 0),
1243
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RNOC_NSP, "gate_rnoc_nsp",
1244
+
EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT,
1245
+
EIC7700_REG_OFFSET_NOC, 29, 0),
1246
+
ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_WDREF, "gate_noc_wdref",
1247
+
EIC7700_CLK_DIV_NOC_WDREF_DYNM, CLK_SET_RATE_PARENT,
1248
+
EIC7700_REG_OFFSET_NOC, 30, 0),
1249
+
};
1250
+
1251
+
/*
1252
+
* This clock notifier is called when the rate of clk_pll_cpu clock is to be
1253
+
* changed. The mux_cpu_root_3mux1_gfree clock should save the current parent
1254
+
* clock and switch its parent clock to fixed_factor_u84_core_lp_div2 before
1255
+
* clk_pll_cpu rate will be changed. Then switch its parent clock back after
1256
+
* the clk_pll_cpu rate is completed.
1257
+
*/
1258
+
static int eic7700_clk_pll_cpu_notifier_cb(struct notifier_block *nb,
1259
+
unsigned long action, void *data)
1260
+
{
1261
+
struct eswin_clock_data *pdata;
1262
+
struct clk_hw *mux_clk;
1263
+
struct clk_hw *lp_clk;
1264
+
int ret = 0;
1265
+
1266
+
pdata = container_of(nb, struct eswin_clock_data, pll_nb);
1267
+
1268
+
mux_clk = &eic7700_mux_clks[0].hw;
1269
+
lp_clk = &eic7700_early_clks[11].hw;
1270
+
1271
+
if (action == PRE_RATE_CHANGE) {
1272
+
pdata->original_clk = clk_hw_get_parent(mux_clk);
1273
+
ret = clk_hw_set_parent(mux_clk, lp_clk);
1274
+
} else if (action == POST_RATE_CHANGE) {
1275
+
ret = clk_hw_set_parent(mux_clk, pdata->original_clk);
1276
+
}
1277
+
1278
+
return notifier_from_errno(ret);
1279
+
}
1280
+
1281
+
static int eic7700_clk_probe(struct platform_device *pdev)
1282
+
{
1283
+
struct eswin_clock_data *clk_data;
1284
+
struct device *dev = &pdev->dev;
1285
+
struct clk *pll_clk;
1286
+
int ret;
1287
+
1288
+
clk_data = eswin_clk_init(pdev, EIC7700_NR_CLKS);
1289
+
if (IS_ERR(clk_data))
1290
+
return dev_err_probe(dev, PTR_ERR(clk_data),
1291
+
"failed to get clk data!\n");
1292
+
1293
+
ret = eswin_clk_register_fixed_rate(dev, eic7700_fixed_rate_clks,
1294
+
ARRAY_SIZE(eic7700_fixed_rate_clks),
1295
+
clk_data);
1296
+
if (ret)
1297
+
return dev_err_probe(dev, ret,
1298
+
"failed to register fixed rate clock\n");
1299
+
1300
+
ret = eswin_clk_register_pll(dev, eic7700_pll_clks,
1301
+
ARRAY_SIZE(eic7700_pll_clks),
1302
+
clk_data);
1303
+
if (ret)
1304
+
return dev_err_probe(dev, ret,
1305
+
"failed to register pll clock\n");
1306
+
1307
+
pll_clk = devm_clk_hw_get_clk(dev, &eic7700_pll_clks[1].hw,
1308
+
"clk_pll_cpu");
1309
+
if (IS_ERR(pll_clk))
1310
+
return dev_err_probe(dev, PTR_ERR(pll_clk),
1311
+
"failed to get clk_pll_cpu\n");
1312
+
1313
+
clk_data->pll_nb.notifier_call = eic7700_clk_pll_cpu_notifier_cb;
1314
+
ret = devm_clk_notifier_register(dev, pll_clk, &clk_data->pll_nb);
1315
+
if (ret)
1316
+
return ret;
1317
+
1318
+
ret = eswin_clk_register_fixed_factor(dev, eic7700_factor_clks,
1319
+
ARRAY_SIZE(eic7700_factor_clks),
1320
+
clk_data);
1321
+
if (ret)
1322
+
return dev_err_probe(dev, ret,
1323
+
"failed to register fixed factor clock\n");
1324
+
1325
+
ret = eswin_clk_register_divider(dev, eic7700_div_clks,
1326
+
ARRAY_SIZE(eic7700_div_clks),
1327
+
clk_data);
1328
+
if (ret)
1329
+
return dev_err_probe(dev, ret,
1330
+
"failed to register divider clock\n");
1331
+
1332
+
ret = eswin_clk_register_gate(dev, eic7700_gate_clks,
1333
+
ARRAY_SIZE(eic7700_gate_clks), clk_data);
1334
+
if (ret)
1335
+
return dev_err_probe(dev, ret,
1336
+
"failed to register gate clock\n");
1337
+
1338
+
ret = eswin_clk_register_clks(dev, eic7700_early_clks,
1339
+
ARRAY_SIZE(eic7700_early_clks), clk_data);
1340
+
if (ret)
1341
+
return dev_err_probe(dev, ret, "failed to register clock\n");
1342
+
1343
+
ret = eswin_clk_register_mux(dev, eic7700_mux_clks,
1344
+
ARRAY_SIZE(eic7700_mux_clks), clk_data);
1345
+
if (ret)
1346
+
return dev_err_probe(dev, ret,
1347
+
"failed to register mux clock\n");
1348
+
1349
+
ret = eswin_clk_register_clks(dev, eic7700_clks,
1350
+
ARRAY_SIZE(eic7700_clks), clk_data);
1351
+
if (ret)
1352
+
return dev_err_probe(dev, ret, "failed to register clock\n");
1353
+
1354
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1355
+
&clk_data->clk_data);
1356
+
}
1357
+
1358
+
static const struct of_device_id eic7700_clock_dt_ids[] = {
1359
+
{ .compatible = "eswin,eic7700-clock", },
1360
+
{ /* sentinel */ }
1361
+
};
1362
+
MODULE_DEVICE_TABLE(of, eic7700_clock_dt_ids);
1363
+
1364
+
static struct platform_driver eic7700_clock_driver = {
1365
+
.probe = eic7700_clk_probe,
1366
+
.driver = {
1367
+
.name = "eic7700-clock",
1368
+
.of_match_table = eic7700_clock_dt_ids,
1369
+
},
1370
+
};
1371
+
module_platform_driver(eic7700_clock_driver);
1372
+
1373
+
MODULE_LICENSE("GPL");
1374
+
MODULE_AUTHOR("Yifeng Huang <huangyifeng@eswincomputing.com>");
1375
+
MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
1376
+
MODULE_DESCRIPTION("ESWIN EIC7700 clock controller driver");
+586
drivers/clk/eswin/clk.c
+586
drivers/clk/eswin/clk.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
4
+
* All rights reserved.
5
+
*
6
+
* Authors:
7
+
* Yifeng Huang <huangyifeng@eswincomputing.com>
8
+
* Xuyang Dong <dongxuyang@eswincomputing.com>
9
+
*/
10
+
11
+
#include <linux/bitfield.h>
12
+
#include <linux/clk-provider.h>
13
+
#include <linux/iopoll.h>
14
+
#include <linux/math.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/slab.h>
17
+
18
+
#include "common.h"
19
+
20
+
#define PLL_EN_MASK GENMASK(1, 0)
21
+
#define PLL_REFDIV_MASK GENMASK(17, 12)
22
+
#define PLL_FBDIV_MASK GENMASK(31, 20)
23
+
#define PLL_FRAC_MASK GENMASK(27, 4)
24
+
#define PLL_POSTDIV1_MASK GENMASK(10, 8)
25
+
#define PLL_POSTDIV2_MASK GENMASK(18, 16)
26
+
27
+
struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev,
28
+
size_t nr_clks)
29
+
{
30
+
struct eswin_clock_data *eclk_data;
31
+
32
+
eclk_data = devm_kzalloc(&pdev->dev,
33
+
struct_size(eclk_data, clk_data.hws, nr_clks),
34
+
GFP_KERNEL);
35
+
if (!eclk_data)
36
+
return ERR_PTR(-ENOMEM);
37
+
38
+
eclk_data->base = devm_platform_ioremap_resource(pdev, 0);
39
+
if (IS_ERR(eclk_data->base))
40
+
return ERR_PTR(-EINVAL);
41
+
42
+
eclk_data->clk_data.num = nr_clks;
43
+
spin_lock_init(&eclk_data->lock);
44
+
45
+
return eclk_data;
46
+
}
47
+
EXPORT_SYMBOL_GPL(eswin_clk_init);
48
+
49
+
/**
50
+
* eswin_calc_pll - calculate PLL values
51
+
* @frac_val: fractional divider
52
+
* @fbdiv_val: feedback divider
53
+
* @rate: reference rate
54
+
* @parent_rate: parent rate
55
+
*
56
+
* Calculate PLL values for frac and fbdiv:
57
+
* fbdiv = rate * 4 / parent_rate
58
+
* frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate
59
+
*/
60
+
static void eswin_calc_pll(u32 *frac_val, u32 *fbdiv_val, unsigned long rate,
61
+
unsigned long parent_rate)
62
+
{
63
+
u32 rem;
64
+
u64 tmp;
65
+
66
+
/* step 1: rate * 4 */
67
+
tmp = rate * 4;
68
+
/* step 2: use do_div() to get the quotient(tmp) and remainder(rem) */
69
+
rem = do_div(tmp, (u32)parent_rate);
70
+
/* fbdiv = rate * 4 / parent_rate */
71
+
*fbdiv_val = (u32)tmp;
72
+
/*
73
+
* step 3: rem << 24
74
+
* 24: 24-bit fractional accuracy
75
+
*/
76
+
tmp = (u64)rem << 24;
77
+
/* step 4: use do_div() to get the quotient(tmp) */
78
+
do_div(tmp, (u32)parent_rate);
79
+
/* frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate */
80
+
*frac_val = (u32)tmp;
81
+
}
82
+
83
+
static inline struct eswin_clk_pll *to_pll_clk(struct clk_hw *hw)
84
+
{
85
+
return container_of(hw, struct eswin_clk_pll, hw);
86
+
}
87
+
88
+
static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
89
+
unsigned long parent_rate)
90
+
{
91
+
struct eswin_clk_pll *clk = to_pll_clk(hw);
92
+
u32 frac_val, fbdiv_val, val, mask;
93
+
int ret;
94
+
95
+
eswin_calc_pll(&frac_val, &fbdiv_val, rate, parent_rate);
96
+
97
+
/* First, disable pll */
98
+
val = readl_relaxed(clk->ctrl_reg0);
99
+
val &= ~PLL_EN_MASK;
100
+
val |= FIELD_PREP(PLL_EN_MASK, 0);
101
+
writel_relaxed(val, clk->ctrl_reg0);
102
+
103
+
val = readl_relaxed(clk->ctrl_reg0);
104
+
val &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK);
105
+
val |= FIELD_PREP(PLL_FBDIV_MASK, fbdiv_val);
106
+
val |= FIELD_PREP(PLL_REFDIV_MASK, 1);
107
+
writel_relaxed(val, clk->ctrl_reg0);
108
+
109
+
val = readl_relaxed(clk->ctrl_reg1);
110
+
val &= ~PLL_FRAC_MASK;
111
+
val |= FIELD_PREP(PLL_FRAC_MASK, frac_val);
112
+
writel_relaxed(val, clk->ctrl_reg1);
113
+
114
+
val = readl_relaxed(clk->ctrl_reg2);
115
+
val &= ~(PLL_POSTDIV1_MASK | PLL_POSTDIV2_MASK);
116
+
val |= FIELD_PREP(PLL_POSTDIV1_MASK, 1);
117
+
val |= FIELD_PREP(PLL_POSTDIV2_MASK, 1);
118
+
writel_relaxed(val, clk->ctrl_reg2);
119
+
120
+
/* Last, enable pll */
121
+
val = readl_relaxed(clk->ctrl_reg0);
122
+
val &= ~PLL_EN_MASK;
123
+
val |= FIELD_PREP(PLL_EN_MASK, 1);
124
+
writel_relaxed(val, clk->ctrl_reg0);
125
+
126
+
/* Usually the pll will lock in 50us */
127
+
mask = GENMASK(clk->lock_shift + clk->lock_width - 1, clk->lock_shift);
128
+
ret = readl_poll_timeout(clk->status_reg, val, val & mask, 1, 50 * 2);
129
+
if (ret)
130
+
pr_err("failed to lock the pll!\n");
131
+
132
+
return ret;
133
+
}
134
+
135
+
static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
136
+
unsigned long parent_rate)
137
+
{
138
+
struct eswin_clk_pll *clk = to_pll_clk(hw);
139
+
u64 fbdiv_val, frac_val, tmp;
140
+
u32 rem, val;
141
+
142
+
val = readl_relaxed(clk->ctrl_reg0);
143
+
val &= PLL_FBDIV_MASK;
144
+
fbdiv_val = (val >> clk->fbdiv_shift);
145
+
146
+
val = readl_relaxed(clk->ctrl_reg1);
147
+
val &= PLL_FRAC_MASK;
148
+
frac_val = (val >> clk->frac_shift);
149
+
150
+
/* rate = 24000000 * (fbdiv + frac / (2 ^ 24)) / 4 */
151
+
tmp = parent_rate * frac_val;
152
+
rem = do_div(tmp, BIT(24));
153
+
if (rem)
154
+
tmp = parent_rate * fbdiv_val + tmp + 1;
155
+
else
156
+
tmp = parent_rate * fbdiv_val + tmp;
157
+
158
+
do_div(tmp, 4);
159
+
160
+
return tmp;
161
+
}
162
+
163
+
static int clk_pll_determine_rate(struct clk_hw *hw,
164
+
struct clk_rate_request *req)
165
+
{
166
+
struct eswin_clk_pll *clk = to_pll_clk(hw);
167
+
168
+
req->rate = clamp(req->rate, clk->min_rate, clk->max_rate);
169
+
req->min_rate = clk->min_rate;
170
+
req->max_rate = clk->max_rate;
171
+
172
+
return 0;
173
+
}
174
+
175
+
int eswin_clk_register_fixed_rate(struct device *dev,
176
+
struct eswin_fixed_rate_clock *clks,
177
+
int nums, struct eswin_clock_data *data)
178
+
{
179
+
struct clk_hw *clk_hw;
180
+
int i;
181
+
182
+
for (i = 0; i < nums; i++) {
183
+
clk_hw = devm_clk_hw_register_fixed_rate(dev, clks[i].name,
184
+
NULL, clks[i].flags,
185
+
clks[i].rate);
186
+
if (IS_ERR(clk_hw))
187
+
return PTR_ERR(clk_hw);
188
+
189
+
clks[i].hw = *clk_hw;
190
+
data->clk_data.hws[clks[i].id] = clk_hw;
191
+
}
192
+
193
+
return 0;
194
+
}
195
+
EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_rate);
196
+
197
+
static const struct clk_ops eswin_clk_pll_ops = {
198
+
.set_rate = clk_pll_set_rate,
199
+
.recalc_rate = clk_pll_recalc_rate,
200
+
.determine_rate = clk_pll_determine_rate,
201
+
};
202
+
203
+
int eswin_clk_register_pll(struct device *dev, struct eswin_pll_clock *clks,
204
+
int nums, struct eswin_clock_data *data)
205
+
{
206
+
struct eswin_clk_pll *p_clk = NULL;
207
+
struct clk_init_data init;
208
+
struct clk_hw *clk_hw;
209
+
int i, ret;
210
+
211
+
p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
212
+
if (!p_clk)
213
+
return -ENOMEM;
214
+
215
+
for (i = 0; i < nums; i++) {
216
+
p_clk->id = clks[i].id;
217
+
p_clk->ctrl_reg0 = data->base + clks[i].ctrl_reg0;
218
+
p_clk->fbdiv_shift = clks[i].fbdiv_shift;
219
+
220
+
p_clk->ctrl_reg1 = data->base + clks[i].ctrl_reg1;
221
+
p_clk->frac_shift = clks[i].frac_shift;
222
+
223
+
p_clk->ctrl_reg2 = data->base + clks[i].ctrl_reg2;
224
+
225
+
p_clk->status_reg = data->base + clks[i].status_reg;
226
+
p_clk->lock_shift = clks[i].lock_shift;
227
+
p_clk->lock_width = clks[i].lock_width;
228
+
229
+
p_clk->max_rate = clks[i].max_rate;
230
+
p_clk->min_rate = clks[i].min_rate;
231
+
232
+
init.name = clks[i].name;
233
+
init.flags = 0;
234
+
init.parent_data = clks[i].parent_data;
235
+
init.num_parents = 1;
236
+
init.ops = &eswin_clk_pll_ops;
237
+
p_clk->hw.init = &init;
238
+
239
+
clk_hw = &p_clk->hw;
240
+
241
+
ret = devm_clk_hw_register(dev, clk_hw);
242
+
if (ret)
243
+
return ret;
244
+
245
+
clks[i].hw = *clk_hw;
246
+
data->clk_data.hws[clks[i].id] = clk_hw;
247
+
p_clk++;
248
+
}
249
+
250
+
return 0;
251
+
}
252
+
EXPORT_SYMBOL_GPL(eswin_clk_register_pll);
253
+
254
+
int eswin_clk_register_fixed_factor(struct device *dev,
255
+
struct eswin_fixed_factor_clock *clks,
256
+
int nums, struct eswin_clock_data *data)
257
+
{
258
+
struct clk_hw *clk_hw;
259
+
int i;
260
+
261
+
for (i = 0; i < nums; i++) {
262
+
clk_hw = devm_clk_hw_register_fixed_factor_index(dev, clks[i].name,
263
+
clks[i].parent_data->index,
264
+
clks[i].flags, clks[i].mult,
265
+
clks[i].div);
266
+
267
+
if (IS_ERR(clk_hw))
268
+
return PTR_ERR(clk_hw);
269
+
270
+
clks[i].hw = *clk_hw;
271
+
data->clk_data.hws[clks[i].id] = clk_hw;
272
+
}
273
+
274
+
return 0;
275
+
}
276
+
EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_factor);
277
+
278
+
int eswin_clk_register_mux(struct device *dev, struct eswin_mux_clock *clks,
279
+
int nums, struct eswin_clock_data *data)
280
+
{
281
+
struct clk_hw *clk_hw;
282
+
int i;
283
+
284
+
for (i = 0; i < nums; i++) {
285
+
clk_hw = devm_clk_hw_register_mux_parent_data_table(dev, clks[i].name,
286
+
clks[i].parent_data,
287
+
clks[i].num_parents,
288
+
clks[i].flags,
289
+
data->base + clks[i].reg,
290
+
clks[i].shift, clks[i].width,
291
+
clks[i].mux_flags,
292
+
clks[i].table, &data->lock);
293
+
294
+
if (IS_ERR(clk_hw))
295
+
return PTR_ERR(clk_hw);
296
+
297
+
clks[i].hw = *clk_hw;
298
+
data->clk_data.hws[clks[i].id] = clk_hw;
299
+
}
300
+
301
+
return 0;
302
+
}
303
+
EXPORT_SYMBOL_GPL(eswin_clk_register_mux);
304
+
305
+
static unsigned int _eswin_get_val(unsigned int div, unsigned long flags,
306
+
u8 width)
307
+
{
308
+
unsigned int maxdiv;
309
+
310
+
maxdiv = clk_div_mask(width);
311
+
div = div > maxdiv ? maxdiv : div;
312
+
313
+
if (flags & ESWIN_PRIV_DIV_MIN_2)
314
+
return (div < 2) ? 2 : div;
315
+
316
+
return div;
317
+
}
318
+
319
+
static unsigned int eswin_div_get_val(unsigned long rate,
320
+
unsigned long parent_rate, u8 width,
321
+
unsigned long flags)
322
+
{
323
+
unsigned int div;
324
+
325
+
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
326
+
327
+
return _eswin_get_val(div, flags, width);
328
+
}
329
+
330
+
static inline struct eswin_divider_clock *to_div_clk(struct clk_hw *hw)
331
+
{
332
+
return container_of(hw, struct eswin_divider_clock, hw);
333
+
}
334
+
335
+
static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
336
+
unsigned long parent_rate)
337
+
{
338
+
struct eswin_divider_clock *dclk = to_div_clk(hw);
339
+
unsigned long flags;
340
+
unsigned int value;
341
+
u32 val;
342
+
343
+
value = eswin_div_get_val(rate, parent_rate, dclk->width,
344
+
dclk->priv_flag);
345
+
346
+
spin_lock_irqsave(dclk->lock, flags);
347
+
348
+
val = readl_relaxed(dclk->ctrl_reg);
349
+
val &= ~(clk_div_mask(dclk->width) << dclk->shift);
350
+
val |= (u32)value << dclk->shift;
351
+
writel_relaxed(val, dclk->ctrl_reg);
352
+
353
+
spin_unlock_irqrestore(dclk->lock, flags);
354
+
355
+
return 0;
356
+
}
357
+
358
+
static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
359
+
unsigned long parent_rate)
360
+
{
361
+
struct eswin_divider_clock *dclk = to_div_clk(hw);
362
+
unsigned int div, val;
363
+
364
+
val = readl_relaxed(dclk->ctrl_reg) >> dclk->shift;
365
+
val &= clk_div_mask(dclk->width);
366
+
div = _eswin_get_val(val, dclk->priv_flag, dclk->width);
367
+
368
+
return DIV_ROUND_UP_ULL((u64)parent_rate, div);
369
+
}
370
+
371
+
static int eswin_clk_bestdiv(unsigned long rate,
372
+
unsigned long best_parent_rate, u8 width,
373
+
unsigned long flags)
374
+
{
375
+
unsigned long bestdiv, up_rate, down_rate;
376
+
int up, down;
377
+
378
+
if (!rate)
379
+
rate = 1;
380
+
381
+
/* closest round */
382
+
up = DIV_ROUND_UP_ULL((u64)best_parent_rate, rate);
383
+
down = best_parent_rate / rate;
384
+
385
+
up_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, up);
386
+
down_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, down);
387
+
388
+
bestdiv = (rate - up_rate) <= (down_rate - rate) ? up : down;
389
+
390
+
return bestdiv;
391
+
}
392
+
393
+
static int clk_div_determine_rate(struct clk_hw *hw,
394
+
struct clk_rate_request *req)
395
+
{
396
+
struct eswin_divider_clock *dclk = to_div_clk(hw);
397
+
int div;
398
+
399
+
div = eswin_clk_bestdiv(req->rate, req->best_parent_rate, dclk->width,
400
+
dclk->priv_flag);
401
+
div = _eswin_get_val(div, dclk->priv_flag, dclk->width);
402
+
req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
403
+
404
+
return 0;
405
+
}
406
+
407
+
static const struct clk_ops eswin_clk_div_ops = {
408
+
.set_rate = clk_div_set_rate,
409
+
.recalc_rate = clk_div_recalc_rate,
410
+
.determine_rate = clk_div_determine_rate,
411
+
};
412
+
413
+
struct clk_hw *eswin_register_clkdiv(struct device *dev, unsigned int id,
414
+
const char *name,
415
+
const struct clk_hw *parent_hw,
416
+
unsigned long flags, void __iomem *reg,
417
+
u8 shift, u8 width,
418
+
unsigned long clk_divider_flags,
419
+
unsigned long priv_flag, spinlock_t *lock)
420
+
{
421
+
struct eswin_divider_clock *dclk;
422
+
struct clk_init_data init;
423
+
struct clk_hw *clk_hw;
424
+
int ret;
425
+
426
+
dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
427
+
if (!dclk)
428
+
return ERR_PTR(-ENOMEM);
429
+
430
+
init.name = name;
431
+
init.ops = &eswin_clk_div_ops;
432
+
init.flags = flags;
433
+
init.parent_hws = &parent_hw;
434
+
init.num_parents = 1;
435
+
436
+
/* struct clk_divider assignments */
437
+
dclk->id = id;
438
+
dclk->ctrl_reg = reg;
439
+
dclk->shift = shift;
440
+
dclk->width = width;
441
+
dclk->div_flags = clk_divider_flags;
442
+
dclk->priv_flag = priv_flag;
443
+
dclk->lock = lock;
444
+
dclk->hw.init = &init;
445
+
446
+
/* register the clock */
447
+
clk_hw = &dclk->hw;
448
+
ret = devm_clk_hw_register(dev, clk_hw);
449
+
if (ret) {
450
+
dev_err(dev, "failed to register divider clock!\n");
451
+
return ERR_PTR(ret);
452
+
}
453
+
454
+
return clk_hw;
455
+
}
456
+
EXPORT_SYMBOL_GPL(eswin_register_clkdiv);
457
+
458
+
int eswin_clk_register_divider(struct device *dev,
459
+
struct eswin_divider_clock *clks,
460
+
int nums, struct eswin_clock_data *data)
461
+
{
462
+
struct clk_hw *clk_hw;
463
+
int i;
464
+
465
+
for (i = 0; i < nums; i++) {
466
+
clk_hw = devm_clk_hw_register_divider_parent_data(dev, clks[i].name,
467
+
clks[i].parent_data,
468
+
clks[i].flags,
469
+
data->base + clks[i].reg,
470
+
clks[i].shift, clks[i].width,
471
+
clks[i].div_flags, &data->lock);
472
+
473
+
if (IS_ERR(clk_hw))
474
+
return PTR_ERR(clk_hw);
475
+
476
+
clks[i].hw = *clk_hw;
477
+
data->clk_data.hws[clks[i].id] = clk_hw;
478
+
}
479
+
480
+
return 0;
481
+
}
482
+
EXPORT_SYMBOL_GPL(eswin_clk_register_divider);
483
+
484
+
int eswin_clk_register_gate(struct device *dev, struct eswin_gate_clock *clks,
485
+
int nums, struct eswin_clock_data *data)
486
+
{
487
+
struct clk_hw *clk_hw;
488
+
int i;
489
+
490
+
for (i = 0; i < nums; i++) {
491
+
clk_hw = devm_clk_hw_register_gate_parent_data(dev, clks[i].name,
492
+
clks[i].parent_data,
493
+
clks[i].flags,
494
+
data->base + clks[i].reg,
495
+
clks[i].bit_idx, clks[i].gate_flags,
496
+
&data->lock);
497
+
498
+
if (IS_ERR(clk_hw))
499
+
return PTR_ERR(clk_hw);
500
+
501
+
clks[i].hw = *clk_hw;
502
+
data->clk_data.hws[clks[i].id] = clk_hw;
503
+
}
504
+
505
+
return 0;
506
+
}
507
+
EXPORT_SYMBOL_GPL(eswin_clk_register_gate);
508
+
509
+
int eswin_clk_register_clks(struct device *dev, struct eswin_clk_info *clks,
510
+
int nums, struct eswin_clock_data *data)
511
+
{
512
+
struct eswin_clk_info *info;
513
+
const struct clk_hw *phw = NULL;
514
+
struct clk_hw *hw;
515
+
int i;
516
+
517
+
for (i = 0; i < nums; i++) {
518
+
info = &clks[i];
519
+
switch (info->type) {
520
+
case CLK_FIXED_FACTOR: {
521
+
const struct eswin_fixed_factor_clock *factor;
522
+
523
+
factor = &info->data.factor;
524
+
phw = data->clk_data.hws[info->pid];
525
+
hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, factor->name, phw,
526
+
factor->flags,
527
+
factor->mult,
528
+
factor->div);
529
+
break;
530
+
}
531
+
case CLK_MUX: {
532
+
const struct eswin_mux_clock *mux = &info->data.mux;
533
+
534
+
hw = devm_clk_hw_register_mux_parent_data_table(dev, mux->name,
535
+
mux->parent_data,
536
+
mux->num_parents,
537
+
mux->flags,
538
+
data->base + mux->reg,
539
+
mux->shift, mux->width,
540
+
mux->mux_flags,
541
+
mux->table, &data->lock);
542
+
break;
543
+
}
544
+
case CLK_DIVIDER: {
545
+
const struct eswin_divider_clock *div = &info->data.div;
546
+
547
+
phw = data->clk_data.hws[info->pid];
548
+
if (div->priv_flag)
549
+
hw = eswin_register_clkdiv(dev, div->id, div->name, phw,
550
+
div->flags, data->base + div->reg,
551
+
div->shift, div->width, div->div_flags,
552
+
div->priv_flag, &data->lock);
553
+
else
554
+
hw = devm_clk_hw_register_divider_parent_hw(dev, div->name, phw,
555
+
div->flags,
556
+
data->base + div->reg,
557
+
div->shift, div->width,
558
+
div->div_flags,
559
+
&data->lock);
560
+
break;
561
+
}
562
+
case CLK_GATE: {
563
+
const struct eswin_gate_clock *gate = &info->data.gate;
564
+
565
+
phw = data->clk_data.hws[info->pid];
566
+
hw = devm_clk_hw_register_gate_parent_hw(dev, gate->name, phw,
567
+
gate->flags,
568
+
data->base + gate->reg,
569
+
gate->bit_idx, gate->gate_flags,
570
+
&data->lock);
571
+
break;
572
+
}
573
+
default:
574
+
dev_err(dev, "Unidentifiable clock type!\n");
575
+
return -EINVAL;
576
+
}
577
+
if (IS_ERR(hw))
578
+
return PTR_ERR(hw);
579
+
580
+
info->hw = *hw;
581
+
data->clk_data.hws[info->id] = hw;
582
+
}
583
+
584
+
return 0;
585
+
}
586
+
EXPORT_SYMBOL_GPL(eswin_clk_register_clks);
+340
drivers/clk/eswin/common.h
+340
drivers/clk/eswin/common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
4
+
* All rights reserved.
5
+
*
6
+
* Authors:
7
+
* Yifeng Huang <huangyifeng@eswincomputing.com>
8
+
* Xuyang Dong <dongxuyang@eswincomputing.com>
9
+
*/
10
+
11
+
#ifndef __ESWIN_COMMON_H__
12
+
#define __ESWIN_COMMON_H__
13
+
14
+
#define APLL_HIGH_FREQ 983040000
15
+
#define APLL_LOW_FREQ 225792000
16
+
#define PLL_HIGH_FREQ 1800000000
17
+
#define PLL_LOW_FREQ 24000000
18
+
19
+
/*
20
+
* ESWIN_PRIV_DIV_MIN_2: If ESWIN_PRIV_DIV_MIN_2 is set, the minimum value of
21
+
* the register is 2, i.e. the minimum division ratio is 2.
22
+
*/
23
+
#define ESWIN_PRIV_DIV_MIN_2 BIT(0)
24
+
25
+
enum eswin_clk_type {
26
+
CLK_FIXED_FACTOR,
27
+
CLK_MUX,
28
+
CLK_DIVIDER,
29
+
CLK_GATE,
30
+
};
31
+
32
+
struct eswin_clock_data {
33
+
void __iomem *base;
34
+
struct clk_hw *original_clk;
35
+
struct notifier_block pll_nb;
36
+
spinlock_t lock; /* protect register read-modify-write cycle */
37
+
struct clk_hw_onecell_data clk_data;
38
+
};
39
+
40
+
struct eswin_divider_clock {
41
+
struct clk_hw hw;
42
+
unsigned int id;
43
+
const char *name;
44
+
const struct clk_parent_data *parent_data;
45
+
void __iomem *ctrl_reg; /* register address of the divider clock */
46
+
unsigned long flags;
47
+
unsigned long reg; /* register offset */
48
+
u8 shift;
49
+
u8 width;
50
+
unsigned long div_flags;
51
+
unsigned long priv_flag;
52
+
spinlock_t *lock; /* protect register read-modify-write cycle */
53
+
};
54
+
55
+
struct eswin_fixed_rate_clock {
56
+
struct clk_hw hw;
57
+
unsigned int id;
58
+
const char *name;
59
+
unsigned long flags;
60
+
unsigned long rate;
61
+
};
62
+
63
+
struct eswin_fixed_factor_clock {
64
+
struct clk_hw hw;
65
+
unsigned int id;
66
+
const char *name;
67
+
const struct clk_parent_data *parent_data;
68
+
unsigned long mult;
69
+
unsigned long div;
70
+
unsigned long flags;
71
+
};
72
+
73
+
struct eswin_gate_clock {
74
+
struct clk_hw hw;
75
+
unsigned int id;
76
+
const char *name;
77
+
const struct clk_parent_data *parent_data;
78
+
unsigned long flags;
79
+
unsigned long reg;
80
+
u8 bit_idx;
81
+
u8 gate_flags;
82
+
};
83
+
84
+
struct eswin_mux_clock {
85
+
struct clk_hw hw;
86
+
unsigned int id;
87
+
const char *name;
88
+
const struct clk_parent_data *parent_data;
89
+
u8 num_parents;
90
+
unsigned long flags;
91
+
unsigned long reg;
92
+
u8 shift;
93
+
u8 width;
94
+
u8 mux_flags;
95
+
u32 *table;
96
+
};
97
+
98
+
struct eswin_pll_clock {
99
+
struct clk_hw hw;
100
+
u32 id;
101
+
const char *name;
102
+
const struct clk_parent_data *parent_data;
103
+
const u32 ctrl_reg0;
104
+
const u8 fbdiv_shift;
105
+
106
+
const u32 ctrl_reg1;
107
+
const u8 frac_shift;
108
+
109
+
const u32 ctrl_reg2;
110
+
111
+
const u32 status_reg;
112
+
const u8 lock_shift;
113
+
const u8 lock_width;
114
+
115
+
const u64 max_rate;
116
+
const u64 min_rate;
117
+
};
118
+
119
+
struct eswin_clk_pll {
120
+
struct clk_hw hw;
121
+
u32 id;
122
+
void __iomem *ctrl_reg0;
123
+
u8 fbdiv_shift;
124
+
125
+
void __iomem *ctrl_reg1;
126
+
u8 frac_shift;
127
+
128
+
void __iomem *ctrl_reg2;
129
+
130
+
void __iomem *status_reg;
131
+
u8 lock_shift;
132
+
u8 lock_width;
133
+
134
+
u64 max_rate;
135
+
u64 min_rate;
136
+
};
137
+
138
+
struct eswin_clk_info {
139
+
unsigned int type;
140
+
unsigned int pid;
141
+
unsigned int id;
142
+
struct clk_hw hw;
143
+
union {
144
+
struct eswin_divider_clock div;
145
+
struct eswin_fixed_factor_clock factor;
146
+
struct eswin_gate_clock gate;
147
+
struct eswin_mux_clock mux;
148
+
} data;
149
+
};
150
+
151
+
struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev,
152
+
size_t nr_clks);
153
+
int eswin_clk_register_fixed_rate(struct device *dev,
154
+
struct eswin_fixed_rate_clock *clks,
155
+
int nums, struct eswin_clock_data *data);
156
+
int eswin_clk_register_pll(struct device *dev, struct eswin_pll_clock *clks,
157
+
int nums, struct eswin_clock_data *data);
158
+
int eswin_clk_register_fixed_factor(struct device *dev,
159
+
struct eswin_fixed_factor_clock *clks,
160
+
int nums, struct eswin_clock_data *data);
161
+
int eswin_clk_register_mux(struct device *dev, struct eswin_mux_clock *clks,
162
+
int nums, struct eswin_clock_data *data);
163
+
int eswin_clk_register_divider(struct device *dev,
164
+
struct eswin_divider_clock *clks,
165
+
int nums, struct eswin_clock_data *data);
166
+
int eswin_clk_register_gate(struct device *dev, struct eswin_gate_clock *clks,
167
+
int nums, struct eswin_clock_data *data);
168
+
int eswin_clk_register_clks(struct device *dev, struct eswin_clk_info *clks,
169
+
int nums, struct eswin_clock_data *data);
170
+
struct clk_hw *eswin_register_clkdiv(struct device *dev, unsigned int id,
171
+
const char *name,
172
+
const struct clk_hw *parent_hw,
173
+
unsigned long flags, void __iomem *reg,
174
+
u8 shift, u8 width,
175
+
unsigned long clk_divider_flags,
176
+
unsigned long priv_flag, spinlock_t *lock);
177
+
178
+
#define ESWIN_DIV(_id, _name, _pdata, _flags, _reg, _shift, _width, \
179
+
_dflags, _pflag) \
180
+
{ \
181
+
.id = _id, \
182
+
.name = _name, \
183
+
.parent_data = _pdata, \
184
+
.flags = _flags, \
185
+
.reg = _reg, \
186
+
.shift = _shift, \
187
+
.width = _width, \
188
+
.div_flags = _dflags, \
189
+
.priv_flag = _pflag, \
190
+
}
191
+
192
+
#define ESWIN_DIV_TYPE(_id, _name, _pid, _flags, _reg, _shift, _width, \
193
+
_dflags, _pflag) \
194
+
{ \
195
+
.type = CLK_DIVIDER, \
196
+
.pid = _pid, \
197
+
.id = _id, \
198
+
.data = { \
199
+
.div = { \
200
+
.name = _name, \
201
+
.flags = _flags, \
202
+
.reg = _reg, \
203
+
.shift = _shift, \
204
+
.width = _width, \
205
+
.div_flags = _dflags, \
206
+
.priv_flag = _pflag, \
207
+
}, \
208
+
}, \
209
+
}
210
+
211
+
#define ESWIN_FACTOR(_id, _name, _pdata, _mult, _div, _flags) \
212
+
{ \
213
+
.id = _id, \
214
+
.name = _name, \
215
+
.parent_data = _pdata, \
216
+
.mult = _mult, \
217
+
.div = _div, \
218
+
.flags = _flags, \
219
+
}
220
+
221
+
#define ESWIN_FACTOR_TYPE(_id, _name, _pid, _mult, _div, _flags) \
222
+
{ \
223
+
.type = CLK_FIXED_FACTOR, \
224
+
.pid = _pid, \
225
+
.id = _id, \
226
+
.data = { \
227
+
.factor = { \
228
+
.name = _name, \
229
+
.mult = _mult, \
230
+
.div = _div, \
231
+
.flags = _flags, \
232
+
}, \
233
+
}, \
234
+
}
235
+
236
+
#define ESWIN_FIXED(_id, _name, _flags, _rate) \
237
+
{ \
238
+
.id = _id, \
239
+
.name = _name, \
240
+
.flags = _flags, \
241
+
.rate = _rate, \
242
+
}
243
+
244
+
#define ESWIN_GATE(_id, _name, _pdata, _flags, _reg, _idx, _gflags) \
245
+
{ \
246
+
.id = _id, \
247
+
.name = _name, \
248
+
.parent_data = _pdata, \
249
+
.flags = _flags, \
250
+
.reg = _reg, \
251
+
.bit_idx = _idx, \
252
+
.gate_flags = _gflags, \
253
+
}
254
+
255
+
#define ESWIN_GATE_TYPE(_id, _name, _pid, _flags, _reg, _idx, _gflags) \
256
+
{ \
257
+
.type = CLK_GATE, \
258
+
.pid = _pid, \
259
+
.id = _id, \
260
+
.data = { \
261
+
.gate = { \
262
+
.name = _name, \
263
+
.flags = _flags, \
264
+
.reg = _reg, \
265
+
.bit_idx = _idx, \
266
+
.gate_flags = _gflags, \
267
+
}, \
268
+
}, \
269
+
}
270
+
271
+
#define ESWIN_MUX(_id, _name, _pdata, _num_parents, _flags, _reg, \
272
+
_shift, _width, _mflags) \
273
+
{ \
274
+
.id = _id, \
275
+
.name = _name, \
276
+
.parent_data = _pdata, \
277
+
.num_parents = _num_parents, \
278
+
.flags = _flags, \
279
+
.reg = _reg, \
280
+
.shift = _shift, \
281
+
.width = _width, \
282
+
.mux_flags = _mflags, \
283
+
.table = NULL, \
284
+
}
285
+
286
+
#define ESWIN_MUX_TBL(_id, _name, _pdata, _num_parents, _flags, _reg, \
287
+
_shift, _width, _mflags, _table) \
288
+
{ \
289
+
.id = _id, \
290
+
.name = _name, \
291
+
.parent_data = _pdata, \
292
+
.num_parents = _num_parents, \
293
+
.flags = _flags, \
294
+
.reg = _reg, \
295
+
.shift = _shift, \
296
+
.width = _width, \
297
+
.mux_flags = _mflags, \
298
+
.table = _table, \
299
+
}
300
+
301
+
#define ESWIN_MUX_TYPE(_id, _name, _pdata, _num_parents, _flags, _reg, \
302
+
_shift, _width, _mflags, _table) \
303
+
{ \
304
+
.type = CLK_MUX, \
305
+
.id = _id, \
306
+
.data = { \
307
+
.mux = { \
308
+
.name = _name, \
309
+
.parent_data = _pdata, \
310
+
.num_parents = _num_parents, \
311
+
.flags = _flags, \
312
+
.reg = _reg, \
313
+
.shift = _shift, \
314
+
.width = _width, \
315
+
.mux_flags = _mflags, \
316
+
.table = _table, \
317
+
}, \
318
+
}, \
319
+
}
320
+
321
+
#define ESWIN_PLL(_id, _name, _pdata, _reg0, _fb_shift, _reg1, \
322
+
_frac_shift, _reg2, _reg, _lock_shift, _lock_width, \
323
+
_max_rate, _min_rate) \
324
+
{ \
325
+
.id = _id, \
326
+
.name = _name, \
327
+
.parent_data = _pdata, \
328
+
.ctrl_reg0 = _reg0, \
329
+
.fbdiv_shift = _fb_shift, \
330
+
.ctrl_reg1 = _reg1, \
331
+
.frac_shift = _frac_shift, \
332
+
.ctrl_reg2 = _reg2, \
333
+
.status_reg = _reg, \
334
+
.lock_shift = _lock_shift, \
335
+
.lock_width = _lock_width, \
336
+
.max_rate = _max_rate, \
337
+
.min_rate = _min_rate, \
338
+
}
339
+
340
+
#endif /* __ESWIN_COMMON_H__ */
+6
-1
drivers/clk/renesas/Kconfig
+6
-1
drivers/clk/renesas/Kconfig
···
39
39
select CLK_R9A07G044 if ARCH_R9A07G044
40
40
select CLK_R9A07G054 if ARCH_R9A07G054
41
41
select CLK_R9A08G045 if ARCH_R9A08G045
42
+
select CLK_R9A08G046 if ARCH_R9A08G046
42
43
select CLK_R9A09G011 if ARCH_R9A09G011
43
44
select CLK_R9A09G047 if ARCH_R9A09G047
44
45
select CLK_R9A09G056 if ARCH_R9A09G056
···
195
194
bool "RZ/G3S clock support" if COMPILE_TEST
196
195
select CLK_RZG2L
197
196
197
+
config CLK_R9A08G046
198
+
bool "RZ/G3L clock support" if COMPILE_TEST
199
+
select CLK_RZG2L
200
+
198
201
config CLK_R9A09G011
199
202
bool "RZ/V2M clock support" if COMPILE_TEST
200
203
select CLK_RZG2L
···
255
250
This is a driver for R-Car USB2 clock selector
256
251
257
252
config CLK_RZG2L
258
-
bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
253
+
bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST
259
254
select RESET_CONTROLLER
260
255
261
256
config CLK_RZV2H
+1
drivers/clk/renesas/Makefile
+1
drivers/clk/renesas/Makefile
···
36
36
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
37
37
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
38
38
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
39
+
obj-$(CONFIG_CLK_R9A08G046) += r9a08g046-cpg.o
39
40
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
40
41
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
41
42
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
+3
-2
drivers/clk/renesas/r9a06g032-clocks.c
+3
-2
drivers/clk/renesas/r9a06g032-clocks.c
···
1342
1342
/* Clear potentially pending resets */
1343
1343
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
1344
1344
clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
1345
-
/* Allow software reset */
1346
-
writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
1345
+
/* Allow watchdog and software resets */
1346
+
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1 |
1347
+
R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
1347
1348
clocks->reg + R9A06G032_SYSCTRL_RSTEN);
1348
1349
1349
1350
error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
+9
drivers/clk/renesas/r9a07g043-cpg.c
+9
drivers/clk/renesas/r9a07g043-cpg.c
···
379
379
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
380
380
};
381
381
382
+
static const unsigned int r9a07g043_crit_resets[] = {
383
+
R9A07G043_DMAC_ARESETN,
384
+
R9A07G043_DMAC_RST_ASYNC,
385
+
};
386
+
382
387
#ifdef CONFIG_ARM64
383
388
static const unsigned int r9a07g043_no_pm_mod_clks[] = {
384
389
MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
···
424
419
#ifdef CONFIG_RISCV
425
420
.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
426
421
#endif
422
+
423
+
/* Critical Resets */
424
+
.crit_resets = r9a07g043_crit_resets,
425
+
.num_crit_resets = ARRAY_SIZE(r9a07g043_crit_resets),
427
426
428
427
.has_clk_mon_regs = true,
429
428
};
+13
drivers/clk/renesas/r9a07g044-cpg.c
+13
drivers/clk/renesas/r9a07g044-cpg.c
···
489
489
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
490
490
};
491
491
492
+
static const unsigned int r9a07g044_crit_resets[] = {
493
+
R9A07G044_DMAC_ARESETN,
494
+
R9A07G044_DMAC_RST_ASYNC,
495
+
};
496
+
492
497
static const unsigned int r9a07g044_no_pm_mod_clks[] = {
493
498
MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
494
499
MOD_CLK_BASE + R9A07G044_CRU_VCLK,
···
524
519
.resets = r9a07g044_resets,
525
520
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
526
521
522
+
/* Critical Resets */
523
+
.crit_resets = r9a07g044_crit_resets,
524
+
.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
525
+
527
526
.has_clk_mon_regs = true,
528
527
};
529
528
#endif
···
556
547
/* Resets */
557
548
.resets = r9a07g044_resets,
558
549
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
550
+
551
+
/* Critical Resets */
552
+
.crit_resets = r9a07g044_crit_resets,
553
+
.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
559
554
560
555
.has_clk_mon_regs = true,
561
556
};
+9
drivers/clk/renesas/r9a08g045-cpg.c
+9
drivers/clk/renesas/r9a08g045-cpg.c
···
361
361
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
362
362
};
363
363
364
+
static const unsigned int r9a08g045_crit_resets[] = {
365
+
R9A08G045_DMAC_ARESETN,
366
+
R9A08G045_DMAC_RST_ASYNC,
367
+
};
368
+
364
369
static const unsigned int r9a08g045_no_pm_mod_clks[] = {
365
370
MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,
366
371
};
···
393
388
/* Resets */
394
389
.resets = r9a08g045_resets,
395
390
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
391
+
392
+
/* Critical Resets */
393
+
.crit_resets = r9a08g045_crit_resets,
394
+
.num_crit_resets = ARRAY_SIZE(r9a08g045_crit_resets),
396
395
397
396
.has_clk_mon_regs = true,
398
397
};
+153
drivers/clk/renesas/r9a08g046-cpg.c
+153
drivers/clk/renesas/r9a08g046-cpg.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* RZ/G3L CPG driver
4
+
*
5
+
* Copyright (C) 2026 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/device.h>
10
+
#include <linux/init.h>
11
+
#include <linux/kernel.h>
12
+
13
+
#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
14
+
15
+
#include "rzg2l-cpg.h"
16
+
17
+
/* RZ/G3L Specific registers. */
18
+
#define G3L_CPG_PL2_DDIV (0x204)
19
+
#define G3L_CPG_PL3_DDIV (0x208)
20
+
#define G3L_CLKDIVSTATUS (0x280)
21
+
22
+
/* RZ/G3L Specific division configuration. */
23
+
#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
24
+
#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
25
+
#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
26
+
27
+
/* RZ/G3L Clock status configuration. */
28
+
#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
29
+
#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
30
+
#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
31
+
32
+
enum clk_ids {
33
+
/* Core Clock Outputs exported to DT */
34
+
LAST_DT_CORE_CLK = R9A08G046_USB_SCLK,
35
+
36
+
/* External Input Clocks */
37
+
CLK_EXTAL,
38
+
CLK_ETH0_TXC_TX_CLK_IN,
39
+
CLK_ETH0_RXC_RX_CLK_IN,
40
+
CLK_ETH1_TXC_TX_CLK_IN,
41
+
CLK_ETH1_RXC_RX_CLK_IN,
42
+
43
+
/* Internal Core Clocks */
44
+
CLK_PLL2,
45
+
CLK_PLL2_DIV2,
46
+
CLK_PLL3,
47
+
CLK_PLL3_DIV2,
48
+
49
+
/* Module Clocks */
50
+
MOD_CLK_BASE,
51
+
};
52
+
53
+
/* Divider tables */
54
+
static const struct clk_div_table dtable_4_128[] = {
55
+
{ 0, 4 },
56
+
{ 1, 8 },
57
+
{ 2, 16 },
58
+
{ 3, 128 },
59
+
{ 0, 0 },
60
+
};
61
+
62
+
static const struct clk_div_table dtable_8_256[] = {
63
+
{ 0, 8 },
64
+
{ 1, 16 },
65
+
{ 2, 32 },
66
+
{ 3, 256 },
67
+
{ 0, 0 },
68
+
};
69
+
70
+
static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
71
+
/* External Clock Inputs */
72
+
DEF_INPUT("extal", CLK_EXTAL),
73
+
DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN),
74
+
DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN),
75
+
DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN),
76
+
DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),
77
+
78
+
/* Internal Core Clocks */
79
+
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
80
+
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
81
+
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
82
+
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
83
+
84
+
/* Core output clk */
85
+
DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
86
+
dtable_8_256, 0, 0, 0, NULL),
87
+
DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
88
+
dtable_4_128, 0, 0, 0, NULL),
89
+
DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
90
+
dtable_4_128, 0, 0, 0, NULL),
91
+
};
92
+
93
+
static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
94
+
DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, 0,
95
+
MSTOP(BUS_PERI_COM, BIT(12))),
96
+
DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0,
97
+
MSTOP(BUS_PERI_CPU, BIT(13))),
98
+
DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1,
99
+
MSTOP(BUS_PERI_CPU, BIT(13))),
100
+
DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0,
101
+
MSTOP(BUS_REG1, BIT(2))),
102
+
DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
103
+
MSTOP(BUS_REG1, BIT(3))),
104
+
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
105
+
MSTOP(BUS_MCPU2, BIT(1))),
106
+
};
107
+
108
+
static const struct rzg2l_reset r9a08g046_resets[] = {
109
+
DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0),
110
+
DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1),
111
+
DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
112
+
DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
113
+
DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
114
+
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
115
+
};
116
+
117
+
static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
118
+
MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,
119
+
MOD_CLK_BASE + R9A08G046_IA55_CLK,
120
+
MOD_CLK_BASE + R9A08G046_DMAC_ACLK,
121
+
};
122
+
123
+
static const unsigned int r9a08g046_crit_resets[] = {
124
+
R9A08G046_DMAC_ARESETN,
125
+
R9A08G046_DMAC_RST_ASYNC,
126
+
};
127
+
128
+
const struct rzg2l_cpg_info r9a08g046_cpg_info = {
129
+
/* Core Clocks */
130
+
.core_clks = r9a08g046_core_clks,
131
+
.num_core_clks = ARRAY_SIZE(r9a08g046_core_clks),
132
+
.last_dt_core_clk = LAST_DT_CORE_CLK,
133
+
.num_total_core_clks = MOD_CLK_BASE,
134
+
135
+
/* Critical Module Clocks */
136
+
.crit_mod_clks = r9a08g046_crit_mod_clks,
137
+
.num_crit_mod_clks = ARRAY_SIZE(r9a08g046_crit_mod_clks),
138
+
139
+
/* Module Clocks */
140
+
.mod_clks = r9a08g046_mod_clks,
141
+
.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),
142
+
.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,
143
+
144
+
/* Resets */
145
+
.resets = r9a08g046_resets,
146
+
.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */
147
+
148
+
/* Critical Resets */
149
+
.crit_resets = r9a08g046_crit_resets,
150
+
.num_crit_resets = ARRAY_SIZE(r9a08g046_crit_resets),
151
+
152
+
.has_clk_mon_regs = true,
153
+
};
+29
drivers/clk/renesas/r9a09g047-cpg.c
+29
drivers/clk/renesas/r9a09g047-cpg.c
···
224
224
BUS_MSTOP(5, BIT(13))),
225
225
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
226
226
BUS_MSTOP(5, BIT(13))),
227
+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
228
+
BUS_MSTOP(11, BIT(0))),
229
+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
230
+
BUS_MSTOP(11, BIT(0))),
231
+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
232
+
BUS_MSTOP(11, BIT(0))),
233
+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
234
+
BUS_MSTOP(11, BIT(1))),
235
+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
236
+
BUS_MSTOP(11, BIT(1))),
237
+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
238
+
BUS_MSTOP(11, BIT(1))),
239
+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
240
+
BUS_MSTOP(11, BIT(2))),
241
+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
242
+
BUS_MSTOP(11, BIT(2))),
243
+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
244
+
BUS_MSTOP(11, BIT(2))),
227
245
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
228
246
BUS_MSTOP(11, BIT(3))),
229
247
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
···
442
424
BUS_MSTOP(8, BIT(6))),
443
425
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
444
426
BUS_MSTOP(8, BIT(6))),
427
+
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
428
+
BUS_MSTOP(1, BIT(15))),
429
+
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
430
+
BUS_MSTOP(1, BIT(15))),
445
431
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
446
432
BUS_MSTOP(9, BIT(4))),
447
433
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
479
457
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
480
458
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
481
459
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
460
+
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
461
+
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
462
+
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
463
+
DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
464
+
DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
465
+
DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
482
466
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
483
467
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
484
468
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
···
531
503
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
532
504
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
533
505
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
506
+
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
534
507
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
535
508
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
536
509
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+27
-33
drivers/clk/renesas/r9a09g056-cpg.c
+27
-33
drivers/clk/renesas/r9a09g056-cpg.c
···
273
273
BUS_MSTOP(11, BIT(15))),
274
274
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
275
275
BUS_MSTOP(12, BIT(0))),
276
-
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
277
-
BUS_MSTOP(3, BIT(10))),
278
-
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
279
-
BUS_MSTOP(3, BIT(10))),
280
276
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
281
277
BUS_MSTOP(1, BIT(0))),
282
278
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
283
279
BUS_MSTOP(1, BIT(0))),
284
-
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
285
-
BUS_MSTOP(5, BIT(12))),
286
-
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
287
-
BUS_MSTOP(5, BIT(12))),
288
-
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
289
-
BUS_MSTOP(5, BIT(13))),
290
-
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
291
-
BUS_MSTOP(5, BIT(13))),
280
+
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
281
+
BUS_MSTOP(3, BIT(11) | BIT(12))),
282
+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
283
+
BUS_MSTOP(11, BIT(0))),
284
+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
285
+
BUS_MSTOP(11, BIT(0))),
286
+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
287
+
BUS_MSTOP(11, BIT(0))),
288
+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
289
+
BUS_MSTOP(11, BIT(1))),
290
+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
291
+
BUS_MSTOP(11, BIT(1))),
292
+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
293
+
BUS_MSTOP(11, BIT(1))),
294
+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
295
+
BUS_MSTOP(11, BIT(2))),
296
+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
297
+
BUS_MSTOP(11, BIT(2))),
298
+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
299
+
BUS_MSTOP(11, BIT(2))),
292
300
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
293
301
BUS_MSTOP(11, BIT(3))),
294
302
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
···
397
389
BUS_MSTOP(11, BIT(12))),
398
390
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
399
391
BUS_MSTOP(11, BIT(12))),
400
-
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
401
-
BUS_MSTOP(11, BIT(0))),
402
-
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
403
-
BUS_MSTOP(11, BIT(0))),
404
-
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
405
-
BUS_MSTOP(11, BIT(0))),
406
-
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
407
-
BUS_MSTOP(11, BIT(1))),
408
-
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
409
-
BUS_MSTOP(11, BIT(1))),
410
-
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
411
-
BUS_MSTOP(11, BIT(1))),
412
-
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
413
-
BUS_MSTOP(11, BIT(2))),
414
-
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
415
-
BUS_MSTOP(11, BIT(2))),
416
-
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
417
-
BUS_MSTOP(11, BIT(2))),
418
392
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
419
393
BUS_MSTOP(3, BIT(14))),
420
394
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
···
493
503
BUS_MSTOP(8, BIT(6))),
494
504
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
495
505
BUS_MSTOP(8, BIT(6))),
506
+
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
507
+
BUS_MSTOP(1, BIT(15))),
508
+
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
509
+
BUS_MSTOP(1, BIT(15))),
496
510
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
497
511
BUS_MSTOP(9, BIT(4))),
498
512
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
563
569
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
564
570
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
565
571
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
566
-
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
567
572
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
568
-
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
569
-
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
570
573
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
571
574
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
572
575
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
···
584
593
DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
585
594
DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
586
595
DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
596
+
DEF_RST(7, 9, 3, 10), /* RTC_0_RST_RTC */
597
+
DEF_RST(7, 10, 3, 11), /* RTC_0_RST_RTC_V */
587
598
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
588
599
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
589
600
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
···
617
624
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
618
625
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
619
626
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
627
+
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
620
628
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
621
629
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
622
630
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+25
-35
drivers/clk/renesas/r9a09g057-cpg.c
+25
-35
drivers/clk/renesas/r9a09g057-cpg.c
···
280
280
BUS_MSTOP(11, BIT(15))),
281
281
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
282
282
BUS_MSTOP(12, BIT(0))),
283
-
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
284
-
BUS_MSTOP(3, BIT(10))),
285
-
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
286
-
BUS_MSTOP(3, BIT(10))),
287
283
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
288
284
BUS_MSTOP(1, BIT(0))),
289
285
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
290
286
BUS_MSTOP(1, BIT(0))),
291
-
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
292
-
BUS_MSTOP(5, BIT(12))),
293
-
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
294
-
BUS_MSTOP(5, BIT(12))),
295
-
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
296
-
BUS_MSTOP(5, BIT(13))),
297
-
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
298
-
BUS_MSTOP(5, BIT(13))),
287
+
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
288
+
BUS_MSTOP(3, BIT(11) | BIT(12))),
289
+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
290
+
BUS_MSTOP(11, BIT(0))),
291
+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
292
+
BUS_MSTOP(11, BIT(0))),
293
+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
294
+
BUS_MSTOP(11, BIT(0))),
295
+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
296
+
BUS_MSTOP(11, BIT(1))),
297
+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
298
+
BUS_MSTOP(11, BIT(1))),
299
+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
300
+
BUS_MSTOP(11, BIT(1))),
301
+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
302
+
BUS_MSTOP(11, BIT(2))),
303
+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
304
+
BUS_MSTOP(11, BIT(2))),
305
+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
306
+
BUS_MSTOP(11, BIT(2))),
299
307
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
300
308
BUS_MSTOP(11, BIT(3))),
301
309
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
···
404
396
BUS_MSTOP(11, BIT(12))),
405
397
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
406
398
BUS_MSTOP(11, BIT(12))),
407
-
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
408
-
BUS_MSTOP(3, BIT(11) | BIT(12))),
409
-
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
410
-
BUS_MSTOP(11, BIT(0))),
411
-
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
412
-
BUS_MSTOP(11, BIT(0))),
413
-
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
414
-
BUS_MSTOP(11, BIT(0))),
415
-
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
416
-
BUS_MSTOP(11, BIT(1))),
417
-
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
418
-
BUS_MSTOP(11, BIT(1))),
419
-
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
420
-
BUS_MSTOP(11, BIT(1))),
421
-
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
422
-
BUS_MSTOP(11, BIT(2))),
423
-
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
424
-
BUS_MSTOP(11, BIT(2))),
425
-
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
426
-
BUS_MSTOP(11, BIT(2))),
427
399
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
428
400
BUS_MSTOP(3, BIT(14))),
429
401
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
···
508
520
BUS_MSTOP(8, BIT(6))),
509
521
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
510
522
BUS_MSTOP(8, BIT(6))),
523
+
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
524
+
BUS_MSTOP(1, BIT(13) | BIT(15))),
525
+
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
526
+
BUS_MSTOP(1, BIT(13) | BIT(15))),
511
527
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
512
528
BUS_MSTOP(9, BIT(4))),
513
529
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
590
598
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
591
599
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
592
600
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
593
-
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
594
601
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
595
-
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
596
-
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
597
602
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
598
603
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
599
604
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
···
646
657
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
647
658
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
648
659
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
660
+
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
649
661
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
650
662
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
651
663
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+2
-2
drivers/clk/renesas/renesas-cpg-mssr.c
+2
-2
drivers/clk/renesas/renesas-cpg-mssr.c
···
569
569
struct cpg_mssr_clk_domain {
570
570
struct generic_pm_domain genpd;
571
571
unsigned int num_core_pm_clks;
572
-
unsigned int core_pm_clks[];
572
+
unsigned int core_pm_clks[] __counted_by(num_core_pm_clks);
573
573
};
574
574
575
575
static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
···
667
667
size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
668
668
int ret;
669
669
670
-
pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
670
+
pd = devm_kzalloc(dev, struct_size(pd, core_pm_clks, num_core_pm_clks), GFP_KERNEL);
671
671
if (!pd)
672
672
return -ENOMEM;
673
673
+78
-13
drivers/clk/renesas/rzg2l-cpg.c
+78
-13
drivers/clk/renesas/rzg2l-cpg.c
···
1439
1439
}
1440
1440
DEFINE_SHOW_ATTRIBUTE(rzg2l_mod_clock_mstop);
1441
1441
1442
-
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
1442
+
static int rzg2l_mod_clock_endisable_helper(struct clk_hw *hw, bool enable,
1443
+
bool set_mstop_state)
1443
1444
{
1444
1445
struct mod_clock *clock = to_mod_clock(hw);
1445
1446
struct rzg2l_cpg_priv *priv = clock->priv;
···
1465
1464
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
1466
1465
if (enable) {
1467
1466
writel(value, priv->base + CLK_ON_R(reg));
1468
-
rzg2l_mod_clock_module_set_state(clock, false);
1467
+
if (set_mstop_state)
1468
+
rzg2l_mod_clock_module_set_state(clock, false);
1469
1469
} else {
1470
-
rzg2l_mod_clock_module_set_state(clock, true);
1470
+
if (set_mstop_state)
1471
+
rzg2l_mod_clock_module_set_state(clock, true);
1471
1472
writel(value, priv->base + CLK_ON_R(reg));
1472
1473
}
1473
1474
}
···
1487
1484
CLK_ON_R(reg), hw->clk);
1488
1485
1489
1486
return error;
1487
+
}
1488
+
1489
+
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
1490
+
{
1491
+
return rzg2l_mod_clock_endisable_helper(hw, enable, true);
1490
1492
}
1491
1493
1492
1494
static int rzg2l_mod_clock_enable(struct clk_hw *hw)
···
1594
1586
return NULL;
1595
1587
}
1596
1588
1589
+
static void rzg2l_mod_clock_init_mstop_helper(struct rzg2l_cpg_priv *priv,
1590
+
struct mod_clock *clk)
1591
+
{
1592
+
/*
1593
+
* Out of reset all modules are enabled. Set module state in case
1594
+
* associated clocks are disabled at probe/resume. Otherwise module
1595
+
* is in invalid HW state.
1596
+
*/
1597
+
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
1598
+
if (!rzg2l_mod_clock_is_enabled(&clk->hw))
1599
+
rzg2l_mod_clock_module_set_state(clk, true);
1600
+
}
1601
+
}
1602
+
1603
+
static void rzg2l_mod_enable_crit_clock_init_mstop(struct rzg2l_cpg_priv *priv)
1604
+
{
1605
+
struct mod_clock *clk;
1606
+
struct clk_hw *hw;
1607
+
1608
+
for_each_mod_clock(clk, hw, priv) {
1609
+
if ((clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL) &&
1610
+
(!rzg2l_mod_clock_is_enabled(&clk->hw)))
1611
+
rzg2l_mod_clock_endisable_helper(&clk->hw, true, false);
1612
+
1613
+
if (clk->mstop)
1614
+
rzg2l_mod_clock_init_mstop_helper(priv, clk);
1615
+
}
1616
+
}
1617
+
1597
1618
static void rzg2l_mod_clock_init_mstop(struct rzg2l_cpg_priv *priv)
1598
1619
{
1599
1620
struct mod_clock *clk;
···
1632
1595
if (!clk->mstop)
1633
1596
continue;
1634
1597
1635
-
/*
1636
-
* Out of reset all modules are enabled. Set module state
1637
-
* in case associated clocks are disabled at probe. Otherwise
1638
-
* module is in invalid HW state.
1639
-
*/
1640
-
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
1641
-
if (!rzg2l_mod_clock_is_enabled(&clk->hw))
1642
-
rzg2l_mod_clock_module_set_state(clk, true);
1643
-
}
1598
+
rzg2l_mod_clock_init_mstop_helper(priv, clk);
1644
1599
}
1645
1600
}
1646
1601
···
1794
1765
dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
1795
1766
assert ? "assert" : "deassert", id, CLK_RST_R(reg));
1796
1767
1768
+
if (assert) {
1769
+
for (unsigned int i = 0; i < priv->info->num_crit_resets; i++) {
1770
+
if (id == priv->info->crit_resets[i])
1771
+
return 0;
1772
+
}
1773
+
}
1774
+
1797
1775
if (!assert)
1798
1776
value |= mask;
1799
1777
writel(value, priv->base + CLK_RST_R(reg));
···
1836
1800
unsigned long id)
1837
1801
{
1838
1802
return __rzg2l_cpg_assert(rcdev, id, false);
1803
+
}
1804
+
1805
+
static int rzg2l_cpg_deassert_crit_resets(struct reset_controller_dev *rcdev,
1806
+
const struct rzg2l_cpg_info *info)
1807
+
{
1808
+
int ret;
1809
+
1810
+
for (unsigned int i = 0; i < info->num_crit_resets; i++) {
1811
+
ret = rzg2l_cpg_deassert(rcdev, info->crit_resets[i]);
1812
+
if (ret)
1813
+
return ret;
1814
+
}
1815
+
1816
+
return 0;
1839
1817
}
1840
1818
1841
1819
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
···
2101
2051
if (error)
2102
2052
return error;
2103
2053
2054
+
error = rzg2l_cpg_deassert_crit_resets(&priv->rcdev, info);
2055
+
if (error)
2056
+
return error;
2057
+
2104
2058
debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fops);
2105
2059
return 0;
2106
2060
}
···
2112
2058
static int rzg2l_cpg_resume(struct device *dev)
2113
2059
{
2114
2060
struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev);
2061
+
int ret;
2115
2062
2116
-
rzg2l_mod_clock_init_mstop(priv);
2063
+
ret = rzg2l_cpg_deassert_crit_resets(&priv->rcdev, priv->info);
2064
+
if (ret)
2065
+
return ret;
2066
+
2067
+
rzg2l_mod_enable_crit_clock_init_mstop(priv);
2117
2068
2118
2069
return 0;
2119
2070
}
···
2150
2091
{
2151
2092
.compatible = "renesas,r9a08g045-cpg",
2152
2093
.data = &r9a08g045_cpg_info,
2094
+
},
2095
+
#endif
2096
+
#ifdef CONFIG_CLK_R9A08G046
2097
+
{
2098
+
.compatible = "renesas,r9a08g046-cpg",
2099
+
.data = &r9a08g046_cpg_info,
2153
2100
},
2154
2101
#endif
2155
2102
#ifdef CONFIG_CLK_R9A09G011
+8
drivers/clk/renesas/rzg2l-cpg.h
+8
drivers/clk/renesas/rzg2l-cpg.h
···
276
276
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
277
277
* should not be disabled without a knowledgeable driver
278
278
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
279
+
* @crit_resets: Array with Reset IDs of critical resets that should not be
280
+
* asserted without a knowledgeable driver
281
+
* @num_crit_resets: Number of entries in crit_resets[]
279
282
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
280
283
*/
281
284
struct rzg2l_cpg_info {
···
305
302
const unsigned int *crit_mod_clks;
306
303
unsigned int num_crit_mod_clks;
307
304
305
+
/* Critical Resets that should not be asserted */
306
+
const unsigned int *crit_resets;
307
+
unsigned int num_crit_resets;
308
+
308
309
bool has_clk_mon_regs;
309
310
};
310
311
···
316
309
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
317
310
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
318
311
extern const struct rzg2l_cpg_info r9a08g045_cpg_info;
312
+
extern const struct rzg2l_cpg_info r9a08g046_cpg_info;
319
313
extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
320
314
321
315
int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data);
+12
include/dt-bindings/clock/econet,en751221-scu.h
+12
include/dt-bindings/clock/econet,en751221-scu.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
3
+
#ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
4
+
#define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
5
+
6
+
#define EN751221_CLK_PCIE 0
7
+
#define EN751221_CLK_SPI 1
8
+
#define EN751221_CLK_BUS 2
9
+
#define EN751221_CLK_CPU 3
10
+
#define EN751221_CLK_GSW 4
11
+
12
+
#endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */
+285
include/dt-bindings/clock/eswin,eic7700-clock.h
+285
include/dt-bindings/clock/eswin,eic7700-clock.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
4
+
* All rights reserved.
5
+
*
6
+
* Device Tree binding constants for EIC7700 clock controller.
7
+
*
8
+
* Authors:
9
+
* Yifeng Huang <huangyifeng@eswincomputing.com>
10
+
* Xuyang Dong <dongxuyang@eswincomputing.com>
11
+
*/
12
+
13
+
#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
14
+
#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
15
+
16
+
#define EIC7700_CLK_XTAL_32K 0
17
+
#define EIC7700_CLK_PLL_CPU 1
18
+
#define EIC7700_CLK_SPLL0_FOUT1 2
19
+
#define EIC7700_CLK_SPLL0_FOUT2 3
20
+
#define EIC7700_CLK_SPLL0_FOUT3 4
21
+
#define EIC7700_CLK_SPLL1_FOUT1 5
22
+
#define EIC7700_CLK_SPLL1_FOUT2 6
23
+
#define EIC7700_CLK_SPLL1_FOUT3 7
24
+
#define EIC7700_CLK_SPLL2_FOUT1 8
25
+
#define EIC7700_CLK_SPLL2_FOUT2 9
26
+
#define EIC7700_CLK_SPLL2_FOUT3 10
27
+
#define EIC7700_CLK_VPLL_FOUT1 11
28
+
#define EIC7700_CLK_VPLL_FOUT2 12
29
+
#define EIC7700_CLK_VPLL_FOUT3 13
30
+
#define EIC7700_CLK_APLL_FOUT1 14
31
+
#define EIC7700_CLK_APLL_FOUT2 15
32
+
#define EIC7700_CLK_APLL_FOUT3 16
33
+
#define EIC7700_CLK_EXT_MCLK 17
34
+
#define EIC7700_CLK_LPDDR_REF_BAK 18
35
+
#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 19
36
+
#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 20
37
+
#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 21
38
+
#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 22
39
+
#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 23
40
+
#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 24
41
+
#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 25
42
+
#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 26
43
+
#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 27
44
+
#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 28
45
+
#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 29
46
+
#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 30
47
+
#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 31
48
+
#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 32
49
+
#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 33
50
+
#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 34
51
+
#define EIC7700_CLK_MUX_SATA_PHY_2MUX1 35
52
+
#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 36
53
+
#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 37
54
+
#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 38
55
+
#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 39
56
+
#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 40
57
+
#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 41
58
+
#define EIC7700_CLK_MUX_RMII_REF_2MUX 42
59
+
#define EIC7700_CLK_MUX_ETH_CORE_2MUX1 43
60
+
#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 44
61
+
#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 45
62
+
#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 46
63
+
#define EIC7700_CLK_DIV_SYS_CFG_DYNM 47
64
+
#define EIC7700_CLK_DIV_NOC_NSP_DYNM 48
65
+
#define EIC7700_CLK_DIV_BOOTSPI_DYNM 49
66
+
#define EIC7700_CLK_DIV_SCPU_CORE_DYNM 50
67
+
#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 51
68
+
#define EIC7700_CLK_DIV_GPU_ACLK_DYNM 52
69
+
#define EIC7700_CLK_DIV_DSP_ACLK_DYNM 53
70
+
#define EIC7700_CLK_DIV_D2D_ACLK_DYNM 54
71
+
#define EIC7700_CLK_DIV_HSP_ACLK_DYNM 55
72
+
#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 56
73
+
#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 57
74
+
#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 58
75
+
#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 59
76
+
#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 60
77
+
#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 61
78
+
#define EIC7700_CLK_DIV_NPU_ACLK_DYNM 62
79
+
#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 63
80
+
#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 64
81
+
#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 65
82
+
#define EIC7700_CLK_DIV_VI_ACLK_DYNM 66
83
+
#define EIC7700_CLK_DIV_VI_DVP_DYNM 67
84
+
#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 68
85
+
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 69
86
+
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 70
87
+
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 71
88
+
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 72
89
+
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 73
90
+
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 74
91
+
#define EIC7700_CLK_DIV_VO_ACLK_DYNM 75
92
+
#define EIC7700_CLK_DIV_IESMCLK_DYNM 76
93
+
#define EIC7700_CLK_DIV_VO_PIXEL_DYNM 77
94
+
#define EIC7700_CLK_DIV_VO_MCLK_DYNM 78
95
+
#define EIC7700_CLK_DIV_VC_ACLK_DYNM 79
96
+
#define EIC7700_CLK_DIV_JD_DYNM 80
97
+
#define EIC7700_CLK_DIV_JE_DYNM 81
98
+
#define EIC7700_CLK_DIV_VE_DYNM 82
99
+
#define EIC7700_CLK_DIV_VD_DYNM 83
100
+
#define EIC7700_CLK_DIV_G2D_DYNM 84
101
+
#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 85
102
+
#define EIC7700_CLK_DIV_CRYPTO_DYNM 86
103
+
#define EIC7700_CLK_DIV_VI_DW_DYNM 87
104
+
#define EIC7700_CLK_DIV_NPU_E31_DYNM 88
105
+
#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 89
106
+
#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 90
107
+
#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 91
108
+
#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 92
109
+
#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 93
110
+
#define EIC7700_CLK_DIV_DDR_ACLK_DYNM 94
111
+
#define EIC7700_CLK_DIV_AON_RTC_DYNM 95
112
+
#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 96
113
+
#define EIC7700_CLK_DIV_VO_CEC_DYNM 97
114
+
#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 98
115
+
#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 99
116
+
#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 100
117
+
#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 101
118
+
#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 102
119
+
#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 103
120
+
#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 104
121
+
#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 105
122
+
#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 106
123
+
#define EIC7700_CLK_GATE_SPLL0_FOUT2 107
124
+
#define EIC7700_CLK_GATE_NOC_NSP_CLK 108
125
+
#define EIC7700_CLK_GATE_BOOTSPI 109
126
+
#define EIC7700_CLK_GATE_BOOTSPI_CFG 110
127
+
#define EIC7700_CLK_GATE_SCPU_CORE 111
128
+
#define EIC7700_CLK_GATE_SCPU_BUS 112
129
+
#define EIC7700_CLK_GATE_LPCPU_CORE 113
130
+
#define EIC7700_CLK_GATE_LPCPU_BUS 114
131
+
#define EIC7700_CLK_GATE_GPU_ACLK 115
132
+
#define EIC7700_CLK_GATE_GPU_GRAY_CLK 116
133
+
#define EIC7700_CLK_GATE_GPU_CFG_CLK 117
134
+
#define EIC7700_CLK_GATE_DSPT_ACLK 118
135
+
#define EIC7700_CLK_GATE_DSPT_CFG_CLK 119
136
+
#define EIC7700_CLK_GATE_D2D_ACLK 120
137
+
#define EIC7700_CLK_GATE_D2D_CFG_CLK 121
138
+
#define EIC7700_CLK_GATE_TCU_ACLK 122
139
+
#define EIC7700_CLK_GATE_TCU_CFG_CLK 123
140
+
#define EIC7700_CLK_GATE_DDRT_CFG_CLK 124
141
+
#define EIC7700_CLK_GATE_DDRT0_P0_ACLK 125
142
+
#define EIC7700_CLK_GATE_DDRT0_P1_ACLK 126
143
+
#define EIC7700_CLK_GATE_DDRT0_P2_ACLK 127
144
+
#define EIC7700_CLK_GATE_DDRT0_P3_ACLK 128
145
+
#define EIC7700_CLK_GATE_DDRT0_P4_ACLK 129
146
+
#define EIC7700_CLK_GATE_DDRT1_P0_ACLK 130
147
+
#define EIC7700_CLK_GATE_DDRT1_P1_ACLK 131
148
+
#define EIC7700_CLK_GATE_DDRT1_P2_ACLK 132
149
+
#define EIC7700_CLK_GATE_DDRT1_P3_ACLK 133
150
+
#define EIC7700_CLK_GATE_DDRT1_P4_ACLK 134
151
+
#define EIC7700_CLK_GATE_TIMER_CLK_0 135
152
+
#define EIC7700_CLK_GATE_TIMER_CLK_1 136
153
+
#define EIC7700_CLK_GATE_TIMER_CLK_2 137
154
+
#define EIC7700_CLK_GATE_TIMER_CLK_3 138
155
+
#define EIC7700_CLK_GATE_TIMER_PCLK_0 139
156
+
#define EIC7700_CLK_GATE_TIMER_PCLK_1 140
157
+
#define EIC7700_CLK_GATE_TIMER_PCLK_2 141
158
+
#define EIC7700_CLK_GATE_TIMER_PCLK_3 142
159
+
#define EIC7700_CLK_GATE_TIMER3_CLK8 143
160
+
#define EIC7700_CLK_GATE_PCIET_ACLK 144
161
+
#define EIC7700_CLK_GATE_PCIET_CFG_CLK 145
162
+
#define EIC7700_CLK_GATE_PCIET_CR_CLK 146
163
+
#define EIC7700_CLK_GATE_PCIET_AUX_CLK 147
164
+
#define EIC7700_CLK_GATE_NPU_ACLK 148
165
+
#define EIC7700_CLK_GATE_NPU_CFG_CLK 149
166
+
#define EIC7700_CLK_GATE_NPU_LLC_ACLK 150
167
+
#define EIC7700_CLK_GATE_NPU_CLK 151
168
+
#define EIC7700_CLK_GATE_NPU_E31_CLK 152
169
+
#define EIC7700_CLK_GATE_VI_ACLK 153
170
+
#define EIC7700_CLK_GATE_VI_DVP_CLK 154
171
+
#define EIC7700_CLK_GATE_VI_CFG_CLK 155
172
+
#define EIC7700_CLK_GATE_VI_DIG_DW_CLK 156
173
+
#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 157
174
+
#define EIC7700_CLK_GATE_VI_SHUTTER_0 158
175
+
#define EIC7700_CLK_GATE_VI_SHUTTER_1 159
176
+
#define EIC7700_CLK_GATE_VI_SHUTTER_2 160
177
+
#define EIC7700_CLK_GATE_VI_SHUTTER_3 161
178
+
#define EIC7700_CLK_GATE_VI_SHUTTER_4 162
179
+
#define EIC7700_CLK_GATE_VI_SHUTTER_5 163
180
+
#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 164
181
+
#define EIC7700_CLK_GATE_VI_PHY_CFG 165
182
+
#define EIC7700_CLK_GATE_VO_ACLK 166
183
+
#define EIC7700_CLK_GATE_VO_CFG_CLK 167
184
+
#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 168
185
+
#define EIC7700_CLK_GATE_VO_PIXEL_CLK 169
186
+
#define EIC7700_CLK_GATE_VO_I2S_MCLK 170
187
+
#define EIC7700_CLK_GATE_HSP_CFG_CLK 171
188
+
#define EIC7700_CLK_GATE_VC_ACLK 172
189
+
#define EIC7700_CLK_GATE_VC_CFG_CLK 173
190
+
#define EIC7700_CLK_GATE_VC_JE_CLK 174
191
+
#define EIC7700_CLK_GATE_VC_JD_CLK 175
192
+
#define EIC7700_CLK_GATE_VC_VE_CLK 176
193
+
#define EIC7700_CLK_GATE_VC_VD_CLK 177
194
+
#define EIC7700_CLK_GATE_G2D_CFG_CLK 178
195
+
#define EIC7700_CLK_GATE_G2D_CLK 179
196
+
#define EIC7700_CLK_GATE_G2D_ACLK 180
197
+
#define EIC7700_CLK_GATE_AONDMA_CFG 181
198
+
#define EIC7700_CLK_GATE_AONDMA_ACLK 182
199
+
#define EIC7700_CLK_GATE_AON_ACLK 183
200
+
#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 184
201
+
#define EIC7700_CLK_GATE_VO_CR_CLK 185
202
+
#define EIC7700_CLK_GATE_HSP_ACLK 186
203
+
#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 187
204
+
#define EIC7700_CLK_GATE_RTC_CFG 188
205
+
#define EIC7700_CLK_GATE_RTC 189
206
+
#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 190
207
+
#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 191
208
+
#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 192
209
+
#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 193
210
+
#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 194
211
+
#define EIC7700_CLK_GATE_HSP_RMII_REF_0 195
212
+
#define EIC7700_CLK_GATE_HSP_RMII_REF_1 196
213
+
#define EIC7700_CLK_GATE_PKA_CFG 197
214
+
#define EIC7700_CLK_GATE_SPACC_CFG 198
215
+
#define EIC7700_CLK_GATE_CRYPTO 199
216
+
#define EIC7700_CLK_GATE_TRNG_CFG 200
217
+
#define EIC7700_CLK_GATE_OTP_CFG 201
218
+
#define EIC7700_CLK_GATE_MAILBOX_0 202
219
+
#define EIC7700_CLK_GATE_MAILBOX_1 203
220
+
#define EIC7700_CLK_GATE_MAILBOX_2 204
221
+
#define EIC7700_CLK_GATE_MAILBOX_3 205
222
+
#define EIC7700_CLK_GATE_MAILBOX_4 206
223
+
#define EIC7700_CLK_GATE_MAILBOX_5 207
224
+
#define EIC7700_CLK_GATE_MAILBOX_6 208
225
+
#define EIC7700_CLK_GATE_MAILBOX_7 209
226
+
#define EIC7700_CLK_GATE_MAILBOX_8 210
227
+
#define EIC7700_CLK_GATE_MAILBOX_9 211
228
+
#define EIC7700_CLK_GATE_MAILBOX_10 212
229
+
#define EIC7700_CLK_GATE_MAILBOX_11 213
230
+
#define EIC7700_CLK_GATE_MAILBOX_12 214
231
+
#define EIC7700_CLK_GATE_MAILBOX_13 215
232
+
#define EIC7700_CLK_GATE_MAILBOX_14 216
233
+
#define EIC7700_CLK_GATE_MAILBOX_15 217
234
+
#define EIC7700_CLK_GATE_LSP_I2C0_PCLK 218
235
+
#define EIC7700_CLK_GATE_LSP_I2C1_PCLK 219
236
+
#define EIC7700_CLK_GATE_LSP_I2C2_PCLK 220
237
+
#define EIC7700_CLK_GATE_LSP_I2C3_PCLK 221
238
+
#define EIC7700_CLK_GATE_LSP_I2C4_PCLK 222
239
+
#define EIC7700_CLK_GATE_LSP_I2C5_PCLK 223
240
+
#define EIC7700_CLK_GATE_LSP_I2C6_PCLK 224
241
+
#define EIC7700_CLK_GATE_LSP_I2C7_PCLK 225
242
+
#define EIC7700_CLK_GATE_LSP_I2C8_PCLK 226
243
+
#define EIC7700_CLK_GATE_LSP_I2C9_PCLK 227
244
+
#define EIC7700_CLK_GATE_LSP_WDT0_PCLK 228
245
+
#define EIC7700_CLK_GATE_LSP_WDT1_PCLK 229
246
+
#define EIC7700_CLK_GATE_LSP_WDT2_PCLK 230
247
+
#define EIC7700_CLK_GATE_LSP_WDT3_PCLK 231
248
+
#define EIC7700_CLK_GATE_LSP_SSI0_PCLK 232
249
+
#define EIC7700_CLK_GATE_LSP_SSI1_PCLK 233
250
+
#define EIC7700_CLK_GATE_LSP_PVT_PCLK 234
251
+
#define EIC7700_CLK_GATE_AON_I2C0_PCLK 235
252
+
#define EIC7700_CLK_GATE_AON_I2C1_PCLK 236
253
+
#define EIC7700_CLK_GATE_LSP_UART0_PCLK 237
254
+
#define EIC7700_CLK_GATE_LSP_UART1_PCLK 238
255
+
#define EIC7700_CLK_GATE_LSP_UART2_PCLK 239
256
+
#define EIC7700_CLK_GATE_LSP_UART3_PCLK 240
257
+
#define EIC7700_CLK_GATE_LSP_UART4_PCLK 241
258
+
#define EIC7700_CLK_GATE_LSP_TIMER_PCLK 242
259
+
#define EIC7700_CLK_GATE_LSP_FAN_PCLK 243
260
+
#define EIC7700_CLK_GATE_LSP_PVT0_CLK 244
261
+
#define EIC7700_CLK_GATE_LSP_PVT1_CLK 245
262
+
#define EIC7700_CLK_GATE_VC_JE_PCLK 246
263
+
#define EIC7700_CLK_GATE_VC_JD_PCLK 247
264
+
#define EIC7700_CLK_GATE_VC_VE_PCLK 248
265
+
#define EIC7700_CLK_GATE_VC_VD_PCLK 249
266
+
#define EIC7700_CLK_GATE_VC_MON_PCLK 250
267
+
#define EIC7700_CLK_GATE_HSP_DMA0_CLK 251
268
+
#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 252
269
+
#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 253
270
+
#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 254
271
+
#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 255
272
+
#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 256
273
+
#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 257
274
+
#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 258
275
+
#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 259
276
+
#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 260
277
+
#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 261
278
+
#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 262
279
+
#define EIC7700_CLK_DIV_NOC_WDREF_DYNM 263
280
+
#define EIC7700_CLK_GATE_DDR0_TRACE 264
281
+
#define EIC7700_CLK_GATE_DDR1_TRACE 265
282
+
#define EIC7700_CLK_GATE_RNOC_NSP 266
283
+
#define EIC7700_CLK_GATE_NOC_WDREF 267
284
+
285
+
#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */
+342
include/dt-bindings/clock/renesas,r9a08g046-cpg.h
+342
include/dt-bindings/clock/renesas,r9a08g046-cpg.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
*
3
+
* Copyright (C) 2026 Renesas Electronics Corp.
4
+
*/
5
+
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
6
+
#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
7
+
8
+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
+
10
+
/* R9A08G046 CPG Core Clocks */
11
+
#define R9A08G046_CLK_I 0
12
+
#define R9A08G046_CLK_IC0 1
13
+
#define R9A08G046_CLK_IC1 2
14
+
#define R9A08G046_CLK_IC2 3
15
+
#define R9A08G046_CLK_IC3 4
16
+
#define R9A08G046_CLK_P0 5
17
+
#define R9A08G046_CLK_P1 6
18
+
#define R9A08G046_CLK_P2 7
19
+
#define R9A08G046_CLK_P3 8
20
+
#define R9A08G046_CLK_P4 9
21
+
#define R9A08G046_CLK_P5 10
22
+
#define R9A08G046_CLK_P6 11
23
+
#define R9A08G046_CLK_P7 12
24
+
#define R9A08G046_CLK_P8 13
25
+
#define R9A08G046_CLK_P9 14
26
+
#define R9A08G046_CLK_P10 15
27
+
#define R9A08G046_CLK_P13 16
28
+
#define R9A08G046_CLK_P14 17
29
+
#define R9A08G046_CLK_P15 18
30
+
#define R9A08G046_CLK_P16 19
31
+
#define R9A08G046_CLK_P17 20
32
+
#define R9A08G046_CLK_P18 21
33
+
#define R9A08G046_CLK_P19 22
34
+
#define R9A08G046_CLK_P20 23
35
+
#define R9A08G046_CLK_M0 24
36
+
#define R9A08G046_CLK_M1 25
37
+
#define R9A08G046_CLK_M2 26
38
+
#define R9A08G046_CLK_M3 27
39
+
#define R9A08G046_CLK_M4 28
40
+
#define R9A08G046_CLK_M5 29
41
+
#define R9A08G046_CLK_M6 30
42
+
#define R9A08G046_CLK_AT 31
43
+
#define R9A08G046_CLK_B 32
44
+
#define R9A08G046_CLK_ETHTX01 33
45
+
#define R9A08G046_CLK_ETHTX02 34
46
+
#define R9A08G046_CLK_ETHRX01 35
47
+
#define R9A08G046_CLK_ETHRX02 36
48
+
#define R9A08G046_CLK_ETHRM0 37
49
+
#define R9A08G046_CLK_ETHTX11 38
50
+
#define R9A08G046_CLK_ETHTX12 39
51
+
#define R9A08G046_CLK_ETHRX11 40
52
+
#define R9A08G046_CLK_ETHRX12 41
53
+
#define R9A08G046_CLK_ETHRM1 42
54
+
#define R9A08G046_CLK_G 43
55
+
#define R9A08G046_CLK_HP 44
56
+
#define R9A08G046_CLK_SD0 45
57
+
#define R9A08G046_CLK_SD1 46
58
+
#define R9A08G046_CLK_SD2 47
59
+
#define R9A08G046_CLK_SPI0 48
60
+
#define R9A08G046_CLK_SPI1 49
61
+
#define R9A08G046_CLK_S0 50
62
+
#define R9A08G046_CLK_SWD 51
63
+
#define R9A08G046_OSCCLK 52
64
+
#define R9A08G046_OSCCLK2 53
65
+
#define R9A08G046_MIPI_DSI_PLLCLK 54
66
+
#define R9A08G046_USB_SCLK 55
67
+
68
+
/* R9A08G046 Module Clocks */
69
+
#define R9A08G046_CA55_SCLK 0
70
+
#define R9A08G046_CA55_PCLK 1
71
+
#define R9A08G046_CA55_ATCLK 2
72
+
#define R9A08G046_CA55_GICCLK 3
73
+
#define R9A08G046_CA55_PERICLK 4
74
+
#define R9A08G046_CA55_ACLK 5
75
+
#define R9A08G046_CA55_TSCLK 6
76
+
#define R9A08G046_CA55_CORECLK0 7
77
+
#define R9A08G046_CA55_CORECLK1 8
78
+
#define R9A08G046_CA55_CORECLK2 9
79
+
#define R9A08G046_CA55_CORECLK3 10
80
+
#define R9A08G046_SRAM_ACPU_ACLK0 11
81
+
#define R9A08G046_SRAM_ACPU_ACLK1 12
82
+
#define R9A08G046_SRAM_ACPU_ACLK2 13
83
+
#define R9A08G046_GIC600_GICCLK 14
84
+
#define R9A08G046_IA55_CLK 15
85
+
#define R9A08G046_IA55_PCLK 16
86
+
#define R9A08G046_MHU_PCLK 17
87
+
#define R9A08G046_SYC_CNT_CLK 18
88
+
#define R9A08G046_DMAC_ACLK 19
89
+
#define R9A08G046_DMAC_PCLK 20
90
+
#define R9A08G046_OSTM0_PCLK 21
91
+
#define R9A08G046_OSTM1_PCLK 22
92
+
#define R9A08G046_OSTM2_PCLK 23
93
+
#define R9A08G046_MTU_X_MCK_MTU3 24
94
+
#define R9A08G046_POE3_CLKM_POE 25
95
+
#define R9A08G046_GPT_PCLK 26
96
+
#define R9A08G046_POEG_A_CLKP 27
97
+
#define R9A08G046_POEG_B_CLKP 28
98
+
#define R9A08G046_POEG_C_CLKP 29
99
+
#define R9A08G046_POEG_D_CLKP 30
100
+
#define R9A08G046_WDT0_PCLK 31
101
+
#define R9A08G046_WDT0_CLK 32
102
+
#define R9A08G046_WDT1_PCLK 33
103
+
#define R9A08G046_WDT1_CLK 34
104
+
#define R9A08G046_WDT2_PCLK 35
105
+
#define R9A08G046_WDT2_CLK 36
106
+
#define R9A08G046_XSPI_HCLK 37
107
+
#define R9A08G046_XSPI_ACLK 38
108
+
#define R9A08G046_XSPI_CLK 39
109
+
#define R9A08G046_XSPI_CLKX2 40
110
+
#define R9A08G046_SDHI0_IMCLK 41
111
+
#define R9A08G046_SDHI0_IMCLK2 42
112
+
#define R9A08G046_SDHI0_CLK_HS 43
113
+
#define R9A08G046_SDHI0_IACLKS 44
114
+
#define R9A08G046_SDHI0_IACLKM 45
115
+
#define R9A08G046_SDHI1_IMCLK 46
116
+
#define R9A08G046_SDHI1_IMCLK2 47
117
+
#define R9A08G046_SDHI1_CLK_HS 48
118
+
#define R9A08G046_SDHI1_IACLKS 49
119
+
#define R9A08G046_SDHI1_IACLKM 50
120
+
#define R9A08G046_SDHI2_IMCLK 51
121
+
#define R9A08G046_SDHI2_IMCLK2 52
122
+
#define R9A08G046_SDHI2_CLK_HS 53
123
+
#define R9A08G046_SDHI2_IACLKS 54
124
+
#define R9A08G046_SDHI2_IACLKM 55
125
+
#define R9A08G046_GE3D_CLK 56
126
+
#define R9A08G046_GE3D_AXI_CLK 57
127
+
#define R9A08G046_GE3D_ACE_CLK 58
128
+
#define R9A08G046_ISU_ACLK 59
129
+
#define R9A08G046_ISU_PCLK 60
130
+
#define R9A08G046_H264_CLK_A 61
131
+
#define R9A08G046_H264_CLK_P 62
132
+
#define R9A08G046_CRU_SYSCLK 63
133
+
#define R9A08G046_CRU_VCLK 64
134
+
#define R9A08G046_CRU_PCLK 65
135
+
#define R9A08G046_CRU_ACLK 66
136
+
#define R9A08G046_MIPI_DSI_SYSCLK 67
137
+
#define R9A08G046_MIPI_DSI_ACLK 68
138
+
#define R9A08G046_MIPI_DSI_PCLK 69
139
+
#define R9A08G046_MIPI_DSI_VCLK 70
140
+
#define R9A08G046_MIPI_DSI_LPCLK 71
141
+
#define R9A08G046_LVDS_PLLCLK 72
142
+
#define R9A08G046_LVDS_CLK_DOT0 73
143
+
#define R9A08G046_LCDC_CLK_A 74
144
+
#define R9A08G046_LCDC_CLK_D 75
145
+
#define R9A08G046_LCDC_CLK_P 76
146
+
#define R9A08G046_SSI0_PCLK2 77
147
+
#define R9A08G046_SSI0_PCLK_SFR 78
148
+
#define R9A08G046_SSI1_PCLK2 79
149
+
#define R9A08G046_SSI1_PCLK_SFR 80
150
+
#define R9A08G046_SSI2_PCLK2 81
151
+
#define R9A08G046_SSI2_PCLK_SFR 82
152
+
#define R9A08G046_SSI3_PCLK2 83
153
+
#define R9A08G046_SSI3_PCLK_SFR 84
154
+
#define R9A08G046_USB_U2H0_HCLK 85
155
+
#define R9A08G046_USB_U2H1_HCLK 86
156
+
#define R9A08G046_USB_U2P0_EXR_CPUCLK 87
157
+
#define R9A08G046_USB_U2P1_EXR_CPUCLK 88
158
+
#define R9A08G046_USB_PCLK 89
159
+
#define R9A08G046_ETH0_CLK_AXI 90
160
+
#define R9A08G046_ETH0_CLK_CHI 91
161
+
#define R9A08G046_ETH0_CLK_TX_I 92
162
+
#define R9A08G046_ETH0_CLK_RX_I 93
163
+
#define R9A08G046_ETH0_CLK_TX_180_I 94
164
+
#define R9A08G046_ETH0_CLK_RX_180_I 95
165
+
#define R9A08G046_ETH0_CLK_RMII_I 96
166
+
#define R9A08G046_ETH0_CLK_PTP_REF_I 97
167
+
#define R9A08G046_ETH0_CLK_TX_I_RMII 98
168
+
#define R9A08G046_ETH0_CLK_RX_I_RMII 99
169
+
#define R9A08G046_ETH1_CLK_AXI 100
170
+
#define R9A08G046_ETH1_CLK_CHI 101
171
+
#define R9A08G046_ETH1_CLK_TX_I 102
172
+
#define R9A08G046_ETH1_CLK_RX_I 103
173
+
#define R9A08G046_ETH1_CLK_TX_180_I 104
174
+
#define R9A08G046_ETH1_CLK_RX_180_I 105
175
+
#define R9A08G046_ETH1_CLK_RMII_I 106
176
+
#define R9A08G046_ETH1_CLK_PTP_REF_I 107
177
+
#define R9A08G046_ETH1_CLK_TX_I_RMII 108
178
+
#define R9A08G046_ETH1_CLK_RX_I_RMII 109
179
+
#define R9A08G046_I2C0_PCLK 110
180
+
#define R9A08G046_I2C1_PCLK 111
181
+
#define R9A08G046_I2C2_PCLK 112
182
+
#define R9A08G046_I2C3_PCLK 113
183
+
#define R9A08G046_SCIF0_CLK_PCK 114
184
+
#define R9A08G046_SCIF1_CLK_PCK 115
185
+
#define R9A08G046_SCIF2_CLK_PCK 116
186
+
#define R9A08G046_SCIF3_CLK_PCK 117
187
+
#define R9A08G046_SCIF4_CLK_PCK 118
188
+
#define R9A08G046_SCIF5_CLK_PCK 119
189
+
#define R9A08G046_RSCI0_PCLK 120
190
+
#define R9A08G046_RSCI0_TCLK 121
191
+
#define R9A08G046_RSCI1_PCLK 122
192
+
#define R9A08G046_RSCI1_TCLK 123
193
+
#define R9A08G046_RSCI2_PCLK 124
194
+
#define R9A08G046_RSCI2_TCLK 125
195
+
#define R9A08G046_RSCI3_PCLK 126
196
+
#define R9A08G046_RSCI3_TCLK 127
197
+
#define R9A08G046_RSPI0_PCLK 128
198
+
#define R9A08G046_RSPI0_TCLK 129
199
+
#define R9A08G046_RSPI1_PCLK 130
200
+
#define R9A08G046_RSPI1_TCLK 131
201
+
#define R9A08G046_RSPI2_PCLK 132
202
+
#define R9A08G046_RSPI2_TCLK 133
203
+
#define R9A08G046_CANFD_PCLK 134
204
+
#define R9A08G046_CANFD_CLK_RAM 135
205
+
#define R9A08G046_GPIO_HCLK 136
206
+
#define R9A08G046_ADC0_ADCLK 137
207
+
#define R9A08G046_ADC0_PCLK 138
208
+
#define R9A08G046_ADC1_ADCLK 139
209
+
#define R9A08G046_ADC1_PCLK 140
210
+
#define R9A08G046_TSU_PCLK 141
211
+
#define R9A08G046_PDM_PCLK 142
212
+
#define R9A08G046_PDM_CCLK 143
213
+
#define R9A08G046_PCI_ACLK 144
214
+
#define R9A08G046_PCI_CLKL1PM 145
215
+
#define R9A08G046_PCI_CLK_PMU 146
216
+
#define R9A08G046_SPDIF_PCLK 147
217
+
#define R9A08G046_I3C_TCLK 148
218
+
#define R9A08G046_I3C_PCLK 149
219
+
#define R9A08G046_VBAT_BCLK 150
220
+
#define R9A08G046_BSC_X_BCK_BSC 151
221
+
222
+
/* R9A08G046 Resets */
223
+
#define R9A08G046_CA55_RST0_0 0
224
+
#define R9A08G046_CA55_RST0_1 1
225
+
#define R9A08G046_CA55_RST0_2 2
226
+
#define R9A08G046_CA55_RST0_3 3
227
+
#define R9A08G046_CA55_RST4_0 4
228
+
#define R9A08G046_CA55_RST4_1 5
229
+
#define R9A08G046_CA55_RST4_2 6
230
+
#define R9A08G046_CA55_RST4_3 7
231
+
#define R9A08G046_CA55_RST8 8
232
+
#define R9A08G046_CA55_RST9 9
233
+
#define R9A08G046_CA55_RST10 10
234
+
#define R9A08G046_CA55_RST11 11
235
+
#define R9A08G046_CA55_RST12 12
236
+
#define R9A08G046_CA55_RST13 13
237
+
#define R9A08G046_CA55_RST14 14
238
+
#define R9A08G046_CA55_RST15 15
239
+
#define R9A08G046_CA55_RST16 16
240
+
#define R9A08G046_SRAM_ACPU_ARESETN0 17
241
+
#define R9A08G046_SRAM_ACPU_ARESETN1 18
242
+
#define R9A08G046_SRAM_ACPU_ARESETN2 19
243
+
#define R9A08G046_GIC600_GICRESET_N 20
244
+
#define R9A08G046_GIC600_DBG_GICRESET_N 21
245
+
#define R9A08G046_IA55_RESETN 22
246
+
#define R9A08G046_MHU_RESETN 23
247
+
#define R9A08G046_SYC_RESETN 24
248
+
#define R9A08G046_DMAC_ARESETN 25
249
+
#define R9A08G046_DMAC_RST_ASYNC 26
250
+
#define R9A08G046_GTM0_PRESETZ 27
251
+
#define R9A08G046_GTM1_PRESETZ 28
252
+
#define R9A08G046_GTM2_PRESETZ 29
253
+
#define R9A08G046_MTU_X_PRESET_MTU3 30
254
+
#define R9A08G046_POE3_RST_M_REG 31
255
+
#define R9A08G046_GPT_RST_C 32
256
+
#define R9A08G046_POEG_A_RST 33
257
+
#define R9A08G046_POEG_B_RST 34
258
+
#define R9A08G046_POEG_C_RST 35
259
+
#define R9A08G046_POEG_D_RST 36
260
+
#define R9A08G046_WDT0_PRESETN 37
261
+
#define R9A08G046_WDT1_PRESETN 38
262
+
#define R9A08G046_WDT2_PRESETN 39
263
+
#define R9A08G046_XSPI_HRESETN 40
264
+
#define R9A08G046_XSPI_ARESETN 41
265
+
#define R9A08G046_SDHI0_IXRST 42
266
+
#define R9A08G046_SDHI1_IXRST 43
267
+
#define R9A08G046_SDHI2_IXRST 44
268
+
#define R9A08G046_SDHI0_IXRSTAXIM 45
269
+
#define R9A08G046_SDHI0_IXRSTAXIS 46
270
+
#define R9A08G046_SDHI1_IXRSTAXIM 47
271
+
#define R9A08G046_SDHI1_IXRSTAXIS 48
272
+
#define R9A08G046_SDHI2_IXRSTAXIM 49
273
+
#define R9A08G046_SDHI2_IXRSTAXIS 50
274
+
#define R9A08G046_GE3D_RESETN 51
275
+
#define R9A08G046_GE3D_AXI_RESETN 52
276
+
#define R9A08G046_GE3D_ACE_RESETN 53
277
+
#define R9A08G046_ISU_ARESETN 54
278
+
#define R9A08G046_ISU_PRESETN 55
279
+
#define R9A08G046_H264_X_RESET_VCP 56
280
+
#define R9A08G046_H264_CP_PRESET_P 57
281
+
#define R9A08G046_CRU_CMN_RSTB 58
282
+
#define R9A08G046_CRU_PRESETN 59
283
+
#define R9A08G046_CRU_ARESETN 60
284
+
#define R9A08G046_MIPI_DSI_CMN_RSTB 61
285
+
#define R9A08G046_MIPI_DSI_ARESET_N 62
286
+
#define R9A08G046_MIPI_DSI_PRESET_N 63
287
+
#define R9A08G046_LCDC_RESET_N 64
288
+
#define R9A08G046_SSI0_RST_M2_REG 65
289
+
#define R9A08G046_SSI1_RST_M2_REG 66
290
+
#define R9A08G046_SSI2_RST_M2_REG 67
291
+
#define R9A08G046_SSI3_RST_M2_REG 68
292
+
#define R9A08G046_USB_U2H0_HRESETN 69
293
+
#define R9A08G046_USB_U2H1_HRESETN 70
294
+
#define R9A08G046_USB_U2P0_EXL_SYSRST 71
295
+
#define R9A08G046_USB_PRESETN 72
296
+
#define R9A08G046_USB_U2P1_EXL_SYSRST 73
297
+
#define R9A08G046_ETH0_ARESET_N 74
298
+
#define R9A08G046_ETH1_ARESET_N 75
299
+
#define R9A08G046_I2C0_MRST 76
300
+
#define R9A08G046_I2C1_MRST 77
301
+
#define R9A08G046_I2C2_MRST 78
302
+
#define R9A08G046_I2C3_MRST 79
303
+
#define R9A08G046_SCIF0_RST_SYSTEM_N 80
304
+
#define R9A08G046_SCIF1_RST_SYSTEM_N 81
305
+
#define R9A08G046_SCIF2_RST_SYSTEM_N 82
306
+
#define R9A08G046_SCIF3_RST_SYSTEM_N 83
307
+
#define R9A08G046_SCIF4_RST_SYSTEM_N 84
308
+
#define R9A08G046_SCIF5_RST_SYSTEM_N 85
309
+
#define R9A08G046_RSPI0_PRESETN 86
310
+
#define R9A08G046_RSPI1_PRESETN 87
311
+
#define R9A08G046_RSPI2_PRESETN 88
312
+
#define R9A08G046_RSPI0_TRESETN 89
313
+
#define R9A08G046_RSPI1_TRESETN 90
314
+
#define R9A08G046_RSPI2_TRESETN 91
315
+
#define R9A08G046_CANFD_RSTP_N 92
316
+
#define R9A08G046_CANFD_RSTC_N 93
317
+
#define R9A08G046_GPIO_RSTN 94
318
+
#define R9A08G046_GPIO_PORT_RESETN 95
319
+
#define R9A08G046_GPIO_SPARE_RESETN 96
320
+
#define R9A08G046_ADC0_PRESETN 97
321
+
#define R9A08G046_ADC0_ADRST_N 98
322
+
#define R9A08G046_ADC1_PRESETN 99
323
+
#define R9A08G046_ADC1_ADRST_N 100
324
+
#define R9A08G046_TSU_PRESETN 101
325
+
#define R9A08G046_PDM_PRESETN 102
326
+
#define R9A08G046_PCI_ARESETN 103
327
+
#define R9A08G046_SPDIF_RST 104
328
+
#define R9A08G046_I3C_TRESETN 105
329
+
#define R9A08G046_I3C_PRESETN 106
330
+
#define R9A08G046_VBAT_BRESETN 107
331
+
#define R9A08G046_RSCI0_PRESETN 108
332
+
#define R9A08G046_RSCI1_PRESETN 109
333
+
#define R9A08G046_RSCI2_PRESETN 110
334
+
#define R9A08G046_RSCI3_PRESETN 111
335
+
#define R9A08G046_RSCI0_TRESETN 112
336
+
#define R9A08G046_RSCI1_TRESETN 113
337
+
#define R9A08G046_RSCI2_TRESETN 114
338
+
#define R9A08G046_RSCI3_TRESETN 115
339
+
#define R9A08G046_LVDS_RESET_N 116
340
+
#define R9A08G046_BSC_X_PRESET_BSC 117
341
+
342
+
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ */
+49
include/dt-bindings/reset/econet,en751221-scu.h
+49
include/dt-bindings/reset/econet,en751221-scu.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
3
+
#ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
4
+
#define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
5
+
6
+
#define EN751221_XPON_PHY_RST 0
7
+
#define EN751221_PCM1_ZSI_ISI_RST 1
8
+
#define EN751221_FE_QDMA1_RST 2
9
+
#define EN751221_FE_QDMA2_RST 3
10
+
#define EN751221_FE_UNZIP_RST 4
11
+
#define EN751221_PCM2_RST 5
12
+
#define EN751221_PTM_MAC_RST 6
13
+
#define EN751221_CRYPTO_RST 7
14
+
#define EN751221_SAR_RST 8
15
+
#define EN751221_TIMER_RST 9
16
+
#define EN751221_INTC_RST 10
17
+
#define EN751221_BONDING_RST 11
18
+
#define EN751221_PCM1_RST 12
19
+
#define EN751221_UART_RST 13
20
+
#define EN751221_GPIO_RST 14
21
+
#define EN751221_GDMA_RST 15
22
+
#define EN751221_I2C_MASTER_RST 16
23
+
#define EN751221_PCM2_ZSI_ISI_RST 17
24
+
#define EN751221_SFC_RST 18
25
+
#define EN751221_UART2_RST 19
26
+
#define EN751221_GDMP_RST 20
27
+
#define EN751221_FE_RST 21
28
+
#define EN751221_USB_HOST_P0_RST 22
29
+
#define EN751221_GSW_RST 23
30
+
#define EN751221_SFC2_PCM_RST 24
31
+
#define EN751221_PCIE0_RST 25
32
+
#define EN751221_PCIE1_RST 26
33
+
#define EN751221_CPU_TIMER_RST 27
34
+
#define EN751221_PCIE_HB_RST 28
35
+
#define EN751221_SIMIF_RST 29
36
+
#define EN751221_XPON_MAC_RST 30
37
+
#define EN751221_GFAST_RST 31
38
+
#define EN751221_CPU_TIMER2_RST 32
39
+
#define EN751221_UART3_RST 33
40
+
#define EN751221_UART4_RST 34
41
+
#define EN751221_UART5_RST 35
42
+
#define EN751221_I2C2_RST 36
43
+
#define EN751221_XSI_MAC_RST 37
44
+
#define EN751221_XSI_PHY_RST 38
45
+
#define EN751221_DMT_RST 39
46
+
#define EN751221_USB_PHY_P0_RST 40
47
+
#define EN751221_USB_PHY_P1_RST 41
48
+
49
+
#endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */
+20
include/linux/clk-provider.h
+20
include/linux/clk-provider.h
···
948
948
(shift), (width), (clk_divider_flags), \
949
949
NULL, (lock))
950
950
/**
951
+
* devm_clk_hw_register_divider_parent_data - register a divider clock with the
952
+
* clock framework
953
+
* @dev: device registering this clock
954
+
* @name: name of this clock
955
+
* @parent_data: parent clk data
956
+
* @flags: framework-specific flags
957
+
* @reg: register address to adjust divider
958
+
* @shift: number of bits to shift the bitfield
959
+
* @width: width of the bitfield
960
+
* @clk_divider_flags: divider-specific flags for this clock
961
+
* @lock: shared register lock for this clock
962
+
*/
963
+
#define devm_clk_hw_register_divider_parent_data(dev, name, parent_data, \
964
+
flags, reg, shift, width, \
965
+
clk_divider_flags, lock) \
966
+
__devm_clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
967
+
(parent_data), (flags), (reg), (shift), \
968
+
(width), (clk_divider_flags), NULL, \
969
+
(lock))
970
+
/**
951
971
* devm_clk_hw_register_divider_table - register a table based divider clock
952
972
* with the clock framework (devres variant)
953
973
* @dev: device registering this clock