tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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r8169: add support for RTL8126A rev.b

Add support for RTL8126A rev.b. Its XID is 0x64a. It is basically
based on the one with XID 0x649, but with different firmware file.

Signed-off-by: ChunHao Lin <hau@realtek.com>
Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://patch.msgid.link/20240830021810.11993-1-hau@realtek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

ChunHao Lin and committed by
Jakub Kicinski 69cb8998 4e3a024b

+29 -15
+1
drivers/net/ethernet/realtek/r8169.h
··· 69 69 RTL_GIGA_MAC_VER_61, 70 70 RTL_GIGA_MAC_VER_63, 71 71 RTL_GIGA_MAC_VER_65, 72 + RTL_GIGA_MAC_VER_66, 72 73 RTL_GIGA_MAC_NONE 73 74 }; 74 75
+27 -15
drivers/net/ethernet/realtek/r8169_main.c
··· 56 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 58 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 59 + #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 59 60 60 61 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 61 62 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ ··· 139 138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 140 139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 141 140 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 141 + [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3}, 142 142 }; 143 143 144 144 static const struct pci_device_id rtl8169_pci_tbl[] = { ··· 1203 1201 case RTL_GIGA_MAC_VER_31: 1204 1202 r8168dp_2_mdio_write(tp, location, val); 1205 1203 break; 1206 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1204 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1207 1205 r8168g_mdio_write(tp, location, val); 1208 1206 break; 1209 1207 default: ··· 1218 1216 case RTL_GIGA_MAC_VER_28: 1219 1217 case RTL_GIGA_MAC_VER_31: 1220 1218 return r8168dp_2_mdio_read(tp, location); 1221 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1219 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1222 1220 return r8168g_mdio_read(tp, location); 1223 1221 default: 1224 1222 return r8169_mdio_read(tp, location); ··· 1427 1425 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1428 1426 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1429 1427 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1430 - case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1428 + case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1431 1429 if (enable) 1432 1430 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1433 1431 else ··· 1594 1592 break; 1595 1593 case RTL_GIGA_MAC_VER_34: 1596 1594 case RTL_GIGA_MAC_VER_37: 1597 - case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1595 + case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1598 1596 if (wolopts) 1599 1597 rtl_mod_config2(tp, 0, PME_SIGNAL); 1600 1598 else ··· 2073 2071 case RTL_GIGA_MAC_VER_61: 2074 2072 case RTL_GIGA_MAC_VER_63: 2075 2073 case RTL_GIGA_MAC_VER_65: 2074 + case RTL_GIGA_MAC_VER_66: 2076 2075 tp->tx_lpi_timer = timer_val; 2077 2076 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2078 2077 break; ··· 2202 2199 enum mac_version ver; 2203 2200 } mac_info[] = { 2204 2201 /* 8126A family. */ 2202 + { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 }, 2205 2203 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2206 2204 2207 2205 /* 8125B family. */ ··· 2474 2470 break; 2475 2471 case RTL_GIGA_MAC_VER_63: 2476 2472 case RTL_GIGA_MAC_VER_65: 2473 + case RTL_GIGA_MAC_VER_66: 2477 2474 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2478 2475 RX_PAUSE_SLOT_ON); 2479 2476 break; ··· 2661 2656 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2662 2657 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2663 2658 break; 2664 - case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65: 2659 + case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2665 2660 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2666 2661 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2667 2662 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); ··· 2904 2899 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2905 2900 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2906 2901 break; 2907 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2902 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2908 2903 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2909 2904 break; 2910 2905 default: ··· 2918 2913 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2919 2914 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2920 2915 break; 2921 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2916 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2922 2917 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2923 2918 break; 2924 2919 default: ··· 2945 2940 rtl_mod_config5(tp, 0, ASPM_en); 2946 2941 switch (tp->mac_version) { 2947 2942 case RTL_GIGA_MAC_VER_65: 2943 + case RTL_GIGA_MAC_VER_66: 2948 2944 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2949 2945 RTL_W8(tp, INT_CFG0_8125, val8); 2950 2946 break; ··· 2956 2950 2957 2951 switch (tp->mac_version) { 2958 2952 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2959 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2953 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2960 2954 /* reset ephy tx/rx disable timer */ 2961 2955 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2962 2956 /* chip can trigger L1.2 */ ··· 2968 2962 } else { 2969 2963 switch (tp->mac_version) { 2970 2964 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2971 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2965 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2972 2966 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2973 2967 break; 2974 2968 default: ··· 2977 2971 2978 2972 switch (tp->mac_version) { 2979 2973 case RTL_GIGA_MAC_VER_65: 2974 + case RTL_GIGA_MAC_VER_66: 2980 2975 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2981 2976 RTL_W8(tp, INT_CFG0_8125, val8); 2982 2977 break; ··· 3697 3690 /* disable new tx descriptor format */ 3698 3691 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3699 3692 3700 - if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3693 + if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3694 + tp->mac_version == RTL_GIGA_MAC_VER_66) 3701 3695 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3702 3696 3703 - if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3697 + if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3698 + tp->mac_version == RTL_GIGA_MAC_VER_66) 3704 3699 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3705 3700 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3706 3701 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); ··· 3720 3711 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3721 3712 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3722 3713 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3723 - if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3714 + if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3715 + tp->mac_version == RTL_GIGA_MAC_VER_66) 3724 3716 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3725 3717 else 3726 3718 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); ··· 3835 3825 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3836 3826 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3837 3827 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3828 + [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a, 3838 3829 }; 3839 3830 3840 3831 if (hw_configs[tp->mac_version]) ··· 3856 3845 break; 3857 3846 case RTL_GIGA_MAC_VER_63: 3858 3847 case RTL_GIGA_MAC_VER_65: 3848 + case RTL_GIGA_MAC_VER_66: 3859 3849 for (i = 0xa00; i < 0xa80; i += 4) 3860 3850 RTL_W32(tp, i, 0); 3861 3851 RTL_W16(tp, INT_CFG1_8125, 0x0000); ··· 4085 4073 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4086 4074 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4087 4075 break; 4088 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 4076 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 4089 4077 rtl_enable_rxdvgate(tp); 4090 4078 fsleep(2000); 4091 4079 break; ··· 4236 4224 4237 4225 switch (tp->mac_version) { 4238 4226 case RTL_GIGA_MAC_VER_34: 4239 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 4227 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 4240 4228 padto = max_t(unsigned int, padto, ETH_ZLEN); 4241 4229 break; 4242 4230 default: ··· 5269 5257 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5270 5258 rtl_hw_init_8168g(tp); 5271 5259 break; 5272 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 5260 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 5273 5261 rtl_hw_init_8125(tp); 5274 5262 break; 5275 5263 default:
+1
drivers/net/ethernet/realtek/r8169_phy_config.c
··· 1159 1159 [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, 1160 1160 [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, 1161 1161 [RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config, 1162 + [RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config, 1162 1163 }; 1163 1164 1164 1165 if (phy_configs[ver])