Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'devicetree-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Add bindings for arm,armv7m-nvic, fsl,icoll, fsl,imx23-digctl, Xilinx
INTC, Analog Devices ADT7411, and a bunch of trivial hwmon devices
- Convert fsl,vf610-mscm-ir, fsl,dsu, via,vt8500-timer, nxp,isp1301,
Marvell Armada NETA and BM, apm,xgene1-msi, fsl,mpic-msi,
himax,hx8357d, and sitronix,st7586 bindings to DT schema format
- Fixes for some display bindings
- More indentation clean-ups in examples
- Add more guidelines and clarifications on writing bindings
* tag 'devicetree-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (31 commits)
dt-bindings: Correct indentation and style in DTS example
dt-bindings: display: mediatek,dp: Allow DisplayPort AUX bus
dt-bindings: fsl: convert fsl,vf610-mscm-ir.txt to yaml format
dt-bindings: interrupt-controller: Add fsl,icoll.yaml
dt-bindings: interrupt-controller: Add missing Xilinx INTC binding
dt-bindings: display: sprd,sharkl3-dsi-host: Fix missing clocks constraints
dt-bindings: display: sprd,sharkl3-dpu: Fix missing clocks constraints
dt-bindings: display: imx: convert fsl,dcu.txt to yaml format
dt-bindings: timer: via,vt8500-timer: Convert to YAML
dt-bindings: net: Convert Marvell Armada NETA and BM to DT schema
dt-bindings: trivial-devices: Add undocumented hwmon devices
dt-bindings: interrupt-controller: Convert apm,xgene1-msi to DT schema
dt-bindings: gpu: mali-bifrost: Add Allwinner A523 compatible
docs: dt: writing-schema: Document preferred order of properties
docs: dt: writing-bindings: Document discouraged instance IDs
docs: dt: writing-bindings: Document compatible and filename naming
docs: dt: submitting-patches: Avoid 'YAML' in the subject and add an example
MAINTAINERS: adjust file entry in INTEL STRATIX10 FIRMWARE DRIVERS
docs: dt: writing-bindings: Consistently use single-whitespace
docs: dt: writing-bindings: Express better expectations of "specific"
...
+1341
-786
+5
-5
Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
+5
-5
Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
···
41
41
examples:
42
42
43
43
- |
44
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
44
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
45
45
46
-
trbe {
47
-
compatible = "arm,trace-buffer-extension";
48
-
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
49
-
};
46
+
trbe {
47
+
compatible = "arm,trace-buffer-extension";
48
+
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
49
+
};
50
50
...
-30
Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
-30
Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
···
1
-
Freescale Vybrid Miscellaneous System Control - Interrupt Router
2
-
3
-
The MSCM IP contains multiple sub modules, this binding describes the second
4
-
block of registers which control the interrupt router. The interrupt router
5
-
allows to configure the recipient of each peripheral interrupt. Furthermore
6
-
it controls the directed processor interrupts. The module is available in all
7
-
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
8
-
which comes with a Cortex-A5/Cortex-M4 combination).
9
-
10
-
Required properties:
11
-
- compatible: "fsl,vf610-mscm-ir"
12
-
- reg: the register range of the MSCM Interrupt Router
13
-
- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
14
-
to get the current CPU ID
15
-
- interrupt-controller: Identifies the node as an interrupt controller
16
-
- #interrupt-cells: Two cells, interrupt number and cells.
17
-
The hardware interrupt number according to interrupt
18
-
assignment of the interrupt router is required.
19
-
Flags get passed only when using GIC as parent. Flags
20
-
encoding as documented by the GIC bindings.
21
-
22
-
Example:
23
-
mscm_ir: interrupt-controller@40001800 {
24
-
compatible = "fsl,vf610-mscm-ir";
25
-
reg = <0x40001800 0x400>;
26
-
fsl,cpucfg = <&mscm_cpucfg>;
27
-
interrupt-controller;
28
-
#interrupt-cells = <2>;
29
-
interrupt-parent = <&intc>;
30
-
}
+10
-10
Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml
+10
-10
Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml
···
55
55
examples:
56
56
- |
57
57
ahb {
58
-
compatible = "st,mlahb", "simple-bus";
59
-
#address-cells = <1>;
60
-
#size-cells = <1>;
61
-
ranges;
62
-
dma-ranges = <0x00000000 0x38000000 0x10000>,
63
-
<0x10000000 0x10000000 0x60000>,
64
-
<0x30000000 0x30000000 0x60000>;
58
+
compatible = "st,mlahb", "simple-bus";
59
+
#address-cells = <1>;
60
+
#size-cells = <1>;
61
+
ranges;
62
+
dma-ranges = <0x00000000 0x38000000 0x10000>,
63
+
<0x10000000 0x10000000 0x60000>,
64
+
<0x30000000 0x30000000 0x60000>;
65
65
66
-
m4_rproc: m4@10000000 {
67
-
reg = <0x10000000 0x40000>;
68
-
};
66
+
m4_rproc: m4@10000000 {
67
+
reg = <0x10000000 0x40000>;
68
+
};
69
69
};
70
70
71
71
...
+3
Documentation/devicetree/bindings/display/arm,pl11x.yaml
+3
Documentation/devicetree/bindings/display/arm,pl11x.yaml
-34
Documentation/devicetree/bindings/display/fsl,dcu.txt
-34
Documentation/devicetree/bindings/display/fsl,dcu.txt
···
1
-
Device Tree bindings for Freescale DCU DRM Driver
2
-
3
-
Required properties:
4
-
- compatible: Should be one of
5
-
* "fsl,ls1021a-dcu".
6
-
* "fsl,vf610-dcu".
7
-
8
-
- reg: Address and length of the register set for dcu.
9
-
- clocks: Handle to "dcu" and "pix" clock (in the order below)
10
-
This can be the same clock (e.g. LS1021a)
11
-
See ../clocks/clock-bindings.txt for details.
12
-
- clock-names: Should be "dcu" and "pix"
13
-
See ../clocks/clock-bindings.txt for details.
14
-
- big-endian Boolean property, LS1021A DCU registers are big-endian.
15
-
- port Video port for the panel output
16
-
17
-
Optional properties:
18
-
- fsl,tcon: The phandle to the timing controller node.
19
-
20
-
Examples:
21
-
dcu: dcu@2ce0000 {
22
-
compatible = "fsl,ls1021a-dcu";
23
-
reg = <0x0 0x2ce0000 0x0 0x10000>;
24
-
clocks = <&platform_clk 0>, <&platform_clk 0>;
25
-
clock-names = "dcu", "pix";
26
-
big-endian;
27
-
fsl,tcon = <&tcon>;
28
-
29
-
port {
30
-
dcu_out: endpoint {
31
-
remote-endpoint = <&panel_out>;
32
-
};
33
-
};
34
-
};
+18
-1
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
+18
-1
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
···
71
71
$ref: /schemas/graph.yaml#/properties/port
72
72
description: The LCDIF output port
73
73
74
+
display:
75
+
$ref: /schemas/types.yaml#/definitions/phandle
76
+
description: phandle to display panel
77
+
deprecated: true
78
+
79
+
display0:
80
+
$ref: panel/panel-common.yaml#
81
+
deprecated: true
82
+
83
+
lcd-supply:
84
+
deprecated: true
85
+
74
86
required:
75
87
- compatible
76
88
- reg
77
89
- clocks
78
90
- interrupts
79
-
- port
80
91
81
92
additionalProperties: false
82
93
···
186
175
properties:
187
176
dmas: false
188
177
dma-names: false
178
+
display: false
179
+
display0: false
180
+
lcd-supply: false
181
+
182
+
required:
183
+
- port
189
184
190
185
examples:
191
186
- |
+71
Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml
+71
Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/fsl,ls1021a-dcu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale DCU DRM Driver
8
+
9
+
maintainers:
10
+
- Frank Li <Frank.Li@nxp.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- fsl,ls1021a-dcu
16
+
- fsl,vf610-dcu
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
interrupts:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
maxItems: 2
26
+
27
+
clock-names:
28
+
items:
29
+
- const: dcu
30
+
- const: pix
31
+
32
+
big-endian: true
33
+
34
+
port:
35
+
$ref: /schemas/graph.yaml#/$defs/port-base
36
+
unevaluatedProperties: false
37
+
description: Video port for the panel output
38
+
39
+
properties:
40
+
endpoint:
41
+
$ref: /schemas/media/video-interfaces.yaml#
42
+
unevaluatedProperties: false
43
+
44
+
fsl,tcon:
45
+
$ref: /schemas/types.yaml#/definitions/phandle
46
+
description: The phandle to the timing controller node.
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
- clocks
52
+
- clock-names
53
+
54
+
additionalProperties: false
55
+
56
+
examples:
57
+
- |
58
+
display-controller@2ce0000 {
59
+
compatible = "fsl,ls1021a-dcu";
60
+
reg = <0x2ce0000 0x10000>;
61
+
clocks = <&platform_clk 0>, <&platform_clk 0>;
62
+
clock-names = "dcu", "pix";
63
+
big-endian;
64
+
fsl,tcon = <&tcon>;
65
+
66
+
port {
67
+
endpoint {
68
+
remote-endpoint = <&panel_out>;
69
+
};
70
+
};
71
+
};
+78
Documentation/devicetree/bindings/display/himax,hx8357.yaml
+78
Documentation/devicetree/bindings/display/himax,hx8357.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/himax,hx8357.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Himax HX8357D display panel
8
+
9
+
description:
10
+
Display panels using a Himax HX8357D controller in SPI
11
+
mode, such as the Adafruit 3.5" TFT for Raspberry Pi.
12
+
13
+
maintainers:
14
+
- Frank Li <Frank.Li@nxp.com>
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- items:
20
+
- enum:
21
+
- adafruit,yx350hv15
22
+
- himax,hx8357b
23
+
- const: himax,hx8357
24
+
- items:
25
+
- enum:
26
+
- himax,hx8369a
27
+
- const: himax,hx8369
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
dc-gpios:
33
+
maxItems: 1
34
+
description: D/C pin
35
+
36
+
rotation:
37
+
enum: [0, 90, 180, 270]
38
+
39
+
backlight:
40
+
description:
41
+
phandle of the backlight device attached to the panel
42
+
43
+
im-gpios:
44
+
maxItems: 3
45
+
46
+
reset-gpios:
47
+
maxItems: 1
48
+
49
+
spi-cpha: true
50
+
51
+
spi-cpol: true
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
57
+
allOf:
58
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
59
+
60
+
unevaluatedProperties: false
61
+
62
+
examples:
63
+
- |
64
+
#include <dt-bindings/gpio/gpio.h>
65
+
66
+
spi {
67
+
#address-cells = <1>;
68
+
#size-cells = <0>;
69
+
70
+
display@0 {
71
+
compatible = "adafruit,yx350hv15", "himax,hx8357";
72
+
reg = <0>;
73
+
spi-max-frequency = <32000000>;
74
+
dc-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
75
+
rotation = <90>;
76
+
backlight = <&backlight>;
77
+
};
78
+
};
-26
Documentation/devicetree/bindings/display/himax,hx8357d.txt
-26
Documentation/devicetree/bindings/display/himax,hx8357d.txt
···
1
-
Himax HX8357D display panels
2
-
3
-
This binding is for display panels using a Himax HX8357D controller in SPI
4
-
mode, such as the Adafruit 3.5" TFT for Raspberry Pi.
5
-
6
-
Required properties:
7
-
- compatible: "adafruit,yx350hv15", "himax,hx8357d"
8
-
- dc-gpios: D/C pin
9
-
- reg: address of the panel on the SPI bus
10
-
11
-
The node for this driver must be a child node of a SPI controller, hence
12
-
all mandatory properties described in ../spi/spi-bus.txt must be specified.
13
-
14
-
Optional properties:
15
-
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
16
-
- backlight: phandle of the backlight device attached to the panel
17
-
18
-
Example:
19
-
display@0{
20
-
compatible = "adafruit,yx350hv15", "himax,hx8357d";
21
-
reg = <0>;
22
-
spi-max-frequency = <32000000>;
23
-
dc-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
24
-
rotation = <90>;
25
-
backlight = <&backlight>;
26
-
};
+3
Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
+3
Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
-22
Documentation/devicetree/bindings/display/sitronix,st7586.txt
-22
Documentation/devicetree/bindings/display/sitronix,st7586.txt
···
1
-
Sitronix ST7586 display panel
2
-
3
-
Required properties:
4
-
- compatible: "lego,ev3-lcd".
5
-
- a0-gpios: The A0 signal (since this binding is for serial mode, this is
6
-
the pin labeled D1 on the controller, not the pin labeled A0)
7
-
- reset-gpios: Reset pin
8
-
9
-
The node for this driver must be a child node of a SPI controller, hence
10
-
all mandatory properties described in ../spi/spi-bus.txt must be specified.
11
-
12
-
Optional properties:
13
-
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
14
-
15
-
Example:
16
-
display@0{
17
-
compatible = "lego,ev3-lcd";
18
-
reg = <0>;
19
-
spi-max-frequency = <10000000>;
20
-
a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
21
-
reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
22
-
};
+61
Documentation/devicetree/bindings/display/sitronix,st7586.yaml
+61
Documentation/devicetree/bindings/display/sitronix,st7586.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/sitronix,st7586.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Sitronix ST7586 Display Controller
8
+
9
+
maintainers:
10
+
- David Lechner <david@lechnology.com>
11
+
12
+
description:
13
+
Sitronix ST7586 is a driver and controller for 4-level gray
14
+
scale and monochrome dot matrix LCD panels.
15
+
https://topwaydisplay.com/sites/default/files/2020-04/ST7586S.pdf
16
+
17
+
$ref: panel/panel-common.yaml#
18
+
19
+
additionalProperties: false
20
+
21
+
properties:
22
+
compatible:
23
+
const: lego,ev3-lcd
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
spi-max-frequency:
29
+
maximum: 50000000
30
+
31
+
a0-gpios:
32
+
description:
33
+
The A0 signal (for serial mode, this is the pin labeled D1 on the
34
+
controller, not the pin labeled A0)
35
+
maxItems: 1
36
+
37
+
reset-gpios: true
38
+
rotation: true
39
+
40
+
required:
41
+
- compatible
42
+
- reg
43
+
- a0-gpios
44
+
- reset-gpios
45
+
46
+
examples:
47
+
- |
48
+
#include <dt-bindings/gpio/gpio.h>
49
+
50
+
spi {
51
+
#address-cells = <1>;
52
+
#size-cells = <0>;
53
+
54
+
display@0 {
55
+
compatible = "lego,ev3-lcd";
56
+
reg = <0>;
57
+
spi-max-frequency = <10000000>;
58
+
a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
59
+
reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
60
+
};
61
+
};
+1
-1
Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
+1
-1
Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
+1
-1
Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml
+1
-1
Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml
+21
-21
Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml
+21
-21
Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml
···
81
81
#include <dt-bindings/interrupt-controller/arm-gic.h>
82
82
#include <dt-bindings/interrupt-controller/irq.h>
83
83
dsp@10803000 {
84
-
compatible = "mediatek,mt8195-dsp";
85
-
reg = <0x10803000 0x1000>,
86
-
<0x10840000 0x40000>;
87
-
reg-names = "cfg", "sram";
88
-
clocks = <&topckgen 10>, //CLK_TOP_ADSP
89
-
<&clk26m>,
90
-
<&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
91
-
<&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
92
-
<&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP
93
-
<&topckgen 34>; //CLK_TOP_AUDIO_H
94
-
clock-names = "adsp_sel",
95
-
"clk26m_ck",
96
-
"audio_local_bus",
97
-
"mainpll_d7_d2",
98
-
"scp_adsp_audiodsp",
99
-
"audio_h";
100
-
memory-region = <&adsp_dma_mem_reserved>,
101
-
<&adsp_mem_reserved>;
102
-
power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
103
-
mbox-names = "rx", "tx";
104
-
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
84
+
compatible = "mediatek,mt8195-dsp";
85
+
reg = <0x10803000 0x1000>,
86
+
<0x10840000 0x40000>;
87
+
reg-names = "cfg", "sram";
88
+
clocks = <&topckgen 10>, //CLK_TOP_ADSP
89
+
<&clk26m>,
90
+
<&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
91
+
<&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
92
+
<&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP
93
+
<&topckgen 34>; //CLK_TOP_AUDIO_H
94
+
clock-names = "adsp_sel",
95
+
"clk26m_ck",
96
+
"audio_local_bus",
97
+
"mainpll_d7_d2",
98
+
"scp_adsp_audiodsp",
99
+
"audio_h";
100
+
memory-region = <&adsp_dma_mem_reserved>,
101
+
<&adsp_mem_reserved>;
102
+
power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
103
+
mbox-names = "rx", "tx";
104
+
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
105
105
};
+26
-26
Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
+26
-26
Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
···
62
62
#include <dt-bindings/gpio/gpio.h>
63
63
64
64
npe: npe@c8006000 {
65
-
compatible = "intel,ixp4xx-network-processing-engine";
66
-
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
67
-
#address-cells = <1>;
68
-
#size-cells = <0>;
65
+
compatible = "intel,ixp4xx-network-processing-engine";
66
+
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
67
+
#address-cells = <1>;
68
+
#size-cells = <0>;
69
69
70
-
hss@0 {
71
-
compatible = "intel,ixp4xx-hss";
72
-
reg = <0>;
73
-
intel,npe-handle = <&npe 0>;
74
-
intel,queue-chl-rxtrig = <&qmgr 12>;
75
-
intel,queue-chl-txready = <&qmgr 34>;
76
-
intel,queue-pkt-rx = <&qmgr 13>;
77
-
intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
78
-
intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
79
-
intel,queue-pkt-txdone = <&qmgr 22>;
80
-
cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
81
-
rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
82
-
dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
83
-
dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
84
-
clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
85
-
};
70
+
hss@0 {
71
+
compatible = "intel,ixp4xx-hss";
72
+
reg = <0>;
73
+
intel,npe-handle = <&npe 0>;
74
+
intel,queue-chl-rxtrig = <&qmgr 12>;
75
+
intel,queue-chl-txready = <&qmgr 34>;
76
+
intel,queue-pkt-rx = <&qmgr 13>;
77
+
intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
78
+
intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
79
+
intel,queue-pkt-txdone = <&qmgr 22>;
80
+
cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
81
+
rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
82
+
dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
83
+
dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
84
+
clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
85
+
};
86
86
87
-
crypto {
88
-
compatible = "intel,ixp4xx-crypto";
89
-
intel,npe-handle = <&npe 2>;
90
-
queue-rx = <&qmgr 30>;
91
-
queue-txready = <&qmgr 29>;
92
-
};
87
+
crypto {
88
+
compatible = "intel,ixp4xx-crypto";
89
+
intel,npe-handle = <&npe 2>;
90
+
queue-rx = <&qmgr 30>;
91
+
queue-txready = <&qmgr 29>;
92
+
};
93
93
};
94
94
...
+1
-1
Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
+1
-1
Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
+1
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+1
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
···
40
40
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
41
41
- items:
42
42
- enum:
43
+
- allwinner,sun55i-a523-mali
43
44
- mediatek,mt8188-mali
44
45
- mediatek,mt8192-mali
45
46
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
+54
Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml
+54
Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/apm,xgene1-msi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: AppliedMicro X-Gene v1 PCIe MSI controller
8
+
9
+
maintainers:
10
+
- Toan Le <toan@os.amperecomputing.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: apm,xgene1-msi
15
+
16
+
msi-controller: true
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
interrupts:
22
+
maxItems: 16
23
+
24
+
required:
25
+
- compatible
26
+
- msi-controller
27
+
- reg
28
+
- interrupts
29
+
30
+
additionalProperties: false
31
+
32
+
examples:
33
+
- |
34
+
msi@79000000 {
35
+
compatible = "apm,xgene1-msi";
36
+
msi-controller;
37
+
reg = <0x79000000 0x900000>;
38
+
interrupts = <0x0 0x10 0x4>,
39
+
<0x0 0x11 0x4>,
40
+
<0x0 0x12 0x4>,
41
+
<0x0 0x13 0x4>,
42
+
<0x0 0x14 0x4>,
43
+
<0x0 0x15 0x4>,
44
+
<0x0 0x16 0x4>,
45
+
<0x0 0x17 0x4>,
46
+
<0x0 0x18 0x4>,
47
+
<0x0 0x19 0x4>,
48
+
<0x0 0x1a 0x4>,
49
+
<0x0 0x1b 0x4>,
50
+
<0x0 0x1c 0x4>,
51
+
<0x0 0x1d 0x4>,
52
+
<0x0 0x1e 0x4>,
53
+
<0x0 0x1f 0x4>;
54
+
};
+2
-1
Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml
+2
-1
Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml
···
17
17
properties:
18
18
compatible:
19
19
enum:
20
+
- arm,armv7m-nvic # deprecated
20
21
- arm,v6m-nvic
21
22
- arm,v7m-nvic
22
23
- arm,v8m-nvic
···
31
30
interrupt-controller: true
32
31
33
32
'#interrupt-cells':
34
-
const: 2
33
+
enum: [1, 2]
35
34
description: |
36
35
Number of cells to encode an interrupt source:
37
36
first = interrupt number, second = priority.
+45
Documentation/devicetree/bindings/interrupt-controller/fsl,icoll.yaml
+45
Documentation/devicetree/bindings/interrupt-controller/fsl,icoll.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/fsl,icoll.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale MXS icoll Interrupt controller
8
+
9
+
maintainers:
10
+
- Frank Li <Frank.Li@nxp.com>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- items:
16
+
- enum:
17
+
- fsl,imx23-icoll
18
+
- fsl,imx28-icoll
19
+
- const: fsl,icoll
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
interrupt-controller: true
25
+
26
+
'#interrupt-cells':
27
+
const: 1
28
+
29
+
required:
30
+
- compatible
31
+
- reg
32
+
- interrupt-controller
33
+
- '#interrupt-cells'
34
+
35
+
additionalProperties: false
36
+
37
+
examples:
38
+
- |
39
+
interrupt-controller@80000000 {
40
+
compatible = "fsl,imx28-icoll", "fsl,icoll";
41
+
reg = <0x80000000 0x2000>;
42
+
interrupt-controller;
43
+
#interrupt-cells = <1>;
44
+
};
45
+
+161
Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml
+161
Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale MSI interrupt controller
8
+
9
+
description: |
10
+
The Freescale hypervisor and msi-address-64
11
+
-------------------------------------------
12
+
13
+
Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
14
+
Freescale MSI driver calculates the address of MSIIR (in the MSI register
15
+
block) and sets that address as the MSI message address.
16
+
17
+
In a virtualized environment, the hypervisor may need to create an IOMMU
18
+
mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement
19
+
because of hardware limitations of the Peripheral Access Management Unit
20
+
(PAMU), which is currently the only IOMMU that the hypervisor supports.
21
+
The ATMU is programmed with the guest physical address, and the PAMU
22
+
intercepts transactions and reroutes them to the true physical address.
23
+
24
+
In the PAMU, each PCI controller is given only one primary window. The
25
+
PAMU restricts DMA operations so that they can only occur within a window.
26
+
Because PCI devices must be able to DMA to memory, the primary window must
27
+
be used to cover all of the guest's memory space.
28
+
29
+
PAMU primary windows can be divided into 256 subwindows, and each
30
+
subwindow can have its own address mapping ("guest physical" to "true
31
+
physical"). However, each subwindow has to have the same alignment, which
32
+
means they cannot be located at just any address. Because of these
33
+
restrictions, it is usually impossible to create a 4KB subwindow that
34
+
covers MSIIR where it's normally located.
35
+
36
+
Therefore, the hypervisor has to create a subwindow inside the same
37
+
primary window used for memory, but mapped to the MSIR block (where MSIIR
38
+
lives). The first subwindow after the end of guest memory is used for
39
+
this. The address specified in the msi-address-64 property is the PCI
40
+
address of MSIIR. The hypervisor configures the PAMU to map that address to
41
+
the true physical address of MSIIR.
42
+
43
+
maintainers:
44
+
- J. Neuschäfer <j.ne@posteo.net>
45
+
46
+
properties:
47
+
compatible:
48
+
oneOf:
49
+
- enum:
50
+
- fsl,mpic-msi
51
+
- fsl,mpic-msi-v4.3
52
+
- fsl,ipic-msi
53
+
- fsl,vmpic-msi
54
+
- fsl,vmpic-msi-v4.3
55
+
- items:
56
+
- enum:
57
+
- fsl,mpc8572-msi
58
+
- fsl,mpc8610-msi
59
+
- fsl,mpc8641-msi
60
+
- const: fsl,mpic-msi
61
+
62
+
reg:
63
+
minItems: 1
64
+
items:
65
+
- description: Address and length of the shared message interrupt
66
+
register set
67
+
- description: Address of aliased MSIIR or MSIIR1 register for platforms
68
+
that have such an alias. If using MSIIR1, the second region must be
69
+
added because different MSI group has different MSIIR1 offset.
70
+
71
+
interrupts:
72
+
minItems: 1
73
+
maxItems: 16
74
+
description:
75
+
Each one of the interrupts here is one entry per 32 MSIs, and routed to
76
+
the host interrupt controller. The interrupts should be set as edge
77
+
sensitive. If msi-available-ranges is present, only the interrupts that
78
+
correspond to available ranges shall be present.
79
+
80
+
msi-available-ranges:
81
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
82
+
items:
83
+
items:
84
+
- description: First MSI interrupt in this range
85
+
- description: Number of MSI interrupts in this range
86
+
description:
87
+
Define which MSI interrupt can be used in the 256 MSI interrupts.
88
+
If not specified, all the MSI interrupts can be used.
89
+
Each available range must begin and end on a multiple of 32 (i.e. no
90
+
splitting an individual MSI register or the associated PIC interrupt).
91
+
92
+
msi-address-64:
93
+
$ref: /schemas/types.yaml#/definitions/uint64
94
+
description:
95
+
64-bit PCI address of the MSIIR register. The MSIIR register is used for
96
+
MSI messaging. The address of MSIIR in PCI address space is the MSI
97
+
message address.
98
+
99
+
This property may be used in virtualized environments where the hypervisor
100
+
has created an alternate mapping for the MSIR block. See the top-level
101
+
description for an explanation.
102
+
103
+
required:
104
+
- compatible
105
+
- reg
106
+
- interrupts
107
+
108
+
allOf:
109
+
- if:
110
+
properties:
111
+
compatible:
112
+
contains:
113
+
enum:
114
+
- fsl,mpic-msi-v4.3
115
+
- fsl,vmpic-msi-v4.3
116
+
then:
117
+
properties:
118
+
interrupts:
119
+
minItems: 16
120
+
description:
121
+
Version 4.3 implies that there are 16 shared interrupts, and they
122
+
are configured through MSIIR1.
123
+
124
+
# MPIC v4.3 does not support this property because the 32 interrupts of
125
+
# an individual register are not continuous when using MSIIR1.
126
+
msi-available-ranges: false
127
+
128
+
reg:
129
+
minItems: 2
130
+
131
+
else:
132
+
properties:
133
+
interrupts:
134
+
maxItems: 8
135
+
description:
136
+
In versions before 4.3, only 8 shared interrupts are available, and
137
+
they are configured through MSIIR.
138
+
139
+
unevaluatedProperties: false
140
+
141
+
examples:
142
+
- |
143
+
msi@41600 {
144
+
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
145
+
reg = <0x41600 0x80>;
146
+
msi-available-ranges = <0 0x100>;
147
+
interrupts = <0xe0 0>, <0xe1 0>, <0xe2 0>, <0xe3 0>,
148
+
<0xe4 0>, <0xe5 0>, <0xe6 0>, <0xe7 0>;
149
+
};
150
+
151
+
- |
152
+
msi@41600 {
153
+
compatible = "fsl,mpic-msi-v4.3";
154
+
reg = <0x41600 0x200>, <0x44148 4>;
155
+
interrupts = <0xe0 0 0 0>, <0xe1 0 0 0>, <0xe2 0 0 0>, <0xe3 0 0 0>,
156
+
<0xe4 0 0 0>, <0xe5 0 0 0>, <0xe6 0 0 0>, <0xe7 0 0 0>,
157
+
<0x100 0 0 0>, <0x101 0 0 0>, <0x102 0 0 0>, <0x103 0 0 0>,
158
+
<0x104 0 0 0>, <0x105 0 0 0>, <0x106 0 0 0>, <0x107 0 0 0>;
159
+
};
160
+
161
+
...
+63
Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml
+63
Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/fsl,vf610-mscm-ir.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale Vybrid Miscellaneous System Control - Interrupt Router
8
+
9
+
description:
10
+
The MSCM IP contains multiple sub modules, this binding describes the second
11
+
block of registers which control the interrupt router. The interrupt router
12
+
allows to configure the recipient of each peripheral interrupt. Furthermore
13
+
it controls the directed processor interrupts. The module is available in all
14
+
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
15
+
which comes with a Cortex-A5/Cortex-M4 combination).
16
+
17
+
18
+
maintainers:
19
+
- Frank Li <Frank.Li@nxp.com>
20
+
21
+
properties:
22
+
compatible:
23
+
const: fsl,vf610-mscm-ir
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
fsl,cpucfg:
29
+
$ref: /schemas/types.yaml#/definitions/phandle
30
+
description:
31
+
The handle to the MSCM CPU configuration node, required
32
+
to get the current CPU ID
33
+
34
+
interrupt-controller: true
35
+
36
+
'#interrupt-cells':
37
+
const: 2
38
+
description:
39
+
Two cells, interrupt number and cells.
40
+
The hardware interrupt number according to interrupt
41
+
assignment of the interrupt router is required.
42
+
Flags get passed only when using GIC as parent. Flags
43
+
encoding as documented by the GIC bindings.
44
+
45
+
required:
46
+
- compatible
47
+
- reg
48
+
- fsl,cpucfg
49
+
- interrupt-controller
50
+
- '#interrupt-cells'
51
+
52
+
additionalProperties: false
53
+
54
+
examples:
55
+
- |
56
+
interrupt-controller@40001800 {
57
+
compatible = "fsl,vf610-mscm-ir";
58
+
reg = <0x40001800 0x400>;
59
+
fsl,cpucfg = <&mscm_cpucfg>;
60
+
interrupt-controller;
61
+
#interrupt-cells = <2>;
62
+
interrupt-parent = <&intc>;
63
+
};
+82
Documentation/devicetree/bindings/interrupt-controller/xlnx,intc.yaml
+82
Documentation/devicetree/bindings/interrupt-controller/xlnx,intc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/xlnx,intc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Xilinx Interrupt Controller
8
+
9
+
maintainers:
10
+
- Michal Simek <michal.simek@amd.com>
11
+
12
+
description:
13
+
The controller is a soft IP core that is configured at build time for the
14
+
number of interrupts and the type of each interrupt. These details cannot
15
+
be changed at run time.
16
+
17
+
properties:
18
+
compatible:
19
+
const: xlnx,xps-intc-1.00.a
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
maxItems: 1
26
+
27
+
power-domains:
28
+
maxItems: 1
29
+
30
+
resets:
31
+
maxItems: 1
32
+
33
+
"#interrupt-cells":
34
+
const: 2
35
+
description:
36
+
Specifies the number of cells needed to encode an interrupt source.
37
+
The value shall be a minimum of 1. The Xilinx device trees typically
38
+
use 2 but the 2nd value is not used.
39
+
40
+
interrupt-controller: true
41
+
42
+
interrupts:
43
+
maxItems: 1
44
+
description:
45
+
Specifies the interrupt of the parent controller from which it is chained.
46
+
47
+
xlnx,kind-of-intr:
48
+
$ref: /schemas/types.yaml#/definitions/uint32
49
+
description:
50
+
A 32 bit value specifying the interrupt type for each possible interrupt
51
+
(1 = edge, 0 = level). The interrupt type typically comes in thru
52
+
the device tree node of the interrupt generating device, but in this case
53
+
the interrupt type is determined by the interrupt controller based on how
54
+
it was implemented.
55
+
56
+
xlnx,num-intr-inputs:
57
+
$ref: /schemas/types.yaml#/definitions/uint32
58
+
minimum: 1
59
+
maximum: 32
60
+
description:
61
+
Specifies the number of interrupts supported by the specific
62
+
implementation of the controller.
63
+
64
+
required:
65
+
- reg
66
+
- "#interrupt-cells"
67
+
- interrupt-controller
68
+
- xlnx,kind-of-intr
69
+
- xlnx,num-intr-inputs
70
+
71
+
additionalProperties: false
72
+
73
+
examples:
74
+
- |
75
+
interrupt-controller@41800000 {
76
+
compatible = "xlnx,xps-intc-1.00.a";
77
+
reg = <0x41800000 0x10000>;
78
+
#interrupt-cells = <2>;
79
+
interrupt-controller;
80
+
xlnx,kind-of-intr = <0x1>;
81
+
xlnx,num-intr-inputs = <1>;
82
+
};
+3
-3
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
+3
-3
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
···
139
139
140
140
/* The IOMMU programming interface uses slot 00:01.0 */
141
141
iommu0: iommu@1,0 {
142
-
compatible = "pci1efd,edf1", "riscv,pci-iommu";
143
-
reg = <0x800 0 0 0 0>;
144
-
#iommu-cells = <1>;
142
+
compatible = "pci1efd,edf1", "riscv,pci-iommu";
143
+
reg = <0x800 0 0 0 0>;
144
+
#iommu-cells = <1>;
145
145
};
146
146
};
147
147
};
+97
-98
Documentation/devicetree/bindings/leds/leds-mt6360.yaml
+97
-98
Documentation/devicetree/bindings/leds/leds-mt6360.yaml
···
87
87
88
88
examples:
89
89
- |
90
-
#include <dt-bindings/leds/common.h>
91
-
led-controller {
92
-
compatible = "mediatek,mt6360-led";
93
-
#address-cells = <1>;
94
-
#size-cells = <0>;
90
+
#include <dt-bindings/leds/common.h>
91
+
led-controller {
92
+
compatible = "mediatek,mt6360-led";
93
+
#address-cells = <1>;
94
+
#size-cells = <0>;
95
95
96
-
multi-led@0 {
97
-
reg = <0>;
98
-
function = LED_FUNCTION_INDICATOR;
99
-
color = <LED_COLOR_ID_RGB>;
100
-
led-max-microamp = <24000>;
101
-
#address-cells = <1>;
102
-
#size-cells = <0>;
103
-
led@0 {
104
-
reg = <0>;
105
-
color = <LED_COLOR_ID_RED>;
106
-
};
107
-
led@1 {
108
-
reg = <1>;
109
-
color = <LED_COLOR_ID_GREEN>;
110
-
};
111
-
led@2 {
112
-
reg = <2>;
113
-
color = <LED_COLOR_ID_BLUE>;
114
-
};
115
-
};
116
-
led@3 {
117
-
reg = <3>;
118
-
function = LED_FUNCTION_INDICATOR;
119
-
color = <LED_COLOR_ID_WHITE>;
120
-
led-max-microamp = <150000>;
121
-
};
122
-
led@4 {
123
-
reg = <4>;
124
-
function = LED_FUNCTION_FLASH;
125
-
color = <LED_COLOR_ID_WHITE>;
126
-
function-enumerator = <1>;
127
-
led-max-microamp = <200000>;
128
-
flash-max-microamp = <500000>;
129
-
flash-max-timeout-us = <1024000>;
130
-
};
131
-
led@5 {
132
-
reg = <5>;
133
-
function = LED_FUNCTION_FLASH;
134
-
color = <LED_COLOR_ID_WHITE>;
135
-
function-enumerator = <2>;
136
-
led-max-microamp = <200000>;
137
-
flash-max-microamp = <500000>;
138
-
flash-max-timeout-us = <1024000>;
139
-
};
140
-
};
96
+
multi-led@0 {
97
+
reg = <0>;
98
+
function = LED_FUNCTION_INDICATOR;
99
+
color = <LED_COLOR_ID_RGB>;
100
+
led-max-microamp = <24000>;
101
+
#address-cells = <1>;
102
+
#size-cells = <0>;
103
+
led@0 {
104
+
reg = <0>;
105
+
color = <LED_COLOR_ID_RED>;
106
+
};
107
+
led@1 {
108
+
reg = <1>;
109
+
color = <LED_COLOR_ID_GREEN>;
110
+
};
111
+
led@2 {
112
+
reg = <2>;
113
+
color = <LED_COLOR_ID_BLUE>;
114
+
};
115
+
};
116
+
led@3 {
117
+
reg = <3>;
118
+
function = LED_FUNCTION_INDICATOR;
119
+
color = <LED_COLOR_ID_WHITE>;
120
+
led-max-microamp = <150000>;
121
+
};
122
+
led@4 {
123
+
reg = <4>;
124
+
function = LED_FUNCTION_FLASH;
125
+
color = <LED_COLOR_ID_WHITE>;
126
+
function-enumerator = <1>;
127
+
led-max-microamp = <200000>;
128
+
flash-max-microamp = <500000>;
129
+
flash-max-timeout-us = <1024000>;
130
+
};
131
+
led@5 {
132
+
reg = <5>;
133
+
function = LED_FUNCTION_FLASH;
134
+
color = <LED_COLOR_ID_WHITE>;
135
+
function-enumerator = <2>;
136
+
led-max-microamp = <200000>;
137
+
flash-max-microamp = <500000>;
138
+
flash-max-timeout-us = <1024000>;
139
+
};
140
+
};
141
141
142
142
- |
143
+
led-controller {
144
+
compatible = "mediatek,mt6360-led";
145
+
#address-cells = <1>;
146
+
#size-cells = <0>;
143
147
144
-
led-controller {
145
-
compatible = "mediatek,mt6360-led";
146
-
#address-cells = <1>;
147
-
#size-cells = <0>;
148
-
149
-
led@0 {
150
-
reg = <0>;
151
-
function = LED_FUNCTION_INDICATOR;
152
-
color = <LED_COLOR_ID_RED>;
153
-
led-max-microamp = <24000>;
154
-
};
155
-
led@1 {
156
-
reg = <1>;
157
-
function = LED_FUNCTION_INDICATOR;
158
-
color = <LED_COLOR_ID_GREEN>;
159
-
led-max-microamp = <24000>;
160
-
};
161
-
led@2 {
162
-
reg = <2>;
163
-
function = LED_FUNCTION_INDICATOR;
164
-
color = <LED_COLOR_ID_BLUE>;
165
-
led-max-microamp = <24000>;
166
-
};
167
-
led@3 {
168
-
reg = <3>;
169
-
function = LED_FUNCTION_INDICATOR;
170
-
color = <LED_COLOR_ID_WHITE>;
171
-
led-max-microamp = <150000>;
172
-
};
173
-
led@4 {
174
-
reg = <4>;
175
-
function = LED_FUNCTION_FLASH;
176
-
color = <LED_COLOR_ID_WHITE>;
177
-
function-enumerator = <1>;
178
-
led-max-microamp = <200000>;
179
-
flash-max-microamp = <500000>;
180
-
flash-max-timeout-us = <1024000>;
181
-
};
182
-
led@5 {
183
-
reg = <5>;
184
-
function = LED_FUNCTION_FLASH;
185
-
color = <LED_COLOR_ID_WHITE>;
186
-
function-enumerator = <2>;
187
-
led-max-microamp = <200000>;
188
-
flash-max-microamp = <500000>;
189
-
flash-max-timeout-us = <1024000>;
190
-
};
191
-
};
148
+
led@0 {
149
+
reg = <0>;
150
+
function = LED_FUNCTION_INDICATOR;
151
+
color = <LED_COLOR_ID_RED>;
152
+
led-max-microamp = <24000>;
153
+
};
154
+
led@1 {
155
+
reg = <1>;
156
+
function = LED_FUNCTION_INDICATOR;
157
+
color = <LED_COLOR_ID_GREEN>;
158
+
led-max-microamp = <24000>;
159
+
};
160
+
led@2 {
161
+
reg = <2>;
162
+
function = LED_FUNCTION_INDICATOR;
163
+
color = <LED_COLOR_ID_BLUE>;
164
+
led-max-microamp = <24000>;
165
+
};
166
+
led@3 {
167
+
reg = <3>;
168
+
function = LED_FUNCTION_INDICATOR;
169
+
color = <LED_COLOR_ID_WHITE>;
170
+
led-max-microamp = <150000>;
171
+
};
172
+
led@4 {
173
+
reg = <4>;
174
+
function = LED_FUNCTION_FLASH;
175
+
color = <LED_COLOR_ID_WHITE>;
176
+
function-enumerator = <1>;
177
+
led-max-microamp = <200000>;
178
+
flash-max-microamp = <500000>;
179
+
flash-max-timeout-us = <1024000>;
180
+
};
181
+
led@5 {
182
+
reg = <5>;
183
+
function = LED_FUNCTION_FLASH;
184
+
color = <LED_COLOR_ID_WHITE>;
185
+
function-enumerator = <2>;
186
+
led-max-microamp = <200000>;
187
+
flash-max-microamp = <500000>;
188
+
flash-max-timeout-us = <1024000>;
189
+
};
190
+
};
192
191
...
+21
-21
Documentation/devicetree/bindings/mips/brcm/soc.yaml
+21
-21
Documentation/devicetree/bindings/mips/brcm/soc.yaml
···
92
92
93
93
examples:
94
94
- |
95
-
/ {
96
-
compatible = "brcm,bcm3368";
97
-
#address-cells = <1>;
98
-
#size-cells = <1>;
99
-
model = "Broadcom 3368";
95
+
/ {
96
+
compatible = "brcm,bcm3368";
97
+
#address-cells = <1>;
98
+
#size-cells = <1>;
99
+
model = "Broadcom 3368";
100
100
101
-
cpus {
102
-
#address-cells = <1>;
103
-
#size-cells = <0>;
101
+
cpus {
102
+
#address-cells = <1>;
103
+
#size-cells = <0>;
104
104
105
-
mips-hpt-frequency = <150000000>;
105
+
mips-hpt-frequency = <150000000>;
106
106
107
-
cpu@0 {
108
-
compatible = "brcm,bmips4350";
109
-
device_type = "cpu";
110
-
reg = <0>;
111
-
};
107
+
cpu@0 {
108
+
compatible = "brcm,bmips4350";
109
+
device_type = "cpu";
110
+
reg = <0>;
111
+
};
112
112
113
-
cpu@1 {
114
-
compatible = "brcm,bmips4350";
115
-
device_type = "cpu";
116
-
reg = <1>;
117
-
};
118
-
};
119
-
};
113
+
cpu@1 {
114
+
compatible = "brcm,bmips4350";
115
+
device_type = "cpu";
116
+
reg = <1>;
117
+
};
118
+
};
119
+
};
120
120
...
+3
-3
Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
+3
-3
Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
···
45
45
#include <dt-bindings/interrupt-controller/irq.h>
46
46
47
47
qmgr: queue-manager@60000000 {
48
-
compatible = "intel,ixp4xx-ahb-queue-manager";
49
-
reg = <0x60000000 0x4000>;
50
-
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
48
+
compatible = "intel,ixp4xx-ahb-queue-manager";
49
+
reg = <0x60000000 0x4000>;
50
+
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
51
51
};
+38
-38
Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+38
-38
Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
···
245
245
#include <dt-bindings/power/r8a7790-sysc.h>
246
246
247
247
sdhi0: mmc@ee100000 {
248
-
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
249
-
reg = <0xee100000 0x328>;
250
-
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
251
-
clocks = <&cpg CPG_MOD 314>;
252
-
dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
253
-
dma-names = "tx", "rx", "tx", "rx";
254
-
max-frequency = <195000000>;
255
-
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
256
-
resets = <&cpg 314>;
248
+
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
249
+
reg = <0xee100000 0x328>;
250
+
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
251
+
clocks = <&cpg CPG_MOD 314>;
252
+
dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
253
+
dma-names = "tx", "rx", "tx", "rx";
254
+
max-frequency = <195000000>;
255
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
256
+
resets = <&cpg 314>;
257
257
};
258
258
259
259
sdhi1: mmc@ee120000 {
260
-
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
261
-
reg = <0xee120000 0x328>;
262
-
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
263
-
clocks = <&cpg CPG_MOD 313>;
264
-
dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
265
-
dma-names = "tx", "rx", "tx", "rx";
266
-
max-frequency = <195000000>;
267
-
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
268
-
resets = <&cpg 313>;
260
+
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
261
+
reg = <0xee120000 0x328>;
262
+
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
263
+
clocks = <&cpg CPG_MOD 313>;
264
+
dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
265
+
dma-names = "tx", "rx", "tx", "rx";
266
+
max-frequency = <195000000>;
267
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
268
+
resets = <&cpg 313>;
269
269
};
270
270
271
271
sdhi2: mmc@ee140000 {
272
-
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
273
-
reg = <0xee140000 0x100>;
274
-
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
275
-
clocks = <&cpg CPG_MOD 312>;
276
-
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
277
-
dma-names = "tx", "rx", "tx", "rx";
278
-
max-frequency = <97500000>;
279
-
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
280
-
resets = <&cpg 312>;
281
-
};
272
+
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
273
+
reg = <0xee140000 0x100>;
274
+
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
275
+
clocks = <&cpg CPG_MOD 312>;
276
+
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
277
+
dma-names = "tx", "rx", "tx", "rx";
278
+
max-frequency = <97500000>;
279
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
280
+
resets = <&cpg 312>;
281
+
};
282
282
283
-
sdhi3: mmc@ee160000 {
284
-
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
285
-
reg = <0xee160000 0x100>;
286
-
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
287
-
clocks = <&cpg CPG_MOD 311>;
288
-
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
289
-
dma-names = "tx", "rx", "tx", "rx";
290
-
max-frequency = <97500000>;
291
-
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
292
-
resets = <&cpg 311>;
283
+
sdhi3: mmc@ee160000 {
284
+
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
285
+
reg = <0xee160000 0x100>;
286
+
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
287
+
clocks = <&cpg CPG_MOD 311>;
288
+
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
289
+
dma-names = "tx", "rx", "tx", "rx";
290
+
max-frequency = <97500000>;
291
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
292
+
resets = <&cpg 311>;
293
293
};
+1
-1
Documentation/devicetree/bindings/mtd/technologic,nand.yaml
+1
-1
Documentation/devicetree/bindings/mtd/technologic,nand.yaml
+79
Documentation/devicetree/bindings/net/marvell,armada-370-neta.yaml
+79
Documentation/devicetree/bindings/net/marvell,armada-370-neta.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/net/marvell,armada-370-neta.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell Armada 370/XP/3700/AC5 Ethernet Controller (NETA)
8
+
9
+
maintainers:
10
+
- Marcin Wojtas <marcin.s.wojtas@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/net/ethernet-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- marvell,armada-370-neta
19
+
- marvell,armada-xp-neta
20
+
- marvell,armada-3700-neta
21
+
- marvell,armada-ac5-neta
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
minItems: 1
31
+
maxItems: 2
32
+
33
+
clock-names:
34
+
minItems: 1
35
+
items:
36
+
- const: core
37
+
- const: bus
38
+
39
+
phys:
40
+
maxItems: 1
41
+
42
+
tx-csum-limit:
43
+
description: Maximum MTU in bytes for Tx checksum offload; default is 1600 for
44
+
armada-370-neta and 9800 for others.
45
+
$ref: /schemas/types.yaml#/definitions/uint32
46
+
47
+
buffer-manager:
48
+
description: Phandle to hardware buffer manager.
49
+
$ref: /schemas/types.yaml#/definitions/phandle
50
+
51
+
bm,pool-long:
52
+
description: Pool ID for packets larger than the short threshold.
53
+
$ref: /schemas/types.yaml#/definitions/uint32
54
+
55
+
bm,pool-short:
56
+
description: Pool ID for packets smaller than the long threshold.
57
+
$ref: /schemas/types.yaml#/definitions/uint32
58
+
59
+
required:
60
+
- compatible
61
+
- reg
62
+
- clocks
63
+
64
+
unevaluatedProperties: false
65
+
66
+
examples:
67
+
- |
68
+
ethernet@70000 {
69
+
compatible = "marvell,armada-370-neta";
70
+
reg = <0x70000 0x2500>;
71
+
interrupts = <8>;
72
+
clocks = <&gate_clk 4>;
73
+
tx-csum-limit = <9800>;
74
+
phy = <&phy0>;
75
+
phy-mode = "rgmii-id";
76
+
buffer-manager = <&bm>;
77
+
bm,pool-long = <0>;
78
+
bm,pool-short = <1>;
79
+
};
+60
Documentation/devicetree/bindings/net/marvell,armada-380-neta-bm.yaml
+60
Documentation/devicetree/bindings/net/marvell,armada-380-neta-bm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/net/marvell,armada-380-neta-bm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell Armada 380/XP Buffer Manager (BM)
8
+
9
+
maintainers:
10
+
- Marcin Wojtas <marcin.s.wojtas@gmail.com>
11
+
12
+
description:
13
+
In order to see how to hook the BM to a given ethernet port, please refer to
14
+
Documentation/devicetree/bindings/net/marvell,armada-370-neta.yaml.
15
+
16
+
properties:
17
+
compatible:
18
+
const: marvell,armada-380-neta-bm
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
clocks:
24
+
maxItems: 1
25
+
26
+
internal-mem:
27
+
description: Phandle to internal SRAM region
28
+
$ref: /schemas/types.yaml#/definitions/phandle
29
+
30
+
patternProperties:
31
+
"^pool[0-3],capacity$":
32
+
description:
33
+
size of external buffer pointers' ring maintained in DRAM for pool 0-3
34
+
$ref: /schemas/types.yaml#/definitions/uint32
35
+
minimum: 128
36
+
maximum: 16352
37
+
38
+
"^pool[0-3],pkt-size$":
39
+
description:
40
+
maximum packet size for a short buffer pool entry (pool 0-3)
41
+
$ref: /schemas/types.yaml#/definitions/uint32
42
+
43
+
required:
44
+
- compatible
45
+
- reg
46
+
- clocks
47
+
- internal-mem
48
+
49
+
additionalProperties: false
50
+
51
+
examples:
52
+
- |
53
+
bm@c8000 {
54
+
compatible = "marvell,armada-380-neta-bm";
55
+
reg = <0xc8000 0xac>;
56
+
clocks = <&gateclk 13>;
57
+
internal-mem = <&bm_bppi>;
58
+
pool2,capacity = <4096>;
59
+
pool1,pkt-size = <512>;
60
+
};
-50
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
-50
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
···
1
-
* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
2
-
3
-
Required properties:
4
-
- compatible: could be one of the following:
5
-
"marvell,armada-370-neta"
6
-
"marvell,armada-xp-neta"
7
-
"marvell,armada-3700-neta"
8
-
"marvell,armada-ac5-neta"
9
-
- reg: address and length of the register set for the device.
10
-
- interrupts: interrupt for the device
11
-
- phy: See ethernet.txt file in the same directory.
12
-
- phy-mode: See ethernet.txt file in the same directory
13
-
- clocks: List of clocks for this device. At least one clock is
14
-
mandatory for the core clock. If several clocks are given, then the
15
-
clock-names property must be used to identify them.
16
-
17
-
Optional properties:
18
-
- tx-csum-limit: maximum mtu supported by port that allow TX checksum.
19
-
Value is presented in bytes. If not used, by default 1600B is set for
20
-
"marvell,armada-370-neta" and 9800B for others.
21
-
- clock-names: List of names corresponding to clocks property; shall be
22
-
"core" for core clock and "bus" for the optional bus clock.
23
-
- phys: comphy for the ethernet port, see ../phy/phy-bindings.txt
24
-
25
-
Optional properties (valid only for Armada XP/38x):
26
-
27
-
- buffer-manager: a phandle to a buffer manager node. Please refer to
28
-
Documentation/devicetree/bindings/net/marvell-neta-bm.txt
29
-
- bm,pool-long: ID of a pool, that will accept all packets of a size
30
-
higher than 'short' pool's threshold (if set) and up to MTU value.
31
-
Obligatory, when the port is supposed to use hardware
32
-
buffer management.
33
-
- bm,pool-short: ID of a pool, that will be used for accepting
34
-
packets of a size lower than given threshold. If not set, the port
35
-
will use a single 'long' pool for all packets, as defined above.
36
-
37
-
Example:
38
-
39
-
ethernet@70000 {
40
-
compatible = "marvell,armada-370-neta";
41
-
reg = <0x70000 0x2500>;
42
-
interrupts = <8>;
43
-
clocks = <&gate_clk 4>;
44
-
tx-csum-limit = <9800>
45
-
phy = <&phy0>;
46
-
phy-mode = "rgmii-id";
47
-
buffer-manager = <&bm>;
48
-
bm,pool-long = <0>;
49
-
bm,pool-short = <1>;
50
-
};
-47
Documentation/devicetree/bindings/net/marvell-neta-bm.txt
-47
Documentation/devicetree/bindings/net/marvell-neta-bm.txt
···
1
-
* Marvell Armada 380/XP Buffer Manager driver (BM)
2
-
3
-
Required properties:
4
-
5
-
- compatible: should be "marvell,armada-380-neta-bm".
6
-
- reg: address and length of the register set for the device.
7
-
- clocks: a pointer to the reference clock for this device.
8
-
- internal-mem: a phandle to BM internal SRAM definition.
9
-
10
-
Optional properties (port):
11
-
12
-
- pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
13
-
in DRAM. Can be set for each pool (id 0 : 3) separately. The value has
14
-
to be chosen between 128 and 16352 and it also has to be aligned to 32.
15
-
Otherwise the driver would adjust a given number or choose default if
16
-
not set.
17
-
- pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
18
-
pointers' pool (id 0 : 3). It will be taken into consideration only when pool
19
-
type is 'short'. For 'long' ones it would be overridden by port's MTU.
20
-
If not set a driver will choose a default value.
21
-
22
-
In order to see how to hook the BM to a given ethernet port, please
23
-
refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt.
24
-
25
-
Example:
26
-
27
-
- main node:
28
-
29
-
bm: bm@c8000 {
30
-
compatible = "marvell,armada-380-neta-bm";
31
-
reg = <0xc8000 0xac>;
32
-
clocks = <&gateclk 13>;
33
-
internal-mem = <&bm_bppi>;
34
-
pool2,capacity = <4096>;
35
-
pool1,pkt-size = <512>;
36
-
};
37
-
38
-
- internal SRAM node:
39
-
40
-
bm_bppi: bm-bppi {
41
-
compatible = "mmio-sram";
42
-
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
43
-
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
44
-
#address-cells = <1>;
45
-
#size-cells = <1>;
46
-
clocks = <&gateclk 13>;
47
-
};
+1
-1
Documentation/devicetree/bindings/nvmem/amlogic,meson6-efuse.yaml
+1
-1
Documentation/devicetree/bindings/nvmem/amlogic,meson6-efuse.yaml
+17
-17
Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+17
-17
Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
···
123
123
#size-cells = <2>;
124
124
125
125
pcie0_ep: pcie-ep@d000000 {
126
-
compatible = "ti,j721e-pcie-ep";
127
-
reg = <0x00 0x02900000 0x00 0x1000>,
128
-
<0x00 0x02907000 0x00 0x400>,
129
-
<0x00 0x0d000000 0x00 0x00800000>,
130
-
<0x00 0x10000000 0x00 0x08000000>;
131
-
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
132
-
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
133
-
max-link-speed = <3>;
134
-
num-lanes = <2>;
135
-
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
136
-
clocks = <&k3_clks 239 1>;
137
-
clock-names = "fck";
138
-
max-functions = /bits/ 8 <6>;
139
-
dma-coherent;
140
-
phys = <&serdes0_pcie_link>;
141
-
phy-names = "pcie-phy";
142
-
};
126
+
compatible = "ti,j721e-pcie-ep";
127
+
reg = <0x00 0x02900000 0x00 0x1000>,
128
+
<0x00 0x02907000 0x00 0x400>,
129
+
<0x00 0x0d000000 0x00 0x00800000>,
130
+
<0x00 0x10000000 0x00 0x08000000>;
131
+
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
132
+
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
133
+
max-link-speed = <3>;
134
+
num-lanes = <2>;
135
+
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
136
+
clocks = <&k3_clks 239 1>;
137
+
clock-names = "fck";
138
+
max-functions = /bits/ 8 <6>;
139
+
dma-coherent;
140
+
phys = <&serdes0_pcie_link>;
141
+
phy-names = "pcie-phy";
142
+
};
143
143
};
-68
Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
-68
Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
···
1
-
* AppliedMicro X-Gene v1 PCIe MSI controller
2
-
3
-
Required properties:
4
-
5
-
- compatible: should be "apm,xgene1-msi" to identify
6
-
X-Gene v1 PCIe MSI controller block.
7
-
- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8
-
- reg: physical base address (0x79000000) and length (0x900000) for controller
9
-
registers. These registers include the MSI termination address and data
10
-
registers as well as the MSI interrupt status registers.
11
-
- reg-names: not required
12
-
- interrupts: A list of 16 interrupt outputs of the controller, starting from
13
-
interrupt number 0x10 to 0x1f.
14
-
- interrupt-names: not required
15
-
16
-
Each PCIe node needs to have property msi-parent that points to an MSI
17
-
controller node
18
-
19
-
Examples:
20
-
21
-
SoC DTSI:
22
-
23
-
+ MSI node:
24
-
msi@79000000 {
25
-
compatible = "apm,xgene1-msi";
26
-
msi-controller;
27
-
reg = <0x00 0x79000000 0x0 0x900000>;
28
-
interrupts = <0x0 0x10 0x4>
29
-
<0x0 0x11 0x4>
30
-
<0x0 0x12 0x4>
31
-
<0x0 0x13 0x4>
32
-
<0x0 0x14 0x4>
33
-
<0x0 0x15 0x4>
34
-
<0x0 0x16 0x4>
35
-
<0x0 0x17 0x4>
36
-
<0x0 0x18 0x4>
37
-
<0x0 0x19 0x4>
38
-
<0x0 0x1a 0x4>
39
-
<0x0 0x1b 0x4>
40
-
<0x0 0x1c 0x4>
41
-
<0x0 0x1d 0x4>
42
-
<0x0 0x1e 0x4>
43
-
<0x0 0x1f 0x4>;
44
-
};
45
-
46
-
+ PCIe controller node with msi-parent property pointing to MSI node:
47
-
pcie0: pcie@1f2b0000 {
48
-
device_type = "pci";
49
-
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
50
-
#interrupt-cells = <1>;
51
-
#size-cells = <2>;
52
-
#address-cells = <3>;
53
-
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
54
-
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
55
-
reg-names = "csr", "cfg";
56
-
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
57
-
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
58
-
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
59
-
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
60
-
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
61
-
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
62
-
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
63
-
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
64
-
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
65
-
dma-coherent;
66
-
clocks = <&pcie0clk 0>;
67
-
msi-parent= <&msi>;
68
-
};
+31
-31
Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
+31
-31
Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
···
115
115
116
116
examples:
117
117
- |
118
-
#include <dt-bindings/interrupt-controller/irq.h>
119
-
#include <dt-bindings/input/linux-event-codes.h>
120
-
#include <dt-bindings/spmi/spmi.h>
118
+
#include <dt-bindings/interrupt-controller/irq.h>
119
+
#include <dt-bindings/input/linux-event-codes.h>
120
+
#include <dt-bindings/spmi/spmi.h>
121
121
122
-
spmi@c440000 {
123
-
reg = <0x0c440000 0x1100>;
124
-
#address-cells = <2>;
125
-
#size-cells = <0>;
122
+
spmi@c440000 {
123
+
reg = <0x0c440000 0x1100>;
124
+
#address-cells = <2>;
125
+
#size-cells = <0>;
126
126
127
-
pmic@0 {
128
-
reg = <0x0 SPMI_USID>;
129
-
#address-cells = <1>;
130
-
#size-cells = <0>;
127
+
pmic@0 {
128
+
reg = <0x0 SPMI_USID>;
129
+
#address-cells = <1>;
130
+
#size-cells = <0>;
131
131
132
-
pon@800 {
133
-
compatible = "qcom,pm8998-pon";
134
-
reg = <0x800>;
132
+
pon@800 {
133
+
compatible = "qcom,pm8998-pon";
134
+
reg = <0x800>;
135
135
136
-
pwrkey {
137
-
compatible = "qcom,pm8941-pwrkey";
138
-
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
139
-
debounce = <15625>;
140
-
bias-pull-up;
141
-
linux,code = <KEY_POWER>;
142
-
};
136
+
pwrkey {
137
+
compatible = "qcom,pm8941-pwrkey";
138
+
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
139
+
debounce = <15625>;
140
+
bias-pull-up;
141
+
linux,code = <KEY_POWER>;
142
+
};
143
143
144
-
resin {
145
-
compatible = "qcom,pm8941-resin";
146
-
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
147
-
debounce = <15625>;
148
-
bias-pull-up;
149
-
linux,code = <KEY_VOLUMEDOWN>;
150
-
};
151
-
};
152
-
};
153
-
};
144
+
resin {
145
+
compatible = "qcom,pm8941-resin";
146
+
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
147
+
debounce = <15625>;
148
+
bias-pull-up;
149
+
linux,code = <KEY_VOLUMEDOWN>;
150
+
};
151
+
};
152
+
};
153
+
};
154
154
...
-111
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
-111
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
···
1
-
* Freescale MSI interrupt controller
2
-
3
-
Required properties:
4
-
- compatible : compatible list, may contain one or two entries
5
-
The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6
-
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7
-
"fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8
-
version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9
-
provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
10
-
should be used. The first entry is optional; the second entry is
11
-
required.
12
-
13
-
- reg : It may contain one or two regions. The first region should contain
14
-
the address and the length of the shared message interrupt register set.
15
-
The second region should contain the address of aliased MSIIR or MSIIR1
16
-
register for platforms that have such an alias, if using MSIIR1, the second
17
-
region must be added because different MSI group has different MSIIR1 offset.
18
-
19
-
- interrupts : each one of the interrupts here is one entry per 32 MSIs,
20
-
and routed to the host interrupt controller. the interrupts should
21
-
be set as edge sensitive. If msi-available-ranges is present, only
22
-
the interrupts that correspond to available ranges shall be present.
23
-
24
-
Optional properties:
25
-
- msi-available-ranges: use <start count> style section to define which
26
-
msi interrupt can be used in the 256 msi interrupts. This property is
27
-
optional, without this, all the MSI interrupts can be used.
28
-
Each available range must begin and end on a multiple of 32 (i.e.
29
-
no splitting an individual MSI register or the associated PIC interrupt).
30
-
MPIC v4.3 does not support this property because the 32 interrupts of an
31
-
individual register are not continuous when using MSIIR1.
32
-
33
-
- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
34
-
is used for MSI messaging. The address of MSIIR in PCI address space is
35
-
the MSI message address.
36
-
37
-
This property may be used in virtualized environments where the hypervisor
38
-
has created an alternate mapping for the MSIR block. See below for an
39
-
explanation.
40
-
41
-
42
-
Example:
43
-
msi@41600 {
44
-
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
45
-
reg = <0x41600 0x80>;
46
-
msi-available-ranges = <0 0x100>;
47
-
interrupts = <
48
-
0xe0 0
49
-
0xe1 0
50
-
0xe2 0
51
-
0xe3 0
52
-
0xe4 0
53
-
0xe5 0
54
-
0xe6 0
55
-
0xe7 0>;
56
-
interrupt-parent = <&mpic>;
57
-
};
58
-
59
-
msi@41600 {
60
-
compatible = "fsl,mpic-msi-v4.3";
61
-
reg = <0x41600 0x200 0x44148 4>;
62
-
interrupts = <
63
-
0xe0 0 0 0
64
-
0xe1 0 0 0
65
-
0xe2 0 0 0
66
-
0xe3 0 0 0
67
-
0xe4 0 0 0
68
-
0xe5 0 0 0
69
-
0xe6 0 0 0
70
-
0xe7 0 0 0
71
-
0x100 0 0 0
72
-
0x101 0 0 0
73
-
0x102 0 0 0
74
-
0x103 0 0 0
75
-
0x104 0 0 0
76
-
0x105 0 0 0
77
-
0x106 0 0 0
78
-
0x107 0 0 0>;
79
-
};
80
-
81
-
The Freescale hypervisor and msi-address-64
82
-
-------------------------------------------
83
-
Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
84
-
Freescale MSI driver calculates the address of MSIIR (in the MSI register
85
-
block) and sets that address as the MSI message address.
86
-
87
-
In a virtualized environment, the hypervisor may need to create an IOMMU
88
-
mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement
89
-
because of hardware limitations of the Peripheral Access Management Unit
90
-
(PAMU), which is currently the only IOMMU that the hypervisor supports.
91
-
The ATMU is programmed with the guest physical address, and the PAMU
92
-
intercepts transactions and reroutes them to the true physical address.
93
-
94
-
In the PAMU, each PCI controller is given only one primary window. The
95
-
PAMU restricts DMA operations so that they can only occur within a window.
96
-
Because PCI devices must be able to DMA to memory, the primary window must
97
-
be used to cover all of the guest's memory space.
98
-
99
-
PAMU primary windows can be divided into 256 subwindows, and each
100
-
subwindow can have its own address mapping ("guest physical" to "true
101
-
physical"). However, each subwindow has to have the same alignment, which
102
-
means they cannot be located at just any address. Because of these
103
-
restrictions, it is usually impossible to create a 4KB subwindow that
104
-
covers MSIIR where it's normally located.
105
-
106
-
Therefore, the hypervisor has to create a subwindow inside the same
107
-
primary window used for memory, but mapped to the MSIR block (where MSIIR
108
-
lives). The first subwindow after the end of guest memory is used for
109
-
this. The address specified in the msi-address-64 property is the PCI
110
-
address of MSIIR. The hypervisor configures the PAMU to map that address to
111
-
the true physical address of MSIIR.
+8
-7
Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
+8
-7
Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
···
36
36
examples:
37
37
- |
38
38
reserved-memory {
39
-
#address-cells = <2>;
40
-
#size-cells = <2>;
41
-
dram_cpu_bpmp_mail: shmem@f1be0000 {
42
-
compatible = "nvidia,tegra264-bpmp-shmem";
43
-
reg = <0x0 0xf1be0000 0x0 0x2000>;
44
-
no-map;
45
-
};
39
+
#address-cells = <2>;
40
+
#size-cells = <2>;
41
+
42
+
shmem@f1be0000 {
43
+
compatible = "nvidia,tegra264-bpmp-shmem";
44
+
reg = <0x0 0xf1be0000 0x0 0x2000>;
45
+
no-map;
46
+
};
46
47
};
47
48
...
+11
-11
Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
+11
-11
Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
···
61
61
#include <dt-bindings/interrupt-controller/arm-gic.h>
62
62
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
63
63
rtc@40006000 {
64
-
compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
65
-
reg = <0x40006000 0x1000>;
66
-
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
67
-
<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
68
-
<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
69
-
interrupt-names = "alarm", "timer", "pps";
70
-
clocks = <&sysctrl R9A06G032_HCLK_RTC>;
71
-
clock-names = "hclk";
72
-
power-domains = <&sysctrl>;
73
-
start-year = <2000>;
74
-
};
64
+
compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
65
+
reg = <0x40006000 0x1000>;
66
+
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
67
+
<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
68
+
<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
69
+
interrupt-names = "alarm", "timer", "pps";
70
+
clocks = <&sysctrl R9A06G032_HCLK_RTC>;
71
+
clock-names = "hclk";
72
+
power-domains = <&sysctrl>;
73
+
start-year = <2000>;
74
+
};
+13
-13
Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
+13
-13
Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
···
186
186
};
187
187
188
188
power-controller {
189
-
compatible = "amlogic,meson-axg-pwrc";
190
-
#power-domain-cells = <1>;
191
-
amlogic,ao-sysctrl = <&sysctrl_AO>;
189
+
compatible = "amlogic,meson-axg-pwrc";
190
+
#power-domain-cells = <1>;
191
+
amlogic,ao-sysctrl = <&sysctrl_AO>;
192
192
193
-
resets = <&reset_viu>,
194
-
<&reset_venc>,
195
-
<&reset_vcbus>,
196
-
<&reset_vencl>,
197
-
<&reset_vid_lock>;
198
-
reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock";
199
-
clocks = <&clk_vpu>, <&clk_vapb>;
200
-
clock-names = "vpu", "vapb";
193
+
resets = <&reset_viu>,
194
+
<&reset_venc>,
195
+
<&reset_vcbus>,
196
+
<&reset_vencl>,
197
+
<&reset_vid_lock>;
198
+
reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock";
199
+
clocks = <&clk_vpu>, <&clk_vapb>;
200
+
clock-names = "vpu", "vapb";
201
201
};
202
202
203
203
phy {
204
-
compatible = "amlogic,axg-mipi-pcie-analog-phy";
205
-
#phy-cells = <0>;
204
+
compatible = "amlogic,axg-mipi-pcie-analog-phy";
205
+
#phy-cells = <0>;
206
206
};
207
207
};
+53
Documentation/devicetree/bindings/soc/fsl/fsl,imx23-digctl.yaml
+53
Documentation/devicetree/bindings/soc/fsl/fsl,imx23-digctl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/fsl/fsl,imx23-digctl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale mxs digctrl for i.MX23/i.MX28
8
+
9
+
description: |
10
+
The digital control block provides overall control of various items within
11
+
the top digital block of the chip, including:
12
+
- Default first-level page table (DFLPT) controls
13
+
- HCLK performance counter
14
+
- Free-running microseconds counter
15
+
- Entropy control
16
+
- BIST controls for ARM Core and On-Chip RAM
17
+
- Chip Revision register
18
+
- USB loop back congtrol
19
+
- Other miscellaneous controls
20
+
21
+
maintainers:
22
+
- Frank Li <Frank.Li@nxp.com>
23
+
24
+
properties:
25
+
compatible:
26
+
oneOf:
27
+
- items:
28
+
- enum:
29
+
- fsl,imx28-digctl
30
+
- const: fsl,imx23-digctl
31
+
- const: fsl,imx23-digctl
32
+
33
+
reg:
34
+
maxItems: 1
35
+
36
+
interrupts:
37
+
maxItems: 1
38
+
39
+
required:
40
+
- compatible
41
+
- reg
42
+
- interrupts
43
+
44
+
additionalProperties: false
45
+
46
+
examples:
47
+
- |
48
+
digctl@8001c000 {
49
+
compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
50
+
reg = <0x8001c000 0x2000>;
51
+
interrupts = <89>;
52
+
};
53
+
+19
-19
Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
+19
-19
Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
···
55
55
examples:
56
56
- |
57
57
eud@88e0000 {
58
-
compatible = "qcom,sc7280-eud", "qcom,eud";
59
-
reg = <0x88e0000 0x2000>,
60
-
<0x88e2000 0x1000>;
58
+
compatible = "qcom,sc7280-eud", "qcom,eud";
59
+
reg = <0x88e0000 0x2000>,
60
+
<0x88e2000 0x1000>;
61
61
62
-
ports {
63
-
#address-cells = <1>;
64
-
#size-cells = <0>;
65
-
port@0 {
66
-
reg = <0>;
67
-
eud_ep: endpoint {
68
-
remote-endpoint = <&usb2_role_switch>;
69
-
};
70
-
};
62
+
ports {
63
+
#address-cells = <1>;
64
+
#size-cells = <0>;
65
+
port@0 {
66
+
reg = <0>;
67
+
eud_ep: endpoint {
68
+
remote-endpoint = <&usb2_role_switch>;
69
+
};
70
+
};
71
71
72
-
port@1 {
73
-
reg = <1>;
74
-
eud_con: endpoint {
75
-
remote-endpoint = <&con_eud>;
76
-
};
77
-
};
78
-
};
72
+
port@1 {
73
+
reg = <1>;
74
+
eud_con: endpoint {
75
+
remote-endpoint = <&con_eud>;
76
+
};
77
+
};
78
+
};
79
79
};
+16
-16
Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml
+16
-16
Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml
···
121
121
};
122
122
123
123
wkup_m3_ipc@1324 {
124
-
compatible = "ti,am3352-wkup-m3-ipc";
125
-
reg = <0x1324 0x24>;
126
-
interrupts = <78>;
127
-
ti,rproc = <&wkup_m3>;
128
-
mboxes = <&am335x_mailbox &mbox_wkupm3>;
129
-
ti,vtt-gpio-pin = <7>;
130
-
firmware-name = "am335x-evm-scale-data.bin";
124
+
compatible = "ti,am3352-wkup-m3-ipc";
125
+
reg = <0x1324 0x24>;
126
+
interrupts = <78>;
127
+
ti,rproc = <&wkup_m3>;
128
+
mboxes = <&am335x_mailbox &mbox_wkupm3>;
129
+
ti,vtt-gpio-pin = <7>;
130
+
firmware-name = "am335x-evm-scale-data.bin";
131
131
};
132
132
};
133
133
···
155
155
pinctrl-0 = <&ddr3_vtt_toggle_default>;
156
156
157
157
ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
158
-
pinctrl-single,pins = <
158
+
pinctrl-single,pins = <
159
159
0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7)
160
-
>;
160
+
>;
161
161
};
162
162
};
163
163
164
164
wkup_m3_ipc@1324 {
165
-
compatible = "ti,am4372-wkup-m3-ipc";
166
-
reg = <0x1324 0x24>;
167
-
interrupts = <78>;
168
-
ti,rproc = <&wkup_m3>;
169
-
mboxes = <&am437x_mailbox &mbox_wkupm3>;
170
-
ti,set-io-isolation;
171
-
firmware-name = "am43x-evm-scale-data.bin";
165
+
compatible = "ti,am4372-wkup-m3-ipc";
166
+
reg = <0x1324 0x24>;
167
+
interrupts = <78>;
168
+
ti,rproc = <&wkup_m3>;
169
+
mboxes = <&am437x_mailbox &mbox_wkupm3>;
170
+
ti,set-io-isolation;
171
+
firmware-name = "am43x-evm-scale-data.bin";
172
172
};
173
173
};
174
174
+10
-2
Documentation/devicetree/bindings/submitting-patches.rst
+10
-2
Documentation/devicetree/bindings/submitting-patches.rst
···
21
21
"<binding dir>: dt-bindings: ..."
22
22
23
23
The 80 characters of the subject are precious. It is recommended to not
24
-
use "Documentation" or "doc" because that is implied. All bindings are
25
-
docs. Repeating "binding" again should also be avoided.
24
+
use "Documentation", "doc" or "YAML" because that is implied. All
25
+
bindings are docs and all new bindings are supposed to be in Devicetree
26
+
schema format. Repeating "binding" again should also be avoided, so for
27
+
a new device it is often enough for example::
28
+
29
+
"dt-bindings: iio: adc: Add ROHM BD79100G"
30
+
31
+
Conversion of other formats to DT schema::
32
+
33
+
"dt-bindings: iio: adc: adi,ad7476: Convert to DT schema"
26
34
27
35
2) DT binding files are written in DT schema format using json-schema
28
36
vocabulary and YAML file format. The DT binding files must pass validation
-15
Documentation/devicetree/bindings/timer/via,vt8500-timer.txt
-15
Documentation/devicetree/bindings/timer/via,vt8500-timer.txt
···
1
-
VIA/Wondermedia VT8500 Timer
2
-
-----------------------------------------------------
3
-
4
-
Required properties:
5
-
- compatible : "via,vt8500-timer"
6
-
- reg : Should contain 1 register ranges(address and length)
7
-
- interrupts : interrupt for the timer
8
-
9
-
Example:
10
-
11
-
timer@d8130100 {
12
-
compatible = "via,vt8500-timer";
13
-
reg = <0xd8130100 0x28>;
14
-
interrupts = <36>;
15
-
};
+51
Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml
+51
Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/timer/via,vt8500-timer.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: VIA/Wondermedia VT8500 Timer
8
+
9
+
description:
10
+
This is the timer block that is a standalone part of the system power
11
+
management controller on VIA/WonderMedia SoCs (VIA VT8500 and alike).
12
+
The hardware has a single 32-bit counter running at 3 MHz and four match
13
+
registers, each of which is associated with a dedicated match interrupt,
14
+
and the first of which can also serve as the system watchdog (if the
15
+
watchdog function is enabled, it will reset the system upon match instead
16
+
of triggering its respective interrupt)
17
+
18
+
maintainers:
19
+
- Alexey Charkov <alchark@gmail.com>
20
+
21
+
properties:
22
+
compatible:
23
+
const: via,vt8500-timer
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
interrupts:
29
+
minItems: 1
30
+
items:
31
+
- description: Channel 0 match. Note that if the watchdog function
32
+
is enabled, this interrupt will not fire and the system will
33
+
reboot instead once the counter reaches match register 0 value
34
+
- description: Channel 1 match
35
+
- description: Channel 2 match
36
+
- description: Channel 3 match
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- interrupts
42
+
43
+
additionalProperties: false
44
+
45
+
examples:
46
+
- |
47
+
timer@d8130100 {
48
+
compatible = "via,vt8500-timer";
49
+
reg = <0xd8130100 0x28>;
50
+
interrupts = <36>;
51
+
};
+54
Documentation/devicetree/bindings/trivial-devices.yaml
+54
Documentation/devicetree/bindings/trivial-devices.yaml
···
41
41
- ad,adm9240
42
42
# AD5110 - Nonvolatile Digital Potentiometer
43
43
- adi,ad5110
44
+
# Temperature sensor with integrated fan control
45
+
- adi,adm1027
46
+
# Analog Devices ADT7411 Temperature Sensor and 8-channel ADC
47
+
- adi,adt7411
48
+
# Temperature sensor with integrated fan control
49
+
- adi,adt7463
50
+
# Temperature sensor with integrated fan control
51
+
- adi,adt7468
44
52
# Analog Devices LT7182S Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher
45
53
- adi,lt7182s
46
54
# AMS iAQ-Core VOC Sensor
···
299
291
- mps,mp2891
300
292
# Monolithic Power Systems Inc. multi-phase controller mp2993
301
293
- mps,mp2993
294
+
# Monolithic Power Systems Inc. hot-swap protection device
295
+
- mps,mp5023
302
296
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5920
303
297
- mps,mp5920
304
298
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
···
309
299
- mps,mp9941
310
300
# Temperature sensor with integrated fan control
311
301
- national,lm63
302
+
# Temperature sensor with integrated fan control
303
+
- national,lm64
304
+
# Temperature sensor
305
+
- national,lm95235
306
+
# Temperature sensor
307
+
- national,lm95245
308
+
# Temperature sensor with integrated fan control
309
+
- national,lm96163
312
310
# Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
313
311
- national,lm80
314
312
# Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
315
313
- national,lm81
316
314
# Temperature sensor with integrated fan control
317
315
- national,lm85
316
+
# Temperature sensor with integrated fan control
317
+
- national,lm85b
318
+
# Temperature sensor with integrated fan control
319
+
- national,lm85c
318
320
# I2C ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator
319
321
- national,lm92
320
322
# Nuvoton Temperature Sensor
321
323
- nuvoton,w83773g
324
+
# NXP ISP1301 USB transceiver
325
+
- nxp,isp1301
322
326
# OKI ML86V7667 video decoder
323
327
- oki,ml86v7667
324
328
# ON Semiconductor ADT7462 Temperature, Voltage Monitor and Fan Controller
···
381
357
- silabs,si7020
382
358
# Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
383
359
- skyworks,sky81452
360
+
# Temperature sensor with integrated fan control
361
+
- smsc,emc6d100
362
+
# Temperature sensor with integrated fan control
363
+
- smsc,emc6d101
364
+
# Temperature sensor with integrated fan control
365
+
- smsc,emc6d102
366
+
# Temperature sensor with integrated fan control
367
+
- smsc,emc6d103
368
+
# Temperature sensor with integrated fan control
369
+
- smsc,emc6d103s
384
370
# SparkFun Qwiic Joystick (COM-15168) with i2c interface
385
371
- sparkfun,qwiic-joystick
386
372
# Sierra Wireless mangOH Green SPI IoT interface
387
373
- swir,mangoh-iotport-spi
388
374
# Ambient Light Sensor with SMBUS/Two Wire Serial Interface
389
375
- taos,tsl2550
376
+
# Digital PWM System Controller PMBus
377
+
- ti,cd9200
378
+
# Digital PWM System Controller PMBus
379
+
- ti,cd9220
380
+
# Digital PWM System Controller PMBus
381
+
- ti,cd9222
382
+
# Digital PWM System Controller PMBus
383
+
- ti,cd9224
384
+
# Digital PWM System Controller PMBus
385
+
- ti,cd9240
386
+
# Digital PWM System Controller PMBus
387
+
- ti,cd9244
388
+
# Digital PWM System Controller PMBus
389
+
- ti,cd9246
390
+
# Digital PWM System Controller PMBus
391
+
- ti,cd9248
390
392
# Temperature and humidity sensor with i2c interface
391
393
- ti,hdc1000
392
394
# Temperature and humidity sensor with i2c interface
···
440
390
- ti,tmp125
441
391
# TI DC-DC converter on PMBus
442
392
- ti,tps40400
393
+
# TI DCAP+ multiphase controller
394
+
- ti,tps53647
395
+
# TI DCAP+ multiphase controller
396
+
- ti,tps53667
443
397
# TI Dual channel DCAP+ multiphase controller TPS53676 with AVSBus
444
398
- ti,tps53676
445
399
# TI Dual channel DCAP+ multiphase controller TPS53679
-24
Documentation/devicetree/bindings/usb/isp1301.txt
-24
Documentation/devicetree/bindings/usb/isp1301.txt
···
1
-
* NXP ISP1301 USB transceiver
2
-
3
-
Required properties:
4
-
- compatible: must be "nxp,isp1301"
5
-
- reg: I2C address of the ISP1301 device
6
-
7
-
Optional properties of devices using ISP1301:
8
-
- transceiver: phandle of isp1301 - this helps the ISP1301 driver to find the
9
-
ISP1301 instance associated with the respective USB driver
10
-
11
-
Example:
12
-
13
-
isp1301: usb-transceiver@2c {
14
-
compatible = "nxp,isp1301";
15
-
reg = <0x2c>;
16
-
};
17
-
18
-
usbd@31020000 {
19
-
compatible = "nxp,lpc3220-udc";
20
-
reg = <0x31020000 0x300>;
21
-
interrupt-parent = <&mic>;
22
-
interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
23
-
transceiver = <&isp1301>;
24
-
};
+1
Documentation/devicetree/bindings/vendor-prefixes.yaml
+1
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml
+2
Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml
···
37
37
- fsl,ls1012a-wdt
38
38
- fsl,ls1021a-wdt
39
39
- fsl,ls1043a-wdt
40
+
- fsl,ls1046a-wdt
40
41
- fsl,vf610-wdt
41
42
- const: fsl,imx21-wdt
42
43
···
106
105
- fsl,ls1012a-wdt
107
106
- fsl,ls1021a-wdt
108
107
- fsl,ls1043a-wdt
108
+
- fsl,ls1046a-wdt
109
109
then:
110
110
properties:
111
111
big-endian: false
+36
-6
Documentation/devicetree/bindings/writing-bindings.rst
+36
-6
Documentation/devicetree/bindings/writing-bindings.rst
···
39
39
Properties
40
40
==========
41
41
42
-
- DO make 'compatible' properties specific. DON'T use wildcards in compatible
43
-
strings. DO use fallback compatibles when devices are the same as or a subset
44
-
of prior implementations. DO add new compatibles in case there are new
45
-
features or bugs.
42
+
- DO make 'compatible' properties specific.
43
+
44
+
- DON'T use wildcards or device-family names in compatible strings.
45
+
46
+
- DO use fallback compatibles when devices are the same as or a superset of
47
+
prior implementations.
48
+
49
+
- DO add new compatibles in case there are new features or bugs.
50
+
51
+
- DO use a SoC-specific compatible for all SoC devices, followed by a
52
+
fallback if appropriate. SoC-specific compatibles are also preferred for
53
+
the fallbacks.
54
+
55
+
- DON'T use bus suffixes to encode the type of interface device is using.
56
+
The parent bus node already implies that interface. DON'T add the type of
57
+
device, if the device cannot be anything else.
46
58
47
59
- DO use a vendor prefix on device-specific property names. Consider if
48
60
properties could be common among devices of the same class. Check other
···
63
51
- DON'T redefine common properties. Just reference the definition and define
64
52
constraints specific to the device.
65
53
54
+
- DON'T add properties to avoid a specific compatible. DON'T add properties if
55
+
they are implied by (deducible from) the compatible.
56
+
66
57
- DO use common property unit suffixes for properties with scientific units.
67
58
Recommended suffixes are listed at
68
59
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/property-units.yaml
69
60
70
61
- DO define properties in terms of constraints. How many entries? What are
71
-
possible values? What is the order?
62
+
possible values? What is the order? All these constraints represent the ABI
63
+
as well.
64
+
65
+
- DON'T make changes that break the ABI without explicit and detailed rationale
66
+
for why the changes have to be made and their impact. ABI impact goes beyond
67
+
the Linux kernel, because it also covers other open-source upstream projects.
68
+
72
69
73
70
Typical cases and caveats
74
71
=========================
···
85
64
- Phandle entries, like clocks/dmas/interrupts/resets, should always be
86
65
explicitly ordered. Include the {clock,dma,interrupt,reset}-names if there is
87
66
more than one phandle. When used, both of these fields need the same
88
-
constraints (e.g. list of items).
67
+
constraints (e.g. list of items).
89
68
90
69
- For names used in {clock,dma,interrupt,reset}-names, do not add any suffix,
91
70
e.g.: "tx" instead of "txirq" (for interrupt).
···
104
83
105
84
- "syscon" is not a generic property. Use vendor and type, e.g.
106
85
"vendor,power-manager-syscon".
86
+
87
+
- Do not add instance index (IDs) properties or custom OF aliases. If the
88
+
devices have different programming model, they might need different
89
+
compatibles. If such devices use some other device in a different way, e.g.
90
+
they program the phy differently, use cell/phandle arguments.
91
+
92
+
- Bindings files should be named like compatible: vendor,device.yaml. In case
93
+
of multiple compatibles in the binding, use one of the fallbacks or a more
94
+
generic name, yet still matching compatible style.
107
95
108
96
Board/SoC .dts Files
109
97
====================
+3
Documentation/devicetree/bindings/writing-schema.rst
+3
Documentation/devicetree/bindings/writing-schema.rst
···
171
171
Use YAML coding style (two-space indentation). For DTS examples in the schema,
172
172
preferred is four-space indentation.
173
173
174
+
Place entries in 'properties' and 'required' sections in the same order, using
175
+
style from Documentation/devicetree/bindings/dts-coding-style.rst.
176
+
174
177
Testing
175
178
-------
176
179
+6
-5
MAINTAINERS
+6
-5
MAINTAINERS
···
3541
3541
F: Documentation/devicetree/bindings/i2c/wm,wm8505-i2c.yaml
3542
3542
F: Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml
3543
3543
F: Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml
3544
+
F: Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml
3544
3545
F: arch/arm/boot/dts/vt8500/
3545
3546
F: arch/arm/mach-vt8500/
3546
3547
F: drivers/clocksource/timer-vt8500.c
···
7568
7567
DRM DRIVER FOR HX8357D PANELS
7569
7568
S: Orphan
7570
7569
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
7571
-
F: Documentation/devicetree/bindings/display/himax,hx8357d.txt
7570
+
F: Documentation/devicetree/bindings/display/himax,hx8357.yaml
7572
7571
F: drivers/gpu/drm/tiny/hx8357d.c
7573
7572
7574
7573
DRM DRIVER FOR HYPERV SYNTHETIC VIDEO DEVICE
···
7861
7860
M: David Lechner <david@lechnology.com>
7862
7861
S: Maintained
7863
7862
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
7864
-
F: Documentation/devicetree/bindings/display/sitronix,st7586.txt
7863
+
F: Documentation/devicetree/bindings/display/sitronix,st7586.yaml
7865
7864
F: drivers/gpu/drm/sitronix/st7586.c
7866
7865
7867
7866
DRM DRIVER FOR SITRONIX ST7571 PANELS
···
8084
8083
L: dri-devel@lists.freedesktop.org
8085
8084
S: Supported
8086
8085
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
8087
-
F: Documentation/devicetree/bindings/display/fsl,dcu.txt
8086
+
F: Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml
8088
8087
F: Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml
8089
8088
F: drivers/gpu/drm/fsl-dcu/
8090
8089
···
12503
12502
S: Maintained
12504
12503
T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
12505
12504
F: Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu
12506
-
F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
12505
+
F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
12507
12506
F: drivers/firmware/stratix10-rsu.c
12508
12507
F: drivers/firmware/stratix10-svc.c
12509
12508
F: include/linux/firmware/intel/stratix10-smc.h
···
19239
19238
L: linux-pci@vger.kernel.org
19240
19239
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
19241
19240
S: Maintained
19242
-
F: Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
19241
+
F: Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml
19243
19242
F: drivers/pci/controller/pci-xgene-msi.c
19244
19243
19245
19244
PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS