Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
virtio-spi: Add virtio-spi.h
Add virtio-spi.h header for virtio SPI.
Signed-off-by: Haixu Cui <quic_haixcui@quicinc.com>
Link: https://patch.msgid.link/20250908092348.1283552-3-quic_haixcui@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Haixu Cui
and committed by
Mark Brown
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MAINTAINERS
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MAINTAINERS
···
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F: include/uapi/linux/virtio_snd.h
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F: sound/virtio/*
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VIRTIO SPI DRIVER
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M: Haixu Cui <quic_haixcui@quicinc.com>
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L: virtualization@lists.linux.dev
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S: Maintained
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F: include/uapi/linux/virtio_spi.h
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VIRTUAL BOX GUEST DEVICE DRIVER
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M: Hans de Goede <hansg@kernel.org>
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M: Arnd Bergmann <arnd@arndb.de>
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include/uapi/linux/virtio_spi.h
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include/uapi/linux/virtio_spi.h
···
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (C) 2023 OpenSynergy GmbH
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* Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H
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#define _LINUX_VIRTIO_VIRTIO_SPI_H
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#include <linux/types.h>
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#include <linux/virtio_config.h>
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#include <linux/virtio_ids.h>
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#include <linux/virtio_types.h>
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/* Sample data on trailing clock edge */
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#define VIRTIO_SPI_CPHA _BITUL(0)
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/* Clock is high when IDLE */
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#define VIRTIO_SPI_CPOL _BITUL(1)
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/* Chip Select is active high */
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#define VIRTIO_SPI_CS_HIGH _BITUL(2)
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/* Transmit LSB first */
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#define VIRTIO_SPI_MODE_LSB_FIRST _BITUL(3)
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/* Loopback mode */
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#define VIRTIO_SPI_MODE_LOOP _BITUL(4)
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/**
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* struct virtio_spi_config - All config fields are read-only for the
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* Virtio SPI driver
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* @cs_max_number: maximum number of chipselect the host SPI controller
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* supports.
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* @cs_change_supported: indicates if the host SPI controller supports to toggle
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* chipselect after each transfer in one message:
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* 0: unsupported, chipselect will be kept in active state throughout the
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* message transaction;
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* 1: supported.
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* Note: Message here contains a sequence of SPI transfers.
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* @tx_nbits_supported: indicates the supported number of bit for writing:
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* bit 0: DUAL (2-bit transfer), 1 for supported
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* bit 1: QUAD (4-bit transfer), 1 for supported
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* bit 2: OCTAL (8-bit transfer), 1 for supported
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* other bits are reserved as 0, 1-bit transfer is always supported.
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* @rx_nbits_supported: indicates the supported number of bit for reading:
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* bit 0: DUAL (2-bit transfer), 1 for supported
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* bit 1: QUAD (4-bit transfer), 1 for supported
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* bit 2: OCTAL (8-bit transfer), 1 for supported
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* other bits are reserved as 0, 1-bit transfer is always supported.
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* @bits_per_word_mask: mask indicating which values of bits_per_word are
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* supported. If not set, no limitation for bits_per_word.
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* @mode_func_supported: indicates the following features are supported or not:
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* bit 0-1: CPHA feature
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* 0b00: invalid, should support as least one CPHA setting
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* 0b01: supports CPHA=0 only
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* 0b10: supports CPHA=1 only
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* 0b11: supports CPHA=0 and CPHA=1.
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* bit 2-3: CPOL feature
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* 0b00: invalid, should support as least one CPOL setting
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* 0b01: supports CPOL=0 only
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* 0b10: supports CPOL=1 only
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* 0b11: supports CPOL=0 and CPOL=1.
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* bit 4: chipselect active high feature, 0 for unsupported and 1 for
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* supported, chipselect active low is supported by default.
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* bit 5: LSB first feature, 0 for unsupported and 1 for supported,
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* MSB first is supported by default.
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* bit 6: loopback mode feature, 0 for unsupported and 1 for supported,
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* normal mode is supported by default.
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* @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no
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* limitation for transfer speed.
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* @max_word_delay_ns: the maximum word delay supported, in nanoseconds.
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* A value of 0 indicates that word delay is unsupported.
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* Each transfer may consist of a sequence of words.
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* @max_cs_setup_ns: the maximum delay supported after chipselect is asserted,
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* in ns unit, 0 means delay is not supported to introduce after chipselect is
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* asserted.
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* @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted,
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* in ns unit, 0 means delay is not supported to introduce before chipselect
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* is deasserted.
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* @max_cs_incative_ns: maximum delay supported after chipselect is deasserted,
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* in ns unit, 0 means delay is not supported to introduce after chipselect is
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* deasserted.
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*/
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struct virtio_spi_config {
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__u8 cs_max_number;
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__u8 cs_change_supported;
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#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL _BITUL(0)
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#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD _BITUL(1)
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#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL _BITUL(2)
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__u8 tx_nbits_supported;
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__u8 rx_nbits_supported;
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__le32 bits_per_word_mask;
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#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 _BITUL(0)
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#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 _BITUL(1)
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#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 _BITUL(2)
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#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 _BITUL(3)
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#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH _BITUL(4)
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#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST _BITUL(5)
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#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK _BITUL(6)
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__le32 mode_func_supported;
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__le32 max_freq_hz;
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__le32 max_word_delay_ns;
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__le32 max_cs_setup_ns;
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__le32 max_cs_hold_ns;
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__le32 max_cs_inactive_ns;
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};
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/**
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* struct spi_transfer_head - virtio SPI transfer descriptor
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* @chip_select_id: chipselect index the SPI transfer used.
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* @bits_per_word: the number of bits in each SPI transfer word.
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* @cs_change: whether to deselect device after finishing this transfer
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* before starting the next transfer, 0 means cs keep asserted and
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* 1 means cs deasserted then asserted again.
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* @tx_nbits: bus width for write transfer.
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* 0,1: bus width is 1, also known as SINGLE
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* 2 : bus width is 2, also known as DUAL
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* 4 : bus width is 4, also known as QUAD
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* 8 : bus width is 8, also known as OCTAL
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* other values are invalid.
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* @rx_nbits: bus width for read transfer.
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* 0,1: bus width is 1, also known as SINGLE
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* 2 : bus width is 2, also known as DUAL
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* 4 : bus width is 4, also known as QUAD
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* 8 : bus width is 8, also known as OCTAL
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* other values are invalid.
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* @reserved: for future use.
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* @mode: SPI transfer mode.
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* bit 0: CPHA, determines the timing (i.e. phase) of the data
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* bits relative to the clock pulses.For CPHA=0, the
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* "out" side changes the data on the trailing edge of the
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* preceding clock cycle, while the "in" side captures the data
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* on (or shortly after) the leading edge of the clock cycle.
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* For CPHA=1, the "out" side changes the data on the leading
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* edge of the current clock cycle, while the "in" side
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* captures the data on (or shortly after) the trailing edge of
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* the clock cycle.
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* bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a
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* clock which idles at 0, and each cycle consists of a pulse
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* of 1. CPOL=1 is a clock which idles at 1, and each cycle
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* consists of a pulse of 0.
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* bit 2: CS_HIGH, if 1, chip select active high, else active low.
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* bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB
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* first, else LSB first.
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* bit 4: LOOP, loopback mode.
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* @freq: the transfer speed in Hz.
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* @word_delay_ns: delay to be inserted between consecutive words of a
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* transfer, in ns unit.
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* @cs_setup_ns: delay to be introduced after CS is asserted, in ns
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* unit.
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* @cs_delay_hold_ns: delay to be introduced before CS is deasserted
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* for each transfer, in ns unit.
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* @cs_change_delay_inactive_ns: delay to be introduced after CS is
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* deasserted and before next asserted, in ns unit.
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*/
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struct spi_transfer_head {
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__u8 chip_select_id;
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__u8 bits_per_word;
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__u8 cs_change;
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__u8 tx_nbits;
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__u8 rx_nbits;
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__u8 reserved[3];
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__le32 mode;
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__le32 freq;
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__le32 word_delay_ns;
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__le32 cs_setup_ns;
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__le32 cs_delay_hold_ns;
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__le32 cs_change_delay_inactive_ns;
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};
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/**
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* struct spi_transfer_result - virtio SPI transfer result
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* @result: Transfer result code.
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* VIRTIO_SPI_TRANS_OK: Transfer successful.
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* VIRTIO_SPI_PARAM_ERR: Parameter error.
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* VIRTIO_SPI_TRANS_ERR: Transfer error.
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*/
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struct spi_transfer_result {
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#define VIRTIO_SPI_TRANS_OK 0
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#define VIRTIO_SPI_PARAM_ERR 1
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#define VIRTIO_SPI_TRANS_ERR 2
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__u8 result;
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};
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#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */