Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc bug fixes from Olof Johansson:
- A set of OMAP fixes, about half of them PM/clock related, the rest
scattered over the platform code but all small and targeted to real
bugs.
- Two small i.MX fixes for SSI device clock setup.
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: clk-imx35: Fix SSI clock registration
ARM: clk-imx25: Fix SSI clock registration
ARM: OMAP4: Fix array size for irq_target_cpu
ARM: OMAP4: hwmod data: temporarily comment out data for the sl2if IP block
ARM: OMAP: hwmod code: Disable module when hwmod enable fails
ARM: OMAP3: hwmod data: fix iva2 reset info
ARM: OMAP3xxx: clockdomain: fix software supervised wakeup/sleep
ARM: OMAP2+: am33xx: Fix the timer fck clock naming convention
ARM: OMAP: Config fix for omap3-touchbook board
ARM: OMAP: sram: skip the first 16K on OMAP3 HS
ARM: OMAP: sram: fix OMAP4 errata handling
ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
+98
-32
+2
-4
arch/arm/mach-imx/clk-imx25.c
+2
-4
arch/arm/mach-imx/clk-imx25.c
···
222
222
clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
223
223
clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
224
224
clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
225
-
clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
226
-
clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
227
-
clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
228
-
clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
225
+
clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
226
+
clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
229
227
clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
230
228
clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
231
229
clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
+2
-4
arch/arm/mach-imx/clk-imx35.c
+2
-4
arch/arm/mach-imx/clk-imx35.c
···
230
230
clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
231
231
clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
232
232
clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
233
-
clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
234
-
clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
235
-
clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
236
-
clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
233
+
clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
234
+
clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
237
235
/* i.mx35 has the i.mx21 type uart */
238
236
clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
239
237
clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
+2
-1
arch/arm/mach-omap2/Kconfig
+2
-1
arch/arm/mach-omap2/Kconfig
···
232
232
select OMAP_PACKAGE_CBB
233
233
select REGULATOR_FIXED_VOLTAGE if REGULATOR
234
234
235
-
config MACH_OMAP3_TOUCHBOOK
235
+
config MACH_TOUCHBOOK
236
236
bool "OMAP3 Touch Book"
237
237
depends on ARCH_OMAP3
238
238
default y
239
+
select OMAP_PACKAGE_CBB
239
240
240
241
config MACH_OMAP_3430SDP
241
242
bool "OMAP 3430 SDP board"
+1
-1
arch/arm/mach-omap2/Makefile
+1
-1
arch/arm/mach-omap2/Makefile
···
255
255
obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
256
256
obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
257
257
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o
258
-
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o
258
+
obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o
259
259
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
260
260
obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o
261
261
+7
-7
arch/arm/mach-omap2/clock33xx_data.c
+7
-7
arch/arm/mach-omap2/clock33xx_data.c
···
1036
1036
CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
1037
1037
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
1038
1038
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
1039
-
CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX),
1040
-
CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX),
1041
-
CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX),
1042
-
CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX),
1043
-
CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX),
1044
-
CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX),
1045
-
CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX),
1039
+
CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
1040
+
CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
1041
+
CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
1042
+
CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
1043
+
CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
1044
+
CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
1045
+
CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
1046
1046
CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
1047
1047
CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
1048
1048
CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
+48
-2
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+48
-2
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
···
241
241
_clkdm_del_autodeps(clkdm);
242
242
}
243
243
244
+
static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
245
+
{
246
+
bool hwsup = false;
247
+
248
+
if (!clkdm->clktrctrl_mask)
249
+
return 0;
250
+
251
+
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
252
+
clkdm->clktrctrl_mask);
253
+
254
+
if (hwsup) {
255
+
/* Disable HW transitions when we are changing deps */
256
+
_disable_hwsup(clkdm);
257
+
_clkdm_add_autodeps(clkdm);
258
+
_enable_hwsup(clkdm);
259
+
} else {
260
+
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
261
+
omap3_clkdm_wakeup(clkdm);
262
+
}
263
+
264
+
return 0;
265
+
}
266
+
267
+
static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
268
+
{
269
+
bool hwsup = false;
270
+
271
+
if (!clkdm->clktrctrl_mask)
272
+
return 0;
273
+
274
+
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
275
+
clkdm->clktrctrl_mask);
276
+
277
+
if (hwsup) {
278
+
/* Disable HW transitions when we are changing deps */
279
+
_disable_hwsup(clkdm);
280
+
_clkdm_del_autodeps(clkdm);
281
+
_enable_hwsup(clkdm);
282
+
} else {
283
+
if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
284
+
omap3_clkdm_sleep(clkdm);
285
+
}
286
+
287
+
return 0;
288
+
}
289
+
244
290
struct clkdm_ops omap2_clkdm_operations = {
245
291
.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
246
292
.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
···
313
267
.clkdm_wakeup = omap3_clkdm_wakeup,
314
268
.clkdm_allow_idle = omap3_clkdm_allow_idle,
315
269
.clkdm_deny_idle = omap3_clkdm_deny_idle,
316
-
.clkdm_clk_enable = omap2_clkdm_clk_enable,
317
-
.clkdm_clk_disable = omap2_clkdm_clk_disable,
270
+
.clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
271
+
.clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
318
272
};
+1
arch/arm/mach-omap2/cm-regbits-34xx.h
+1
arch/arm/mach-omap2/cm-regbits-34xx.h
+1
-1
arch/arm/mach-omap2/omap-wakeupgen.c
+1
-1
arch/arm/mach-omap2/omap-wakeupgen.c
···
46
46
static void __iomem *wakeupgen_base;
47
47
static void __iomem *sar_base;
48
48
static DEFINE_SPINLOCK(wakeupgen_lock);
49
-
static unsigned int irq_target_cpu[NR_IRQS];
49
+
static unsigned int irq_target_cpu[MAX_IRQS];
50
50
static unsigned int irq_banks = MAX_NR_REG_BANKS;
51
51
static unsigned int max_irqs = MAX_IRQS;
52
52
static unsigned int omap_secure_apis;
+1
arch/arm/mach-omap2/omap_hwmod.c
+1
arch/arm/mach-omap2/omap_hwmod.c
+12
-3
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+12
-3
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
···
100
100
101
101
/* IVA2 (IVA2) */
102
102
static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
103
-
{ .name = "logic", .rst_shift = 0 },
104
-
{ .name = "seq0", .rst_shift = 1 },
105
-
{ .name = "seq1", .rst_shift = 2 },
103
+
{ .name = "logic", .rst_shift = 0, .st_shift = 8 },
104
+
{ .name = "seq0", .rst_shift = 1, .st_shift = 9 },
105
+
{ .name = "seq1", .rst_shift = 2, .st_shift = 10 },
106
106
};
107
107
108
108
static struct omap_hwmod omap3xxx_iva_hwmod = {
···
112
112
.rst_lines = omap3xxx_iva_resets,
113
113
.rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114
114
.main_clk = "iva2_ck",
115
+
.prcm = {
116
+
.omap2 = {
117
+
.module_offs = OMAP3430_IVA2_MOD,
118
+
.prcm_reg_id = 1,
119
+
.module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
120
+
.idlest_reg_id = 1,
121
+
.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
122
+
}
123
+
},
115
124
};
116
125
117
126
/* timer class */
+6
-6
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+6
-6
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
···
4210
4210
};
4211
4211
4212
4212
/* dsp -> sl2if */
4213
-
static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4213
+
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4214
4214
.master = &omap44xx_dsp_hwmod,
4215
4215
.slave = &omap44xx_sl2if_hwmod,
4216
4216
.clk = "dpll_iva_m5x2_ck",
···
4828
4828
};
4829
4829
4830
4830
/* iva -> sl2if */
4831
-
static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4831
+
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4832
4832
.master = &omap44xx_iva_hwmod,
4833
4833
.slave = &omap44xx_sl2if_hwmod,
4834
4834
.clk = "dpll_iva_m5x2_ck",
···
5362
5362
};
5363
5363
5364
5364
/* l3_main_2 -> sl2if */
5365
-
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5365
+
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5366
5366
.master = &omap44xx_l3_main_2_hwmod,
5367
5367
.slave = &omap44xx_sl2if_hwmod,
5368
5368
.clk = "l3_div_ck",
···
6032
6032
&omap44xx_l4_abe__dmic,
6033
6033
&omap44xx_l4_abe__dmic_dma,
6034
6034
&omap44xx_dsp__iva,
6035
-
&omap44xx_dsp__sl2if,
6035
+
/* &omap44xx_dsp__sl2if, */
6036
6036
&omap44xx_l4_cfg__dsp,
6037
6037
&omap44xx_l3_main_2__dss,
6038
6038
&omap44xx_l4_per__dss,
···
6068
6068
&omap44xx_l4_per__i2c4,
6069
6069
&omap44xx_l3_main_2__ipu,
6070
6070
&omap44xx_l3_main_2__iss,
6071
-
&omap44xx_iva__sl2if,
6071
+
/* &omap44xx_iva__sl2if, */
6072
6072
&omap44xx_l3_main_2__iva,
6073
6073
&omap44xx_l4_wkup__kbd,
6074
6074
&omap44xx_l4_cfg__mailbox,
···
6099
6099
&omap44xx_l4_cfg__cm_core,
6100
6100
&omap44xx_l4_wkup__prm,
6101
6101
&omap44xx_l4_wkup__scrm,
6102
-
&omap44xx_l3_main_2__sl2if,
6102
+
/* &omap44xx_l3_main_2__sl2if, */
6103
6103
&omap44xx_l4_abe__slimbus1,
6104
6104
&omap44xx_l4_abe__slimbus1_dma,
6105
6105
&omap44xx_l4_per__slimbus2,
+7
arch/arm/mach-omap2/timer.c
+7
arch/arm/mach-omap2/timer.c
···
260
260
return 0;
261
261
}
262
262
263
+
#ifdef CONFIG_OMAP_32K_TIMER
263
264
/* Setup free-running counter for clocksource */
264
265
static int __init omap2_sync32k_clocksource_init(void)
265
266
{
···
300
299
301
300
return ret;
302
301
}
302
+
#else
303
+
static inline int omap2_sync32k_clocksource_init(void)
304
+
{
305
+
return -ENODEV;
306
+
}
307
+
#endif
303
308
304
309
static void __init omap2_gptimer_clocksource_init(int gptimer_id,
305
310
const char *fck_source)
+8
-3
arch/arm/plat-omap/sram.c
+8
-3
arch/arm/plat-omap/sram.c
···
68
68
69
69
static unsigned long omap_sram_start;
70
70
static void __iomem *omap_sram_base;
71
+
static unsigned long omap_sram_skip;
71
72
static unsigned long omap_sram_size;
72
73
static void __iomem *omap_sram_ceil;
73
74
···
107
106
*/
108
107
static void __init omap_detect_sram(void)
109
108
{
109
+
omap_sram_skip = SRAM_BOOTLOADER_SZ;
110
110
if (cpu_class_is_omap2()) {
111
111
if (is_sram_locked()) {
112
112
if (cpu_is_omap34xx()) {
···
115
113
if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
116
114
(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
117
115
omap_sram_size = 0x7000; /* 28K */
116
+
omap_sram_skip += SZ_16K;
118
117
} else {
119
118
omap_sram_size = 0x8000; /* 32K */
120
119
}
···
178
175
return;
179
176
180
177
#ifdef CONFIG_OMAP4_ERRATA_I688
178
+
if (cpu_is_omap44xx()) {
181
179
omap_sram_start += PAGE_SIZE;
182
180
omap_sram_size -= SZ_16K;
181
+
}
183
182
#endif
184
183
if (cpu_is_omap34xx()) {
185
184
/*
···
208
203
* Looks like we need to preserve some bootloader code at the
209
204
* beginning of SRAM for jumping to flash for reboot to work...
210
205
*/
211
-
memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
212
-
omap_sram_size - SRAM_BOOTLOADER_SZ);
206
+
memset_io(omap_sram_base + omap_sram_skip, 0,
207
+
omap_sram_size - omap_sram_skip);
213
208
}
214
209
215
210
/*
···
223
218
{
224
219
unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
225
220
226
-
available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
221
+
available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
227
222
228
223
if (size > available) {
229
224
pr_err("Not enough space in SRAM\n");