tjh.dev / kernel
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clk: samsung: exynos5433: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-8-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Krzysztof Kozlowski 6a44298d 62eef444

+44 -21
+44 -21
drivers/clk/samsung/clk-exynos5433.c
··· 21 21 #include "clk-exynos-arm64.h" 22 22 #include "clk-pll.h" 23 23 24 + /* NOTE: Must be equal to the last clock ID increased by one */ 25 + #define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1) 26 + #define CLKS_NR_CPIF (CLK_SCLK_UFS_MPHY + 1) 27 + #define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1) 28 + #define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1) 29 + #define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1) 30 + #define CLKS_NR_FSYS (CLK_PCIE + 1) 31 + #define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1) 32 + #define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1) 33 + #define CLKS_NR_AUD (CLK_SCLK_AUD_I2S + 1) 34 + #define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1) 35 + #define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1) 36 + #define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1) 37 + #define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1) 38 + #define CLKS_NR_ATLAS (CLK_SCLK_ATLAS + 1) 39 + #define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1) 40 + #define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1) 41 + #define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1) 42 + #define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1) 43 + #define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1) 44 + #define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1) 45 + #define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1) 46 + 24 47 /* 25 48 * Register offset definitions for CMU_TOP 26 49 */ ··· 821 798 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), 822 799 .fixed_factor_clks = top_fixed_factor_clks, 823 800 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 824 - .nr_clk_ids = TOP_NR_CLK, 801 + .nr_clk_ids = CLKS_NR_TOP, 825 802 .clk_regs = top_clk_regs, 826 803 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 827 804 .suspend_regs = top_suspend_regs, ··· 900 877 .nr_div_clks = ARRAY_SIZE(cpif_div_clks), 901 878 .gate_clks = cpif_gate_clks, 902 879 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), 903 - .nr_clk_ids = CPIF_NR_CLK, 880 + .nr_clk_ids = CLKS_NR_CPIF, 904 881 .clk_regs = cpif_clk_regs, 905 882 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), 906 883 .suspend_regs = cpif_suspend_regs, ··· 1554 1531 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1555 1532 .fixed_factor_clks = mif_fixed_factor_clks, 1556 1533 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), 1557 - .nr_clk_ids = MIF_NR_CLK, 1534 + .nr_clk_ids = CLKS_NR_MIF, 1558 1535 .clk_regs = mif_clk_regs, 1559 1536 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1560 1537 }; ··· 1753 1730 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1754 1731 .gate_clks = peric_gate_clks, 1755 1732 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 1756 - .nr_clk_ids = PERIC_NR_CLK, 1733 + .nr_clk_ids = CLKS_NR_PERIC, 1757 1734 .clk_regs = peric_clk_regs, 1758 1735 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 1759 1736 .suspend_regs = peric_suspend_regs, ··· 1947 1924 static const struct samsung_cmu_info peris_cmu_info __initconst = { 1948 1925 .gate_clks = peris_gate_clks, 1949 1926 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1950 - .nr_clk_ids = PERIS_NR_CLK, 1927 + .nr_clk_ids = CLKS_NR_PERIS, 1951 1928 .clk_regs = peris_clk_regs, 1952 1929 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 1953 1930 }; ··· 2359 2336 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 2360 2337 .fixed_clks = fsys_fixed_clks, 2361 2338 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), 2362 - .nr_clk_ids = FSYS_NR_CLK, 2339 + .nr_clk_ids = CLKS_NR_FSYS, 2363 2340 .clk_regs = fsys_clk_regs, 2364 2341 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 2365 2342 .suspend_regs = fsys_suspend_regs, ··· 2482 2459 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 2483 2460 .gate_clks = g2d_gate_clks, 2484 2461 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 2485 - .nr_clk_ids = G2D_NR_CLK, 2462 + .nr_clk_ids = CLKS_NR_G2D, 2486 2463 .clk_regs = g2d_clk_regs, 2487 2464 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 2488 2465 .suspend_regs = g2d_suspend_regs, ··· 2910 2887 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), 2911 2888 .fixed_factor_clks = disp_fixed_factor_clks, 2912 2889 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), 2913 - .nr_clk_ids = DISP_NR_CLK, 2890 + .nr_clk_ids = CLKS_NR_DISP, 2914 2891 .clk_regs = disp_clk_regs, 2915 2892 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 2916 2893 .suspend_regs = disp_suspend_regs, ··· 3080 3057 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 3081 3058 .fixed_clks = aud_fixed_clks, 3082 3059 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 3083 - .nr_clk_ids = AUD_NR_CLK, 3060 + .nr_clk_ids = CLKS_NR_AUD, 3084 3061 .clk_regs = aud_clk_regs, 3085 3062 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 3086 3063 .suspend_regs = aud_suspend_regs, ··· 3212 3189 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ 3213 3190 .gate_clks = bus##id##_gate_clks, \ 3214 3191 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ 3215 - .nr_clk_ids = BUSx_NR_CLK 3192 + .nr_clk_ids = CLKS_NR_BUSX 3216 3193 3217 3194 static const struct samsung_cmu_info bus0_cmu_info __initconst = { 3218 3195 CMU_BUS_INFO_CLKS(0), ··· 3363 3340 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 3364 3341 .gate_clks = g3d_gate_clks, 3365 3342 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 3366 - .nr_clk_ids = G3D_NR_CLK, 3343 + .nr_clk_ids = CLKS_NR_G3D, 3367 3344 .clk_regs = g3d_clk_regs, 3368 3345 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 3369 3346 .suspend_regs = g3d_suspend_regs, ··· 3506 3483 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 3507 3484 .gate_clks = gscl_gate_clks, 3508 3485 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), 3509 - .nr_clk_ids = GSCL_NR_CLK, 3486 + .nr_clk_ids = CLKS_NR_GSCL, 3510 3487 .clk_regs = gscl_clk_regs, 3511 3488 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 3512 3489 .suspend_regs = gscl_suspend_regs, ··· 3716 3693 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), 3717 3694 .cpu_clks = apollo_cpu_clks, 3718 3695 .nr_cpu_clks = ARRAY_SIZE(apollo_cpu_clks), 3719 - .nr_clk_ids = APOLLO_NR_CLK, 3696 + .nr_clk_ids = CLKS_NR_APOLLO, 3720 3697 .clk_regs = apollo_clk_regs, 3721 3698 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), 3722 3699 }; ··· 3961 3938 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks), 3962 3939 .cpu_clks = atlas_cpu_clks, 3963 3940 .nr_cpu_clks = ARRAY_SIZE(atlas_cpu_clks), 3964 - .nr_clk_ids = ATLAS_NR_CLK, 3941 + .nr_clk_ids = CLKS_NR_ATLAS, 3965 3942 .clk_regs = atlas_clk_regs, 3966 3943 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), 3967 3944 }; ··· 4135 4112 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 4136 4113 .gate_clks = mscl_gate_clks, 4137 4114 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 4138 - .nr_clk_ids = MSCL_NR_CLK, 4115 + .nr_clk_ids = CLKS_NR_MSCL, 4139 4116 .clk_regs = mscl_clk_regs, 4140 4117 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 4141 4118 .suspend_regs = mscl_suspend_regs, ··· 4243 4220 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 4244 4221 .gate_clks = mfc_gate_clks, 4245 4222 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 4246 - .nr_clk_ids = MFC_NR_CLK, 4223 + .nr_clk_ids = CLKS_NR_MFC, 4247 4224 .clk_regs = mfc_clk_regs, 4248 4225 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 4249 4226 .suspend_regs = mfc_suspend_regs, ··· 4353 4330 .nr_div_clks = ARRAY_SIZE(hevc_div_clks), 4354 4331 .gate_clks = hevc_gate_clks, 4355 4332 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks), 4356 - .nr_clk_ids = HEVC_NR_CLK, 4333 + .nr_clk_ids = CLKS_NR_HEVC, 4357 4334 .clk_regs = hevc_clk_regs, 4358 4335 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), 4359 4336 .suspend_regs = hevc_suspend_regs, ··· 4606 4583 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 4607 4584 .gate_clks = isp_gate_clks, 4608 4585 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 4609 - .nr_clk_ids = ISP_NR_CLK, 4586 + .nr_clk_ids = CLKS_NR_ISP, 4610 4587 .clk_regs = isp_clk_regs, 4611 4588 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 4612 4589 .suspend_regs = isp_suspend_regs, ··· 5088 5065 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks), 5089 5066 .fixed_clks = cam0_fixed_clks, 5090 5067 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks), 5091 - .nr_clk_ids = CAM0_NR_CLK, 5068 + .nr_clk_ids = CLKS_NR_CAM0, 5092 5069 .clk_regs = cam0_clk_regs, 5093 5070 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), 5094 5071 .suspend_regs = cam0_suspend_regs, ··· 5463 5440 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks), 5464 5441 .fixed_clks = cam1_fixed_clks, 5465 5442 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks), 5466 - .nr_clk_ids = CAM1_NR_CLK, 5443 + .nr_clk_ids = CLKS_NR_CAM1, 5467 5444 .clk_regs = cam1_clk_regs, 5468 5445 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), 5469 5446 .suspend_regs = cam1_suspend_regs, ··· 5495 5472 static const struct samsung_cmu_info imem_cmu_info __initconst = { 5496 5473 .gate_clks = imem_gate_clks, 5497 5474 .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), 5498 - .nr_clk_ids = IMEM_NR_CLK, 5475 + .nr_clk_ids = CLKS_NR_IMEM, 5499 5476 .clk_regs = imem_clk_regs, 5500 5477 .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), 5501 5478 .clk_name = "aclk_imem_200",