ASoC: fsl_asrc: Add support for i.MX952 platform

Add a compatible string, clock mapping table and enable the option
'start_before_dma' to support ASRC on the i.MX952 platform.

The clock mapping table is to map the clock sources on i.MX952 to the
clock ids in the driver, the clock ids are for all the clock sources on
all supported platforms.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260206014805.3897764-4-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Shengjiu Wang and committed by

Mark Brown 4 months ago 6a8c6f55 83447a38

+30

2 changed files

expand all

sound

soc

fsl

fsl_asrc.c

fsl_asrc.h

+16

sound/soc/fsl/fsl_asrc.c

··· 106 106 }, 107 107 }; 108 108 109 + static unsigned char clk_map_imx952[ASRC_CLK_MAP_LEN] = { 110 + 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 111 + 0x0, 0x1, 0x2, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x4, 0x5, 0x6, 0x8, 0xf, 0xf, 112 + 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0x9, 0xa, 0xb, 0xc, 0xd, 0xf, 0xf, 0xf, 0xf, 113 + }; 114 + 109 115 /* 110 116 * According to RM, the divider range is 1 ~ 8, 111 117 * prescaler is power of 2 from 1 ~ 128. ··· 1343 1337 asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx]; 1344 1338 asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx]; 1345 1339 } 1340 + } else if (of_device_is_compatible(np, "fsl,imx952-asrc")) { 1341 + asrc_priv->clk_map[IN] = clk_map_imx952; 1342 + asrc_priv->clk_map[OUT] = clk_map_imx952; 1346 1343 } 1347 1344 1348 1345 asrc->channel_avail = 10; ··· 1584 1575 .channel_bits = 4, 1585 1576 }; 1586 1577 1578 + static const struct fsl_asrc_soc_data fsl_asrc_imx952_data = { 1579 + .use_edma = true, 1580 + .channel_bits = 4, 1581 + .start_before_dma = true, 1582 + }; 1583 + 1587 1584 static const struct of_device_id fsl_asrc_ids[] = { 1588 1585 { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data }, 1589 1586 { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data }, 1590 1587 { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data }, 1591 1588 { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data }, 1589 + { .compatible = "fsl,imx952-asrc", .data = &fsl_asrc_imx952_data }, 1592 1590 {} 1593 1591 }; 1594 1592 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);

+14

sound/soc/fsl/fsl_asrc.h

··· 326 326 INCLK_SAI6_TX_BCLK = 0x22, 327 327 INCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, 328 328 INCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, 329 + 330 + INCLK_SAI2_TX_BCLK = 0x26, 331 + INCLK_SAI3_TX_BCLK = 0x27, 332 + INCLK_SAI4_RX_BCLK = 0x28, 333 + INCLK_SAI4_TX_BCLK = 0x29, 334 + INCLK_SAI5_RX_BCLK = 0x2a, 335 + INCLK_SAI5_TX_BCLK = 0x2b, 329 336 }; 330 337 331 338 enum asrc_outclk { ··· 373 366 OUTCLK_SAI6_TX_BCLK = 0x22, 374 367 OUTCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, 375 368 OUTCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, 369 + 370 + OUTCLK_SAI2_TX_BCLK = 0x26, 371 + OUTCLK_SAI3_TX_BCLK = 0x27, 372 + OUTCLK_SAI4_RX_BCLK = 0x28, 373 + OUTCLK_SAI4_TX_BCLK = 0x29, 374 + OUTCLK_SAI5_RX_BCLK = 0x2a, 375 + OUTCLK_SAI5_TX_BCLK = 0x2b, 376 376 }; 377 377 378 378 #define ASRC_CLK_MAX_NUM 16

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