Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

+1

drivers/gpu/drm/ast/ast_ttm.c

··· 323 323 324 324 astbo->gem.driver_private = NULL; 325 325 astbo->bo.bdev = &ast->ttm.bdev; 326 + astbo->bo.bdev->dev_mapping = dev->dev_mapping; 326 327 327 328 ast_ttm_placement(astbo, TTM_PL_FLAG_VRAM | TTM_PL_FLAG_SYSTEM); 328 329

+1

drivers/gpu/drm/cirrus/cirrus_ttm.c

··· 328 328 329 329 cirrusbo->gem.driver_private = NULL; 330 330 cirrusbo->bo.bdev = &cirrus->ttm.bdev; 331 + cirrusbo->bo.bdev->dev_mapping = dev->dev_mapping; 331 332 332 333 cirrus_ttm_placement(cirrusbo, TTM_PL_FLAG_VRAM | TTM_PL_FLAG_SYSTEM); 333 334

+4 -1

drivers/gpu/drm/drm_irq.c

··· 708 708 /* Subtract time delta from raw timestamp to get final 709 709 * vblank_time timestamp for end of vblank. 710 710 */ 711 - etime = ktime_sub_ns(etime, delta_ns); 711 + if (delta_ns < 0) 712 + etime = ktime_add_ns(etime, -delta_ns); 713 + else 714 + etime = ktime_sub_ns(etime, delta_ns); 712 715 *vblank_time = ktime_to_timeval(etime); 713 716 714 717 DRM_DEBUG("crtc %d : v %d p(%d,%d)@ %ld.%ld -> %ld.%ld [e %d us, %d rep]\n",

+9 -3

drivers/gpu/drm/i915/i915_reg.h

··· 1856 1856 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1857 1857 1858 1858 #define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114) 1859 - /* HDMI/DP bits are gen4+ */ 1860 - #define PORTB_HOTPLUG_LIVE_STATUS (1 << 29) 1859 + /* 1860 + * HDMI/DP bits are gen4+ 1861 + * 1862 + * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 1863 + * Please check the detailed lore in the commit message for for experimental 1864 + * evidence. 1865 + */ 1866 + #define PORTD_HOTPLUG_LIVE_STATUS (1 << 29) 1861 1867 #define PORTC_HOTPLUG_LIVE_STATUS (1 << 28) 1862 - #define PORTD_HOTPLUG_LIVE_STATUS (1 << 27) 1868 + #define PORTB_HOTPLUG_LIVE_STATUS (1 << 27) 1863 1869 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 1864 1870 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 1865 1871 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)

+3 -1

drivers/gpu/drm/i915/intel_display.c

··· 8269 8269 8270 8270 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 8271 8271 base.head) { 8272 + enum pipe pipe; 8272 8273 if (encoder->base.crtc != &crtc->base) 8273 8274 continue; 8274 - if (encoder->get_config) 8275 + if (encoder->get_config && 8276 + encoder->get_hw_state(encoder, &pipe)) 8275 8277 encoder->get_config(encoder, &pipe_config); 8276 8278 } 8277 8279

+16 -2

drivers/gpu/drm/i915/intel_panel.c

··· 497 497 goto out; 498 498 } 499 499 500 - /* scale to hardware */ 501 - level = level * freq / max; 500 + /* scale to hardware, but be careful to not overflow */ 501 + if (freq < max) 502 + level = level * freq / max; 503 + else 504 + level = freq / max * level; 502 505 503 506 dev_priv->backlight.level = level; 504 507 if (dev_priv->backlight.device) ··· 517 514 { 518 515 struct drm_i915_private *dev_priv = dev->dev_private; 519 516 unsigned long flags; 517 + 518 + /* 519 + * Do not disable backlight on the vgaswitcheroo path. When switching 520 + * away from i915, the other client may depend on i915 to handle the 521 + * backlight. This will leave the backlight on unnecessarily when 522 + * another client is not activated. 523 + */ 524 + if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) { 525 + DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n"); 526 + return; 527 + } 520 528 521 529 spin_lock_irqsave(&dev_priv->backlight.lock, flags); 522 530

+18

drivers/gpu/drm/i915/intel_pm.c

··· 5063 5063 } 5064 5064 } else { 5065 5065 if (enable_requested) { 5066 + unsigned long irqflags; 5067 + enum pipe p; 5068 + 5066 5069 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 5070 + POSTING_READ(HSW_PWR_WELL_DRIVER); 5067 5071 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 5072 + 5073 + /* 5074 + * After this, the registers on the pipes that are part 5075 + * of the power well will become zero, so we have to 5076 + * adjust our counters according to that. 5077 + * 5078 + * FIXME: Should we do this in general in 5079 + * drm_vblank_post_modeset? 5080 + */ 5081 + spin_lock_irqsave(&dev->vbl_lock, irqflags); 5082 + for_each_pipe(p) 5083 + if (p != PIPE_A) 5084 + dev->last_vblank[p] = 0; 5085 + spin_unlock_irqrestore(&dev->vbl_lock, irqflags); 5068 5086 } 5069 5087 } 5070 5088 }

+1

drivers/gpu/drm/mgag200/mgag200_ttm.c

··· 323 323 324 324 mgabo->gem.driver_private = NULL; 325 325 mgabo->bo.bdev = &mdev->ttm.bdev; 326 + mgabo->bo.bdev->dev_mapping = dev->dev_mapping; 326 327 327 328 mgag200_ttm_placement(mgabo, TTM_PL_FLAG_VRAM | TTM_PL_FLAG_SYSTEM); 328 329

+2 -15

drivers/gpu/drm/radeon/btc_dpm.c

··· 2548 2548 { 2549 2549 struct rv7xx_power_info *pi; 2550 2550 struct evergreen_power_info *eg_pi; 2551 - int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 2552 - u16 data_offset, size; 2553 - u8 frev, crev; 2554 2551 struct atom_clock_dividers dividers; 2555 2552 int ret; 2556 2553 ··· 2630 2633 eg_pi->vddci_control = 2631 2634 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 2632 2635 2633 - if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 2634 - &frev, &crev, &data_offset)) { 2635 - pi->sclk_ss = true; 2636 - pi->mclk_ss = true; 2637 - pi->dynamic_ss = true; 2638 - } else { 2639 - pi->sclk_ss = false; 2640 - pi->mclk_ss = false; 2641 - pi->dynamic_ss = true; 2642 - } 2636 + rv770_get_engine_memory_ss(rdev); 2643 2637 2644 2638 pi->asi = RV770_ASI_DFLT; 2645 2639 pi->pasi = CYPRESS_HASI_DFLT; ··· 2647 2659 2648 2660 pi->dynamic_pcie_gen2 = true; 2649 2661 2650 - if (pi->gfx_clock_gating && 2651 - (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 2662 + if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 2652 2663 pi->thermal_protection = true; 2653 2664 else 2654 2665 pi->thermal_protection = false;

+15 -3

drivers/gpu/drm/radeon/cik.c

··· 2587 2587 if (rdev->wb.enabled) { 2588 2588 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 2589 2589 } else { 2590 + mutex_lock(&rdev->srbm_mutex); 2590 2591 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); 2591 2592 rptr = RREG32(CP_HQD_PQ_RPTR); 2592 2593 cik_srbm_select(rdev, 0, 0, 0, 0); 2594 + mutex_unlock(&rdev->srbm_mutex); 2593 2595 } 2594 2596 rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 2595 2597 ··· 2606 2604 if (rdev->wb.enabled) { 2607 2605 wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]); 2608 2606 } else { 2607 + mutex_lock(&rdev->srbm_mutex); 2609 2608 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); 2610 2609 wptr = RREG32(CP_HQD_PQ_WPTR); 2611 2610 cik_srbm_select(rdev, 0, 0, 0, 0); 2611 + mutex_unlock(&rdev->srbm_mutex); 2612 2612 } 2613 2613 wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 2614 2614 ··· 2901 2897 WREG32(CP_CPF_DEBUG, tmp); 2902 2898 2903 2899 /* init the pipes */ 2900 + mutex_lock(&rdev->srbm_mutex); 2904 2901 for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); i++) { 2905 2902 int me = (i < 4) ? 1 : 2; 2906 2903 int pipe = (i < 4) ? i : (i - 4); ··· 2924 2919 WREG32(CP_HPD_EOP_CONTROL, tmp); 2925 2920 } 2926 2921 cik_srbm_select(rdev, 0, 0, 0, 0); 2922 + mutex_unlock(&rdev->srbm_mutex); 2927 2923 2928 2924 /* init the queues. Just two for now. */ 2929 2925 for (i = 0; i < 2; i++) { ··· 2978 2972 mqd->static_thread_mgmt23[0] = 0xffffffff; 2979 2973 mqd->static_thread_mgmt23[1] = 0xffffffff; 2980 2974 2975 + mutex_lock(&rdev->srbm_mutex); 2981 2976 cik_srbm_select(rdev, rdev->ring[idx].me, 2982 2977 rdev->ring[idx].pipe, 2983 2978 rdev->ring[idx].queue, 0); ··· 3106 3099 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); 3107 3100 3108 3101 cik_srbm_select(rdev, 0, 0, 0, 0); 3102 + mutex_unlock(&rdev->srbm_mutex); 3109 3103 3110 3104 radeon_bo_kunmap(rdev->ring[idx].mqd_obj); 3111 3105 radeon_bo_unreserve(rdev->ring[idx].mqd_obj); ··· 4328 4320 4329 4321 /* XXX SH_MEM regs */ 4330 4322 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4323 + mutex_lock(&rdev->srbm_mutex); 4331 4324 for (i = 0; i < 16; i++) { 4332 4325 cik_srbm_select(rdev, 0, 0, 0, i); 4333 4326 /* CP and shaders */ ··· 4344 4335 /* XXX SDMA RLC - todo */ 4345 4336 } 4346 4337 cik_srbm_select(rdev, 0, 0, 0, 0); 4338 + mutex_unlock(&rdev->srbm_mutex); 4347 4339 4348 4340 cik_pcie_gart_tlb_flush(rdev); 4349 4341 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", ··· 5964 5954 struct radeon_ring *ring; 5965 5955 int r; 5966 5956 5957 + cik_mc_program(rdev); 5958 + 5967 5959 if (rdev->flags & RADEON_IS_IGP) { 5968 5960 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || 5969 5961 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) { ··· 5997 5985 if (r) 5998 5986 return r; 5999 5987 6000 - cik_mc_program(rdev); 6001 5988 r = cik_pcie_gart_enable(rdev); 6002 5989 if (r) 6003 5990 return r; ··· 6205 6194 radeon_vm_manager_fini(rdev); 6206 6195 cik_cp_enable(rdev, false); 6207 6196 cik_sdma_enable(rdev, false); 6208 - r600_uvd_rbc_stop(rdev); 6197 + r600_uvd_stop(rdev); 6209 6198 radeon_uvd_suspend(rdev); 6210 6199 cik_irq_suspend(rdev); 6211 6200 radeon_wb_disable(rdev); ··· 6369 6358 radeon_vm_manager_fini(rdev); 6370 6359 radeon_ib_pool_fini(rdev); 6371 6360 radeon_irq_kms_fini(rdev); 6361 + r600_uvd_stop(rdev); 6372 6362 radeon_uvd_fini(rdev); 6373 6363 cik_pcie_gart_fini(rdev); 6374 6364 r600_vram_scratch_fini(rdev); ··· 6990 6978 6991 6979 /* programm the VCPU memory controller bits 0-27 */ 6992 6980 addr = rdev->uvd.gpu_addr >> 3; 6993 - size = RADEON_GPU_PAGE_ALIGN(rdev->uvd.fw_size + 4) >> 3; 6981 + size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3; 6994 6982 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); 6995 6983 WREG32(UVD_VCPU_CACHE_SIZE0, size); 6996 6984

+2 -15

drivers/gpu/drm/radeon/cypress_dpm.c

··· 2038 2038 { 2039 2039 struct rv7xx_power_info *pi; 2040 2040 struct evergreen_power_info *eg_pi; 2041 - int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 2042 - uint16_t data_offset, size; 2043 - uint8_t frev, crev; 2044 2041 struct atom_clock_dividers dividers; 2045 2042 int ret; 2046 2043 ··· 2089 2092 eg_pi->vddci_control = 2090 2093 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 2091 2094 2092 - if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 2093 - &frev, &crev, &data_offset)) { 2094 - pi->sclk_ss = true; 2095 - pi->mclk_ss = true; 2096 - pi->dynamic_ss = true; 2097 - } else { 2098 - pi->sclk_ss = false; 2099 - pi->mclk_ss = false; 2100 - pi->dynamic_ss = true; 2101 - } 2095 + rv770_get_engine_memory_ss(rdev); 2102 2096 2103 2097 pi->asi = RV770_ASI_DFLT; 2104 2098 pi->pasi = CYPRESS_HASI_DFLT; ··· 2110 2122 2111 2123 pi->dynamic_pcie_gen2 = true; 2112 2124 2113 - if (pi->gfx_clock_gating && 2114 - (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 2125 + if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 2115 2126 pi->thermal_protection = true; 2116 2127 else 2117 2128 pi->thermal_protection = false;

+4 -2

drivers/gpu/drm/radeon/evergreen.c

··· 5106 5106 /* enable aspm */ 5107 5107 evergreen_program_aspm(rdev); 5108 5108 5109 + evergreen_mc_program(rdev); 5110 + 5109 5111 if (ASIC_IS_DCE5(rdev)) { 5110 5112 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 5111 5113 r = ni_init_microcode(rdev); ··· 5135 5133 if (r) 5136 5134 return r; 5137 5135 5138 - evergreen_mc_program(rdev); 5139 5136 if (rdev->flags & RADEON_IS_AGP) { 5140 5137 evergreen_agp_enable(rdev); 5141 5138 } else { ··· 5292 5291 int evergreen_suspend(struct radeon_device *rdev) 5293 5292 { 5294 5293 r600_audio_fini(rdev); 5294 + r600_uvd_stop(rdev); 5295 5295 radeon_uvd_suspend(rdev); 5296 5296 r700_cp_stop(rdev); 5297 5297 r600_dma_stop(rdev); 5298 - r600_uvd_rbc_stop(rdev); 5299 5298 evergreen_irq_suspend(rdev); 5300 5299 radeon_wb_disable(rdev); 5301 5300 evergreen_pcie_gart_disable(rdev); ··· 5430 5429 radeon_ib_pool_fini(rdev); 5431 5430 radeon_irq_kms_fini(rdev); 5432 5431 evergreen_pcie_gart_fini(rdev); 5432 + r600_uvd_stop(rdev); 5433 5433 radeon_uvd_fini(rdev); 5434 5434 r600_vram_scratch_fini(rdev); 5435 5435 radeon_gem_fini(rdev);

+24 -2

drivers/gpu/drm/radeon/evergreen_hdmi.c

··· 148 148 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 149 149 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 150 150 u32 base_rate = 24000; 151 + u32 max_ratio = clock / base_rate; 152 + u32 dto_phase; 153 + u32 dto_modulo = clock; 154 + u32 wallclock_ratio; 155 + u32 dto_cntl; 151 156 152 157 if (!dig || !dig->afmt) 153 158 return; 159 + 160 + if (max_ratio >= 8) { 161 + dto_phase = 192 * 1000; 162 + wallclock_ratio = 3; 163 + } else if (max_ratio >= 4) { 164 + dto_phase = 96 * 1000; 165 + wallclock_ratio = 2; 166 + } else if (max_ratio >= 2) { 167 + dto_phase = 48 * 1000; 168 + wallclock_ratio = 1; 169 + } else { 170 + dto_phase = 24 * 1000; 171 + wallclock_ratio = 0; 172 + } 173 + dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 174 + dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 175 + WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 154 176 155 177 /* XXX two dtos; generally use dto0 for hdmi */ 156 178 /* Express [24MHz / target pixel clock] as an exact rational ··· 180 158 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 181 159 */ 182 160 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); 183 - WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); 184 - WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 161 + WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 162 + WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); 185 163 } 186 164 187 165

+3

drivers/gpu/drm/radeon/evergreend.h

··· 497 497 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 498 498 #define DCCG_AUDIO_DTO0_LOAD 0x05b8 499 499 #define DCCG_AUDIO_DTO0_CNTL 0x05bc 500 + # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) 501 + # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 502 + # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 500 503 501 504 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 502 505 #define DCCG_AUDIO_DTO1_MODULE 0x05c4

+11 -5

drivers/gpu/drm/radeon/ni.c

··· 794 794 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { 795 795 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 796 796 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 797 - if (err) 798 - goto out; 799 - if (rdev->smc_fw->size != smc_req_size) { 797 + if (err) { 798 + printk(KERN_ERR 799 + "smc: error loading firmware \"%s\"\n", 800 + fw_name); 801 + release_firmware(rdev->smc_fw); 802 + rdev->smc_fw = NULL; 803 + } else if (rdev->smc_fw->size != smc_req_size) { 800 804 printk(KERN_ERR 801 805 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 802 806 rdev->mc_fw->size, fw_name); ··· 2083 2079 /* enable aspm */ 2084 2080 evergreen_program_aspm(rdev); 2085 2081 2082 + evergreen_mc_program(rdev); 2083 + 2086 2084 if (rdev->flags & RADEON_IS_IGP) { 2087 2085 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2088 2086 r = ni_init_microcode(rdev); ··· 2113 2107 if (r) 2114 2108 return r; 2115 2109 2116 - evergreen_mc_program(rdev); 2117 2110 r = cayman_pcie_gart_enable(rdev); 2118 2111 if (r) 2119 2112 return r; ··· 2291 2286 radeon_vm_manager_fini(rdev); 2292 2287 cayman_cp_enable(rdev, false); 2293 2288 cayman_dma_stop(rdev); 2294 - r600_uvd_rbc_stop(rdev); 2289 + r600_uvd_stop(rdev); 2295 2290 radeon_uvd_suspend(rdev); 2296 2291 evergreen_irq_suspend(rdev); 2297 2292 radeon_wb_disable(rdev); ··· 2423 2418 radeon_vm_manager_fini(rdev); 2424 2419 radeon_ib_pool_fini(rdev); 2425 2420 radeon_irq_kms_fini(rdev); 2421 + r600_uvd_stop(rdev); 2426 2422 radeon_uvd_fini(rdev); 2427 2423 cayman_pcie_gart_fini(rdev); 2428 2424 r600_vram_scratch_fini(rdev);

+2 -15

drivers/gpu/drm/radeon/ni_dpm.c

··· 4067 4067 struct rv7xx_power_info *pi; 4068 4068 struct evergreen_power_info *eg_pi; 4069 4069 struct ni_power_info *ni_pi; 4070 - int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 4071 - u16 data_offset, size; 4072 - u8 frev, crev; 4073 4070 struct atom_clock_dividers dividers; 4074 4071 int ret; 4075 4072 ··· 4159 4162 eg_pi->vddci_control = 4160 4163 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 4161 4164 4162 - if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 4163 - &frev, &crev, &data_offset)) { 4164 - pi->sclk_ss = true; 4165 - pi->mclk_ss = true; 4166 - pi->dynamic_ss = true; 4167 - } else { 4168 - pi->sclk_ss = false; 4169 - pi->mclk_ss = false; 4170 - pi->dynamic_ss = true; 4171 - } 4165 + rv770_get_engine_memory_ss(rdev); 4172 4166 4173 4167 pi->asi = RV770_ASI_DFLT; 4174 4168 pi->pasi = CYPRESS_HASI_DFLT; ··· 4176 4188 4177 4189 pi->dynamic_pcie_gen2 = true; 4178 4190 4179 - if (pi->gfx_clock_gating && 4180 - (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 4191 + if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 4181 4192 pi->thermal_protection = true; 4182 4193 else 4183 4194 pi->thermal_protection = false;

+32 -9

drivers/gpu/drm/radeon/r600.c

··· 2299 2299 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2300 2300 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2301 2301 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2302 - if (err) 2303 - goto out; 2304 - if (rdev->smc_fw->size != smc_req_size) { 2302 + if (err) { 2303 + printk(KERN_ERR 2304 + "smc: error loading firmware \"%s\"\n", 2305 + fw_name); 2306 + release_firmware(rdev->smc_fw); 2307 + rdev->smc_fw = NULL; 2308 + } else if (rdev->smc_fw->size != smc_req_size) { 2305 2309 printk(KERN_ERR 2306 2310 "smc: Bogus length %zu in firmware \"%s\"\n", 2307 2311 rdev->smc_fw->size, fw_name); ··· 2701 2697 return 0; 2702 2698 } 2703 2699 2704 - void r600_uvd_rbc_stop(struct radeon_device *rdev) 2700 + void r600_uvd_stop(struct radeon_device *rdev) 2705 2701 { 2706 2702 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2707 2703 2708 2704 /* force RBC into idle state */ 2709 2705 WREG32(UVD_RBC_RB_CNTL, 0x11010101); 2706 + 2707 + /* Stall UMC and register bus before resetting VCPU */ 2708 + WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 2709 + WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); 2710 + mdelay(1); 2711 + 2712 + /* put VCPU into reset */ 2713 + WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); 2714 + mdelay(5); 2715 + 2716 + /* disable VCPU clock */ 2717 + WREG32(UVD_VCPU_CNTL, 0x0); 2718 + 2719 + /* Unstall UMC and register bus */ 2720 + WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); 2721 + WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); 2722 + 2710 2723 ring->ready = false; 2711 2724 } 2712 2725 ··· 2742 2721 2743 2722 /* disable interupt */ 2744 2723 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); 2724 + 2725 + /* Stall UMC and register bus before resetting VCPU */ 2726 + WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 2727 + WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); 2728 + mdelay(1); 2745 2729 2746 2730 /* put LMI, VCPU, RBC etc... into reset */ 2747 2731 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET | ··· 2776 2750 WREG32(UVD_MPC_SET_MUXB1, 0x0); 2777 2751 WREG32(UVD_MPC_SET_ALU, 0); 2778 2752 WREG32(UVD_MPC_SET_MUX, 0x88); 2779 - 2780 - /* Stall UMC */ 2781 - WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 2782 - WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); 2783 2753 2784 2754 /* take all subblocks out of reset, except VCPU */ 2785 2755 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); ··· 3334 3312 /* enable pcie gen2 link */ 3335 3313 r600_pcie_gen2_enable(rdev); 3336 3314 3315 + r600_mc_program(rdev); 3316 + 3337 3317 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3338 3318 r = r600_init_microcode(rdev); 3339 3319 if (r) { ··· 3348 3324 if (r) 3349 3325 return r; 3350 3326 3351 - r600_mc_program(rdev); 3352 3327 if (rdev->flags & RADEON_IS_AGP) { 3353 3328 r600_agp_enable(rdev); 3354 3329 } else {

+34 -3

drivers/gpu/drm/radeon/r600_hdmi.c

··· 226 226 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 227 227 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 228 228 u32 base_rate = 24000; 229 + u32 max_ratio = clock / base_rate; 230 + u32 dto_phase; 231 + u32 dto_modulo = clock; 232 + u32 wallclock_ratio; 233 + u32 dto_cntl; 229 234 230 235 if (!dig || !dig->afmt) 231 236 return; 237 + 238 + if (max_ratio >= 8) { 239 + dto_phase = 192 * 1000; 240 + wallclock_ratio = 3; 241 + } else if (max_ratio >= 4) { 242 + dto_phase = 96 * 1000; 243 + wallclock_ratio = 2; 244 + } else if (max_ratio >= 2) { 245 + dto_phase = 48 * 1000; 246 + wallclock_ratio = 1; 247 + } else { 248 + dto_phase = 24 * 1000; 249 + wallclock_ratio = 0; 250 + } 232 251 233 252 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. 234 253 * doesn't matter which one you use. Just use the first one. ··· 261 242 /* according to the reg specs, this should DCE3.2 only, but in 262 243 * practice it seems to cover DCE3.0 as well. 263 244 */ 264 - WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); 265 - WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 266 - WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 245 + if (dig->dig_encoder == 0) { 246 + dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 247 + dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 248 + WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 249 + WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 250 + WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); 251 + WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 252 + } else { 253 + dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 254 + dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 255 + WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); 256 + WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); 257 + WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); 258 + WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 259 + } 267 260 } else { 268 261 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ 269 262 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |

+3

drivers/gpu/drm/radeon/r600d.h

··· 933 933 #define DCCG_AUDIO_DTO0_LOAD 0x051c 934 934 # define DTO_LOAD (1 << 31) 935 935 #define DCCG_AUDIO_DTO0_CNTL 0x0520 936 + # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) 937 + # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 938 + # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 936 939 937 940 #define DCCG_AUDIO_DTO1_PHASE 0x0524 938 941 #define DCCG_AUDIO_DTO1_MODULE 0x0528

+3 -1

drivers/gpu/drm/radeon/radeon.h

··· 1468 1468 void *cpu_addr; 1469 1469 uint64_t gpu_addr; 1470 1470 void *saved_bo; 1471 - unsigned fw_size; 1472 1471 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1473 1472 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1474 1473 struct delayed_work idle_work; ··· 2065 2066 const struct firmware *mec_fw; /* CIK MEC firmware */ 2066 2067 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2067 2068 const struct firmware *smc_fw; /* SMC firmware */ 2069 + const struct firmware *uvd_fw; /* UVD firmware */ 2068 2070 struct r600_blit r600_blit; 2069 2071 struct r600_vram_scratch vram_scratch; 2070 2072 int msi_enabled; /* msi enabled */ ··· 2095 2095 /* ACPI interface */ 2096 2096 struct radeon_atif atif; 2097 2097 struct radeon_atcs atcs; 2098 + /* srbm instance registers */ 2099 + struct mutex srbm_mutex; 2098 2100 }; 2099 2101 2100 2102 int radeon_device_init(struct radeon_device *rdev,

+1 -1

drivers/gpu/drm/radeon/radeon_asic.h

··· 441 441 /* uvd */ 442 442 int r600_uvd_init(struct radeon_device *rdev); 443 443 int r600_uvd_rbc_start(struct radeon_device *rdev); 444 - void r600_uvd_rbc_stop(struct radeon_device *rdev); 444 + void r600_uvd_stop(struct radeon_device *rdev); 445 445 int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 446 446 void r600_uvd_fence_emit(struct radeon_device *rdev, 447 447 struct radeon_fence *fence);

+3

drivers/gpu/drm/radeon/radeon_device.c

··· 1163 1163 mutex_init(&rdev->gem.mutex); 1164 1164 mutex_init(&rdev->pm.mutex); 1165 1165 mutex_init(&rdev->gpu_clock_mutex); 1166 + mutex_init(&rdev->srbm_mutex); 1166 1167 init_rwsem(&rdev->pm.mclk_lock); 1167 1168 init_rwsem(&rdev->exclusive_lock); 1168 1169 init_waitqueue_head(&rdev->irq.vblank_queue); ··· 1520 1519 radeon_save_bios_scratch_regs(rdev); 1521 1520 /* block TTM */ 1522 1521 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1522 + radeon_pm_suspend(rdev); 1523 1523 radeon_suspend(rdev); 1524 1524 1525 1525 for (i = 0; i < RADEON_NUM_RINGS; ++i) { ··· 1566 1564 } 1567 1565 } 1568 1566 1567 + radeon_pm_resume(rdev); 1569 1568 drm_helper_resume_force_mode(rdev->ddev); 1570 1569 1571 1570 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);

+1 -1

drivers/gpu/drm/radeon/radeon_fence.c

··· 782 782 783 783 } else { 784 784 /* put fence directly behind firmware */ 785 - index = ALIGN(rdev->uvd.fw_size, 8); 785 + index = ALIGN(rdev->uvd_fw->size, 8); 786 786 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index; 787 787 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; 788 788 }

-1

drivers/gpu/drm/radeon/radeon_gart.c

··· 207 207 if (rdev->gart.robj == NULL) { 208 208 return; 209 209 } 210 - radeon_gart_table_vram_unpin(rdev); 211 210 radeon_bo_unref(&rdev->gart.robj); 212 211 } 213 212

+8 -1

drivers/gpu/drm/radeon/radeon_pm.c

··· 1176 1176 case CHIP_VERDE: 1177 1177 case CHIP_OLAND: 1178 1178 case CHIP_HAINAN: 1179 - if (radeon_dpm == 1) 1179 + /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1180 + if (!rdev->rlc_fw) 1181 + rdev->pm.pm_method = PM_METHOD_PROFILE; 1182 + else if ((rdev->family >= CHIP_RV770) && 1183 + (!(rdev->flags & RADEON_IS_IGP)) && 1184 + (!rdev->smc_fw)) 1185 + rdev->pm.pm_method = PM_METHOD_PROFILE; 1186 + else if (radeon_dpm == 1) 1180 1187 rdev->pm.pm_method = PM_METHOD_DPM; 1181 1188 else 1182 1189 rdev->pm.pm_method = PM_METHOD_PROFILE;

+70 -23

drivers/gpu/drm/radeon/radeon_uvd.c

··· 56 56 57 57 int radeon_uvd_init(struct radeon_device *rdev) 58 58 { 59 - const struct firmware *fw; 60 59 unsigned long bo_size; 61 60 const char *fw_name; 62 61 int i, r; ··· 104 105 return -EINVAL; 105 106 } 106 107 107 - r = request_firmware(&fw, fw_name, rdev->dev); 108 + r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); 108 109 if (r) { 109 110 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", 110 111 fw_name); 111 112 return r; 112 113 } 113 114 114 - bo_size = RADEON_GPU_PAGE_ALIGN(fw->size + 8) + 115 + bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + 115 116 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE; 116 117 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 117 118 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo); ··· 144 145 145 146 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 146 147 147 - rdev->uvd.fw_size = fw->size; 148 - memset(rdev->uvd.cpu_addr, 0, bo_size); 149 - memcpy(rdev->uvd.cpu_addr, fw->data, fw->size); 150 - 151 - release_firmware(fw); 152 - 153 148 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 154 149 atomic_set(&rdev->uvd.handles[i], 0); 155 150 rdev->uvd.filp[i] = NULL; ··· 167 174 } 168 175 169 176 radeon_bo_unref(&rdev->uvd.vcpu_bo); 177 + 178 + release_firmware(rdev->uvd_fw); 170 179 } 171 180 172 181 int radeon_uvd_suspend(struct radeon_device *rdev) 173 182 { 174 183 unsigned size; 184 + void *ptr; 185 + int i; 175 186 176 187 if (rdev->uvd.vcpu_bo == NULL) 177 188 return 0; 178 189 190 + for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) 191 + if (atomic_read(&rdev->uvd.handles[i])) 192 + break; 193 + 194 + if (i == RADEON_MAX_UVD_HANDLES) 195 + return 0; 196 + 179 197 size = radeon_bo_size(rdev->uvd.vcpu_bo); 198 + size -= rdev->uvd_fw->size; 199 + 200 + ptr = rdev->uvd.cpu_addr; 201 + ptr += rdev->uvd_fw->size; 202 + 180 203 rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 181 - memcpy(rdev->uvd.saved_bo, rdev->uvd.cpu_addr, size); 204 + memcpy(rdev->uvd.saved_bo, ptr, size); 182 205 183 206 return 0; 184 207 } 185 208 186 209 int radeon_uvd_resume(struct radeon_device *rdev) 187 210 { 211 + unsigned size; 212 + void *ptr; 213 + 188 214 if (rdev->uvd.vcpu_bo == NULL) 189 215 return -EINVAL; 190 216 217 + memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 218 + 219 + size = radeon_bo_size(rdev->uvd.vcpu_bo); 220 + size -= rdev->uvd_fw->size; 221 + 222 + ptr = rdev->uvd.cpu_addr; 223 + ptr += rdev->uvd_fw->size; 224 + 191 225 if (rdev->uvd.saved_bo != NULL) { 192 - unsigned size = radeon_bo_size(rdev->uvd.vcpu_bo); 193 - memcpy(rdev->uvd.cpu_addr, rdev->uvd.saved_bo, size); 226 + memcpy(ptr, rdev->uvd.saved_bo, size); 194 227 kfree(rdev->uvd.saved_bo); 195 228 rdev->uvd.saved_bo = NULL; 196 - } 229 + } else 230 + memset(ptr, 0, size); 197 231 198 232 return 0; 199 233 } ··· 235 215 { 236 216 int i, r; 237 217 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 238 - if (rdev->uvd.filp[i] == filp) { 239 - uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 218 + uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 219 + if (handle != 0 && rdev->uvd.filp[i] == filp) { 240 220 struct radeon_fence *fence; 241 221 242 222 r = radeon_uvd_get_destroy_msg(rdev, ··· 357 337 } 358 338 359 339 r = radeon_bo_kmap(bo, &ptr); 360 - if (r) 340 + if (r) { 341 + DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); 361 342 return r; 343 + } 362 344 363 345 msg = ptr + offset; 364 346 ··· 386 364 radeon_bo_kunmap(bo); 387 365 return 0; 388 366 } else { 389 - /* it's a create msg, no special handling needed */ 390 367 radeon_bo_kunmap(bo); 368 + 369 + if (msg_type != 0) { 370 + DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 371 + return -EINVAL; 372 + } 373 + 374 + /* it's a create msg, no special handling needed */ 391 375 } 392 376 393 377 /* create or decode, validate the handle */ ··· 416 388 417 389 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, 418 390 int data0, int data1, 419 - unsigned buf_sizes[]) 391 + unsigned buf_sizes[], bool *has_msg_cmd) 420 392 { 421 393 struct radeon_cs_chunk *relocs_chunk; 422 394 struct radeon_cs_reloc *reloc; ··· 445 417 446 418 if (cmd < 0x4) { 447 419 if ((end - start) < buf_sizes[cmd]) { 448 - DRM_ERROR("buffer to small (%d / %d)!\n", 420 + DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 449 421 (unsigned)(end - start), buf_sizes[cmd]); 450 422 return -EINVAL; 451 423 } ··· 470 442 } 471 443 472 444 if (cmd == 0) { 445 + if (*has_msg_cmd) { 446 + DRM_ERROR("More than one message in a UVD-IB!\n"); 447 + return -EINVAL; 448 + } 449 + *has_msg_cmd = true; 473 450 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); 474 451 if (r) 475 452 return r; 453 + } else if (!*has_msg_cmd) { 454 + DRM_ERROR("Message needed before other commands are send!\n"); 455 + return -EINVAL; 476 456 } 477 457 478 458 return 0; ··· 489 453 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p, 490 454 struct radeon_cs_packet *pkt, 491 455 int *data0, int *data1, 492 - unsigned buf_sizes[]) 456 + unsigned buf_sizes[], 457 + bool *has_msg_cmd) 493 458 { 494 459 int i, r; 495 460 ··· 504 467 *data1 = p->idx; 505 468 break; 506 469 case UVD_GPCOM_VCPU_CMD: 507 - r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes); 470 + r = radeon_uvd_cs_reloc(p, *data0, *data1, 471 + buf_sizes, has_msg_cmd); 508 472 if (r) 509 473 return r; 510 474 break; ··· 525 487 { 526 488 struct radeon_cs_packet pkt; 527 489 int r, data0 = 0, data1 = 0; 490 + 491 + /* does the IB has a msg command */ 492 + bool has_msg_cmd = false; 528 493 529 494 /* minimum buffer sizes */ 530 495 unsigned buf_sizes[] = { ··· 555 514 return r; 556 515 switch (pkt.type) { 557 516 case RADEON_PACKET_TYPE0: 558 - r = radeon_uvd_cs_reg(p, &pkt, &data0, 559 - &data1, buf_sizes); 517 + r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1, 518 + buf_sizes, &has_msg_cmd); 560 519 if (r) 561 520 return r; 562 521 break; ··· 568 527 return -EINVAL; 569 528 } 570 529 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 530 + 531 + if (!has_msg_cmd) { 532 + DRM_ERROR("UVD-IBs need a msg command!\n"); 533 + return -EINVAL; 534 + } 535 + 571 536 return 0; 572 537 } 573 538

+11 -11

drivers/gpu/drm/radeon/rv6xx_dpm.c

··· 1944 1944 1945 1945 int rv6xx_dpm_init(struct radeon_device *rdev) 1946 1946 { 1947 - int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1948 - uint16_t data_offset, size; 1949 - uint8_t frev, crev; 1947 + struct radeon_atom_ss ss; 1950 1948 struct atom_clock_dividers dividers; 1951 1949 struct rv6xx_power_info *pi; 1952 1950 int ret; ··· 1987 1989 1988 1990 pi->gfx_clock_gating = true; 1989 1991 1990 - if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 1991 - &frev, &crev, &data_offset)) { 1992 - pi->sclk_ss = true; 1993 - pi->mclk_ss = true; 1992 + pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, 1993 + ASIC_INTERNAL_ENGINE_SS, 0); 1994 + pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, 1995 + ASIC_INTERNAL_MEMORY_SS, 0); 1996 + 1997 + /* Disable sclk ss, causes hangs on a lot of systems */ 1998 + pi->sclk_ss = false; 1999 + 2000 + if (pi->sclk_ss || pi->mclk_ss) 1994 2001 pi->dynamic_ss = true; 1995 - } else { 1996 - pi->sclk_ss = false; 1997 - pi->mclk_ss = false; 2002 + else 1998 2003 pi->dynamic_ss = false; 1999 - } 2000 2004 2001 2005 pi->dynamic_pcie_gen2 = true; 2002 2006

+5 -2

drivers/gpu/drm/radeon/rv770.c

··· 813 813 814 814 /* programm the VCPU memory controller bits 0-27 */ 815 815 addr = rdev->uvd.gpu_addr >> 3; 816 - size = RADEON_GPU_PAGE_ALIGN(rdev->uvd.fw_size + 4) >> 3; 816 + size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3; 817 817 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); 818 818 WREG32(UVD_VCPU_CACHE_SIZE0, size); 819 819 ··· 1829 1829 /* enable pcie gen2 link */ 1830 1830 rv770_pcie_gen2_enable(rdev); 1831 1831 1832 + rv770_mc_program(rdev); 1833 + 1832 1834 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1833 1835 r = r600_init_microcode(rdev); 1834 1836 if (r) { ··· 1843 1841 if (r) 1844 1842 return r; 1845 1843 1846 - rv770_mc_program(rdev); 1847 1844 if (rdev->flags & RADEON_IS_AGP) { 1848 1845 rv770_agp_enable(rdev); 1849 1846 } else { ··· 1984 1983 int rv770_suspend(struct radeon_device *rdev) 1985 1984 { 1986 1985 r600_audio_fini(rdev); 1986 + r600_uvd_stop(rdev); 1987 1987 radeon_uvd_suspend(rdev); 1988 1988 r700_cp_stop(rdev); 1989 1989 r600_dma_stop(rdev); ··· 2100 2098 radeon_ib_pool_fini(rdev); 2101 2099 radeon_irq_kms_fini(rdev); 2102 2100 rv770_pcie_gart_fini(rdev); 2101 + r600_uvd_stop(rdev); 2103 2102 radeon_uvd_fini(rdev); 2104 2103 r600_vram_scratch_fini(rdev); 2105 2104 radeon_gem_fini(rdev);

+18 -15

drivers/gpu/drm/radeon/rv770_dpm.c

··· 2319 2319 return 0; 2320 2320 } 2321 2321 2322 + void rv770_get_engine_memory_ss(struct radeon_device *rdev) 2323 + { 2324 + struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2325 + struct radeon_atom_ss ss; 2326 + 2327 + pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, 2328 + ASIC_INTERNAL_ENGINE_SS, 0); 2329 + pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, 2330 + ASIC_INTERNAL_MEMORY_SS, 0); 2331 + 2332 + if (pi->sclk_ss || pi->mclk_ss) 2333 + pi->dynamic_ss = true; 2334 + else 2335 + pi->dynamic_ss = false; 2336 + } 2337 + 2322 2338 int rv770_dpm_init(struct radeon_device *rdev) 2323 2339 { 2324 2340 struct rv7xx_power_info *pi; 2325 - int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 2326 - uint16_t data_offset, size; 2327 - uint8_t frev, crev; 2328 2341 struct atom_clock_dividers dividers; 2329 2342 int ret; 2330 2343 ··· 2382 2369 pi->mvdd_control = 2383 2370 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0); 2384 2371 2385 - if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 2386 - &frev, &crev, &data_offset)) { 2387 - pi->sclk_ss = true; 2388 - pi->mclk_ss = true; 2389 - pi->dynamic_ss = true; 2390 - } else { 2391 - pi->sclk_ss = false; 2392 - pi->mclk_ss = false; 2393 - pi->dynamic_ss = false; 2394 - } 2372 + rv770_get_engine_memory_ss(rdev); 2395 2373 2396 2374 pi->asi = RV770_ASI_DFLT; 2397 2375 pi->pasi = RV770_HASI_DFLT; ··· 2397 2393 2398 2394 pi->dynamic_pcie_gen2 = true; 2399 2395 2400 - if (pi->gfx_clock_gating && 2401 - (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 2396 + if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 2402 2397 pi->thermal_protection = true; 2403 2398 else 2404 2399 pi->thermal_protection = false;

+1

drivers/gpu/drm/radeon/rv770_dpm.h

··· 275 275 void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 276 276 struct radeon_ps *new_ps, 277 277 struct radeon_ps *old_ps); 278 + void rv770_get_engine_memory_ss(struct radeon_device *rdev); 278 279 279 280 /* smc */ 280 281 int rv770_read_smc_soft_register(struct radeon_device *rdev,

+13 -6

drivers/gpu/drm/radeon/si.c

··· 1663 1663 1664 1664 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 1665 1665 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 1666 - if (err) 1667 - goto out; 1668 - if (rdev->smc_fw->size != smc_req_size) { 1666 + if (err) { 1667 + printk(KERN_ERR 1668 + "smc: error loading firmware \"%s\"\n", 1669 + fw_name); 1670 + release_firmware(rdev->smc_fw); 1671 + rdev->smc_fw = NULL; 1672 + } else if (rdev->smc_fw->size != smc_req_size) { 1669 1673 printk(KERN_ERR 1670 1674 "si_smc: Bogus length %zu in firmware \"%s\"\n", 1671 1675 rdev->smc_fw->size, fw_name); ··· 6422 6418 /* enable aspm */ 6423 6419 si_program_aspm(rdev); 6424 6420 6421 + si_mc_program(rdev); 6422 + 6425 6423 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || 6426 6424 !rdev->rlc_fw || !rdev->mc_fw) { 6427 6425 r = si_init_microcode(rdev); ··· 6443 6437 if (r) 6444 6438 return r; 6445 6439 6446 - si_mc_program(rdev); 6447 6440 r = si_pcie_gart_enable(rdev); 6448 6441 if (r) 6449 6442 return r; ··· 6626 6621 si_cp_enable(rdev, false); 6627 6622 cayman_dma_stop(rdev); 6628 6623 if (rdev->has_uvd) { 6629 - r600_uvd_rbc_stop(rdev); 6624 + r600_uvd_stop(rdev); 6630 6625 radeon_uvd_suspend(rdev); 6631 6626 } 6632 6627 si_irq_suspend(rdev); ··· 6768 6763 radeon_vm_manager_fini(rdev); 6769 6764 radeon_ib_pool_fini(rdev); 6770 6765 radeon_irq_kms_fini(rdev); 6771 - if (rdev->has_uvd) 6766 + if (rdev->has_uvd) { 6767 + r600_uvd_stop(rdev); 6772 6768 radeon_uvd_fini(rdev); 6769 + } 6773 6770 si_pcie_gart_fini(rdev); 6774 6771 r600_vram_scratch_fini(rdev); 6775 6772 radeon_gem_fini(rdev);

+34 -27

drivers/gpu/drm/radeon/si_dpm.c

··· 2903 2903 { 2904 2904 struct ni_ps *ps = ni_get_ps(rps); 2905 2905 struct radeon_clock_and_voltage_limits *max_limits; 2906 - bool disable_mclk_switching; 2906 + bool disable_mclk_switching = false; 2907 + bool disable_sclk_switching = false; 2907 2908 u32 mclk, sclk; 2908 2909 u16 vddc, vddci; 2909 2910 int i; ··· 2912 2911 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2913 2912 ni_dpm_vblank_too_short(rdev)) 2914 2913 disable_mclk_switching = true; 2915 - else 2916 - disable_mclk_switching = false; 2914 + 2915 + if (rps->vclk || rps->dclk) { 2916 + disable_mclk_switching = true; 2917 + disable_sclk_switching = true; 2918 + } 2917 2919 2918 2920 if (rdev->pm.dpm.ac_power) 2919 2921 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; ··· 2944 2940 2945 2941 if (disable_mclk_switching) { 2946 2942 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2947 - sclk = ps->performance_levels[0].sclk; 2948 - vddc = ps->performance_levels[0].vddc; 2949 2943 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2950 2944 } else { 2951 - sclk = ps->performance_levels[0].sclk; 2952 2945 mclk = ps->performance_levels[0].mclk; 2953 - vddc = ps->performance_levels[0].vddc; 2954 2946 vddci = ps->performance_levels[0].vddci; 2947 + } 2948 + 2949 + if (disable_sclk_switching) { 2950 + sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2951 + vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2952 + } else { 2953 + sclk = ps->performance_levels[0].sclk; 2954 + vddc = ps->performance_levels[0].vddc; 2955 2955 } 2956 2956 2957 2957 /* adjusted low state */ ··· 2964 2956 ps->performance_levels[0].vddc = vddc; 2965 2957 ps->performance_levels[0].vddci = vddci; 2966 2958 2967 - for (i = 1; i < ps->performance_level_count; i++) { 2968 - if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2969 - ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2970 - if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2971 - ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2959 + if (disable_sclk_switching) { 2960 + sclk = ps->performance_levels[0].sclk; 2961 + for (i = 1; i < ps->performance_level_count; i++) { 2962 + if (sclk < ps->performance_levels[i].sclk) 2963 + sclk = ps->performance_levels[i].sclk; 2964 + } 2965 + for (i = 0; i < ps->performance_level_count; i++) { 2966 + ps->performance_levels[i].sclk = sclk; 2967 + ps->performance_levels[i].vddc = vddc; 2968 + } 2969 + } else { 2970 + for (i = 1; i < ps->performance_level_count; i++) { 2971 + if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2972 + ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2973 + if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2974 + ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2975 + } 2972 2976 } 2973 2977 2974 2978 if (disable_mclk_switching) { ··· 6273 6253 struct evergreen_power_info *eg_pi; 6274 6254 struct ni_power_info *ni_pi; 6275 6255 struct si_power_info *si_pi; 6276 - int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 6277 - u16 data_offset, size; 6278 - u8 frev, crev; 6279 6256 struct atom_clock_dividers dividers; 6280 6257 int ret; 6281 6258 u32 mask; ··· 6363 6346 si_pi->vddc_phase_shed_control = 6364 6347 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6365 6348 6366 - if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 6367 - &frev, &crev, &data_offset)) { 6368 - pi->sclk_ss = true; 6369 - pi->mclk_ss = true; 6370 - pi->dynamic_ss = true; 6371 - } else { 6372 - pi->sclk_ss = false; 6373 - pi->mclk_ss = false; 6374 - pi->dynamic_ss = true; 6375 - } 6349 + rv770_get_engine_memory_ss(rdev); 6376 6350 6377 6351 pi->asi = RV770_ASI_DFLT; 6378 6352 pi->pasi = CYPRESS_HASI_DFLT; ··· 6374 6366 eg_pi->sclk_deep_sleep = true; 6375 6367 si_pi->sclk_deep_sleep_above_low = false; 6376 6368 6377 - if (pi->gfx_clock_gating && 6378 - (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 6369 + if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6379 6370 pi->thermal_protection = true; 6380 6371 else 6381 6372 pi->thermal_protection = false;

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