Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'gpio-v4.15-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.15 kernel cycle:
Core:
- Fix the semantics of raw GPIO to actually be raw. No inversion
semantics as before, but also no open draining, and allow the raw
operations to affect lines used for interrupts as the caller
supposedly knows what they are doing if they are getting the big
hammer.
- Rewrote the __inner_function() notation calls to names that make
more sense. I just find this kind of code disturbing.
- Drop the .irq_base() field from the gpiochip since now all IRQs are
mapped dynamically. This is nice.
- Support for .get_multiple() in the core driver API. This allows us
to read several GPIO lines with a single register read. This has
high value for some usecases: it can be used to create
oscilloscopes and signal analyzers and other things that rely on
reading several lines at exactly the same instant. Also a generally
nice optimization. This uses the new assign_bit() macro from the
bitops lib that was ACKed by Andrew Morton and is implemented for
two drivers, one of them being the generic MMIO driver so everyone
using that will be able to benefit from this.
- Do not allow requests of Open Drain and Open Source setting of a
GPIO line simultaneously. If the hardware actually supports
enabling both at the same time the electrical result would be
disastrous.
- A new interrupt chip core helper. This will be helpful to deal with
"banked" GPIOs, which means GPIO controllers with several logical
blocks of GPIO inside them. This is several gpiochips per device in
the device model, in contrast to the case when there is a 1-to-1
relationship between a device and a gpiochip.
New drivers:
- Maxim MAX3191x industrial serializer, a very interesting piece of
professional I/O hardware.
- Uniphier GPIO driver. This is the GPIO block from the recent
Socionext (ex Fujitsu and Panasonic) platform.
- Tegra 186 driver. This is based on the new banked GPIO
infrastructure.
Other improvements:
- Some documentation improvements.
- Wakeup support for the DesignWare DWAPB GPIO controller.
- Reset line support on the DesignWare DWAPB GPIO controller.
- Several non-critical bug fixes and improvements for the Broadcom
BRCMSTB driver.
- Misc non-critical bug fixes like exotic errorpaths, removal of dead
code etc.
- Explicit comments on fall-through switch() statements"
* tag 'gpio-v4.15-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (65 commits)
gpio: tegra186: Remove tegra186_gpio_lock_class
gpio: rcar: Add r8a77995 (R-Car D3) support
pinctrl: bcm2835: Fix some merge fallout
gpio: Fix undefined lock_dep_class
gpio: Automatically add lockdep keys
gpio: Introduce struct gpio_irq_chip.first
gpio: Disambiguate struct gpio_irq_chip.nested
gpio: Add Tegra186 support
gpio: Export gpiochip_irq_{map,unmap}()
gpio: Implement tighter IRQ chip integration
gpio: Move lock_key into struct gpio_irq_chip
gpio: Move irq_valid_mask into struct gpio_irq_chip
gpio: Move irq_nested into struct gpio_irq_chip
gpio: Move irq_chained_parent to struct gpio_irq_chip
gpio: Move irq_default_type to struct gpio_irq_chip
gpio: Move irq_handler to struct gpio_irq_chip
gpio: Move irqdomain into struct gpio_irq_chip
gpio: Move irqchip into struct gpio_irq_chip
gpio: Introduce struct gpio_irq_chip
pinctrl: armada-37xx: remove unused variable
...
+3157
-515
+1
-1
Documentation/ABI/obsolete/sysfs-gpio
+1
-1
Documentation/ABI/obsolete/sysfs-gpio
···
11
11
Kernel code may export it for complete or partial access.
12
12
13
13
GPIOs are identified as they are inside the kernel, using integers in
14
-
the range 0..INT_MAX. See Documentation/gpio.txt for more information.
14
+
the range 0..INT_MAX. See Documentation/gpio/gpio.txt for more information.
15
15
16
16
/sys/class/gpio
17
17
/export ... asks the kernel to export a GPIO to userspace
+26
Documentation/devicetree/bindings/common-properties.txt
+26
Documentation/devicetree/bindings/common-properties.txt
···
1
1
Common properties
2
+
=================
3
+
4
+
Endianness
5
+
----------
2
6
3
7
The Devicetree Specification does not define any properties related to hardware
4
8
byteswapping, but endianness issues show up frequently in porting Linux to
···
61
57
reg = <0x40031000 0x1000>;
62
58
...
63
59
little-endian;
60
+
};
61
+
62
+
Daisy-chained devices
63
+
---------------------
64
+
65
+
Many serially-attached GPIO and IIO devices are daisy-chainable. To the
66
+
host controller, a daisy-chain appears as a single device, but the number
67
+
of inputs and outputs it provides is the sum of inputs and outputs provided
68
+
by all of its devices. The driver needs to know how many devices the
69
+
daisy-chain comprises to determine the amount of data exchanged, how many
70
+
inputs and outputs to register and so on.
71
+
72
+
Optional properties:
73
+
- #daisy-chained-devices: Number of devices in the daisy-chain (default is 1).
74
+
75
+
Example:
76
+
gpio@0 {
77
+
compatible = "name";
78
+
reg = <0>;
79
+
gpio-controller;
80
+
#gpio-cells = <2>;
81
+
#daisy-chained-devices = <3>;
64
82
};
+59
Documentation/devicetree/bindings/gpio/gpio-max3191x.txt
+59
Documentation/devicetree/bindings/gpio/gpio-max3191x.txt
···
1
+
GPIO driver for Maxim MAX3191x industrial serializer
2
+
3
+
Required properties:
4
+
- compatible: Must be one of:
5
+
"maxim,max31910"
6
+
"maxim,max31911"
7
+
"maxim,max31912"
8
+
"maxim,max31913"
9
+
"maxim,max31953"
10
+
"maxim,max31963"
11
+
- reg: Chip select number.
12
+
- gpio-controller: Marks the device node as a GPIO controller.
13
+
- #gpio-cells: Should be two. For consumer use see gpio.txt.
14
+
15
+
Optional properties:
16
+
- #daisy-chained-devices:
17
+
Number of chips in the daisy-chain (default is 1).
18
+
- maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
19
+
The number of GPIOs must equal "#daisy-chained-devices"
20
+
(if each chip is driven by a separate pin) or 1
21
+
(if all chips are wired to the same pin).
22
+
- maxim,fault-gpios: GPIO pins to read fault of each chip.
23
+
The number of GPIOs must equal "#daisy-chained-devices"
24
+
or 1.
25
+
- maxim,db0-gpios: GPIO pins to configure debounce of each chip.
26
+
The number of GPIOs must equal "#daisy-chained-devices"
27
+
or 1.
28
+
- maxim,db1-gpios: GPIO pins to configure debounce of each chip.
29
+
The number of GPIOs must equal "maxim,db0-gpios".
30
+
- maxim,modesel-8bit: Boolean whether the modesel pin of the chips is
31
+
pulled high (8-bit mode). Use this if the modesel pin
32
+
is hardwired and consequently "maxim,modesel-gpios"
33
+
cannot be specified. By default if neither this nor
34
+
"maxim,modesel-gpios" is given, the driver assumes
35
+
that modesel is pulled low (16-bit mode).
36
+
- maxim,ignore-undervoltage:
37
+
Boolean whether to ignore undervoltage alarms signaled
38
+
by the "maxim,fault-gpios" or by the status byte
39
+
(in 16-bit mode). Use this if the chips are powered
40
+
through 5VOUT instead of VCC24V, in which case they
41
+
will constantly signal undervoltage.
42
+
43
+
For other required and optional properties of SPI slave nodes please refer to
44
+
../spi/spi-bus.txt.
45
+
46
+
Example:
47
+
gpio@0 {
48
+
compatible = "maxim,max31913";
49
+
reg = <0>;
50
+
gpio-controller;
51
+
#gpio-cells = <2>;
52
+
53
+
maxim,modesel-gpios = <&gpio2 23>;
54
+
maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
55
+
maxim,db0-gpios = <&gpio2 25>;
56
+
maxim,db1-gpios = <&gpio2 26>;
57
+
58
+
spi-max-frequency = <25000000>;
59
+
};
+52
Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
+52
Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
···
1
+
UniPhier GPIO controller
2
+
3
+
Required properties:
4
+
- compatible: Should be "socionext,uniphier-gpio".
5
+
- reg: Specifies offset and length of the register set for the device.
6
+
- gpio-controller: Marks the device node as a GPIO controller.
7
+
- #gpio-cells: Should be 2. The first cell is the pin number and the second
8
+
cell is used to specify optional parameters.
9
+
- interrupt-parent: Specifies the parent interrupt controller.
10
+
- interrupt-controller: Marks the device node as an interrupt controller.
11
+
- #interrupt-cells: Should be 2. The first cell defines the interrupt number.
12
+
The second cell bits[3:0] is used to specify trigger type as follows:
13
+
1 = low-to-high edge triggered
14
+
2 = high-to-low edge triggered
15
+
4 = active high level-sensitive
16
+
8 = active low level-sensitive
17
+
Valid combinations are 1, 2, 3, 4, 8.
18
+
- ngpios: Specifies the number of GPIO lines.
19
+
- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt)
20
+
- socionext,interrupt-ranges: Specifies an interrupt number mapping between
21
+
this GPIO controller and its interrupt parent, in the form of arbitrary
22
+
number of <child-interrupt-base parent-interrupt-base length> triplets.
23
+
24
+
Optional properties:
25
+
- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt)
26
+
27
+
Example:
28
+
gpio: gpio@55000000 {
29
+
compatible = "socionext,uniphier-gpio";
30
+
reg = <0x55000000 0x200>;
31
+
interrupt-parent = <&aidet>;
32
+
interrupt-controller;
33
+
#interrupt-cells = <2>;
34
+
gpio-controller;
35
+
#gpio-cells = <2>;
36
+
gpio-ranges = <&pinctrl 0 0 0>;
37
+
gpio-ranges-group-names = "gpio_range";
38
+
ngpios = <248>;
39
+
socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
40
+
};
41
+
42
+
Consumer Example:
43
+
44
+
sdhci0_pwrseq {
45
+
compatible = "mmc-pwrseq-emmc";
46
+
reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
47
+
};
48
+
49
+
Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document.
50
+
Unfortunately, only the one's place is octal in the port numbering. (That is,
51
+
PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper
52
+
macro to calculate 29 * 8 + 4.
+2
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+2
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
···
14
14
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
15
15
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
16
16
- "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
17
+
- "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller.
18
+
- "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller.
17
19
- "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
18
20
- "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
19
21
- "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
+1
Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
+1
Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
+49
-14
Documentation/gpio/consumer.txt
+49
-14
Documentation/gpio/consumer.txt
···
10
10
==============================
11
11
12
12
Drivers that can't work without standard GPIO calls should have Kconfig entries
13
-
that depend on GPIOLIB. The functions that allow a driver to obtain and use
14
-
GPIOs are available by including the following file:
13
+
that depend on GPIOLIB or select GPIOLIB. The functions that allow a driver to
14
+
obtain and use GPIOs are available by including the following file:
15
15
16
16
#include <linux/gpio/consumer.h>
17
17
18
+
There are static inline stubs for all functions in the header file in the case
19
+
where GPIOLIB is disabled. When these stubs are called they will emit
20
+
warnings. These stubs are used for two use cases:
21
+
22
+
- Simple compile coverage with e.g. COMPILE_TEST - it does not matter that
23
+
the current platform does not enable or select GPIOLIB because we are not
24
+
going to execute the system anyway.
25
+
26
+
- Truly optional GPIOLIB support - where the driver does not really make use
27
+
of the GPIOs on certain compile-time configurations for certain systems, but
28
+
will use it under other compile-time configurations. In this case the
29
+
consumer must make sure not to call into these functions, or the user will
30
+
be met with console warnings that may be perceived as intimidating.
31
+
18
32
All the functions that work with the descriptor-based GPIO interface are
19
33
prefixed with gpiod_. The gpio_ prefix is used for the legacy interface. No
20
-
other function in the kernel should use these prefixes.
34
+
other function in the kernel should use these prefixes. The use of the legacy
35
+
functions is strongly discouraged, new code should use <linux/gpio/consumer.h>
36
+
and descriptors exclusively.
21
37
22
38
23
39
Obtaining and Disposing GPIOs
···
295
279
physical line level and worry about the logical value instead.
296
280
297
281
298
-
Set multiple GPIO outputs with a single function call
299
-
-----------------------------------------------------
300
-
The following functions set the output values of an array of GPIOs:
282
+
Access multiple GPIOs with a single function call
283
+
-------------------------------------------------
284
+
The following functions get or set the values of an array of GPIOs:
285
+
286
+
int gpiod_get_array_value(unsigned int array_size,
287
+
struct gpio_desc **desc_array,
288
+
int *value_array);
289
+
int gpiod_get_raw_array_value(unsigned int array_size,
290
+
struct gpio_desc **desc_array,
291
+
int *value_array);
292
+
int gpiod_get_array_value_cansleep(unsigned int array_size,
293
+
struct gpio_desc **desc_array,
294
+
int *value_array);
295
+
int gpiod_get_raw_array_value_cansleep(unsigned int array_size,
296
+
struct gpio_desc **desc_array,
297
+
int *value_array);
301
298
302
299
void gpiod_set_array_value(unsigned int array_size,
303
300
struct gpio_desc **desc_array,
···
325
296
struct gpio_desc **desc_array,
326
297
int *value_array)
327
298
328
-
The array can be an arbitrary set of GPIOs. The functions will try to set
299
+
The array can be an arbitrary set of GPIOs. The functions will try to access
329
300
GPIOs belonging to the same bank or chip simultaneously if supported by the
330
301
corresponding chip driver. In that case a significantly improved performance
331
-
can be expected. If simultaneous setting is not possible the GPIOs will be set
332
-
sequentially.
302
+
can be expected. If simultaneous access is not possible the GPIOs will be
303
+
accessed sequentially.
333
304
334
-
The gpiod_set_array() functions take three arguments:
305
+
The functions take three arguments:
335
306
* array_size - the number of array elements
336
307
* desc_array - an array of GPIO descriptors
337
-
* value_array - an array of values to assign to the GPIOs
308
+
* value_array - an array to store the GPIOs' values (get) or
309
+
an array of values to assign to the GPIOs (set)
338
310
339
311
The descriptor array can be obtained using the gpiod_get_array() function
340
312
or one of its variants. If the group of descriptors returned by that function
341
-
matches the desired group of GPIOs, those GPIOs can be set by simply using
313
+
matches the desired group of GPIOs, those GPIOs can be accessed by simply using
342
314
the struct gpio_descs returned by gpiod_get_array():
343
315
344
316
struct gpio_descs *my_gpio_descs = gpiod_get_array(...);
345
317
gpiod_set_array_value(my_gpio_descs->ndescs, my_gpio_descs->desc,
346
318
my_gpio_values);
347
319
348
-
It is also possible to set a completely arbitrary array of descriptors. The
320
+
It is also possible to access a completely arbitrary array of descriptors. The
349
321
descriptors may be obtained using any combination of gpiod_get() and
350
322
gpiod_get_array(). Afterwards the array of descriptors has to be setup
351
-
manually before it can be used with gpiod_set_array().
323
+
manually before it can be passed to one of the above functions.
352
324
353
325
Note that for optimal performance GPIOs belonging to the same chip should be
354
326
contiguous within the array of descriptors.
327
+
328
+
The return value of gpiod_get_array_value() and its variants is 0 on success
329
+
or negative on error. Note the difference to gpiod_get_value(), which returns
330
+
0 or 1 on success to convey the GPIO value. With the array functions, the GPIO
331
+
values are stored in value_array rather than passed back as return value.
355
332
356
333
357
334
GPIOs mapped to IRQs
+3
-3
Documentation/gpio/driver.txt
+3
-3
Documentation/gpio/driver.txt
···
254
254
static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
255
255
unsigned long wa_lock_flags;
256
256
raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
257
-
generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, bit));
257
+
generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, bit));
258
258
raw_spin_unlock_irqrestore(&bank->wa_lock, wa_lock_flags);
259
259
260
260
* GENERIC CHAINED GPIO irqchips: these are the same as "CHAINED GPIO irqchips",
···
313
313
mark all the child IRQs as having the other IRQ as parent.
314
314
315
315
If there is a need to exclude certain GPIOs from the IRQ domain, you can
316
-
set .irq_need_valid_mask of the gpiochip before gpiochip_add_data() is
317
-
called. This allocates an .irq_valid_mask with as many bits set as there
316
+
set .irq.need_valid_mask of the gpiochip before gpiochip_add_data() is
317
+
called. This allocates an .irq.valid_mask with as many bits set as there
318
318
are GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this
319
319
mask. The mask must be filled in before gpiochip_irqchip_add() or
320
320
gpiochip_irqchip_add_nested() is called.
+9
MAINTAINERS
+9
MAINTAINERS
···
2029
2029
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2030
2030
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
2031
2031
S: Maintained
2032
+
F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
2032
2033
F: arch/arm/boot/dts/uniphier*
2033
2034
F: arch/arm/include/asm/hardware/cache-uniphier.h
2034
2035
F: arch/arm/mach-uniphier/
···
2037
2036
F: arch/arm64/boot/dts/socionext/
2038
2037
F: drivers/bus/uniphier-system-bus.c
2039
2038
F: drivers/clk/uniphier/
2039
+
F: drivers/gpio/gpio-uniphier.c
2040
2040
F: drivers/i2c/busses/i2c-uniphier*
2041
2041
F: drivers/irqchip/irq-uniphier-aidet.c
2042
2042
F: drivers/pinctrl/uniphier/
···
12946
12944
F: arch/arc/plat-axs10x
12947
12945
F: arch/arc/boot/dts/ax*
12948
12946
F: Documentation/devicetree/bindings/arc/axs10*
12947
+
12948
+
SYNOPSYS DESIGNWARE APB GPIO DRIVER
12949
+
M: Hoan Tran <hotran@apm.com>
12950
+
L: linux-gpio@vger.kernel.org
12951
+
S: Maintained
12952
+
F: drivers/gpio/gpio-dwapb.c
12953
+
F: Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
12949
12954
12950
12955
SYNOPSYS DESIGNWARE DMAC DRIVER
12951
12956
M: Viresh Kumar <vireshk@kernel.org>
+1
-1
drivers/bcma/driver_gpio.c
+1
-1
drivers/bcma/driver_gpio.c
···
113
113
return IRQ_NONE;
114
114
115
115
for_each_set_bit(gpio, &irqs, gc->ngpio)
116
-
generic_handle_irq(irq_find_mapping(gc->irqdomain, gpio));
116
+
generic_handle_irq(irq_find_mapping(gc->irq.domain, gpio));
117
117
bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
118
118
119
119
return IRQ_HANDLED;
+29
-3
drivers/gpio/Kconfig
+29
-3
drivers/gpio/Kconfig
···
139
139
default y if (ARCH_BRCMSTB || BMIPS_GENERIC)
140
140
depends on OF_GPIO && (ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST)
141
141
select GPIO_GENERIC
142
-
select GPIOLIB_IRQCHIP
142
+
select IRQ_DOMAIN
143
143
help
144
144
Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
145
145
···
286
286
Requires ACPI device enumeration code to set up a platform device.
287
287
288
288
config GPIO_MB86S7X
289
-
bool "GPIO support for Fujitsu MB86S7x Platforms"
290
-
depends on ARCH_MB86S7X || COMPILE_TEST
289
+
tristate "GPIO support for Fujitsu MB86S7x Platforms"
291
290
help
292
291
Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs.
293
292
···
441
442
help
442
443
Say yes here to support GPIO pins on NVIDIA Tegra SoCs.
443
444
445
+
config GPIO_TEGRA186
446
+
tristate "NVIDIA Tegra186 GPIO support"
447
+
default ARCH_TEGRA_186_SOC
448
+
depends on ARCH_TEGRA_186_SOC || COMPILE_TEST
449
+
depends on OF_GPIO
450
+
select GPIOLIB_IRQCHIP
451
+
help
452
+
Say yes here to support GPIO pins on NVIDIA Tegra186 SoCs.
453
+
444
454
config GPIO_TS4800
445
455
tristate "TS-4800 DIO blocks and compatibles"
446
456
depends on OF_GPIO
···
482
474
default y
483
475
help
484
476
Say yes here to support Toumaz Xenif TZ1090 PDC GPIOs.
477
+
478
+
config GPIO_UNIPHIER
479
+
tristate "UniPhier GPIO support"
480
+
depends on ARCH_UNIPHIER || COMPILE_TEST
481
+
depends on OF_GPIO
482
+
select IRQ_DOMAIN_HIERARCHY
483
+
help
484
+
Say yes here to support UniPhier GPIOs.
485
485
486
486
config GPIO_VF610
487
487
def_bool y
···
1271
1255
Driver for 74x164 compatible serial-in/parallel-out 8-outputs
1272
1256
shift registers. This driver can be used to provide access
1273
1257
to more gpio outputs.
1258
+
1259
+
config GPIO_MAX3191X
1260
+
tristate "Maxim MAX3191x industrial serializer"
1261
+
select CRC8
1262
+
help
1263
+
GPIO driver for Maxim MAX31910, MAX31911, MAX31912, MAX31913,
1264
+
MAX31953 and MAX31963 industrial serializer, a daisy-chainable
1265
+
chip to make 8 digital 24V inputs available via SPI. Supports
1266
+
CRC checksums to guard against electromagnetic interference,
1267
+
as well as undervoltage and overtemperature detection.
1274
1268
1275
1269
config GPIO_MAX7301
1276
1270
tristate "Maxim MAX7301 GPIO expander"
+3
drivers/gpio/Makefile
+3
drivers/gpio/Makefile
···
70
70
obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
71
71
obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
72
72
obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
73
+
obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
73
74
obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o
74
75
obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
75
76
obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
···
115
114
obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o
116
115
obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
117
116
obj-$(CONFIG_GPIO_TEGRA) += gpio-tegra.o
117
+
obj-$(CONFIG_GPIO_TEGRA186) += gpio-tegra186.o
118
118
obj-$(CONFIG_GPIO_THUNDERX) += gpio-thunderx.o
119
119
obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o
120
120
obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o
···
134
132
obj-$(CONFIG_GPIO_TZ1090) += gpio-tz1090.o
135
133
obj-$(CONFIG_GPIO_TZ1090_PDC) += gpio-tz1090-pdc.o
136
134
obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o
135
+
obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o
137
136
obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o
138
137
obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o
139
138
obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o
+1
-1
drivers/gpio/gpio-104-dio-48e.c
+1
-1
drivers/gpio/gpio-104-dio-48e.c
+1
-1
drivers/gpio/gpio-104-idi-48.c
+1
-1
drivers/gpio/gpio-104-idi-48.c
+1
-1
drivers/gpio/gpio-104-idio-16.c
+1
-1
drivers/gpio/gpio-104-idio-16.c
+14
-17
drivers/gpio/gpio-adnp.c
+14
-17
drivers/gpio/gpio-adnp.c
···
192
192
mutex_lock(&adnp->i2c_lock);
193
193
194
194
err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
195
-
if (err < 0) {
196
-
mutex_unlock(&adnp->i2c_lock);
197
-
return;
198
-
}
195
+
if (err < 0)
196
+
goto unlock;
199
197
200
198
err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
201
-
if (err < 0) {
202
-
mutex_unlock(&adnp->i2c_lock);
203
-
return;
204
-
}
199
+
if (err < 0)
200
+
goto unlock;
205
201
206
202
err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
207
-
if (err < 0) {
208
-
mutex_unlock(&adnp->i2c_lock);
209
-
return;
210
-
}
203
+
if (err < 0)
204
+
goto unlock;
211
205
212
206
err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
213
-
if (err < 0) {
214
-
mutex_unlock(&adnp->i2c_lock);
215
-
return;
216
-
}
207
+
if (err < 0)
208
+
goto unlock;
217
209
218
210
mutex_unlock(&adnp->i2c_lock);
219
211
···
232
240
direction, level, interrupt, pending);
233
241
}
234
242
}
243
+
244
+
return;
245
+
246
+
unlock:
247
+
mutex_unlock(&adnp->i2c_lock);
235
248
}
236
249
237
250
static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
···
320
323
321
324
for_each_set_bit(bit, &pending, 8) {
322
325
unsigned int child_irq;
323
-
child_irq = irq_find_mapping(adnp->gpio.irqdomain,
326
+
child_irq = irq_find_mapping(adnp->gpio.irq.domain,
324
327
base + bit);
325
328
handle_nested_irq(child_irq);
326
329
}
+2
-2
drivers/gpio/gpio-altera.c
+2
-2
drivers/gpio/gpio-altera.c
···
211
211
altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
212
212
chip = irq_desc_get_chip(desc);
213
213
mm_gc = &altera_gc->mmchip;
214
-
irqdomain = altera_gc->mmchip.gc.irqdomain;
214
+
irqdomain = altera_gc->mmchip.gc.irq.domain;
215
215
216
216
chained_irq_enter(chip, desc);
217
217
···
239
239
altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
240
240
chip = irq_desc_get_chip(desc);
241
241
mm_gc = &altera_gc->mmchip;
242
-
irqdomain = altera_gc->mmchip.gc.irqdomain;
242
+
irqdomain = altera_gc->mmchip.gc.irq.domain;
243
243
244
244
chained_irq_enter(chip, desc);
245
245
+6
-3
drivers/gpio/gpio-aspeed.c
+6
-3
drivers/gpio/gpio-aspeed.c
···
411
411
switch (type & IRQ_TYPE_SENSE_MASK) {
412
412
case IRQ_TYPE_EDGE_BOTH:
413
413
type2 |= bit;
414
+
/* fall through */
414
415
case IRQ_TYPE_EDGE_RISING:
415
416
type0 |= bit;
417
+
/* fall through */
416
418
case IRQ_TYPE_EDGE_FALLING:
417
419
handler = handle_edge_irq;
418
420
break;
419
421
case IRQ_TYPE_LEVEL_HIGH:
420
422
type0 |= bit;
423
+
/* fall through */
421
424
case IRQ_TYPE_LEVEL_LOW:
422
425
type1 |= bit;
423
426
handler = handle_level_irq;
···
469
466
reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS));
470
467
471
468
for_each_set_bit(p, ®, 32) {
472
-
girq = irq_find_mapping(gc->irqdomain, i * 32 + p);
469
+
girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
473
470
generic_handle_irq(girq);
474
471
}
475
472
···
501
498
if (i >= gpio->config->nr_gpios)
502
499
break;
503
500
504
-
clear_bit(i, gpio->chip.irq_valid_mask);
501
+
clear_bit(i, gpio->chip.irq.valid_mask);
505
502
}
506
503
507
504
props++;
···
856
853
gpio->chip.set_config = aspeed_gpio_set_config;
857
854
gpio->chip.label = dev_name(&pdev->dev);
858
855
gpio->chip.base = -1;
859
-
gpio->chip.irq_need_valid_mask = true;
856
+
gpio->chip.irq.need_valid_mask = true;
860
857
861
858
rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
862
859
if (rc < 0)
+2
-1
drivers/gpio/gpio-ath79.c
+2
-1
drivers/gpio/gpio-ath79.c
···
132
132
133
133
case IRQ_TYPE_LEVEL_HIGH:
134
134
polarity |= mask;
135
+
/* fall through */
135
136
case IRQ_TYPE_LEVEL_LOW:
136
137
type |= mask;
137
138
break;
···
209
208
if (pending) {
210
209
for_each_set_bit(irq, &pending, gc->ngpio)
211
210
generic_handle_irq(
212
-
irq_linear_revmap(gc->irqdomain, irq));
211
+
irq_linear_revmap(gc->irq.domain, irq));
213
212
}
214
213
215
214
chained_irq_exit(irqchip, desc);
+322
-98
drivers/gpio/gpio-brcmstb.c
+322
-98
drivers/gpio/gpio-brcmstb.c
···
1
1
/*
2
-
* Copyright (C) 2015 Broadcom Corporation
2
+
* Copyright (C) 2015-2017 Broadcom
3
3
*
4
4
* This program is free software; you can redistribute it and/or
5
5
* modify it under the terms of the GNU General Public License as
···
19
19
#include <linux/irqdomain.h>
20
20
#include <linux/irqchip/chained_irq.h>
21
21
#include <linux/interrupt.h>
22
-
#include <linux/reboot.h>
22
+
#include <linux/bitops.h>
23
23
24
-
#define GIO_BANK_SIZE 0x20
25
-
#define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
26
-
#define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
27
-
#define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
28
-
#define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
29
-
#define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
30
-
#define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
31
-
#define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
32
-
#define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
24
+
enum gio_reg_index {
25
+
GIO_REG_ODEN = 0,
26
+
GIO_REG_DATA,
27
+
GIO_REG_IODIR,
28
+
GIO_REG_EC,
29
+
GIO_REG_EI,
30
+
GIO_REG_MASK,
31
+
GIO_REG_LEVEL,
32
+
GIO_REG_STAT,
33
+
NUMBER_OF_GIO_REGISTERS
34
+
};
35
+
36
+
#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
37
+
#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
38
+
#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
39
+
#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
40
+
#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
41
+
#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
42
+
#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
43
+
#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
44
+
#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
45
+
#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
33
46
34
47
struct brcmstb_gpio_bank {
35
48
struct list_head node;
···
50
37
struct gpio_chip gc;
51
38
struct brcmstb_gpio_priv *parent_priv;
52
39
u32 width;
53
-
struct irq_chip irq_chip;
40
+
u32 wake_active;
41
+
u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
54
42
};
55
43
56
44
struct brcmstb_gpio_priv {
57
45
struct list_head bank_list;
58
46
void __iomem *reg_base;
59
47
struct platform_device *pdev;
48
+
struct irq_domain *irq_domain;
49
+
struct irq_chip irq_chip;
60
50
int parent_irq;
61
51
int gpio_base;
62
-
bool can_wake;
52
+
int num_gpios;
63
53
int parent_wake_irq;
64
-
struct notifier_block reboot_notifier;
65
54
};
66
55
67
-
#define MAX_GPIO_PER_BANK 32
56
+
#define MAX_GPIO_PER_BANK 32
68
57
#define GPIO_BANK(gpio) ((gpio) >> 5)
69
58
/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
70
59
#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
···
78
63
return bank->parent_priv;
79
64
}
80
65
66
+
static unsigned long
67
+
__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
68
+
{
69
+
void __iomem *reg_base = bank->parent_priv->reg_base;
70
+
71
+
return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
72
+
bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
73
+
}
74
+
75
+
static unsigned long
76
+
brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
77
+
{
78
+
unsigned long status;
79
+
unsigned long flags;
80
+
81
+
spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
82
+
status = __brcmstb_gpio_get_active_irqs(bank);
83
+
spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
84
+
85
+
return status;
86
+
}
87
+
88
+
static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
89
+
struct brcmstb_gpio_bank *bank)
90
+
{
91
+
return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
92
+
}
93
+
81
94
static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
82
-
unsigned int offset, bool enable)
95
+
unsigned int hwirq, bool enable)
83
96
{
84
97
struct gpio_chip *gc = &bank->gc;
85
98
struct brcmstb_gpio_priv *priv = bank->parent_priv;
86
-
u32 mask = gc->pin2mask(gc, offset);
99
+
u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
87
100
u32 imask;
88
101
unsigned long flags;
89
102
···
123
80
imask &= ~mask;
124
81
gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
125
82
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
83
+
}
84
+
85
+
static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
86
+
{
87
+
struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
88
+
/* gc_offset is relative to this gpio_chip; want real offset */
89
+
int hwirq = offset + (gc->base - priv->gpio_base);
90
+
91
+
if (hwirq >= priv->num_gpios)
92
+
return -ENXIO;
93
+
return irq_create_mapping(priv->irq_domain, hwirq);
126
94
}
127
95
128
96
/* -------------------- IRQ chip functions -------------------- */
···
154
100
brcmstb_gpio_set_imask(bank, d->hwirq, true);
155
101
}
156
102
103
+
static void brcmstb_gpio_irq_ack(struct irq_data *d)
104
+
{
105
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
106
+
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
107
+
struct brcmstb_gpio_priv *priv = bank->parent_priv;
108
+
u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
109
+
110
+
gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
111
+
}
112
+
157
113
static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
158
114
{
159
115
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
160
116
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
161
117
struct brcmstb_gpio_priv *priv = bank->parent_priv;
162
-
u32 mask = BIT(d->hwirq);
118
+
u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
163
119
u32 edge_insensitive, iedge_insensitive;
164
120
u32 edge_config, iedge_config;
165
121
u32 level, ilevel;
···
177
113
178
114
switch (type) {
179
115
case IRQ_TYPE_LEVEL_LOW:
180
-
level = 0;
116
+
level = mask;
181
117
edge_config = 0;
182
118
edge_insensitive = 0;
183
119
break;
184
120
case IRQ_TYPE_LEVEL_HIGH:
185
121
level = mask;
186
-
edge_config = 0;
122
+
edge_config = mask;
187
123
edge_insensitive = 0;
188
124
break;
189
125
case IRQ_TYPE_EDGE_FALLING:
···
230
166
{
231
167
int ret = 0;
232
168
233
-
/*
234
-
* Only enable wake IRQ once for however many hwirqs can wake
235
-
* since they all use the same wake IRQ. Mask will be set
236
-
* up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
237
-
*/
238
169
if (enable)
239
170
ret = enable_irq_wake(priv->parent_wake_irq);
240
171
else
···
243
184
static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
244
185
{
245
186
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
246
-
struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
187
+
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
188
+
struct brcmstb_gpio_priv *priv = bank->parent_priv;
189
+
u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
190
+
191
+
/*
192
+
* Do not do anything specific for now, suspend/resume callbacks will
193
+
* configure the interrupt mask appropriately
194
+
*/
195
+
if (enable)
196
+
bank->wake_active |= mask;
197
+
else
198
+
bank->wake_active &= ~mask;
247
199
248
200
return brcmstb_gpio_priv_set_wake(priv, enable);
249
201
}
···
265
195
266
196
if (!priv || irq != priv->parent_wake_irq)
267
197
return IRQ_NONE;
268
-
pm_wakeup_event(&priv->pdev->dev, 0);
198
+
199
+
/* Nothing to do */
269
200
return IRQ_HANDLED;
270
201
}
271
202
272
203
static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
273
204
{
274
205
struct brcmstb_gpio_priv *priv = bank->parent_priv;
275
-
struct irq_domain *irq_domain = bank->gc.irqdomain;
276
-
void __iomem *reg_base = priv->reg_base;
206
+
struct irq_domain *domain = priv->irq_domain;
207
+
int hwbase = bank->gc.base - priv->gpio_base;
277
208
unsigned long status;
278
-
unsigned long flags;
279
209
280
-
spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
281
-
while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
282
-
bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
283
-
int bit;
210
+
while ((status = brcmstb_gpio_get_active_irqs(bank))) {
211
+
unsigned int irq, offset;
284
212
285
-
for_each_set_bit(bit, &status, 32) {
286
-
u32 stat = bank->gc.read_reg(reg_base +
287
-
GIO_STAT(bank->id));
288
-
if (bit >= bank->width)
213
+
for_each_set_bit(offset, &status, 32) {
214
+
if (offset >= bank->width)
289
215
dev_warn(&priv->pdev->dev,
290
216
"IRQ for invalid GPIO (bank=%d, offset=%d)\n",
291
-
bank->id, bit);
292
-
bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
293
-
stat | BIT(bit));
294
-
generic_handle_irq(irq_find_mapping(irq_domain, bit));
217
+
bank->id, offset);
218
+
irq = irq_linear_revmap(domain, hwbase + offset);
219
+
generic_handle_irq(irq);
295
220
}
296
221
}
297
-
spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
298
222
}
299
223
300
224
/* Each UPG GIO block has one IRQ for all banks */
301
225
static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
302
226
{
303
-
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
304
-
struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
227
+
struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
305
228
struct irq_chip *chip = irq_desc_get_chip(desc);
306
229
struct brcmstb_gpio_bank *bank;
307
230
···
307
244
chained_irq_exit(chip, desc);
308
245
}
309
246
310
-
static int brcmstb_gpio_reboot(struct notifier_block *nb,
311
-
unsigned long action, void *data)
247
+
static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
248
+
struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
312
249
{
313
-
struct brcmstb_gpio_priv *priv =
314
-
container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
250
+
struct brcmstb_gpio_bank *bank;
251
+
int i = 0;
315
252
316
-
/* Enable GPIO for S5 cold boot */
317
-
if (action == SYS_POWER_OFF)
318
-
brcmstb_gpio_priv_set_wake(priv, 1);
319
-
320
-
return NOTIFY_DONE;
253
+
/* banks are in descending order */
254
+
list_for_each_entry_reverse(bank, &priv->bank_list, node) {
255
+
i += bank->gc.ngpio;
256
+
if (hwirq < i)
257
+
return bank;
258
+
}
259
+
return NULL;
321
260
}
261
+
262
+
/*
263
+
* This lock class tells lockdep that GPIO irqs are in a different
264
+
* category than their parents, so it won't report false recursion.
265
+
*/
266
+
static struct lock_class_key brcmstb_gpio_irq_lock_class;
267
+
268
+
269
+
static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
270
+
irq_hw_number_t hwirq)
271
+
{
272
+
struct brcmstb_gpio_priv *priv = d->host_data;
273
+
struct brcmstb_gpio_bank *bank =
274
+
brcmstb_gpio_hwirq_to_bank(priv, hwirq);
275
+
struct platform_device *pdev = priv->pdev;
276
+
int ret;
277
+
278
+
if (!bank)
279
+
return -EINVAL;
280
+
281
+
dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
282
+
irq, (int)hwirq, bank->id);
283
+
ret = irq_set_chip_data(irq, &bank->gc);
284
+
if (ret < 0)
285
+
return ret;
286
+
irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class);
287
+
irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
288
+
irq_set_noprobe(irq);
289
+
return 0;
290
+
}
291
+
292
+
static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
293
+
{
294
+
irq_set_chip_and_handler(irq, NULL, NULL);
295
+
irq_set_chip_data(irq, NULL);
296
+
}
297
+
298
+
static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
299
+
.map = brcmstb_gpio_irq_map,
300
+
.unmap = brcmstb_gpio_irq_unmap,
301
+
.xlate = irq_domain_xlate_twocell,
302
+
};
322
303
323
304
/* Make sure that the number of banks matches up between properties */
324
305
static int brcmstb_gpio_sanity_check_banks(struct device *dev,
···
385
278
{
386
279
struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
387
280
struct brcmstb_gpio_bank *bank;
388
-
int ret = 0;
281
+
int offset, ret = 0, virq;
389
282
390
283
if (!priv) {
391
284
dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
392
285
return -EFAULT;
286
+
}
287
+
288
+
if (priv->parent_irq > 0)
289
+
irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
290
+
291
+
/* Remove all IRQ mappings and delete the domain */
292
+
if (priv->irq_domain) {
293
+
for (offset = 0; offset < priv->num_gpios; offset++) {
294
+
virq = irq_find_mapping(priv->irq_domain, offset);
295
+
irq_dispose_mapping(virq);
296
+
}
297
+
irq_domain_remove(priv->irq_domain);
393
298
}
394
299
395
300
/*
···
411
292
list_for_each_entry(bank, &priv->bank_list, node)
412
293
gpiochip_remove(&bank->gc);
413
294
414
-
if (priv->reboot_notifier.notifier_call) {
415
-
ret = unregister_reboot_notifier(&priv->reboot_notifier);
416
-
if (ret)
417
-
dev_err(&pdev->dev,
418
-
"failed to unregister reboot notifier\n");
419
-
}
420
295
return ret;
421
296
}
422
297
···
445
332
return offset;
446
333
}
447
334
448
-
/* Before calling, must have bank->parent_irq set and gpiochip registered */
335
+
/* priv->parent_irq and priv->num_gpios must be set before calling */
449
336
static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
450
-
struct brcmstb_gpio_bank *bank)
337
+
struct brcmstb_gpio_priv *priv)
451
338
{
452
-
struct brcmstb_gpio_priv *priv = bank->parent_priv;
453
339
struct device *dev = &pdev->dev;
454
340
struct device_node *np = dev->of_node;
455
341
int err;
456
342
457
-
bank->irq_chip.name = dev_name(dev);
458
-
bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
459
-
bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
460
-
bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
343
+
priv->irq_domain =
344
+
irq_domain_add_linear(np, priv->num_gpios,
345
+
&brcmstb_gpio_irq_domain_ops,
346
+
priv);
347
+
if (!priv->irq_domain) {
348
+
dev_err(dev, "Couldn't allocate IRQ domain\n");
349
+
return -ENXIO;
350
+
}
461
351
462
-
/* Ensures that all non-wakeup IRQs are disabled at suspend */
463
-
bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
464
-
465
-
if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
466
-
of_property_read_bool(np, "wakeup-source")) {
352
+
if (of_property_read_bool(np, "wakeup-source")) {
467
353
priv->parent_wake_irq = platform_get_irq(pdev, 1);
468
354
if (priv->parent_wake_irq < 0) {
355
+
priv->parent_wake_irq = 0;
469
356
dev_warn(dev,
470
357
"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
471
358
} else {
472
359
/*
473
-
* Set wakeup capability before requesting wakeup
474
-
* interrupt, so we can process boot-time "wakeups"
475
-
* (e.g., from S5 cold boot)
360
+
* Set wakeup capability so we can process boot-time
361
+
* "wakeups" (e.g., from S5 cold boot)
476
362
*/
477
363
device_set_wakeup_capable(dev, true);
478
364
device_wakeup_enable(dev);
479
365
err = devm_request_irq(dev, priv->parent_wake_irq,
480
-
brcmstb_gpio_wake_irq_handler, 0,
481
-
"brcmstb-gpio-wake", priv);
366
+
brcmstb_gpio_wake_irq_handler,
367
+
IRQF_SHARED,
368
+
"brcmstb-gpio-wake", priv);
482
369
483
370
if (err < 0) {
484
371
dev_err(dev, "Couldn't request wake IRQ");
485
-
return err;
372
+
goto out_free_domain;
486
373
}
487
-
488
-
priv->reboot_notifier.notifier_call =
489
-
brcmstb_gpio_reboot;
490
-
register_reboot_notifier(&priv->reboot_notifier);
491
-
priv->can_wake = true;
492
374
}
493
375
}
494
376
495
-
if (priv->can_wake)
496
-
bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
377
+
priv->irq_chip.name = dev_name(dev);
378
+
priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
379
+
priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
380
+
priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
381
+
priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
382
+
priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
497
383
498
-
err = gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
499
-
handle_simple_irq, IRQ_TYPE_NONE);
500
-
if (err)
501
-
return err;
502
-
gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
503
-
priv->parent_irq, brcmstb_gpio_irq_handler);
384
+
if (priv->parent_wake_irq)
385
+
priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
386
+
387
+
irq_set_chained_handler_and_data(priv->parent_irq,
388
+
brcmstb_gpio_irq_handler, priv);
389
+
irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
390
+
391
+
return 0;
392
+
393
+
out_free_domain:
394
+
irq_domain_remove(priv->irq_domain);
395
+
396
+
return err;
397
+
}
398
+
399
+
static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
400
+
struct brcmstb_gpio_bank *bank)
401
+
{
402
+
struct gpio_chip *gc = &bank->gc;
403
+
unsigned int i;
404
+
405
+
for (i = 0; i < GIO_REG_STAT; i++)
406
+
bank->saved_regs[i] = gc->read_reg(priv->reg_base +
407
+
GIO_BANK_OFF(bank->id, i));
408
+
}
409
+
410
+
static void brcmstb_gpio_quiesce(struct device *dev, bool save)
411
+
{
412
+
struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
413
+
struct brcmstb_gpio_bank *bank;
414
+
struct gpio_chip *gc;
415
+
u32 imask;
416
+
417
+
/* disable non-wake interrupt */
418
+
if (priv->parent_irq >= 0)
419
+
disable_irq(priv->parent_irq);
420
+
421
+
list_for_each_entry(bank, &priv->bank_list, node) {
422
+
gc = &bank->gc;
423
+
424
+
if (save)
425
+
brcmstb_gpio_bank_save(priv, bank);
426
+
427
+
/* Unmask GPIOs which have been flagged as wake-up sources */
428
+
if (priv->parent_wake_irq)
429
+
imask = bank->wake_active;
430
+
else
431
+
imask = 0;
432
+
gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
433
+
imask);
434
+
}
435
+
}
436
+
437
+
static void brcmstb_gpio_shutdown(struct platform_device *pdev)
438
+
{
439
+
/* Enable GPIO for S5 cold boot */
440
+
brcmstb_gpio_quiesce(&pdev->dev, false);
441
+
}
442
+
443
+
#ifdef CONFIG_PM_SLEEP
444
+
static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
445
+
struct brcmstb_gpio_bank *bank)
446
+
{
447
+
struct gpio_chip *gc = &bank->gc;
448
+
unsigned int i;
449
+
450
+
for (i = 0; i < GIO_REG_STAT; i++)
451
+
gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
452
+
bank->saved_regs[i]);
453
+
}
454
+
455
+
static int brcmstb_gpio_suspend(struct device *dev)
456
+
{
457
+
brcmstb_gpio_quiesce(dev, true);
458
+
return 0;
459
+
}
460
+
461
+
static int brcmstb_gpio_resume(struct device *dev)
462
+
{
463
+
struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
464
+
struct brcmstb_gpio_bank *bank;
465
+
bool need_wakeup_event = false;
466
+
467
+
list_for_each_entry(bank, &priv->bank_list, node) {
468
+
need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
469
+
brcmstb_gpio_bank_restore(priv, bank);
470
+
}
471
+
472
+
if (priv->parent_wake_irq && need_wakeup_event)
473
+
pm_wakeup_event(dev, 0);
474
+
475
+
/* enable non-wake interrupt */
476
+
if (priv->parent_irq >= 0)
477
+
enable_irq(priv->parent_irq);
504
478
505
479
return 0;
506
480
}
481
+
482
+
#else
483
+
#define brcmstb_gpio_suspend NULL
484
+
#define brcmstb_gpio_resume NULL
485
+
#endif /* CONFIG_PM_SLEEP */
486
+
487
+
static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
488
+
.suspend_noirq = brcmstb_gpio_suspend,
489
+
.resume_noirq = brcmstb_gpio_resume,
490
+
};
507
491
508
492
static int brcmstb_gpio_probe(struct platform_device *pdev)
509
493
{
···
616
406
int err;
617
407
static int gpio_base;
618
408
unsigned long flags = 0;
409
+
bool need_wakeup_event = false;
619
410
620
411
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
621
412
if (!priv)
···
696
485
gc->of_node = np;
697
486
gc->owner = THIS_MODULE;
698
487
gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
488
+
if (!gc->label) {
489
+
err = -ENOMEM;
490
+
goto fail;
491
+
}
699
492
gc->base = gpio_base;
700
493
gc->of_gpio_n_cells = 2;
701
494
gc->of_xlate = brcmstb_gpio_of_xlate;
702
495
/* not all ngpio lines are valid, will use bank width later */
703
496
gc->ngpio = MAX_GPIO_PER_BANK;
497
+
if (priv->parent_irq > 0)
498
+
gc->to_irq = brcmstb_gpio_to_irq;
704
499
705
500
/*
706
501
* Mask all interrupts by default, since wakeup interrupts may
707
502
* be retained from S5 cold boot
708
503
*/
504
+
need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
709
505
gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
710
506
711
507
err = gpiochip_add_data(gc, bank);
···
723
505
}
724
506
gpio_base += gc->ngpio;
725
507
726
-
if (priv->parent_irq > 0) {
727
-
err = brcmstb_gpio_irq_setup(pdev, bank);
728
-
if (err)
729
-
goto fail;
730
-
}
731
-
732
508
dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
733
509
gc->base, gc->ngpio, bank->width);
734
510
···
732
520
num_banks++;
733
521
}
734
522
523
+
priv->num_gpios = gpio_base - priv->gpio_base;
524
+
if (priv->parent_irq > 0) {
525
+
err = brcmstb_gpio_irq_setup(pdev, priv);
526
+
if (err)
527
+
goto fail;
528
+
}
529
+
735
530
dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
736
531
num_banks, priv->gpio_base, gpio_base - 1);
532
+
533
+
if (priv->parent_wake_irq && need_wakeup_event)
534
+
pm_wakeup_event(dev, 0);
737
535
738
536
return 0;
739
537
···
763
541
.driver = {
764
542
.name = "brcmstb-gpio",
765
543
.of_match_table = brcmstb_gpio_of_match,
544
+
.pm = &brcmstb_gpio_pm_ops,
766
545
},
767
546
.probe = brcmstb_gpio_probe,
768
547
.remove = brcmstb_gpio_remove,
548
+
.shutdown = brcmstb_gpio_shutdown,
769
549
};
770
550
module_platform_driver(brcmstb_gpio_driver);
771
551
+1
-1
drivers/gpio/gpio-crystalcove.c
+1
-1
drivers/gpio/gpio-crystalcove.c
+1
-1
drivers/gpio/gpio-dln2.c
+1
-1
drivers/gpio/gpio-dln2.c
+33
-3
drivers/gpio/gpio-dwapb.c
+33
-3
drivers/gpio/gpio-dwapb.c
···
25
25
#include <linux/of_irq.h>
26
26
#include <linux/platform_device.h>
27
27
#include <linux/property.h>
28
+
#include <linux/reset.h>
28
29
#include <linux/spinlock.h>
29
30
#include <linux/platform_data/gpio-dwapb.h>
30
31
#include <linux/slab.h>
···
78
77
u32 int_type;
79
78
u32 int_pol;
80
79
u32 int_deb;
80
+
u32 wake_en;
81
81
};
82
82
#endif
83
83
···
99
97
unsigned int nr_ports;
100
98
struct irq_domain *domain;
101
99
unsigned int flags;
100
+
struct reset_control *rst;
102
101
};
103
102
104
103
static inline u32 gpio_reg_v2_convert(unsigned int offset)
···
298
295
return 0;
299
296
}
300
297
298
+
#ifdef CONFIG_PM_SLEEP
299
+
static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
300
+
{
301
+
struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
302
+
struct dwapb_gpio *gpio = igc->private;
303
+
struct dwapb_context *ctx = gpio->ports[0].ctx;
304
+
305
+
if (enable)
306
+
ctx->wake_en |= BIT(d->hwirq);
307
+
else
308
+
ctx->wake_en &= ~BIT(d->hwirq);
309
+
310
+
return 0;
311
+
}
312
+
#endif
313
+
301
314
static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
302
315
unsigned offset, unsigned debounce)
303
316
{
304
317
struct dwapb_gpio_port *port = gpiochip_get_data(gc);
305
318
struct dwapb_gpio *gpio = port->gpio;
306
319
unsigned long flags, val_deb;
307
-
unsigned long mask = gc->pin2mask(gc, offset);
320
+
unsigned long mask = BIT(offset);
308
321
309
322
spin_lock_irqsave(&gc->bgpio_lock, flags);
310
323
···
404
385
ct->chip.irq_disable = dwapb_irq_disable;
405
386
ct->chip.irq_request_resources = dwapb_irq_reqres;
406
387
ct->chip.irq_release_resources = dwapb_irq_relres;
388
+
#ifdef CONFIG_PM_SLEEP
389
+
ct->chip.irq_set_wake = dwapb_irq_set_wake;
390
+
#endif
407
391
ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
408
392
ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
409
393
ct->type = IRQ_TYPE_LEVEL_MASK;
···
482
460
(pp->idx * GPIO_SWPORT_DDR_SIZE);
483
461
484
462
err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
485
-
NULL, false);
463
+
NULL, 0);
486
464
if (err) {
487
465
dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
488
466
port->idx);
···
631
609
gpio->dev = &pdev->dev;
632
610
gpio->nr_ports = pdata->nports;
633
611
612
+
gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
613
+
if (IS_ERR(gpio->rst))
614
+
return PTR_ERR(gpio->rst);
615
+
616
+
reset_control_deassert(gpio->rst);
617
+
634
618
gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
635
619
sizeof(*gpio->ports), GFP_KERNEL);
636
620
if (!gpio->ports)
···
688
660
689
661
dwapb_gpio_unregister(gpio);
690
662
dwapb_irq_teardown(gpio);
663
+
reset_control_assert(gpio->rst);
691
664
692
665
return 0;
693
666
}
···
728
699
ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
729
700
730
701
/* Mask out interrupts */
731
-
dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
702
+
dwapb_write(gpio, GPIO_INTMASK,
703
+
0xffffffff & ~ctx->wake_en);
732
704
}
733
705
}
734
706
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+1
-1
drivers/gpio/gpio-ftgpio010.c
+1
-1
drivers/gpio/gpio-ftgpio010.c
···
150
150
stat = readl(g->base + GPIO_INT_STAT);
151
151
if (stat)
152
152
for_each_set_bit(offset, &stat, gc->ngpio)
153
-
generic_handle_irq(irq_find_mapping(gc->irqdomain,
153
+
generic_handle_irq(irq_find_mapping(gc->irq.domain,
154
154
offset));
155
155
156
156
chained_irq_exit(irqchip, desc);
+3
-3
drivers/gpio/gpio-grgpio.c
+3
-3
drivers/gpio/gpio-grgpio.c
···
35
35
#include <linux/interrupt.h>
36
36
#include <linux/irq.h>
37
37
#include <linux/irqdomain.h>
38
+
#include <linux/bitops.h>
38
39
39
40
#define GRGPIO_MAX_NGPIO 32
40
41
···
97
96
int val)
98
97
{
99
98
struct gpio_chip *gc = &priv->gc;
100
-
unsigned long mask = gc->pin2mask(gc, offset);
101
99
102
100
if (val)
103
-
priv->imask |= mask;
101
+
priv->imask |= BIT(offset);
104
102
else
105
-
priv->imask &= ~mask;
103
+
priv->imask &= ~BIT(offset);
106
104
gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
107
105
}
108
106
+1
-1
drivers/gpio/gpio-ingenic.c
+1
-1
drivers/gpio/gpio-ingenic.c
+1
-1
drivers/gpio/gpio-intel-mid.c
+1
-1
drivers/gpio/gpio-intel-mid.c
+3
-4
drivers/gpio/gpio-loongson1.c
+3
-4
drivers/gpio/gpio-loongson1.c
···
11
11
#include <linux/module.h>
12
12
#include <linux/gpio/driver.h>
13
13
#include <linux/platform_device.h>
14
+
#include <linux/bitops.h>
14
15
15
16
/* Loongson 1 GPIO Register Definitions */
16
17
#define GPIO_CFG 0x0
···
23
22
24
23
static int ls1x_gpio_request(struct gpio_chip *gc, unsigned int offset)
25
24
{
26
-
unsigned long pinmask = gc->pin2mask(gc, offset);
27
25
unsigned long flags;
28
26
29
27
spin_lock_irqsave(&gc->bgpio_lock, flags);
30
-
__raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | pinmask,
28
+
__raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | BIT(offset),
31
29
gpio_reg_base + GPIO_CFG);
32
30
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
33
31
···
35
35
36
36
static void ls1x_gpio_free(struct gpio_chip *gc, unsigned int offset)
37
37
{
38
-
unsigned long pinmask = gc->pin2mask(gc, offset);
39
38
unsigned long flags;
40
39
41
40
spin_lock_irqsave(&gc->bgpio_lock, flags);
42
-
__raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~pinmask,
41
+
__raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~BIT(offset),
43
42
gpio_reg_base + GPIO_CFG);
44
43
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
45
44
}
+1
-1
drivers/gpio/gpio-lynxpoint.c
+1
-1
drivers/gpio/gpio-lynxpoint.c
+492
drivers/gpio/gpio-max3191x.c
+492
drivers/gpio/gpio-max3191x.c
···
1
+
/*
2
+
* gpio-max3191x.c - GPIO driver for Maxim MAX3191x industrial serializer
3
+
*
4
+
* Copyright (C) 2017 KUNBUS GmbH
5
+
*
6
+
* The MAX3191x makes 8 digital 24V inputs available via SPI.
7
+
* Multiple chips can be daisy-chained, the spec does not impose
8
+
* a limit on the number of chips and neither does this driver.
9
+
*
10
+
* Either of two modes is selectable: In 8-bit mode, only the state
11
+
* of the inputs is clocked out to achieve high readout speeds;
12
+
* In 16-bit mode, an additional status byte is clocked out with
13
+
* a CRC and indicator bits for undervoltage and overtemperature.
14
+
* The driver returns an error instead of potentially bogus data
15
+
* if any of these fault conditions occur. However it does allow
16
+
* readout of non-faulting chips in the same daisy-chain.
17
+
*
18
+
* MAX3191x supports four debounce settings and the driver is
19
+
* capable of configuring these differently for each chip in the
20
+
* daisy-chain.
21
+
*
22
+
* If the chips are hardwired to 8-bit mode ("modesel" pulled high),
23
+
* gpio-pisosr.c can be used alternatively to this driver.
24
+
*
25
+
* https://datasheets.maximintegrated.com/en/ds/MAX31910.pdf
26
+
* https://datasheets.maximintegrated.com/en/ds/MAX31911.pdf
27
+
* https://datasheets.maximintegrated.com/en/ds/MAX31912.pdf
28
+
* https://datasheets.maximintegrated.com/en/ds/MAX31913.pdf
29
+
* https://datasheets.maximintegrated.com/en/ds/MAX31953-MAX31963.pdf
30
+
*
31
+
* This program is free software; you can redistribute it and/or modify
32
+
* it under the terms of the GNU General Public License (version 2) as
33
+
* published by the Free Software Foundation.
34
+
*/
35
+
36
+
#include <linux/bitmap.h>
37
+
#include <linux/crc8.h>
38
+
#include <linux/gpio/consumer.h>
39
+
#include <linux/gpio/driver.h>
40
+
#include <linux/module.h>
41
+
#include <linux/spi/spi.h>
42
+
43
+
enum max3191x_mode {
44
+
STATUS_BYTE_ENABLED,
45
+
STATUS_BYTE_DISABLED,
46
+
};
47
+
48
+
/**
49
+
* struct max3191x_chip - max3191x daisy-chain
50
+
* @gpio: GPIO controller struct
51
+
* @lock: protects read sequences
52
+
* @nchips: number of chips in the daisy-chain
53
+
* @mode: current mode, 0 for 16-bit, 1 for 8-bit;
54
+
* for simplicity, all chips in the daisy-chain are assumed
55
+
* to use the same mode
56
+
* @modesel_pins: GPIO pins to configure modesel of each chip
57
+
* @fault_pins: GPIO pins to detect fault of each chip
58
+
* @db0_pins: GPIO pins to configure debounce of each chip
59
+
* @db1_pins: GPIO pins to configure debounce of each chip
60
+
* @mesg: SPI message to perform a readout
61
+
* @xfer: SPI transfer used by @mesg
62
+
* @crc_error: bitmap signaling CRC error for each chip
63
+
* @overtemp: bitmap signaling overtemperature alarm for each chip
64
+
* @undervolt1: bitmap signaling undervoltage alarm for each chip
65
+
* @undervolt2: bitmap signaling undervoltage warning for each chip
66
+
* @fault: bitmap signaling assertion of @fault_pins for each chip
67
+
* @ignore_uv: whether to ignore undervoltage alarms;
68
+
* set by a device property if the chips are powered through
69
+
* 5VOUT instead of VCC24V, in which case they will constantly
70
+
* signal undervoltage;
71
+
* for simplicity, all chips in the daisy-chain are assumed
72
+
* to be powered the same way
73
+
*/
74
+
struct max3191x_chip {
75
+
struct gpio_chip gpio;
76
+
struct mutex lock;
77
+
u32 nchips;
78
+
enum max3191x_mode mode;
79
+
struct gpio_descs *modesel_pins;
80
+
struct gpio_descs *fault_pins;
81
+
struct gpio_descs *db0_pins;
82
+
struct gpio_descs *db1_pins;
83
+
struct spi_message mesg;
84
+
struct spi_transfer xfer;
85
+
unsigned long *crc_error;
86
+
unsigned long *overtemp;
87
+
unsigned long *undervolt1;
88
+
unsigned long *undervolt2;
89
+
unsigned long *fault;
90
+
bool ignore_uv;
91
+
};
92
+
93
+
#define MAX3191X_NGPIO 8
94
+
#define MAX3191X_CRC8_POLYNOMIAL 0xa8 /* (x^5) + x^4 + x^2 + x^0 */
95
+
96
+
DECLARE_CRC8_TABLE(max3191x_crc8);
97
+
98
+
static int max3191x_get_direction(struct gpio_chip *gpio, unsigned int offset)
99
+
{
100
+
return 1; /* always in */
101
+
}
102
+
103
+
static int max3191x_direction_input(struct gpio_chip *gpio, unsigned int offset)
104
+
{
105
+
return 0;
106
+
}
107
+
108
+
static int max3191x_direction_output(struct gpio_chip *gpio,
109
+
unsigned int offset, int value)
110
+
{
111
+
return -EINVAL;
112
+
}
113
+
114
+
static void max3191x_set(struct gpio_chip *gpio, unsigned int offset, int value)
115
+
{ }
116
+
117
+
static void max3191x_set_multiple(struct gpio_chip *gpio, unsigned long *mask,
118
+
unsigned long *bits)
119
+
{ }
120
+
121
+
static unsigned int max3191x_wordlen(struct max3191x_chip *max3191x)
122
+
{
123
+
return max3191x->mode == STATUS_BYTE_ENABLED ? 2 : 1;
124
+
}
125
+
126
+
static int max3191x_readout_locked(struct max3191x_chip *max3191x)
127
+
{
128
+
struct device *dev = max3191x->gpio.parent;
129
+
struct spi_device *spi = to_spi_device(dev);
130
+
int val, i, ot = 0, uv1 = 0;
131
+
132
+
val = spi_sync(spi, &max3191x->mesg);
133
+
if (val) {
134
+
dev_err_ratelimited(dev, "SPI receive error %d\n", val);
135
+
return val;
136
+
}
137
+
138
+
for (i = 0; i < max3191x->nchips; i++) {
139
+
if (max3191x->mode == STATUS_BYTE_ENABLED) {
140
+
u8 in = ((u8 *)max3191x->xfer.rx_buf)[i * 2];
141
+
u8 status = ((u8 *)max3191x->xfer.rx_buf)[i * 2 + 1];
142
+
143
+
val = (status & 0xf8) != crc8(max3191x_crc8, &in, 1, 0);
144
+
__assign_bit(i, max3191x->crc_error, val);
145
+
if (val)
146
+
dev_err_ratelimited(dev,
147
+
"chip %d: CRC error\n", i);
148
+
149
+
ot = (status >> 1) & 1;
150
+
__assign_bit(i, max3191x->overtemp, ot);
151
+
if (ot)
152
+
dev_err_ratelimited(dev,
153
+
"chip %d: overtemperature\n", i);
154
+
155
+
if (!max3191x->ignore_uv) {
156
+
uv1 = !((status >> 2) & 1);
157
+
__assign_bit(i, max3191x->undervolt1, uv1);
158
+
if (uv1)
159
+
dev_err_ratelimited(dev,
160
+
"chip %d: undervoltage\n", i);
161
+
162
+
val = !(status & 1);
163
+
__assign_bit(i, max3191x->undervolt2, val);
164
+
if (val && !uv1)
165
+
dev_warn_ratelimited(dev,
166
+
"chip %d: voltage warn\n", i);
167
+
}
168
+
}
169
+
170
+
if (max3191x->fault_pins && !max3191x->ignore_uv) {
171
+
/* fault pin shared by all chips or per chip */
172
+
struct gpio_desc *fault_pin =
173
+
(max3191x->fault_pins->ndescs == 1)
174
+
? max3191x->fault_pins->desc[0]
175
+
: max3191x->fault_pins->desc[i];
176
+
177
+
val = gpiod_get_value_cansleep(fault_pin);
178
+
if (val < 0) {
179
+
dev_err_ratelimited(dev,
180
+
"GPIO read error %d\n", val);
181
+
return val;
182
+
}
183
+
__assign_bit(i, max3191x->fault, val);
184
+
if (val && !uv1 && !ot)
185
+
dev_err_ratelimited(dev,
186
+
"chip %d: fault\n", i);
187
+
}
188
+
}
189
+
190
+
return 0;
191
+
}
192
+
193
+
static bool max3191x_chip_is_faulting(struct max3191x_chip *max3191x,
194
+
unsigned int chipnum)
195
+
{
196
+
/* without status byte the only diagnostic is the fault pin */
197
+
if (!max3191x->ignore_uv && test_bit(chipnum, max3191x->fault))
198
+
return true;
199
+
200
+
if (max3191x->mode == STATUS_BYTE_DISABLED)
201
+
return false;
202
+
203
+
return test_bit(chipnum, max3191x->crc_error) ||
204
+
test_bit(chipnum, max3191x->overtemp) ||
205
+
(!max3191x->ignore_uv &&
206
+
test_bit(chipnum, max3191x->undervolt1));
207
+
}
208
+
209
+
static int max3191x_get(struct gpio_chip *gpio, unsigned int offset)
210
+
{
211
+
struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
212
+
int ret, chipnum, wordlen = max3191x_wordlen(max3191x);
213
+
u8 in;
214
+
215
+
mutex_lock(&max3191x->lock);
216
+
ret = max3191x_readout_locked(max3191x);
217
+
if (ret)
218
+
goto out_unlock;
219
+
220
+
chipnum = offset / MAX3191X_NGPIO;
221
+
if (max3191x_chip_is_faulting(max3191x, chipnum)) {
222
+
ret = -EIO;
223
+
goto out_unlock;
224
+
}
225
+
226
+
in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen];
227
+
ret = (in >> (offset % MAX3191X_NGPIO)) & 1;
228
+
229
+
out_unlock:
230
+
mutex_unlock(&max3191x->lock);
231
+
return ret;
232
+
}
233
+
234
+
static int max3191x_get_multiple(struct gpio_chip *gpio, unsigned long *mask,
235
+
unsigned long *bits)
236
+
{
237
+
struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
238
+
int ret, bit = 0, wordlen = max3191x_wordlen(max3191x);
239
+
240
+
mutex_lock(&max3191x->lock);
241
+
ret = max3191x_readout_locked(max3191x);
242
+
if (ret)
243
+
goto out_unlock;
244
+
245
+
while ((bit = find_next_bit(mask, gpio->ngpio, bit)) != gpio->ngpio) {
246
+
unsigned int chipnum = bit / MAX3191X_NGPIO;
247
+
unsigned long in, shift, index;
248
+
249
+
if (max3191x_chip_is_faulting(max3191x, chipnum)) {
250
+
ret = -EIO;
251
+
goto out_unlock;
252
+
}
253
+
254
+
in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen];
255
+
shift = round_down(bit % BITS_PER_LONG, MAX3191X_NGPIO);
256
+
index = bit / BITS_PER_LONG;
257
+
bits[index] &= ~(mask[index] & (0xff << shift));
258
+
bits[index] |= mask[index] & (in << shift); /* copy bits */
259
+
260
+
bit = (chipnum + 1) * MAX3191X_NGPIO; /* go to next chip */
261
+
}
262
+
263
+
out_unlock:
264
+
mutex_unlock(&max3191x->lock);
265
+
return ret;
266
+
}
267
+
268
+
static int max3191x_set_config(struct gpio_chip *gpio, unsigned int offset,
269
+
unsigned long config)
270
+
{
271
+
struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
272
+
u32 debounce, chipnum, db0_val, db1_val;
273
+
274
+
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
275
+
return -ENOTSUPP;
276
+
277
+
if (!max3191x->db0_pins || !max3191x->db1_pins)
278
+
return -EINVAL;
279
+
280
+
debounce = pinconf_to_config_argument(config);
281
+
switch (debounce) {
282
+
case 0:
283
+
db0_val = 0;
284
+
db1_val = 0;
285
+
break;
286
+
case 1 ... 25:
287
+
db0_val = 0;
288
+
db1_val = 1;
289
+
break;
290
+
case 26 ... 750:
291
+
db0_val = 1;
292
+
db1_val = 0;
293
+
break;
294
+
case 751 ... 3000:
295
+
db0_val = 1;
296
+
db1_val = 1;
297
+
break;
298
+
default:
299
+
return -EINVAL;
300
+
}
301
+
302
+
if (max3191x->db0_pins->ndescs == 1)
303
+
chipnum = 0; /* all chips use the same pair of debounce pins */
304
+
else
305
+
chipnum = offset / MAX3191X_NGPIO; /* per chip debounce pins */
306
+
307
+
mutex_lock(&max3191x->lock);
308
+
gpiod_set_value_cansleep(max3191x->db0_pins->desc[chipnum], db0_val);
309
+
gpiod_set_value_cansleep(max3191x->db1_pins->desc[chipnum], db1_val);
310
+
mutex_unlock(&max3191x->lock);
311
+
return 0;
312
+
}
313
+
314
+
static void gpiod_set_array_single_value_cansleep(unsigned int ndescs,
315
+
struct gpio_desc **desc,
316
+
int value)
317
+
{
318
+
int i, values[ndescs];
319
+
320
+
for (i = 0; i < ndescs; i++)
321
+
values[i] = value;
322
+
323
+
gpiod_set_array_value_cansleep(ndescs, desc, values);
324
+
}
325
+
326
+
static struct gpio_descs *devm_gpiod_get_array_optional_count(
327
+
struct device *dev, const char *con_id,
328
+
enum gpiod_flags flags, unsigned int expected)
329
+
{
330
+
struct gpio_descs *descs;
331
+
int found = gpiod_count(dev, con_id);
332
+
333
+
if (found == -ENOENT)
334
+
return NULL;
335
+
336
+
if (found != expected && found != 1) {
337
+
dev_err(dev, "ignoring %s-gpios: found %d, expected %u or 1\n",
338
+
con_id, found, expected);
339
+
return NULL;
340
+
}
341
+
342
+
descs = devm_gpiod_get_array_optional(dev, con_id, flags);
343
+
344
+
if (IS_ERR(descs)) {
345
+
dev_err(dev, "failed to get %s-gpios: %ld\n",
346
+
con_id, PTR_ERR(descs));
347
+
return NULL;
348
+
}
349
+
350
+
return descs;
351
+
}
352
+
353
+
static int max3191x_probe(struct spi_device *spi)
354
+
{
355
+
struct device *dev = &spi->dev;
356
+
struct max3191x_chip *max3191x;
357
+
int n, ret;
358
+
359
+
max3191x = devm_kzalloc(dev, sizeof(*max3191x), GFP_KERNEL);
360
+
if (!max3191x)
361
+
return -ENOMEM;
362
+
spi_set_drvdata(spi, max3191x);
363
+
364
+
max3191x->nchips = 1;
365
+
device_property_read_u32(dev, "#daisy-chained-devices",
366
+
&max3191x->nchips);
367
+
368
+
n = BITS_TO_LONGS(max3191x->nchips);
369
+
max3191x->crc_error = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
370
+
max3191x->undervolt1 = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
371
+
max3191x->undervolt2 = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
372
+
max3191x->overtemp = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
373
+
max3191x->fault = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
374
+
max3191x->xfer.rx_buf = devm_kcalloc(dev, max3191x->nchips,
375
+
2, GFP_KERNEL);
376
+
if (!max3191x->crc_error || !max3191x->undervolt1 ||
377
+
!max3191x->overtemp || !max3191x->undervolt2 ||
378
+
!max3191x->fault || !max3191x->xfer.rx_buf)
379
+
return -ENOMEM;
380
+
381
+
max3191x->modesel_pins = devm_gpiod_get_array_optional_count(dev,
382
+
"maxim,modesel", GPIOD_ASIS, max3191x->nchips);
383
+
max3191x->fault_pins = devm_gpiod_get_array_optional_count(dev,
384
+
"maxim,fault", GPIOD_IN, max3191x->nchips);
385
+
max3191x->db0_pins = devm_gpiod_get_array_optional_count(dev,
386
+
"maxim,db0", GPIOD_OUT_LOW, max3191x->nchips);
387
+
max3191x->db1_pins = devm_gpiod_get_array_optional_count(dev,
388
+
"maxim,db1", GPIOD_OUT_LOW, max3191x->nchips);
389
+
390
+
max3191x->mode = device_property_read_bool(dev, "maxim,modesel-8bit")
391
+
? STATUS_BYTE_DISABLED : STATUS_BYTE_ENABLED;
392
+
if (max3191x->modesel_pins)
393
+
gpiod_set_array_single_value_cansleep(
394
+
max3191x->modesel_pins->ndescs,
395
+
max3191x->modesel_pins->desc, max3191x->mode);
396
+
397
+
max3191x->ignore_uv = device_property_read_bool(dev,
398
+
"maxim,ignore-undervoltage");
399
+
400
+
if (max3191x->db0_pins && max3191x->db1_pins &&
401
+
max3191x->db0_pins->ndescs != max3191x->db1_pins->ndescs) {
402
+
dev_err(dev, "ignoring maxim,db*-gpios: array len mismatch\n");
403
+
devm_gpiod_put_array(dev, max3191x->db0_pins);
404
+
devm_gpiod_put_array(dev, max3191x->db1_pins);
405
+
max3191x->db0_pins = NULL;
406
+
max3191x->db1_pins = NULL;
407
+
}
408
+
409
+
max3191x->xfer.len = max3191x->nchips * max3191x_wordlen(max3191x);
410
+
spi_message_init_with_transfers(&max3191x->mesg, &max3191x->xfer, 1);
411
+
412
+
max3191x->gpio.label = spi->modalias;
413
+
max3191x->gpio.owner = THIS_MODULE;
414
+
max3191x->gpio.parent = dev;
415
+
max3191x->gpio.base = -1;
416
+
max3191x->gpio.ngpio = max3191x->nchips * MAX3191X_NGPIO;
417
+
max3191x->gpio.can_sleep = true;
418
+
419
+
max3191x->gpio.get_direction = max3191x_get_direction;
420
+
max3191x->gpio.direction_input = max3191x_direction_input;
421
+
max3191x->gpio.direction_output = max3191x_direction_output;
422
+
max3191x->gpio.set = max3191x_set;
423
+
max3191x->gpio.set_multiple = max3191x_set_multiple;
424
+
max3191x->gpio.get = max3191x_get;
425
+
max3191x->gpio.get_multiple = max3191x_get_multiple;
426
+
max3191x->gpio.set_config = max3191x_set_config;
427
+
428
+
mutex_init(&max3191x->lock);
429
+
430
+
ret = gpiochip_add_data(&max3191x->gpio, max3191x);
431
+
if (ret) {
432
+
mutex_destroy(&max3191x->lock);
433
+
return ret;
434
+
}
435
+
436
+
return 0;
437
+
}
438
+
439
+
static int max3191x_remove(struct spi_device *spi)
440
+
{
441
+
struct max3191x_chip *max3191x = spi_get_drvdata(spi);
442
+
443
+
gpiochip_remove(&max3191x->gpio);
444
+
mutex_destroy(&max3191x->lock);
445
+
446
+
return 0;
447
+
}
448
+
449
+
static int __init max3191x_register_driver(struct spi_driver *sdrv)
450
+
{
451
+
crc8_populate_msb(max3191x_crc8, MAX3191X_CRC8_POLYNOMIAL);
452
+
return spi_register_driver(sdrv);
453
+
}
454
+
455
+
#ifdef CONFIG_OF
456
+
static const struct of_device_id max3191x_of_id[] = {
457
+
{ .compatible = "maxim,max31910" },
458
+
{ .compatible = "maxim,max31911" },
459
+
{ .compatible = "maxim,max31912" },
460
+
{ .compatible = "maxim,max31913" },
461
+
{ .compatible = "maxim,max31953" },
462
+
{ .compatible = "maxim,max31963" },
463
+
{ }
464
+
};
465
+
MODULE_DEVICE_TABLE(of, max3191x_of_id);
466
+
#endif
467
+
468
+
static const struct spi_device_id max3191x_spi_id[] = {
469
+
{ "max31910" },
470
+
{ "max31911" },
471
+
{ "max31912" },
472
+
{ "max31913" },
473
+
{ "max31953" },
474
+
{ "max31963" },
475
+
{ }
476
+
};
477
+
MODULE_DEVICE_TABLE(spi, max3191x_spi_id);
478
+
479
+
static struct spi_driver max3191x_driver = {
480
+
.driver = {
481
+
.name = "max3191x",
482
+
.of_match_table = of_match_ptr(max3191x_of_id),
483
+
},
484
+
.probe = max3191x_probe,
485
+
.remove = max3191x_remove,
486
+
.id_table = max3191x_spi_id,
487
+
};
488
+
module_driver(max3191x_driver, max3191x_register_driver, spi_unregister_driver);
489
+
490
+
MODULE_AUTHOR("Lukas Wunner <lukas@wunner.de>");
491
+
MODULE_DESCRIPTION("GPIO driver for Maxim MAX3191x industrial serializer");
492
+
MODULE_LICENSE("GPL v2");
+1
-1
drivers/gpio/gpio-max732x.c
+1
-1
drivers/gpio/gpio-max732x.c
+6
-6
drivers/gpio/gpio-mb86s7x.c
+6
-6
drivers/gpio/gpio-mb86s7x.c
···
17
17
#include <linux/io.h>
18
18
#include <linux/init.h>
19
19
#include <linux/clk.h>
20
+
#include <linux/module.h>
20
21
#include <linux/err.h>
21
22
#include <linux/errno.h>
22
23
#include <linux/ioport.h>
···
53
52
spin_lock_irqsave(&gchip->lock, flags);
54
53
55
54
val = readl(gchip->base + PFR(gpio));
56
-
if (!(val & OFFSET(gpio))) {
57
-
spin_unlock_irqrestore(&gchip->lock, flags);
58
-
return -EINVAL;
59
-
}
60
-
61
55
val &= ~OFFSET(gpio);
62
56
writel(val, gchip->base + PFR(gpio));
63
57
···
205
209
{ .compatible = "fujitsu,mb86s70-gpio" },
206
210
{ /* sentinel */ }
207
211
};
212
+
MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids);
208
213
209
214
static struct platform_driver mb86s70_gpio_driver = {
210
215
.driver = {
···
215
218
.probe = mb86s70_gpio_probe,
216
219
.remove = mb86s70_gpio_remove,
217
220
};
221
+
module_platform_driver(mb86s70_gpio_driver);
218
222
219
-
builtin_platform_driver(mb86s70_gpio_driver);
223
+
MODULE_DESCRIPTION("MB86S7x GPIO Driver");
224
+
MODULE_ALIAS("platform:mb86s70-gpio");
225
+
MODULE_LICENSE("GPL");
+1
-1
drivers/gpio/gpio-merrifield.c
+1
-1
drivers/gpio/gpio-merrifield.c
+102
-28
drivers/gpio/gpio-mmio.c
+102
-28
drivers/gpio/gpio-mmio.c
···
126
126
return ioread32be(reg);
127
127
}
128
128
129
-
static unsigned long bgpio_pin2mask(struct gpio_chip *gc, unsigned int pin)
129
+
static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
130
130
{
131
-
return BIT(pin);
132
-
}
133
-
134
-
static unsigned long bgpio_pin2mask_be(struct gpio_chip *gc,
135
-
unsigned int pin)
136
-
{
137
-
return BIT(gc->bgpio_bits - 1 - pin);
131
+
if (gc->be_bits)
132
+
return BIT(gc->bgpio_bits - 1 - line);
133
+
return BIT(line);
138
134
}
139
135
140
136
static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
141
137
{
142
-
unsigned long pinmask = gc->pin2mask(gc, gpio);
138
+
unsigned long pinmask = bgpio_line2mask(gc, gpio);
143
139
144
140
if (gc->bgpio_dir & pinmask)
145
141
return !!(gc->read_reg(gc->reg_set) & pinmask);
···
143
147
return !!(gc->read_reg(gc->reg_dat) & pinmask);
144
148
}
145
149
150
+
/*
151
+
* This assumes that the bits in the GPIO register are in native endianness.
152
+
* We only assign the function pointer if we have that.
153
+
*/
154
+
static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
155
+
unsigned long *bits)
156
+
{
157
+
unsigned long get_mask = 0;
158
+
unsigned long set_mask = 0;
159
+
int bit = 0;
160
+
161
+
while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio) {
162
+
if (gc->bgpio_dir & BIT(bit))
163
+
set_mask |= BIT(bit);
164
+
else
165
+
get_mask |= BIT(bit);
166
+
}
167
+
168
+
if (set_mask)
169
+
*bits |= gc->read_reg(gc->reg_set) & set_mask;
170
+
if (get_mask)
171
+
*bits |= gc->read_reg(gc->reg_dat) & get_mask;
172
+
173
+
return 0;
174
+
}
175
+
146
176
static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
147
177
{
148
-
return !!(gc->read_reg(gc->reg_dat) & gc->pin2mask(gc, gpio));
178
+
return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
179
+
}
180
+
181
+
/*
182
+
* This only works if the bits in the GPIO register are in native endianness.
183
+
* It is dirt simple and fast in this case. (Also the most common case.)
184
+
*/
185
+
static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
186
+
unsigned long *bits)
187
+
{
188
+
189
+
*bits = gc->read_reg(gc->reg_dat) & *mask;
190
+
return 0;
191
+
}
192
+
193
+
/*
194
+
* With big endian mirrored bit order it becomes more tedious.
195
+
*/
196
+
static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
197
+
unsigned long *bits)
198
+
{
199
+
unsigned long readmask = 0;
200
+
unsigned long val;
201
+
int bit;
202
+
203
+
/* Create a mirrored mask */
204
+
bit = 0;
205
+
while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio)
206
+
readmask |= bgpio_line2mask(gc, bit);
207
+
208
+
/* Read the register */
209
+
val = gc->read_reg(gc->reg_dat) & readmask;
210
+
211
+
/*
212
+
* Mirror the result into the "bits" result, this will give line 0
213
+
* in bit 0 ... line 31 in bit 31 for a 32bit register.
214
+
*/
215
+
bit = 0;
216
+
while ((bit = find_next_bit(&val, gc->ngpio, bit)) != gc->ngpio)
217
+
*bits |= bgpio_line2mask(gc, bit);
218
+
219
+
return 0;
149
220
}
150
221
151
222
static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
···
221
158
222
159
static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
223
160
{
224
-
unsigned long mask = gc->pin2mask(gc, gpio);
161
+
unsigned long mask = bgpio_line2mask(gc, gpio);
225
162
unsigned long flags;
226
163
227
164
spin_lock_irqsave(&gc->bgpio_lock, flags);
···
239
176
static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
240
177
int val)
241
178
{
242
-
unsigned long mask = gc->pin2mask(gc, gpio);
179
+
unsigned long mask = bgpio_line2mask(gc, gpio);
243
180
244
181
if (val)
245
182
gc->write_reg(gc->reg_set, mask);
···
249
186
250
187
static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
251
188
{
252
-
unsigned long mask = gc->pin2mask(gc, gpio);
189
+
unsigned long mask = bgpio_line2mask(gc, gpio);
253
190
unsigned long flags;
254
191
255
192
spin_lock_irqsave(&gc->bgpio_lock, flags);
···
279
216
break;
280
217
if (__test_and_clear_bit(i, mask)) {
281
218
if (test_bit(i, bits))
282
-
*set_mask |= gc->pin2mask(gc, i);
219
+
*set_mask |= bgpio_line2mask(gc, i);
283
220
else
284
-
*clear_mask |= gc->pin2mask(gc, i);
221
+
*clear_mask |= bgpio_line2mask(gc, i);
285
222
}
286
223
}
287
224
}
···
357
294
358
295
spin_lock_irqsave(&gc->bgpio_lock, flags);
359
296
360
-
gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
297
+
gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
361
298
gc->write_reg(gc->reg_dir, gc->bgpio_dir);
362
299
363
300
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
···
368
305
static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
369
306
{
370
307
/* Return 0 if output, 1 of input */
371
-
return !(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
308
+
return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
372
309
}
373
310
374
311
static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
···
379
316
380
317
spin_lock_irqsave(&gc->bgpio_lock, flags);
381
318
382
-
gc->bgpio_dir |= gc->pin2mask(gc, gpio);
319
+
gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
383
320
gc->write_reg(gc->reg_dir, gc->bgpio_dir);
384
321
385
322
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
···
393
330
394
331
spin_lock_irqsave(&gc->bgpio_lock, flags);
395
332
396
-
gc->bgpio_dir |= gc->pin2mask(gc, gpio);
333
+
gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
397
334
gc->write_reg(gc->reg_dir, gc->bgpio_dir);
398
335
399
336
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
···
409
346
410
347
spin_lock_irqsave(&gc->bgpio_lock, flags);
411
348
412
-
gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
349
+
gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
413
350
gc->write_reg(gc->reg_dir, gc->bgpio_dir);
414
351
415
352
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
···
420
357
static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
421
358
{
422
359
/* Return 0 if output, 1 if input */
423
-
return !!(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
360
+
return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
424
361
}
425
362
426
363
static int bgpio_setup_accessors(struct device *dev,
427
364
struct gpio_chip *gc,
428
-
bool bit_be,
429
365
bool byte_be)
430
366
{
431
367
···
467
405
dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
468
406
return -EINVAL;
469
407
}
470
-
471
-
gc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
472
408
473
409
return 0;
474
410
}
···
522
462
}
523
463
524
464
if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
525
-
(flags & BGPIOF_READ_OUTPUT_REG_SET))
465
+
(flags & BGPIOF_READ_OUTPUT_REG_SET)) {
526
466
gc->get = bgpio_get_set;
527
-
else
467
+
if (!gc->be_bits)
468
+
gc->get_multiple = bgpio_get_set_multiple;
469
+
/*
470
+
* We deliberately avoid assigning the ->get_multiple() call
471
+
* for big endian mirrored registers which are ALSO reflecting
472
+
* their value in the set register when used as output. It is
473
+
* simply too much complexity, let the GPIO core fall back to
474
+
* reading each line individually in that fringe case.
475
+
*/
476
+
} else {
528
477
gc->get = bgpio_get;
478
+
if (gc->be_bits)
479
+
gc->get_multiple = bgpio_get_multiple_be;
480
+
else
481
+
gc->get_multiple = bgpio_get_multiple;
482
+
}
529
483
530
484
return 0;
531
485
}
···
600
526
gc->base = -1;
601
527
gc->ngpio = gc->bgpio_bits;
602
528
gc->request = bgpio_request;
529
+
gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
603
530
604
531
ret = bgpio_setup_io(gc, dat, set, clr, flags);
605
532
if (ret)
606
533
return ret;
607
534
608
-
ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN,
609
-
flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
535
+
ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
610
536
if (ret)
611
537
return ret;
612
538
+17
-6
drivers/gpio/gpio-mpc8xxx.c
+17
-6
drivers/gpio/gpio-mpc8xxx.c
···
21
21
#include <linux/slab.h>
22
22
#include <linux/irq.h>
23
23
#include <linux/gpio/driver.h>
24
+
#include <linux/bitops.h>
24
25
25
26
#define MPC8XXX_GPIO_PINS 32
26
27
···
45
44
unsigned int irqn;
46
45
};
47
46
47
+
/*
48
+
* This hardware has a big endian bit assignment such that GPIO line 0 is
49
+
* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
50
+
* This inline helper give the right bitmask for a certain line.
51
+
*/
52
+
static inline u32 mpc_pin2mask(unsigned int offset)
53
+
{
54
+
return BIT(31 - offset);
55
+
}
56
+
48
57
/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
49
58
* defined as output cannot be determined by reading GPDAT register,
50
59
* so we use shadow data register instead. The status of input pins
···
70
59
val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
71
60
out_shadow = gc->bgpio_data & out_mask;
72
61
73
-
return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
62
+
return !!((val | out_shadow) & mpc_pin2mask(gpio));
74
63
}
75
64
76
65
static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
···
131
120
132
121
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
133
122
gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
134
-
| gc->pin2mask(gc, irqd_to_hwirq(d)));
123
+
| mpc_pin2mask(irqd_to_hwirq(d)));
135
124
136
125
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
137
126
}
···
146
135
147
136
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
148
137
gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
149
-
& ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
138
+
& ~mpc_pin2mask(irqd_to_hwirq(d)));
150
139
151
140
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
152
141
}
···
157
146
struct gpio_chip *gc = &mpc8xxx_gc->gc;
158
147
159
148
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
160
-
gc->pin2mask(gc, irqd_to_hwirq(d)));
149
+
mpc_pin2mask(irqd_to_hwirq(d)));
161
150
}
162
151
163
152
static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
···
171
160
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
172
161
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
173
162
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
174
-
| gc->pin2mask(gc, irqd_to_hwirq(d)));
163
+
| mpc_pin2mask(irqd_to_hwirq(d)));
175
164
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
176
165
break;
177
166
···
179
168
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
180
169
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
181
170
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
182
-
& ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
171
+
& ~mpc_pin2mask(irqd_to_hwirq(d)));
183
172
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
184
173
break;
185
174
+1
-1
drivers/gpio/gpio-omap.c
+1
-1
drivers/gpio/gpio-omap.c
+1
-1
drivers/gpio/gpio-pca953x.c
+1
-1
drivers/gpio/gpio-pca953x.c
···
608
608
for (i = 0; i < NBANK(chip); i++) {
609
609
while (pending[i]) {
610
610
level = __ffs(pending[i]);
611
-
handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
611
+
handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
612
612
level + (BANK_SZ * i)));
613
613
pending[i] &= ~(1 << level);
614
614
nhandled++;
+1
-1
drivers/gpio/gpio-pcf857x.c
+1
-1
drivers/gpio/gpio-pcf857x.c
+1
-1
drivers/gpio/gpio-pci-idio-16.c
+1
-1
drivers/gpio/gpio-pci-idio-16.c
+1
-1
drivers/gpio/gpio-pl061.c
+1
-1
drivers/gpio/gpio-pl061.c
+9
-15
drivers/gpio/gpio-rcar.c
+9
-15
drivers/gpio/gpio-rcar.c
···
24
24
#include <linux/irq.h>
25
25
#include <linux/module.h>
26
26
#include <linux/of.h>
27
+
#include <linux/of_device.h>
27
28
#include <linux/pinctrl/consumer.h>
28
29
#include <linux/platform_device.h>
29
30
#include <linux/pm_runtime.h>
···
207
206
gpio_rcar_read(p, INTMSK))) {
208
207
offset = __ffs(pending);
209
208
gpio_rcar_write(p, INTCLR, BIT(offset));
210
-
generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
209
+
generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
211
210
offset));
212
211
irqs_handled++;
213
212
}
···
394
393
static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
395
394
{
396
395
struct device_node *np = p->pdev->dev.of_node;
397
-
const struct of_device_id *match;
398
396
const struct gpio_rcar_info *info;
399
397
struct of_phandle_args args;
400
398
int ret;
401
399
402
-
match = of_match_node(gpio_rcar_of_table, np);
403
-
if (!match)
404
-
return -EINVAL;
405
-
406
-
info = match->data;
400
+
info = of_device_get_match_data(&p->pdev->dev);
407
401
408
402
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
409
403
*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
···
452
456
453
457
pm_runtime_enable(dev);
454
458
455
-
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
456
459
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
457
-
458
-
if (!io || !irq) {
459
-
dev_err(dev, "missing IRQ or IOMEM\n");
460
+
if (!irq) {
461
+
dev_err(dev, "missing IRQ\n");
460
462
ret = -EINVAL;
461
463
goto err0;
462
464
}
463
465
464
-
p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
465
-
if (!p->base) {
466
-
dev_err(dev, "failed to remap I/O memory\n");
467
-
ret = -ENXIO;
466
+
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
467
+
p->base = devm_ioremap_resource(dev, io);
468
+
if (IS_ERR(p->base)) {
469
+
ret = PTR_ERR(p->base);
468
470
goto err0;
469
471
}
470
472
+2
-2
drivers/gpio/gpio-reg.c
+2
-2
drivers/gpio/gpio-reg.c
···
103
103
struct gpio_reg *r = to_gpio_reg(gc);
104
104
int irq = r->irqs[offset];
105
105
106
-
if (irq >= 0 && r->irqdomain)
107
-
irq = irq_find_mapping(r->irqdomain, irq);
106
+
if (irq >= 0 && r->irq.domain)
107
+
irq = irq_find_mapping(r->irq.domain, irq);
108
108
109
109
return irq;
110
110
}
+5
-5
drivers/gpio/gpio-stmpe.c
+5
-5
drivers/gpio/gpio-stmpe.c
···
299
299
if (ret < 0)
300
300
return;
301
301
edge_det = !!(ret & mask);
302
-
302
+
/* fall through */
303
303
case STMPE1801:
304
304
rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
305
305
fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
···
312
312
if (ret < 0)
313
313
return;
314
314
fall = !!(ret & mask);
315
-
315
+
/* fall through */
316
316
case STMPE801:
317
317
case STMPE1600:
318
318
irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
···
397
397
while (stat) {
398
398
int bit = __ffs(stat);
399
399
int line = bank * 8 + bit;
400
-
int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
400
+
int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
401
401
line);
402
402
403
403
handle_nested_irq(child_irq);
···
451
451
of_property_read_u32(np, "st,norequest-mask",
452
452
&stmpe_gpio->norequest_mask);
453
453
if (stmpe_gpio->norequest_mask)
454
-
stmpe_gpio->chip.irq_need_valid_mask = true;
454
+
stmpe_gpio->chip.irq.need_valid_mask = true;
455
455
456
456
if (irq < 0)
457
457
dev_info(&pdev->dev,
···
482
482
/* Forbid unused lines to be mapped as IRQs */
483
483
for (i = 0; i < sizeof(u32); i++)
484
484
if (stmpe_gpio->norequest_mask & BIT(i))
485
-
clear_bit(i, stmpe_gpio->chip.irq_valid_mask);
485
+
clear_bit(i, stmpe_gpio->chip.irq.valid_mask);
486
486
}
487
487
ret = gpiochip_irqchip_add_nested(&stmpe_gpio->chip,
488
488
&stmpe_gpio_irq_chip,
+3
drivers/gpio/gpio-tb10x.c
+3
drivers/gpio/gpio-tb10x.c
···
193
193
194
194
tb10x_gpio->gc.label =
195
195
devm_kasprintf(&pdev->dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
196
+
if (!tb10x_gpio->gc.label)
197
+
return -ENOMEM;
198
+
196
199
tb10x_gpio->gc.parent = &pdev->dev;
197
200
tb10x_gpio->gc.owner = THIS_MODULE;
198
201
tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in;
+1
-1
drivers/gpio/gpio-tc3589x.c
+1
-1
drivers/gpio/gpio-tc3589x.c
+620
drivers/gpio/gpio-tegra186.c
+620
drivers/gpio/gpio-tegra186.c
···
1
+
/*
2
+
* Copyright (c) 2016-2017 NVIDIA Corporation
3
+
*
4
+
* Author: Thierry Reding <treding@nvidia.com>
5
+
*
6
+
* This software is licensed under the terms of the GNU General Public
7
+
* License version 2, as published by the Free Software Foundation, and
8
+
* may be copied, distributed, and modified under those terms.
9
+
*/
10
+
11
+
#include <linux/gpio/driver.h>
12
+
#include <linux/interrupt.h>
13
+
#include <linux/irq.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of_device.h>
16
+
#include <linux/platform_device.h>
17
+
18
+
#include <dt-bindings/gpio/tegra186-gpio.h>
19
+
20
+
#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
21
+
#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
22
+
#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
23
+
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
24
+
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
25
+
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
26
+
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
27
+
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
28
+
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
29
+
#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
30
+
31
+
#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
32
+
#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
33
+
34
+
#define TEGRA186_GPIO_INPUT 0x08
35
+
#define TEGRA186_GPIO_INPUT_HIGH BIT(0)
36
+
37
+
#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
38
+
#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
39
+
40
+
#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
41
+
#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
42
+
43
+
#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
44
+
45
+
#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
46
+
47
+
struct tegra_gpio_port {
48
+
const char *name;
49
+
unsigned int offset;
50
+
unsigned int pins;
51
+
unsigned int irq;
52
+
};
53
+
54
+
struct tegra_gpio_soc {
55
+
const struct tegra_gpio_port *ports;
56
+
unsigned int num_ports;
57
+
const char *name;
58
+
};
59
+
60
+
struct tegra_gpio {
61
+
struct gpio_chip gpio;
62
+
struct irq_chip intc;
63
+
unsigned int num_irq;
64
+
unsigned int *irq;
65
+
66
+
const struct tegra_gpio_soc *soc;
67
+
68
+
void __iomem *base;
69
+
};
70
+
71
+
static const struct tegra_gpio_port *
72
+
tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
73
+
{
74
+
unsigned int start = 0, i;
75
+
76
+
for (i = 0; i < gpio->soc->num_ports; i++) {
77
+
const struct tegra_gpio_port *port = &gpio->soc->ports[i];
78
+
79
+
if (*pin >= start && *pin < start + port->pins) {
80
+
*pin -= start;
81
+
return port;
82
+
}
83
+
84
+
start += port->pins;
85
+
}
86
+
87
+
return NULL;
88
+
}
89
+
90
+
static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
91
+
unsigned int pin)
92
+
{
93
+
const struct tegra_gpio_port *port;
94
+
95
+
port = tegra186_gpio_get_port(gpio, &pin);
96
+
if (!port)
97
+
return NULL;
98
+
99
+
return gpio->base + port->offset + pin * 0x20;
100
+
}
101
+
102
+
static int tegra186_gpio_get_direction(struct gpio_chip *chip,
103
+
unsigned int offset)
104
+
{
105
+
struct tegra_gpio *gpio = gpiochip_get_data(chip);
106
+
void __iomem *base;
107
+
u32 value;
108
+
109
+
base = tegra186_gpio_get_base(gpio, offset);
110
+
if (WARN_ON(base == NULL))
111
+
return -ENODEV;
112
+
113
+
value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
114
+
if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
115
+
return 0;
116
+
117
+
return 1;
118
+
}
119
+
120
+
static int tegra186_gpio_direction_input(struct gpio_chip *chip,
121
+
unsigned int offset)
122
+
{
123
+
struct tegra_gpio *gpio = gpiochip_get_data(chip);
124
+
void __iomem *base;
125
+
u32 value;
126
+
127
+
base = tegra186_gpio_get_base(gpio, offset);
128
+
if (WARN_ON(base == NULL))
129
+
return -ENODEV;
130
+
131
+
value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
132
+
value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
133
+
writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
134
+
135
+
value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
136
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
137
+
value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
138
+
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
139
+
140
+
return 0;
141
+
}
142
+
143
+
static int tegra186_gpio_direction_output(struct gpio_chip *chip,
144
+
unsigned int offset, int level)
145
+
{
146
+
struct tegra_gpio *gpio = gpiochip_get_data(chip);
147
+
void __iomem *base;
148
+
u32 value;
149
+
150
+
/* configure output level first */
151
+
chip->set(chip, offset, level);
152
+
153
+
base = tegra186_gpio_get_base(gpio, offset);
154
+
if (WARN_ON(base == NULL))
155
+
return -EINVAL;
156
+
157
+
/* set the direction */
158
+
value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
159
+
value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
160
+
writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
161
+
162
+
value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
163
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
164
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
165
+
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
166
+
167
+
return 0;
168
+
}
169
+
170
+
static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
171
+
{
172
+
struct tegra_gpio *gpio = gpiochip_get_data(chip);
173
+
void __iomem *base;
174
+
u32 value;
175
+
176
+
base = tegra186_gpio_get_base(gpio, offset);
177
+
if (WARN_ON(base == NULL))
178
+
return -ENODEV;
179
+
180
+
value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
181
+
if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
182
+
value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
183
+
else
184
+
value = readl(base + TEGRA186_GPIO_INPUT);
185
+
186
+
return value & BIT(0);
187
+
}
188
+
189
+
static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
190
+
int level)
191
+
{
192
+
struct tegra_gpio *gpio = gpiochip_get_data(chip);
193
+
void __iomem *base;
194
+
u32 value;
195
+
196
+
base = tegra186_gpio_get_base(gpio, offset);
197
+
if (WARN_ON(base == NULL))
198
+
return;
199
+
200
+
value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
201
+
if (level == 0)
202
+
value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
203
+
else
204
+
value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
205
+
206
+
writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
207
+
}
208
+
209
+
static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
210
+
const struct of_phandle_args *spec,
211
+
u32 *flags)
212
+
{
213
+
struct tegra_gpio *gpio = gpiochip_get_data(chip);
214
+
unsigned int port, pin, i, offset = 0;
215
+
216
+
if (WARN_ON(chip->of_gpio_n_cells < 2))
217
+
return -EINVAL;
218
+
219
+
if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
220
+
return -EINVAL;
221
+
222
+
port = spec->args[0] / 8;
223
+
pin = spec->args[0] % 8;
224
+
225
+
if (port >= gpio->soc->num_ports) {
226
+
dev_err(chip->parent, "invalid port number: %u\n", port);
227
+
return -EINVAL;
228
+
}
229
+
230
+
for (i = 0; i < port; i++)
231
+
offset += gpio->soc->ports[i].pins;
232
+
233
+
if (flags)
234
+
*flags = spec->args[1];
235
+
236
+
return offset + pin;
237
+
}
238
+
239
+
static void tegra186_irq_ack(struct irq_data *data)
240
+
{
241
+
struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
242
+
void __iomem *base;
243
+
244
+
base = tegra186_gpio_get_base(gpio, data->hwirq);
245
+
if (WARN_ON(base == NULL))
246
+
return;
247
+
248
+
writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
249
+
}
250
+
251
+
static void tegra186_irq_mask(struct irq_data *data)
252
+
{
253
+
struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
254
+
void __iomem *base;
255
+
u32 value;
256
+
257
+
base = tegra186_gpio_get_base(gpio, data->hwirq);
258
+
if (WARN_ON(base == NULL))
259
+
return;
260
+
261
+
value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
262
+
value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
263
+
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
264
+
}
265
+
266
+
static void tegra186_irq_unmask(struct irq_data *data)
267
+
{
268
+
struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
269
+
void __iomem *base;
270
+
u32 value;
271
+
272
+
base = tegra186_gpio_get_base(gpio, data->hwirq);
273
+
if (WARN_ON(base == NULL))
274
+
return;
275
+
276
+
value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
277
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
278
+
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
279
+
}
280
+
281
+
static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow)
282
+
{
283
+
struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
284
+
void __iomem *base;
285
+
u32 value;
286
+
287
+
base = tegra186_gpio_get_base(gpio, data->hwirq);
288
+
if (WARN_ON(base == NULL))
289
+
return -ENODEV;
290
+
291
+
value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
292
+
value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
293
+
value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
294
+
295
+
switch (flow & IRQ_TYPE_SENSE_MASK) {
296
+
case IRQ_TYPE_NONE:
297
+
break;
298
+
299
+
case IRQ_TYPE_EDGE_RISING:
300
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
301
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
302
+
break;
303
+
304
+
case IRQ_TYPE_EDGE_FALLING:
305
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
306
+
break;
307
+
308
+
case IRQ_TYPE_EDGE_BOTH:
309
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
310
+
break;
311
+
312
+
case IRQ_TYPE_LEVEL_HIGH:
313
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
314
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
315
+
break;
316
+
317
+
case IRQ_TYPE_LEVEL_LOW:
318
+
value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
319
+
break;
320
+
321
+
default:
322
+
return -EINVAL;
323
+
}
324
+
325
+
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
326
+
327
+
if ((flow & IRQ_TYPE_EDGE_BOTH) == 0)
328
+
irq_set_handler_locked(data, handle_level_irq);
329
+
else
330
+
irq_set_handler_locked(data, handle_edge_irq);
331
+
332
+
return 0;
333
+
}
334
+
335
+
static void tegra186_gpio_irq(struct irq_desc *desc)
336
+
{
337
+
struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
338
+
struct irq_domain *domain = gpio->gpio.irq.domain;
339
+
struct irq_chip *chip = irq_desc_get_chip(desc);
340
+
unsigned int parent = irq_desc_get_irq(desc);
341
+
unsigned int i, offset = 0;
342
+
343
+
chained_irq_enter(chip, desc);
344
+
345
+
for (i = 0; i < gpio->soc->num_ports; i++) {
346
+
const struct tegra_gpio_port *port = &gpio->soc->ports[i];
347
+
void __iomem *base = gpio->base + port->offset;
348
+
unsigned int pin, irq;
349
+
unsigned long value;
350
+
351
+
/* skip ports that are not associated with this controller */
352
+
if (parent != gpio->irq[port->irq])
353
+
goto skip;
354
+
355
+
value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
356
+
357
+
for_each_set_bit(pin, &value, port->pins) {
358
+
irq = irq_find_mapping(domain, offset + pin);
359
+
if (WARN_ON(irq == 0))
360
+
continue;
361
+
362
+
generic_handle_irq(irq);
363
+
}
364
+
365
+
skip:
366
+
offset += port->pins;
367
+
}
368
+
369
+
chained_irq_exit(chip, desc);
370
+
}
371
+
372
+
static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain,
373
+
struct device_node *np,
374
+
const u32 *spec, unsigned int size,
375
+
unsigned long *hwirq,
376
+
unsigned int *type)
377
+
{
378
+
struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
379
+
unsigned int port, pin, i, offset = 0;
380
+
381
+
if (size < 2)
382
+
return -EINVAL;
383
+
384
+
port = spec[0] / 8;
385
+
pin = spec[0] % 8;
386
+
387
+
if (port >= gpio->soc->num_ports) {
388
+
dev_err(gpio->gpio.parent, "invalid port number: %u\n", port);
389
+
return -EINVAL;
390
+
}
391
+
392
+
for (i = 0; i < port; i++)
393
+
offset += gpio->soc->ports[i].pins;
394
+
395
+
*type = spec[1] & IRQ_TYPE_SENSE_MASK;
396
+
*hwirq = offset + pin;
397
+
398
+
return 0;
399
+
}
400
+
401
+
static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = {
402
+
.map = gpiochip_irq_map,
403
+
.unmap = gpiochip_irq_unmap,
404
+
.xlate = tegra186_gpio_irq_domain_xlate,
405
+
};
406
+
407
+
static int tegra186_gpio_probe(struct platform_device *pdev)
408
+
{
409
+
unsigned int i, j, offset;
410
+
struct gpio_irq_chip *irq;
411
+
struct tegra_gpio *gpio;
412
+
struct resource *res;
413
+
char **names;
414
+
int err;
415
+
416
+
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
417
+
if (!gpio)
418
+
return -ENOMEM;
419
+
420
+
gpio->soc = of_device_get_match_data(&pdev->dev);
421
+
422
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
423
+
gpio->base = devm_ioremap_resource(&pdev->dev, res);
424
+
if (IS_ERR(gpio->base))
425
+
return PTR_ERR(gpio->base);
426
+
427
+
err = platform_irq_count(pdev);
428
+
if (err < 0)
429
+
return err;
430
+
431
+
gpio->num_irq = err;
432
+
433
+
gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
434
+
GFP_KERNEL);
435
+
if (!gpio->irq)
436
+
return -ENOMEM;
437
+
438
+
for (i = 0; i < gpio->num_irq; i++) {
439
+
err = platform_get_irq(pdev, i);
440
+
if (err < 0)
441
+
return err;
442
+
443
+
gpio->irq[i] = err;
444
+
}
445
+
446
+
gpio->gpio.label = gpio->soc->name;
447
+
gpio->gpio.parent = &pdev->dev;
448
+
449
+
gpio->gpio.get_direction = tegra186_gpio_get_direction;
450
+
gpio->gpio.direction_input = tegra186_gpio_direction_input;
451
+
gpio->gpio.direction_output = tegra186_gpio_direction_output;
452
+
gpio->gpio.get = tegra186_gpio_get,
453
+
gpio->gpio.set = tegra186_gpio_set;
454
+
455
+
gpio->gpio.base = -1;
456
+
457
+
for (i = 0; i < gpio->soc->num_ports; i++)
458
+
gpio->gpio.ngpio += gpio->soc->ports[i].pins;
459
+
460
+
names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
461
+
sizeof(*names), GFP_KERNEL);
462
+
if (!names)
463
+
return -ENOMEM;
464
+
465
+
for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
466
+
const struct tegra_gpio_port *port = &gpio->soc->ports[i];
467
+
char *name;
468
+
469
+
for (j = 0; j < port->pins; j++) {
470
+
name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
471
+
"P%s.%02x", port->name, j);
472
+
if (!name)
473
+
return -ENOMEM;
474
+
475
+
names[offset + j] = name;
476
+
}
477
+
478
+
offset += port->pins;
479
+
}
480
+
481
+
gpio->gpio.names = (const char * const *)names;
482
+
483
+
gpio->gpio.of_node = pdev->dev.of_node;
484
+
gpio->gpio.of_gpio_n_cells = 2;
485
+
gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
486
+
487
+
gpio->intc.name = pdev->dev.of_node->name;
488
+
gpio->intc.irq_ack = tegra186_irq_ack;
489
+
gpio->intc.irq_mask = tegra186_irq_mask;
490
+
gpio->intc.irq_unmask = tegra186_irq_unmask;
491
+
gpio->intc.irq_set_type = tegra186_irq_set_type;
492
+
493
+
irq = &gpio->gpio.irq;
494
+
irq->chip = &gpio->intc;
495
+
irq->domain_ops = &tegra186_gpio_irq_domain_ops;
496
+
irq->handler = handle_simple_irq;
497
+
irq->default_type = IRQ_TYPE_NONE;
498
+
irq->parent_handler = tegra186_gpio_irq;
499
+
irq->parent_handler_data = gpio;
500
+
irq->num_parents = gpio->num_irq;
501
+
irq->parents = gpio->irq;
502
+
503
+
irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
504
+
sizeof(*irq->map), GFP_KERNEL);
505
+
if (!irq->map)
506
+
return -ENOMEM;
507
+
508
+
for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
509
+
const struct tegra_gpio_port *port = &gpio->soc->ports[i];
510
+
511
+
for (j = 0; j < port->pins; j++)
512
+
irq->map[offset + j] = irq->parents[port->irq];
513
+
514
+
offset += port->pins;
515
+
}
516
+
517
+
platform_set_drvdata(pdev, gpio);
518
+
519
+
err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
520
+
if (err < 0)
521
+
return err;
522
+
523
+
return 0;
524
+
}
525
+
526
+
static int tegra186_gpio_remove(struct platform_device *pdev)
527
+
{
528
+
return 0;
529
+
}
530
+
531
+
#define TEGRA_MAIN_GPIO_PORT(port, base, count, controller) \
532
+
[TEGRA_MAIN_GPIO_PORT_##port] = { \
533
+
.name = #port, \
534
+
.offset = base, \
535
+
.pins = count, \
536
+
.irq = controller, \
537
+
}
538
+
539
+
static const struct tegra_gpio_port tegra186_main_ports[] = {
540
+
TEGRA_MAIN_GPIO_PORT( A, 0x2000, 7, 2),
541
+
TEGRA_MAIN_GPIO_PORT( B, 0x3000, 7, 3),
542
+
TEGRA_MAIN_GPIO_PORT( C, 0x3200, 7, 3),
543
+
TEGRA_MAIN_GPIO_PORT( D, 0x3400, 6, 3),
544
+
TEGRA_MAIN_GPIO_PORT( E, 0x2200, 8, 2),
545
+
TEGRA_MAIN_GPIO_PORT( F, 0x2400, 6, 2),
546
+
TEGRA_MAIN_GPIO_PORT( G, 0x4200, 6, 4),
547
+
TEGRA_MAIN_GPIO_PORT( H, 0x1000, 7, 1),
548
+
TEGRA_MAIN_GPIO_PORT( I, 0x0800, 8, 0),
549
+
TEGRA_MAIN_GPIO_PORT( J, 0x5000, 8, 5),
550
+
TEGRA_MAIN_GPIO_PORT( K, 0x5200, 1, 5),
551
+
TEGRA_MAIN_GPIO_PORT( L, 0x1200, 8, 1),
552
+
TEGRA_MAIN_GPIO_PORT( M, 0x5600, 6, 5),
553
+
TEGRA_MAIN_GPIO_PORT( N, 0x0000, 7, 0),
554
+
TEGRA_MAIN_GPIO_PORT( O, 0x0200, 4, 0),
555
+
TEGRA_MAIN_GPIO_PORT( P, 0x4000, 7, 4),
556
+
TEGRA_MAIN_GPIO_PORT( Q, 0x0400, 6, 0),
557
+
TEGRA_MAIN_GPIO_PORT( R, 0x0a00, 6, 0),
558
+
TEGRA_MAIN_GPIO_PORT( T, 0x0600, 4, 0),
559
+
TEGRA_MAIN_GPIO_PORT( X, 0x1400, 8, 1),
560
+
TEGRA_MAIN_GPIO_PORT( Y, 0x1600, 7, 1),
561
+
TEGRA_MAIN_GPIO_PORT(BB, 0x2600, 2, 2),
562
+
TEGRA_MAIN_GPIO_PORT(CC, 0x5400, 4, 5),
563
+
};
564
+
565
+
static const struct tegra_gpio_soc tegra186_main_soc = {
566
+
.num_ports = ARRAY_SIZE(tegra186_main_ports),
567
+
.ports = tegra186_main_ports,
568
+
.name = "tegra186-gpio",
569
+
};
570
+
571
+
#define TEGRA_AON_GPIO_PORT(port, base, count, controller) \
572
+
[TEGRA_AON_GPIO_PORT_##port] = { \
573
+
.name = #port, \
574
+
.offset = base, \
575
+
.pins = count, \
576
+
.irq = controller, \
577
+
}
578
+
579
+
static const struct tegra_gpio_port tegra186_aon_ports[] = {
580
+
TEGRA_AON_GPIO_PORT( S, 0x0200, 5, 0),
581
+
TEGRA_AON_GPIO_PORT( U, 0x0400, 6, 0),
582
+
TEGRA_AON_GPIO_PORT( V, 0x0800, 8, 0),
583
+
TEGRA_AON_GPIO_PORT( W, 0x0a00, 8, 0),
584
+
TEGRA_AON_GPIO_PORT( Z, 0x0e00, 4, 0),
585
+
TEGRA_AON_GPIO_PORT(AA, 0x0c00, 8, 0),
586
+
TEGRA_AON_GPIO_PORT(EE, 0x0600, 3, 0),
587
+
TEGRA_AON_GPIO_PORT(FF, 0x0000, 5, 0),
588
+
};
589
+
590
+
static const struct tegra_gpio_soc tegra186_aon_soc = {
591
+
.num_ports = ARRAY_SIZE(tegra186_aon_ports),
592
+
.ports = tegra186_aon_ports,
593
+
.name = "tegra186-gpio-aon",
594
+
};
595
+
596
+
static const struct of_device_id tegra186_gpio_of_match[] = {
597
+
{
598
+
.compatible = "nvidia,tegra186-gpio",
599
+
.data = &tegra186_main_soc
600
+
}, {
601
+
.compatible = "nvidia,tegra186-gpio-aon",
602
+
.data = &tegra186_aon_soc
603
+
}, {
604
+
/* sentinel */
605
+
}
606
+
};
607
+
608
+
static struct platform_driver tegra186_gpio_driver = {
609
+
.driver = {
610
+
.name = "tegra186-gpio",
611
+
.of_match_table = tegra186_gpio_of_match,
612
+
},
613
+
.probe = tegra186_gpio_probe,
614
+
.remove = tegra186_gpio_remove,
615
+
};
616
+
module_platform_driver(tegra186_gpio_driver);
617
+
618
+
MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
619
+
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
620
+
MODULE_LICENSE("GPL v2");
-13
drivers/gpio/gpio-thunderx.c
-13
drivers/gpio/gpio-thunderx.c
···
417
417
.flags = IRQCHIP_SET_TYPE_MASKED
418
418
};
419
419
420
-
static int thunderx_gpio_irq_map(struct irq_domain *d, unsigned int irq,
421
-
irq_hw_number_t hwirq)
422
-
{
423
-
struct thunderx_gpio *txgpio = d->host_data;
424
-
425
-
if (hwirq >= txgpio->chip.ngpio)
426
-
return -EINVAL;
427
-
if (!thunderx_gpio_is_gpio_nowarn(txgpio, hwirq))
428
-
return -EPERM;
429
-
return 0;
430
-
}
431
-
432
420
static int thunderx_gpio_irq_translate(struct irq_domain *d,
433
421
struct irq_fwspec *fwspec,
434
422
irq_hw_number_t *hwirq,
···
443
455
}
444
456
445
457
static const struct irq_domain_ops thunderx_gpio_irqd_ops = {
446
-
.map = thunderx_gpio_irq_map,
447
458
.alloc = thunderx_gpio_irq_alloc,
448
459
.translate = thunderx_gpio_irq_translate
449
460
};
+508
drivers/gpio/gpio-uniphier.c
+508
drivers/gpio/gpio-uniphier.c
···
1
+
/*
2
+
* Copyright (C) 2017 Socionext Inc.
3
+
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License version 2 as
7
+
* published by the Free Software Foundation.
8
+
*
9
+
* This program is distributed in the hope that it will be useful,
10
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
11
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
+
* GNU General Public License for more details.
13
+
*/
14
+
15
+
#include <linux/bitops.h>
16
+
#include <linux/gpio/driver.h>
17
+
#include <linux/irq.h>
18
+
#include <linux/irqdomain.h>
19
+
#include <linux/module.h>
20
+
#include <linux/of.h>
21
+
#include <linux/of_device.h>
22
+
#include <linux/of_irq.h>
23
+
#include <linux/platform_device.h>
24
+
#include <linux/spinlock.h>
25
+
#include <dt-bindings/gpio/uniphier-gpio.h>
26
+
27
+
#define UNIPHIER_GPIO_BANK_MASK \
28
+
GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0)
29
+
30
+
#define UNIPHIER_GPIO_IRQ_MAX_NUM 24
31
+
32
+
#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
33
+
#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
34
+
#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
35
+
#define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */
36
+
#define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */
37
+
#define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */
38
+
39
+
struct uniphier_gpio_priv {
40
+
struct gpio_chip chip;
41
+
struct irq_chip irq_chip;
42
+
struct irq_domain *domain;
43
+
void __iomem *regs;
44
+
spinlock_t lock;
45
+
u32 saved_vals[0];
46
+
};
47
+
48
+
static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
49
+
{
50
+
unsigned int reg;
51
+
52
+
reg = (bank + 1) * 8;
53
+
54
+
/*
55
+
* Unfortunately, the GPIO port registers are not contiguous because
56
+
* offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
57
+
*/
58
+
if (reg >= UNIPHIER_GPIO_IRQ_EN)
59
+
reg += 0x10;
60
+
61
+
return reg;
62
+
}
63
+
64
+
static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
65
+
unsigned int *bank, u32 *mask)
66
+
{
67
+
*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
68
+
*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
69
+
}
70
+
71
+
static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
72
+
unsigned int reg, u32 mask, u32 val)
73
+
{
74
+
unsigned long flags;
75
+
u32 tmp;
76
+
77
+
spin_lock_irqsave(&priv->lock, flags);
78
+
tmp = readl(priv->regs + reg);
79
+
tmp &= ~mask;
80
+
tmp |= mask & val;
81
+
writel(tmp, priv->regs + reg);
82
+
spin_unlock_irqrestore(&priv->lock, flags);
83
+
}
84
+
85
+
static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
86
+
unsigned int reg, u32 mask, u32 val)
87
+
{
88
+
struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
89
+
90
+
if (!mask)
91
+
return;
92
+
93
+
uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
94
+
mask, val);
95
+
}
96
+
97
+
static void uniphier_gpio_offset_write(struct gpio_chip *chip,
98
+
unsigned int offset, unsigned int reg,
99
+
int val)
100
+
{
101
+
unsigned int bank;
102
+
u32 mask;
103
+
104
+
uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
105
+
106
+
uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
107
+
}
108
+
109
+
static int uniphier_gpio_offset_read(struct gpio_chip *chip,
110
+
unsigned int offset, unsigned int reg)
111
+
{
112
+
struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
113
+
unsigned int bank, reg_offset;
114
+
u32 mask;
115
+
116
+
uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
117
+
reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
118
+
119
+
return !!(readl(priv->regs + reg_offset) & mask);
120
+
}
121
+
122
+
static int uniphier_gpio_get_direction(struct gpio_chip *chip,
123
+
unsigned int offset)
124
+
{
125
+
return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR);
126
+
}
127
+
128
+
static int uniphier_gpio_direction_input(struct gpio_chip *chip,
129
+
unsigned int offset)
130
+
{
131
+
uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);
132
+
133
+
return 0;
134
+
}
135
+
136
+
static int uniphier_gpio_direction_output(struct gpio_chip *chip,
137
+
unsigned int offset, int val)
138
+
{
139
+
uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
140
+
uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);
141
+
142
+
return 0;
143
+
}
144
+
145
+
static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
146
+
{
147
+
return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
148
+
}
149
+
150
+
static void uniphier_gpio_set(struct gpio_chip *chip,
151
+
unsigned int offset, int val)
152
+
{
153
+
uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
154
+
}
155
+
156
+
static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
157
+
unsigned long *mask, unsigned long *bits)
158
+
{
159
+
unsigned int bank, shift, bank_mask, bank_bits;
160
+
int i;
161
+
162
+
for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) {
163
+
bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
164
+
shift = i % BITS_PER_LONG;
165
+
bank_mask = (mask[BIT_WORD(i)] >> shift) &
166
+
UNIPHIER_GPIO_BANK_MASK;
167
+
bank_bits = bits[BIT_WORD(i)] >> shift;
168
+
169
+
uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
170
+
bank_mask, bank_bits);
171
+
}
172
+
}
173
+
174
+
static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
175
+
{
176
+
struct irq_fwspec fwspec;
177
+
178
+
if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
179
+
return -ENXIO;
180
+
181
+
fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
182
+
fwspec.param_count = 2;
183
+
fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
184
+
fwspec.param[1] = IRQ_TYPE_NONE;
185
+
186
+
return irq_create_fwspec_mapping(&fwspec);
187
+
}
188
+
189
+
static void uniphier_gpio_irq_mask(struct irq_data *data)
190
+
{
191
+
struct uniphier_gpio_priv *priv = data->chip_data;
192
+
u32 mask = BIT(data->hwirq);
193
+
194
+
uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
195
+
196
+
return irq_chip_mask_parent(data);
197
+
}
198
+
199
+
static void uniphier_gpio_irq_unmask(struct irq_data *data)
200
+
{
201
+
struct uniphier_gpio_priv *priv = data->chip_data;
202
+
u32 mask = BIT(data->hwirq);
203
+
204
+
uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
205
+
206
+
return irq_chip_unmask_parent(data);
207
+
}
208
+
209
+
static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
210
+
{
211
+
struct uniphier_gpio_priv *priv = data->chip_data;
212
+
u32 mask = BIT(data->hwirq);
213
+
u32 val = 0;
214
+
215
+
if (type == IRQ_TYPE_EDGE_BOTH) {
216
+
val = mask;
217
+
type = IRQ_TYPE_EDGE_FALLING;
218
+
}
219
+
220
+
uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
221
+
/* To enable both edge detection, the noise filter must be enabled. */
222
+
uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
223
+
224
+
return irq_chip_set_type_parent(data, type);
225
+
}
226
+
227
+
static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
228
+
unsigned int hwirq)
229
+
{
230
+
struct device_node *np = priv->chip.parent->of_node;
231
+
const __be32 *range;
232
+
u32 base, parent_base, size;
233
+
int len;
234
+
235
+
range = of_get_property(np, "socionext,interrupt-ranges", &len);
236
+
if (!range)
237
+
return -EINVAL;
238
+
239
+
len /= sizeof(*range);
240
+
241
+
for (; len >= 3; len -= 3) {
242
+
base = be32_to_cpu(*range++);
243
+
parent_base = be32_to_cpu(*range++);
244
+
size = be32_to_cpu(*range++);
245
+
246
+
if (base <= hwirq && hwirq < base + size)
247
+
return hwirq - base + parent_base;
248
+
}
249
+
250
+
return -ENOENT;
251
+
}
252
+
253
+
static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
254
+
struct irq_fwspec *fwspec,
255
+
unsigned long *out_hwirq,
256
+
unsigned int *out_type)
257
+
{
258
+
if (WARN_ON(fwspec->param_count < 2))
259
+
return -EINVAL;
260
+
261
+
*out_hwirq = fwspec->param[0];
262
+
*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
263
+
264
+
return 0;
265
+
}
266
+
267
+
static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
268
+
unsigned int virq,
269
+
unsigned int nr_irqs, void *arg)
270
+
{
271
+
struct uniphier_gpio_priv *priv = domain->host_data;
272
+
struct irq_fwspec parent_fwspec;
273
+
irq_hw_number_t hwirq;
274
+
unsigned int type;
275
+
int ret;
276
+
277
+
if (WARN_ON(nr_irqs != 1))
278
+
return -EINVAL;
279
+
280
+
ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
281
+
if (ret)
282
+
return ret;
283
+
284
+
ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
285
+
if (ret < 0)
286
+
return ret;
287
+
288
+
/* parent is UniPhier AIDET */
289
+
parent_fwspec.fwnode = domain->parent->fwnode;
290
+
parent_fwspec.param_count = 2;
291
+
parent_fwspec.param[0] = ret;
292
+
parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
293
+
IRQ_TYPE_EDGE_FALLING : type;
294
+
295
+
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
296
+
&priv->irq_chip, priv);
297
+
if (ret)
298
+
return ret;
299
+
300
+
return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
301
+
}
302
+
303
+
static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
304
+
struct irq_data *data, bool early)
305
+
{
306
+
struct uniphier_gpio_priv *priv = domain->host_data;
307
+
struct gpio_chip *chip = &priv->chip;
308
+
309
+
gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
310
+
return 0;
311
+
}
312
+
313
+
static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
314
+
struct irq_data *data)
315
+
{
316
+
struct uniphier_gpio_priv *priv = domain->host_data;
317
+
struct gpio_chip *chip = &priv->chip;
318
+
319
+
gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
320
+
}
321
+
322
+
static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
323
+
.alloc = uniphier_gpio_irq_domain_alloc,
324
+
.free = irq_domain_free_irqs_common,
325
+
.activate = uniphier_gpio_irq_domain_activate,
326
+
.deactivate = uniphier_gpio_irq_domain_deactivate,
327
+
.translate = uniphier_gpio_irq_domain_translate,
328
+
};
329
+
330
+
static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
331
+
{
332
+
/*
333
+
* Due to the hardware design, the noise filter must be enabled to
334
+
* detect both edge interrupts. This filter is intended to remove the
335
+
* noise from the irq lines. It does not work for GPIO input, so GPIO
336
+
* debounce is not supported. Unfortunately, the filter period is
337
+
* shared among all irq lines. Just choose a sensible period here.
338
+
*/
339
+
writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
340
+
}
341
+
342
+
static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
343
+
{
344
+
return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
345
+
}
346
+
347
+
static int uniphier_gpio_probe(struct platform_device *pdev)
348
+
{
349
+
struct device *dev = &pdev->dev;
350
+
struct device_node *parent_np;
351
+
struct irq_domain *parent_domain;
352
+
struct uniphier_gpio_priv *priv;
353
+
struct gpio_chip *chip;
354
+
struct irq_chip *irq_chip;
355
+
struct resource *regs;
356
+
unsigned int nregs;
357
+
u32 ngpios;
358
+
int ret;
359
+
360
+
parent_np = of_irq_find_parent(dev->of_node);
361
+
if (!parent_np)
362
+
return -ENXIO;
363
+
364
+
parent_domain = irq_find_host(parent_np);
365
+
of_node_put(parent_np);
366
+
if (!parent_domain)
367
+
return -EPROBE_DEFER;
368
+
369
+
ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
370
+
if (ret)
371
+
return ret;
372
+
373
+
nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
374
+
priv = devm_kzalloc(dev,
375
+
sizeof(*priv) + sizeof(priv->saved_vals[0]) * nregs,
376
+
GFP_KERNEL);
377
+
if (!priv)
378
+
return -ENOMEM;
379
+
380
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
381
+
priv->regs = devm_ioremap_resource(dev, regs);
382
+
if (IS_ERR(priv->regs))
383
+
return PTR_ERR(priv->regs);
384
+
385
+
spin_lock_init(&priv->lock);
386
+
387
+
chip = &priv->chip;
388
+
chip->label = dev_name(dev);
389
+
chip->parent = dev;
390
+
chip->request = gpiochip_generic_request;
391
+
chip->free = gpiochip_generic_free;
392
+
chip->get_direction = uniphier_gpio_get_direction;
393
+
chip->direction_input = uniphier_gpio_direction_input;
394
+
chip->direction_output = uniphier_gpio_direction_output;
395
+
chip->get = uniphier_gpio_get;
396
+
chip->set = uniphier_gpio_set;
397
+
chip->set_multiple = uniphier_gpio_set_multiple;
398
+
chip->to_irq = uniphier_gpio_to_irq;
399
+
chip->base = -1;
400
+
chip->ngpio = ngpios;
401
+
402
+
irq_chip = &priv->irq_chip;
403
+
irq_chip->name = dev_name(dev);
404
+
irq_chip->irq_mask = uniphier_gpio_irq_mask;
405
+
irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
406
+
irq_chip->irq_eoi = irq_chip_eoi_parent;
407
+
irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
408
+
irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
409
+
410
+
uniphier_gpio_hw_init(priv);
411
+
412
+
ret = devm_gpiochip_add_data(dev, chip, priv);
413
+
if (ret)
414
+
return ret;
415
+
416
+
priv->domain = irq_domain_create_hierarchy(
417
+
parent_domain, 0,
418
+
UNIPHIER_GPIO_IRQ_MAX_NUM,
419
+
of_node_to_fwnode(dev->of_node),
420
+
&uniphier_gpio_irq_domain_ops, priv);
421
+
if (!priv->domain)
422
+
return -ENOMEM;
423
+
424
+
platform_set_drvdata(pdev, priv);
425
+
426
+
return 0;
427
+
}
428
+
429
+
static int uniphier_gpio_remove(struct platform_device *pdev)
430
+
{
431
+
struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);
432
+
433
+
irq_domain_remove(priv->domain);
434
+
435
+
return 0;
436
+
}
437
+
438
+
static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
439
+
{
440
+
struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
441
+
unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
442
+
u32 *val = priv->saved_vals;
443
+
unsigned int reg;
444
+
int i;
445
+
446
+
for (i = 0; i < nbanks; i++) {
447
+
reg = uniphier_gpio_bank_to_reg(i);
448
+
449
+
*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
450
+
*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
451
+
}
452
+
453
+
*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
454
+
*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
455
+
*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
456
+
457
+
return 0;
458
+
}
459
+
460
+
static int __maybe_unused uniphier_gpio_resume(struct device *dev)
461
+
{
462
+
struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
463
+
unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
464
+
const u32 *val = priv->saved_vals;
465
+
unsigned int reg;
466
+
int i;
467
+
468
+
for (i = 0; i < nbanks; i++) {
469
+
reg = uniphier_gpio_bank_to_reg(i);
470
+
471
+
writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
472
+
writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
473
+
}
474
+
475
+
writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
476
+
writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
477
+
writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
478
+
479
+
uniphier_gpio_hw_init(priv);
480
+
481
+
return 0;
482
+
}
483
+
484
+
static const struct dev_pm_ops uniphier_gpio_pm_ops = {
485
+
SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
486
+
uniphier_gpio_resume)
487
+
};
488
+
489
+
static const struct of_device_id uniphier_gpio_match[] = {
490
+
{ .compatible = "socionext,uniphier-gpio" },
491
+
{ /* sentinel */ }
492
+
};
493
+
MODULE_DEVICE_TABLE(of, uniphier_gpio_match);
494
+
495
+
static struct platform_driver uniphier_gpio_driver = {
496
+
.probe = uniphier_gpio_probe,
497
+
.remove = uniphier_gpio_remove,
498
+
.driver = {
499
+
.name = "uniphier-gpio",
500
+
.of_match_table = uniphier_gpio_match,
501
+
.pm = &uniphier_gpio_pm_ops,
502
+
},
503
+
};
504
+
module_platform_driver(uniphier_gpio_driver);
505
+
506
+
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
507
+
MODULE_DESCRIPTION("UniPhier GPIO driver");
508
+
MODULE_LICENSE("GPL");
+1
-1
drivers/gpio/gpio-vf610.c
+1
-1
drivers/gpio/gpio-vf610.c
···
160
160
for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
161
161
vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
162
162
163
-
generic_handle_irq(irq_find_mapping(port->gc.irqdomain, pin));
163
+
generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
164
164
}
165
165
166
166
chained_irq_exit(chip, desc);
+1
-1
drivers/gpio/gpio-wcove.c
+1
-1
drivers/gpio/gpio-wcove.c
···
350
350
offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
351
351
mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
352
352
BIT(gpio);
353
-
virq = irq_find_mapping(wg->chip.irqdomain, gpio);
353
+
virq = irq_find_mapping(wg->chip.irq.domain, gpio);
354
354
handle_nested_irq(virq);
355
355
regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
356
356
mask, mask);
+1
-1
drivers/gpio/gpio-ws16c48.c
+1
-1
drivers/gpio/gpio-ws16c48.c
+3
-12
drivers/gpio/gpio-xgene-sb.c
+3
-12
drivers/gpio/gpio-xgene-sb.c
···
130
130
(gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
131
131
return -ENXIO;
132
132
133
-
if (gc->parent->of_node)
134
-
fwspec.fwnode = of_node_to_fwnode(gc->parent->of_node);
135
-
else
136
-
fwspec.fwnode = gc->parent->fwnode;
133
+
fwspec.fwnode = gc->parent->fwnode;
137
134
fwspec.param_count = 2;
138
135
fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
139
136
fwspec.param[1] = IRQ_TYPE_NONE;
···
230
233
struct resource *res;
231
234
void __iomem *regs;
232
235
struct irq_domain *parent_domain = NULL;
233
-
struct fwnode_handle *fwnode;
234
236
u32 val32;
235
237
236
238
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
···
283
287
284
288
platform_set_drvdata(pdev, priv);
285
289
286
-
if (pdev->dev.of_node)
287
-
fwnode = of_node_to_fwnode(pdev->dev.of_node);
288
-
else
289
-
fwnode = pdev->dev.fwnode;
290
-
291
290
priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
292
-
0, priv->nirq, fwnode,
291
+
0, priv->nirq, pdev->dev.fwnode,
293
292
&xgene_gpio_sb_domain_ops, priv);
294
293
if (!priv->irq_domain)
295
294
return -ENODEV;
296
295
297
-
priv->gc.irqdomain = priv->irq_domain;
296
+
priv->gc.irq.domain = priv->irq_domain;
298
297
299
298
ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
300
299
if (ret) {
+1
-1
drivers/gpio/gpio-xlp.c
+1
-1
drivers/gpio/gpio-xlp.c
+1
-1
drivers/gpio/gpio-zx.c
+1
-1
drivers/gpio/gpio-zx.c
+1
-1
drivers/gpio/gpio-zynq.c
+1
-1
drivers/gpio/gpio-zynq.c
+2
-2
drivers/gpio/gpiolib-of.c
+2
-2
drivers/gpio/gpiolib-of.c
+423
-159
drivers/gpio/gpiolib.c
+423
-159
drivers/gpio/gpiolib.c
···
72
72
LIST_HEAD(gpio_devices);
73
73
74
74
static void gpiochip_free_hogs(struct gpio_chip *chip);
75
+
static int gpiochip_add_irqchip(struct gpio_chip *gpiochip,
76
+
struct lock_class_key *key);
75
77
static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip);
76
78
static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip);
77
79
static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip);
···
367
365
struct linehandle_state *lh = filep->private_data;
368
366
void __user *ip = (void __user *)arg;
369
367
struct gpiohandle_data ghd;
368
+
int vals[GPIOHANDLES_MAX];
370
369
int i;
371
370
372
371
if (cmd == GPIOHANDLE_GET_LINE_VALUES_IOCTL) {
373
-
int val;
372
+
/* TODO: check if descriptors are really input */
373
+
int ret = gpiod_get_array_value_complex(false,
374
+
true,
375
+
lh->numdescs,
376
+
lh->descs,
377
+
vals);
378
+
if (ret)
379
+
return ret;
374
380
375
381
memset(&ghd, 0, sizeof(ghd));
376
-
377
-
/* TODO: check if descriptors are really input */
378
-
for (i = 0; i < lh->numdescs; i++) {
379
-
val = gpiod_get_value_cansleep(lh->descs[i]);
380
-
if (val < 0)
381
-
return val;
382
-
ghd.values[i] = val;
383
-
}
382
+
for (i = 0; i < lh->numdescs; i++)
383
+
ghd.values[i] = vals[i];
384
384
385
385
if (copy_to_user(ip, &ghd, sizeof(ghd)))
386
386
return -EFAULT;
387
387
388
388
return 0;
389
389
} else if (cmd == GPIOHANDLE_SET_LINE_VALUES_IOCTL) {
390
-
int vals[GPIOHANDLES_MAX];
391
-
392
390
/* TODO: check if descriptors are really output */
393
391
if (copy_from_user(&ghd, ip, sizeof(ghd)))
394
392
return -EFAULT;
···
446
444
struct linehandle_state *lh;
447
445
struct file *file;
448
446
int fd, i, ret;
447
+
u32 lflags;
449
448
450
449
if (copy_from_user(&handlereq, ip, sizeof(handlereq)))
451
450
return -EFAULT;
452
451
if ((handlereq.lines == 0) || (handlereq.lines > GPIOHANDLES_MAX))
452
+
return -EINVAL;
453
+
454
+
lflags = handlereq.flags;
455
+
456
+
/* Return an error if an unknown flag is set */
457
+
if (lflags & ~GPIOHANDLE_REQUEST_VALID_FLAGS)
458
+
return -EINVAL;
459
+
460
+
/* OPEN_DRAIN and OPEN_SOURCE flags only make sense for output mode. */
461
+
if (!(lflags & GPIOHANDLE_REQUEST_OUTPUT) &&
462
+
((lflags & GPIOHANDLE_REQUEST_OPEN_DRAIN) ||
463
+
(lflags & GPIOHANDLE_REQUEST_OPEN_SOURCE)))
453
464
return -EINVAL;
454
465
455
466
lh = kzalloc(sizeof(*lh), GFP_KERNEL);
···
485
470
/* Request each GPIO */
486
471
for (i = 0; i < handlereq.lines; i++) {
487
472
u32 offset = handlereq.lineoffsets[i];
488
-
u32 lflags = handlereq.flags;
489
473
struct gpio_desc *desc;
490
474
491
475
if (offset >= gdev->ngpio) {
492
-
ret = -EINVAL;
493
-
goto out_free_descs;
494
-
}
495
-
496
-
/* Return an error if a unknown flag is set */
497
-
if (lflags & ~GPIOHANDLE_REQUEST_VALID_FLAGS) {
498
476
ret = -EINVAL;
499
477
goto out_free_descs;
500
478
}
···
1099
1091
}
1100
1092
}
1101
1093
1102
-
/**
1103
-
* gpiochip_add_data() - register a gpio_chip
1104
-
* @chip: the chip to register, with chip->base initialized
1105
-
* @data: driver-private data associated with this chip
1106
-
*
1107
-
* Context: potentially before irqs will work
1108
-
*
1109
-
* When gpiochip_add_data() is called very early during boot, so that GPIOs
1110
-
* can be freely used, the chip->parent device must be registered before
1111
-
* the gpio framework's arch_initcall(). Otherwise sysfs initialization
1112
-
* for GPIOs will fail rudely.
1113
-
*
1114
-
* gpiochip_add_data() must only be called after gpiolib initialization,
1115
-
* ie after core_initcall().
1116
-
*
1117
-
* If chip->base is negative, this requests dynamic assignment of
1118
-
* a range of valid GPIOs.
1119
-
*
1120
-
* Returns:
1121
-
* A negative errno if the chip can't be registered, such as because the
1122
-
* chip->base is invalid or already associated with a different chip.
1123
-
* Otherwise it returns zero as a success code.
1124
-
*/
1125
-
int gpiochip_add_data(struct gpio_chip *chip, void *data)
1094
+
int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
1095
+
struct lock_class_key *key)
1126
1096
{
1127
1097
unsigned long flags;
1128
1098
int status = 0;
···
1246
1260
if (status)
1247
1261
goto err_remove_from_list;
1248
1262
1263
+
status = gpiochip_add_irqchip(chip, key);
1264
+
if (status)
1265
+
goto err_remove_chip;
1266
+
1249
1267
status = of_gpiochip_add(chip);
1250
1268
if (status)
1251
1269
goto err_remove_chip;
···
1293
1303
kfree(gdev);
1294
1304
return status;
1295
1305
}
1296
-
EXPORT_SYMBOL_GPL(gpiochip_add_data);
1306
+
EXPORT_SYMBOL_GPL(gpiochip_add_data_with_key);
1297
1307
1298
1308
/**
1299
1309
* gpiochip_get_data() - get per-subdriver data for the chip
···
1488
1498
1489
1499
static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
1490
1500
{
1491
-
if (!gpiochip->irq_need_valid_mask)
1501
+
if (!gpiochip->irq.need_valid_mask)
1492
1502
return 0;
1493
1503
1494
-
gpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
1504
+
gpiochip->irq.valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
1495
1505
sizeof(long), GFP_KERNEL);
1496
-
if (!gpiochip->irq_valid_mask)
1506
+
if (!gpiochip->irq.valid_mask)
1497
1507
return -ENOMEM;
1498
1508
1499
1509
/* Assume by default all GPIOs are valid */
1500
-
bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);
1510
+
bitmap_fill(gpiochip->irq.valid_mask, gpiochip->ngpio);
1501
1511
1502
1512
return 0;
1503
1513
}
1504
1514
1505
1515
static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
1506
1516
{
1507
-
kfree(gpiochip->irq_valid_mask);
1508
-
gpiochip->irq_valid_mask = NULL;
1517
+
kfree(gpiochip->irq.valid_mask);
1518
+
gpiochip->irq.valid_mask = NULL;
1509
1519
}
1510
1520
1511
1521
static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
1512
1522
unsigned int offset)
1513
1523
{
1514
1524
/* No mask means all valid */
1515
-
if (likely(!gpiochip->irq_valid_mask))
1525
+
if (likely(!gpiochip->irq.valid_mask))
1516
1526
return true;
1517
-
return test_bit(offset, gpiochip->irq_valid_mask);
1527
+
return test_bit(offset, gpiochip->irq.valid_mask);
1518
1528
}
1519
1529
1520
1530
/**
···
1534
1544
{
1535
1545
unsigned int offset;
1536
1546
1537
-
if (!gpiochip->irqdomain) {
1547
+
if (!gpiochip->irq.domain) {
1538
1548
chip_err(gpiochip, "called %s before setting up irqchip\n",
1539
1549
__func__);
1540
1550
return;
···
1554
1564
irq_set_chained_handler_and_data(parent_irq, parent_handler,
1555
1565
gpiochip);
1556
1566
1557
-
gpiochip->irq_chained_parent = parent_irq;
1567
+
gpiochip->irq.parents = &parent_irq;
1568
+
gpiochip->irq.num_parents = 1;
1558
1569
}
1559
1570
1560
1571
/* Set the parent IRQ for all affected IRQs */
1561
1572
for (offset = 0; offset < gpiochip->ngpio; offset++) {
1562
1573
if (!gpiochip_irqchip_irq_valid(gpiochip, offset))
1563
1574
continue;
1564
-
irq_set_parent(irq_find_mapping(gpiochip->irqdomain, offset),
1575
+
irq_set_parent(irq_find_mapping(gpiochip->irq.domain, offset),
1565
1576
parent_irq);
1566
1577
}
1567
1578
}
···
1582
1591
unsigned int parent_irq,
1583
1592
irq_flow_handler_t parent_handler)
1584
1593
{
1594
+
if (gpiochip->irq.threaded) {
1595
+
chip_err(gpiochip, "tried to chain a threaded gpiochip\n");
1596
+
return;
1597
+
}
1598
+
1585
1599
gpiochip_set_cascaded_irqchip(gpiochip, irqchip, parent_irq,
1586
1600
parent_handler);
1587
1601
}
···
1603
1607
struct irq_chip *irqchip,
1604
1608
unsigned int parent_irq)
1605
1609
{
1606
-
if (!gpiochip->irq_nested) {
1607
-
chip_err(gpiochip, "tried to nest a chained gpiochip\n");
1608
-
return;
1609
-
}
1610
1610
gpiochip_set_cascaded_irqchip(gpiochip, irqchip, parent_irq,
1611
1611
NULL);
1612
1612
}
···
1618
1626
* gpiochip by assigning the gpiochip as chip data, and using the irqchip
1619
1627
* stored inside the gpiochip.
1620
1628
*/
1621
-
static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
1622
-
irq_hw_number_t hwirq)
1629
+
int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
1630
+
irq_hw_number_t hwirq)
1623
1631
{
1624
1632
struct gpio_chip *chip = d->host_data;
1633
+
int err = 0;
1625
1634
1626
1635
if (!gpiochip_irqchip_irq_valid(chip, hwirq))
1627
1636
return -ENXIO;
···
1632
1639
* This lock class tells lockdep that GPIO irqs are in a different
1633
1640
* category than their parents, so it won't report false recursion.
1634
1641
*/
1635
-
irq_set_lockdep_class(irq, chip->lock_key);
1636
-
irq_set_chip_and_handler(irq, chip->irqchip, chip->irq_handler);
1642
+
irq_set_lockdep_class(irq, chip->irq.lock_key);
1643
+
irq_set_chip_and_handler(irq, chip->irq.chip, chip->irq.handler);
1637
1644
/* Chips that use nested thread handlers have them marked */
1638
-
if (chip->irq_nested)
1645
+
if (chip->irq.threaded)
1639
1646
irq_set_nested_thread(irq, 1);
1640
1647
irq_set_noprobe(irq);
1648
+
1649
+
if (chip->irq.num_parents == 1)
1650
+
err = irq_set_parent(irq, chip->irq.parents[0]);
1651
+
else if (chip->irq.map)
1652
+
err = irq_set_parent(irq, chip->irq.map[hwirq]);
1653
+
1654
+
if (err < 0)
1655
+
return err;
1641
1656
1642
1657
/*
1643
1658
* No set-up of the hardware will happen if IRQ_TYPE_NONE
1644
1659
* is passed as default type.
1645
1660
*/
1646
-
if (chip->irq_default_type != IRQ_TYPE_NONE)
1647
-
irq_set_irq_type(irq, chip->irq_default_type);
1661
+
if (chip->irq.default_type != IRQ_TYPE_NONE)
1662
+
irq_set_irq_type(irq, chip->irq.default_type);
1648
1663
1649
1664
return 0;
1650
1665
}
1666
+
EXPORT_SYMBOL_GPL(gpiochip_irq_map);
1651
1667
1652
-
static void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)
1668
+
void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)
1653
1669
{
1654
1670
struct gpio_chip *chip = d->host_data;
1655
1671
1656
-
if (chip->irq_nested)
1672
+
if (chip->irq.threaded)
1657
1673
irq_set_nested_thread(irq, 0);
1658
1674
irq_set_chip_and_handler(irq, NULL, NULL);
1659
1675
irq_set_chip_data(irq, NULL);
1660
1676
}
1677
+
EXPORT_SYMBOL_GPL(gpiochip_irq_unmap);
1661
1678
1662
1679
static const struct irq_domain_ops gpiochip_domain_ops = {
1663
1680
.map = gpiochip_irq_map,
···
1705
1702
{
1706
1703
if (!gpiochip_irqchip_irq_valid(chip, offset))
1707
1704
return -ENXIO;
1708
-
return irq_create_mapping(chip->irqdomain, offset);
1705
+
1706
+
return irq_create_mapping(chip->irq.domain, offset);
1707
+
}
1708
+
1709
+
/**
1710
+
* gpiochip_add_irqchip() - adds an IRQ chip to a GPIO chip
1711
+
* @gpiochip: the GPIO chip to add the IRQ chip to
1712
+
* @lock_key: lockdep class
1713
+
*/
1714
+
static int gpiochip_add_irqchip(struct gpio_chip *gpiochip,
1715
+
struct lock_class_key *lock_key)
1716
+
{
1717
+
struct irq_chip *irqchip = gpiochip->irq.chip;
1718
+
const struct irq_domain_ops *ops;
1719
+
struct device_node *np;
1720
+
unsigned int type;
1721
+
unsigned int i;
1722
+
1723
+
if (!irqchip)
1724
+
return 0;
1725
+
1726
+
if (gpiochip->irq.parent_handler && gpiochip->can_sleep) {
1727
+
chip_err(gpiochip, "you cannot have chained interrupts on a "
1728
+
"chip that may sleep\n");
1729
+
return -EINVAL;
1730
+
}
1731
+
1732
+
np = gpiochip->gpiodev->dev.of_node;
1733
+
type = gpiochip->irq.default_type;
1734
+
1735
+
/*
1736
+
* Specifying a default trigger is a terrible idea if DT or ACPI is
1737
+
* used to configure the interrupts, as you may end up with
1738
+
* conflicting triggers. Tell the user, and reset to NONE.
1739
+
*/
1740
+
if (WARN(np && type != IRQ_TYPE_NONE,
1741
+
"%s: Ignoring %u default trigger\n", np->full_name, type))
1742
+
type = IRQ_TYPE_NONE;
1743
+
1744
+
if (has_acpi_companion(gpiochip->parent) && type != IRQ_TYPE_NONE) {
1745
+
acpi_handle_warn(ACPI_HANDLE(gpiochip->parent),
1746
+
"Ignoring %u default trigger\n", type);
1747
+
type = IRQ_TYPE_NONE;
1748
+
}
1749
+
1750
+
gpiochip->to_irq = gpiochip_to_irq;
1751
+
gpiochip->irq.default_type = type;
1752
+
gpiochip->irq.lock_key = lock_key;
1753
+
1754
+
if (gpiochip->irq.domain_ops)
1755
+
ops = gpiochip->irq.domain_ops;
1756
+
else
1757
+
ops = &gpiochip_domain_ops;
1758
+
1759
+
gpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio,
1760
+
gpiochip->irq.first,
1761
+
ops, gpiochip);
1762
+
if (!gpiochip->irq.domain)
1763
+
return -EINVAL;
1764
+
1765
+
/*
1766
+
* It is possible for a driver to override this, but only if the
1767
+
* alternative functions are both implemented.
1768
+
*/
1769
+
if (!irqchip->irq_request_resources &&
1770
+
!irqchip->irq_release_resources) {
1771
+
irqchip->irq_request_resources = gpiochip_irq_reqres;
1772
+
irqchip->irq_release_resources = gpiochip_irq_relres;
1773
+
}
1774
+
1775
+
if (gpiochip->irq.parent_handler) {
1776
+
void *data = gpiochip->irq.parent_handler_data ?: gpiochip;
1777
+
1778
+
for (i = 0; i < gpiochip->irq.num_parents; i++) {
1779
+
/*
1780
+
* The parent IRQ chip is already using the chip_data
1781
+
* for this IRQ chip, so our callbacks simply use the
1782
+
* handler_data.
1783
+
*/
1784
+
irq_set_chained_handler_and_data(gpiochip->irq.parents[i],
1785
+
gpiochip->irq.parent_handler,
1786
+
data);
1787
+
}
1788
+
}
1789
+
1790
+
acpi_gpiochip_request_interrupts(gpiochip);
1791
+
1792
+
return 0;
1709
1793
}
1710
1794
1711
1795
/**
···
1807
1717
1808
1718
acpi_gpiochip_free_interrupts(gpiochip);
1809
1719
1810
-
if (gpiochip->irq_chained_parent) {
1811
-
irq_set_chained_handler(gpiochip->irq_chained_parent, NULL);
1812
-
irq_set_handler_data(gpiochip->irq_chained_parent, NULL);
1720
+
if (gpiochip->irq.chip && gpiochip->irq.parent_handler) {
1721
+
struct gpio_irq_chip *irq = &gpiochip->irq;
1722
+
unsigned int i;
1723
+
1724
+
for (i = 0; i < irq->num_parents; i++)
1725
+
irq_set_chained_handler_and_data(irq->parents[i],
1726
+
NULL, NULL);
1813
1727
}
1814
1728
1815
1729
/* Remove all IRQ mappings and delete the domain */
1816
-
if (gpiochip->irqdomain) {
1730
+
if (gpiochip->irq.domain) {
1731
+
unsigned int irq;
1732
+
1817
1733
for (offset = 0; offset < gpiochip->ngpio; offset++) {
1818
1734
if (!gpiochip_irqchip_irq_valid(gpiochip, offset))
1819
1735
continue;
1820
-
irq_dispose_mapping(
1821
-
irq_find_mapping(gpiochip->irqdomain, offset));
1736
+
1737
+
irq = irq_find_mapping(gpiochip->irq.domain, offset);
1738
+
irq_dispose_mapping(irq);
1822
1739
}
1823
-
irq_domain_remove(gpiochip->irqdomain);
1740
+
1741
+
irq_domain_remove(gpiochip->irq.domain);
1824
1742
}
1825
1743
1826
-
if (gpiochip->irqchip) {
1827
-
gpiochip->irqchip->irq_request_resources = NULL;
1828
-
gpiochip->irqchip->irq_release_resources = NULL;
1829
-
gpiochip->irqchip = NULL;
1744
+
if (gpiochip->irq.chip) {
1745
+
gpiochip->irq.chip->irq_request_resources = NULL;
1746
+
gpiochip->irq.chip->irq_release_resources = NULL;
1747
+
gpiochip->irq.chip = NULL;
1830
1748
}
1831
1749
1832
1750
gpiochip_irqchip_free_valid_mask(gpiochip);
···
1849
1751
* @handler: the irq handler to use (often a predefined irq core function)
1850
1752
* @type: the default type for IRQs on this irqchip, pass IRQ_TYPE_NONE
1851
1753
* to have the core avoid setting up any default type in the hardware.
1852
-
* @nested: whether this is a nested irqchip calling handle_nested_irq()
1853
-
* in its IRQ handler
1754
+
* @threaded: whether this irqchip uses a nested thread handler
1854
1755
* @lock_key: lockdep class
1855
1756
*
1856
1757
* This function closely associates a certain irqchip with a certain
···
1871
1774
unsigned int first_irq,
1872
1775
irq_flow_handler_t handler,
1873
1776
unsigned int type,
1874
-
bool nested,
1777
+
bool threaded,
1875
1778
struct lock_class_key *lock_key)
1876
1779
{
1877
1780
struct device_node *of_node;
···
1883
1786
pr_err("missing gpiochip .dev parent pointer\n");
1884
1787
return -EINVAL;
1885
1788
}
1886
-
gpiochip->irq_nested = nested;
1789
+
gpiochip->irq.threaded = threaded;
1887
1790
of_node = gpiochip->parent->of_node;
1888
1791
#ifdef CONFIG_OF_GPIO
1889
1792
/*
···
1908
1811
type = IRQ_TYPE_NONE;
1909
1812
}
1910
1813
1911
-
gpiochip->irqchip = irqchip;
1912
-
gpiochip->irq_handler = handler;
1913
-
gpiochip->irq_default_type = type;
1814
+
gpiochip->irq.chip = irqchip;
1815
+
gpiochip->irq.handler = handler;
1816
+
gpiochip->irq.default_type = type;
1914
1817
gpiochip->to_irq = gpiochip_to_irq;
1915
-
gpiochip->lock_key = lock_key;
1916
-
gpiochip->irqdomain = irq_domain_add_simple(of_node,
1818
+
gpiochip->irq.lock_key = lock_key;
1819
+
gpiochip->irq.domain = irq_domain_add_simple(of_node,
1917
1820
gpiochip->ngpio, first_irq,
1918
1821
&gpiochip_domain_ops, gpiochip);
1919
-
if (!gpiochip->irqdomain) {
1920
-
gpiochip->irqchip = NULL;
1822
+
if (!gpiochip->irq.domain) {
1823
+
gpiochip->irq.chip = NULL;
1921
1824
return -EINVAL;
1922
1825
}
1923
1826
···
1938
1841
EXPORT_SYMBOL_GPL(gpiochip_irqchip_add_key);
1939
1842
1940
1843
#else /* CONFIG_GPIOLIB_IRQCHIP */
1844
+
1845
+
static inline int gpiochip_add_irqchip(struct gpio_chip *gpiochip,
1846
+
struct lock_class_key *key)
1847
+
{
1848
+
return 0;
1849
+
}
1941
1850
1942
1851
static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) {}
1943
1852
static inline int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
···
2116
2013
* on each other, and help provide better diagnostics in debugfs.
2117
2014
* They're called even less than the "set direction" calls.
2118
2015
*/
2119
-
static int __gpiod_request(struct gpio_desc *desc, const char *label)
2016
+
static int gpiod_request_commit(struct gpio_desc *desc, const char *label)
2120
2017
{
2121
2018
struct gpio_chip *chip = desc->gdev->chip;
2122
2019
int status;
···
2209
2106
gdev = desc->gdev;
2210
2107
2211
2108
if (try_module_get(gdev->owner)) {
2212
-
status = __gpiod_request(desc, label);
2109
+
status = gpiod_request_commit(desc, label);
2213
2110
if (status < 0)
2214
2111
module_put(gdev->owner);
2215
2112
else
···
2222
2119
return status;
2223
2120
}
2224
2121
2225
-
static bool __gpiod_free(struct gpio_desc *desc)
2122
+
static bool gpiod_free_commit(struct gpio_desc *desc)
2226
2123
{
2227
2124
bool ret = false;
2228
2125
unsigned long flags;
···
2257
2154
2258
2155
void gpiod_free(struct gpio_desc *desc)
2259
2156
{
2260
-
if (desc && desc->gdev && __gpiod_free(desc)) {
2157
+
if (desc && desc->gdev && gpiod_free_commit(desc)) {
2261
2158
module_put(desc->gdev->owner);
2262
2159
put_device(&desc->gdev->dev);
2263
2160
} else {
···
2320
2217
return desc;
2321
2218
}
2322
2219
2323
-
err = __gpiod_request(desc, label);
2220
+
err = gpiod_request_commit(desc, label);
2324
2221
if (err < 0)
2325
2222
return ERR_PTR(err);
2326
2223
···
2338
2235
void gpiochip_free_own_desc(struct gpio_desc *desc)
2339
2236
{
2340
2237
if (desc)
2341
-
__gpiod_free(desc);
2238
+
gpiod_free_commit(desc);
2342
2239
}
2343
2240
EXPORT_SYMBOL_GPL(gpiochip_free_own_desc);
2344
2241
···
2394
2291
return gc->set_config ? gc->set_config(gc, offset, config) : -ENOTSUPP;
2395
2292
}
2396
2293
2397
-
static int _gpiod_direction_output_raw(struct gpio_desc *desc, int value)
2294
+
static int gpiod_direction_output_raw_commit(struct gpio_desc *desc, int value)
2398
2295
{
2399
2296
struct gpio_chip *gc = desc->gdev->chip;
2400
2297
int val = !!value;
2401
2298
int ret;
2402
2299
2403
-
/* GPIOs used for IRQs shall not be set as output */
2404
-
if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
2405
-
gpiod_err(desc,
2406
-
"%s: tried to set a GPIO tied to an IRQ as output\n",
2407
-
__func__);
2408
-
return -EIO;
2409
-
}
2410
-
2411
-
if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
2412
-
/* First see if we can enable open drain in hardware */
2413
-
ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
2414
-
PIN_CONFIG_DRIVE_OPEN_DRAIN);
2415
-
if (!ret)
2416
-
goto set_output_value;
2417
-
/* Emulate open drain by not actively driving the line high */
2418
-
if (val)
2419
-
return gpiod_direction_input(desc);
2420
-
}
2421
-
else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) {
2422
-
ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
2423
-
PIN_CONFIG_DRIVE_OPEN_SOURCE);
2424
-
if (!ret)
2425
-
goto set_output_value;
2426
-
/* Emulate open source by not actively driving the line low */
2427
-
if (!val)
2428
-
return gpiod_direction_input(desc);
2429
-
} else {
2430
-
gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
2431
-
PIN_CONFIG_DRIVE_PUSH_PULL);
2432
-
}
2433
-
2434
-
set_output_value:
2435
2300
if (!gc->set || !gc->direction_output) {
2436
2301
gpiod_warn(desc,
2437
2302
"%s: missing set() or direction_output() operations\n",
···
2429
2358
int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
2430
2359
{
2431
2360
VALIDATE_DESC(desc);
2432
-
return _gpiod_direction_output_raw(desc, value);
2361
+
return gpiod_direction_output_raw_commit(desc, value);
2433
2362
}
2434
2363
EXPORT_SYMBOL_GPL(gpiod_direction_output_raw);
2435
2364
···
2447
2376
*/
2448
2377
int gpiod_direction_output(struct gpio_desc *desc, int value)
2449
2378
{
2379
+
struct gpio_chip *gc = desc->gdev->chip;
2380
+
int ret;
2381
+
2450
2382
VALIDATE_DESC(desc);
2451
2383
if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
2452
2384
value = !value;
2453
2385
else
2454
2386
value = !!value;
2455
-
return _gpiod_direction_output_raw(desc, value);
2387
+
2388
+
/* GPIOs used for IRQs shall not be set as output */
2389
+
if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
2390
+
gpiod_err(desc,
2391
+
"%s: tried to set a GPIO tied to an IRQ as output\n",
2392
+
__func__);
2393
+
return -EIO;
2394
+
}
2395
+
2396
+
if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
2397
+
/* First see if we can enable open drain in hardware */
2398
+
ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
2399
+
PIN_CONFIG_DRIVE_OPEN_DRAIN);
2400
+
if (!ret)
2401
+
goto set_output_value;
2402
+
/* Emulate open drain by not actively driving the line high */
2403
+
if (value)
2404
+
return gpiod_direction_input(desc);
2405
+
}
2406
+
else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) {
2407
+
ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
2408
+
PIN_CONFIG_DRIVE_OPEN_SOURCE);
2409
+
if (!ret)
2410
+
goto set_output_value;
2411
+
/* Emulate open source by not actively driving the line low */
2412
+
if (!value)
2413
+
return gpiod_direction_input(desc);
2414
+
} else {
2415
+
gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc),
2416
+
PIN_CONFIG_DRIVE_PUSH_PULL);
2417
+
}
2418
+
2419
+
set_output_value:
2420
+
return gpiod_direction_output_raw_commit(desc, value);
2456
2421
}
2457
2422
EXPORT_SYMBOL_GPL(gpiod_direction_output);
2458
2423
···
2555
2448
* that the GPIO was actually requested.
2556
2449
*/
2557
2450
2558
-
static int _gpiod_get_raw_value(const struct gpio_desc *desc)
2451
+
static int gpiod_get_raw_value_commit(const struct gpio_desc *desc)
2559
2452
{
2560
2453
struct gpio_chip *chip;
2561
2454
int offset;
···
2567
2460
value = value < 0 ? value : !!value;
2568
2461
trace_gpio_value(desc_to_gpio(desc), 1, value);
2569
2462
return value;
2463
+
}
2464
+
2465
+
static int gpio_chip_get_multiple(struct gpio_chip *chip,
2466
+
unsigned long *mask, unsigned long *bits)
2467
+
{
2468
+
if (chip->get_multiple) {
2469
+
return chip->get_multiple(chip, mask, bits);
2470
+
} else if (chip->get) {
2471
+
int i, value;
2472
+
2473
+
for_each_set_bit(i, mask, chip->ngpio) {
2474
+
value = chip->get(chip, i);
2475
+
if (value < 0)
2476
+
return value;
2477
+
__assign_bit(i, bits, value);
2478
+
}
2479
+
return 0;
2480
+
}
2481
+
return -EIO;
2482
+
}
2483
+
2484
+
int gpiod_get_array_value_complex(bool raw, bool can_sleep,
2485
+
unsigned int array_size,
2486
+
struct gpio_desc **desc_array,
2487
+
int *value_array)
2488
+
{
2489
+
int i = 0;
2490
+
2491
+
while (i < array_size) {
2492
+
struct gpio_chip *chip = desc_array[i]->gdev->chip;
2493
+
unsigned long mask[BITS_TO_LONGS(chip->ngpio)];
2494
+
unsigned long bits[BITS_TO_LONGS(chip->ngpio)];
2495
+
int first, j, ret;
2496
+
2497
+
if (!can_sleep)
2498
+
WARN_ON(chip->can_sleep);
2499
+
2500
+
/* collect all inputs belonging to the same chip */
2501
+
first = i;
2502
+
memset(mask, 0, sizeof(mask));
2503
+
do {
2504
+
const struct gpio_desc *desc = desc_array[i];
2505
+
int hwgpio = gpio_chip_hwgpio(desc);
2506
+
2507
+
__set_bit(hwgpio, mask);
2508
+
i++;
2509
+
} while ((i < array_size) &&
2510
+
(desc_array[i]->gdev->chip == chip));
2511
+
2512
+
ret = gpio_chip_get_multiple(chip, mask, bits);
2513
+
if (ret)
2514
+
return ret;
2515
+
2516
+
for (j = first; j < i; j++) {
2517
+
const struct gpio_desc *desc = desc_array[j];
2518
+
int hwgpio = gpio_chip_hwgpio(desc);
2519
+
int value = test_bit(hwgpio, bits);
2520
+
2521
+
if (!raw && test_bit(FLAG_ACTIVE_LOW, &desc->flags))
2522
+
value = !value;
2523
+
value_array[j] = value;
2524
+
trace_gpio_value(desc_to_gpio(desc), 1, value);
2525
+
}
2526
+
}
2527
+
return 0;
2570
2528
}
2571
2529
2572
2530
/**
···
2649
2477
VALIDATE_DESC(desc);
2650
2478
/* Should be using gpio_get_value_cansleep() */
2651
2479
WARN_ON(desc->gdev->chip->can_sleep);
2652
-
return _gpiod_get_raw_value(desc);
2480
+
return gpiod_get_raw_value_commit(desc);
2653
2481
}
2654
2482
EXPORT_SYMBOL_GPL(gpiod_get_raw_value);
2655
2483
···
2671
2499
/* Should be using gpio_get_value_cansleep() */
2672
2500
WARN_ON(desc->gdev->chip->can_sleep);
2673
2501
2674
-
value = _gpiod_get_raw_value(desc);
2502
+
value = gpiod_get_raw_value_commit(desc);
2675
2503
if (value < 0)
2676
2504
return value;
2677
2505
···
2682
2510
}
2683
2511
EXPORT_SYMBOL_GPL(gpiod_get_value);
2684
2512
2513
+
/**
2514
+
* gpiod_get_raw_array_value() - read raw values from an array of GPIOs
2515
+
* @array_size: number of elements in the descriptor / value arrays
2516
+
* @desc_array: array of GPIO descriptors whose values will be read
2517
+
* @value_array: array to store the read values
2518
+
*
2519
+
* Read the raw values of the GPIOs, i.e. the values of the physical lines
2520
+
* without regard for their ACTIVE_LOW status. Return 0 in case of success,
2521
+
* else an error code.
2522
+
*
2523
+
* This function should be called from contexts where we cannot sleep,
2524
+
* and it will complain if the GPIO chip functions potentially sleep.
2525
+
*/
2526
+
int gpiod_get_raw_array_value(unsigned int array_size,
2527
+
struct gpio_desc **desc_array, int *value_array)
2528
+
{
2529
+
if (!desc_array)
2530
+
return -EINVAL;
2531
+
return gpiod_get_array_value_complex(true, false, array_size,
2532
+
desc_array, value_array);
2533
+
}
2534
+
EXPORT_SYMBOL_GPL(gpiod_get_raw_array_value);
2535
+
2536
+
/**
2537
+
* gpiod_get_array_value() - read values from an array of GPIOs
2538
+
* @array_size: number of elements in the descriptor / value arrays
2539
+
* @desc_array: array of GPIO descriptors whose values will be read
2540
+
* @value_array: array to store the read values
2541
+
*
2542
+
* Read the logical values of the GPIOs, i.e. taking their ACTIVE_LOW status
2543
+
* into account. Return 0 in case of success, else an error code.
2544
+
*
2545
+
* This function should be called from contexts where we cannot sleep,
2546
+
* and it will complain if the GPIO chip functions potentially sleep.
2547
+
*/
2548
+
int gpiod_get_array_value(unsigned int array_size,
2549
+
struct gpio_desc **desc_array, int *value_array)
2550
+
{
2551
+
if (!desc_array)
2552
+
return -EINVAL;
2553
+
return gpiod_get_array_value_complex(false, false, array_size,
2554
+
desc_array, value_array);
2555
+
}
2556
+
EXPORT_SYMBOL_GPL(gpiod_get_array_value);
2557
+
2685
2558
/*
2686
-
* _gpio_set_open_drain_value() - Set the open drain gpio's value.
2559
+
* gpio_set_open_drain_value_commit() - Set the open drain gpio's value.
2687
2560
* @desc: gpio descriptor whose state need to be set.
2688
2561
* @value: Non-zero for setting it HIGH otherwise it will set to LOW.
2689
2562
*/
2690
-
static void _gpio_set_open_drain_value(struct gpio_desc *desc, bool value)
2563
+
static void gpio_set_open_drain_value_commit(struct gpio_desc *desc, bool value)
2691
2564
{
2692
2565
int err = 0;
2693
2566
struct gpio_chip *chip = desc->gdev->chip;
···
2759
2542
* @desc: gpio descriptor whose state need to be set.
2760
2543
* @value: Non-zero for setting it HIGH otherwise it will set to LOW.
2761
2544
*/
2762
-
static void _gpio_set_open_source_value(struct gpio_desc *desc, bool value)
2545
+
static void gpio_set_open_source_value_commit(struct gpio_desc *desc, bool value)
2763
2546
{
2764
2547
int err = 0;
2765
2548
struct gpio_chip *chip = desc->gdev->chip;
···
2781
2564
__func__, err);
2782
2565
}
2783
2566
2784
-
static void _gpiod_set_raw_value(struct gpio_desc *desc, bool value)
2567
+
static void gpiod_set_raw_value_commit(struct gpio_desc *desc, bool value)
2785
2568
{
2786
2569
struct gpio_chip *chip;
2787
2570
2788
2571
chip = desc->gdev->chip;
2789
2572
trace_gpio_value(desc_to_gpio(desc), 0, value);
2790
-
if (test_bit(FLAG_OPEN_DRAIN, &desc->flags))
2791
-
_gpio_set_open_drain_value(desc, value);
2792
-
else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags))
2793
-
_gpio_set_open_source_value(desc, value);
2794
-
else
2795
-
chip->set(chip, gpio_chip_hwgpio(desc), value);
2573
+
chip->set(chip, gpio_chip_hwgpio(desc), value);
2796
2574
}
2797
2575
2798
2576
/*
···
2842
2630
* collect all normal outputs belonging to the same chip
2843
2631
* open drain and open source outputs are set individually
2844
2632
*/
2845
-
if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
2846
-
_gpio_set_open_drain_value(desc, value);
2847
-
} else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) {
2848
-
_gpio_set_open_source_value(desc, value);
2633
+
if (test_bit(FLAG_OPEN_DRAIN, &desc->flags) && !raw) {
2634
+
gpio_set_open_drain_value_commit(desc, value);
2635
+
} else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags) && !raw) {
2636
+
gpio_set_open_source_value_commit(desc, value);
2849
2637
} else {
2850
2638
__set_bit(hwgpio, mask);
2851
2639
if (value)
···
2879
2667
VALIDATE_DESC_VOID(desc);
2880
2668
/* Should be using gpiod_set_value_cansleep() */
2881
2669
WARN_ON(desc->gdev->chip->can_sleep);
2882
-
_gpiod_set_raw_value(desc, value);
2670
+
gpiod_set_raw_value_commit(desc, value);
2883
2671
}
2884
2672
EXPORT_SYMBOL_GPL(gpiod_set_raw_value);
2885
2673
···
2888
2676
* @desc: gpio whose value will be assigned
2889
2677
* @value: value to assign
2890
2678
*
2891
-
* Set the logical value of the GPIO, i.e. taking its ACTIVE_LOW status into
2892
-
* account
2679
+
* Set the logical value of the GPIO, i.e. taking its ACTIVE_LOW,
2680
+
* OPEN_DRAIN and OPEN_SOURCE flags into account.
2893
2681
*
2894
2682
* This function should be called from contexts where we cannot sleep, and will
2895
2683
* complain if the GPIO chip functions potentially sleep.
···
2901
2689
WARN_ON(desc->gdev->chip->can_sleep);
2902
2690
if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
2903
2691
value = !value;
2904
-
_gpiod_set_raw_value(desc, value);
2692
+
if (test_bit(FLAG_OPEN_DRAIN, &desc->flags))
2693
+
gpio_set_open_drain_value_commit(desc, value);
2694
+
else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags))
2695
+
gpio_set_open_source_value_commit(desc, value);
2696
+
else
2697
+
gpiod_set_raw_value_commit(desc, value);
2905
2698
}
2906
2699
EXPORT_SYMBOL_GPL(gpiod_set_value);
2907
2700
···
3107
2890
if (offset >= chip->ngpio)
3108
2891
return false;
3109
2892
3110
-
return !test_bit(FLAG_SLEEP_MAY_LOOSE_VALUE,
2893
+
return !test_bit(FLAG_SLEEP_MAY_LOSE_VALUE,
3111
2894
&chip->gpiodev->descs[offset].flags);
3112
2895
}
3113
2896
EXPORT_SYMBOL_GPL(gpiochip_line_is_persistent);
···
3125
2908
{
3126
2909
might_sleep_if(extra_checks);
3127
2910
VALIDATE_DESC(desc);
3128
-
return _gpiod_get_raw_value(desc);
2911
+
return gpiod_get_raw_value_commit(desc);
3129
2912
}
3130
2913
EXPORT_SYMBOL_GPL(gpiod_get_raw_value_cansleep);
3131
2914
···
3144
2927
3145
2928
might_sleep_if(extra_checks);
3146
2929
VALIDATE_DESC(desc);
3147
-
value = _gpiod_get_raw_value(desc);
2930
+
value = gpiod_get_raw_value_commit(desc);
3148
2931
if (value < 0)
3149
2932
return value;
3150
2933
···
3154
2937
return value;
3155
2938
}
3156
2939
EXPORT_SYMBOL_GPL(gpiod_get_value_cansleep);
2940
+
2941
+
/**
2942
+
* gpiod_get_raw_array_value_cansleep() - read raw values from an array of GPIOs
2943
+
* @array_size: number of elements in the descriptor / value arrays
2944
+
* @desc_array: array of GPIO descriptors whose values will be read
2945
+
* @value_array: array to store the read values
2946
+
*
2947
+
* Read the raw values of the GPIOs, i.e. the values of the physical lines
2948
+
* without regard for their ACTIVE_LOW status. Return 0 in case of success,
2949
+
* else an error code.
2950
+
*
2951
+
* This function is to be called from contexts that can sleep.
2952
+
*/
2953
+
int gpiod_get_raw_array_value_cansleep(unsigned int array_size,
2954
+
struct gpio_desc **desc_array,
2955
+
int *value_array)
2956
+
{
2957
+
might_sleep_if(extra_checks);
2958
+
if (!desc_array)
2959
+
return -EINVAL;
2960
+
return gpiod_get_array_value_complex(true, true, array_size,
2961
+
desc_array, value_array);
2962
+
}
2963
+
EXPORT_SYMBOL_GPL(gpiod_get_raw_array_value_cansleep);
2964
+
2965
+
/**
2966
+
* gpiod_get_array_value_cansleep() - read values from an array of GPIOs
2967
+
* @array_size: number of elements in the descriptor / value arrays
2968
+
* @desc_array: array of GPIO descriptors whose values will be read
2969
+
* @value_array: array to store the read values
2970
+
*
2971
+
* Read the logical values of the GPIOs, i.e. taking their ACTIVE_LOW status
2972
+
* into account. Return 0 in case of success, else an error code.
2973
+
*
2974
+
* This function is to be called from contexts that can sleep.
2975
+
*/
2976
+
int gpiod_get_array_value_cansleep(unsigned int array_size,
2977
+
struct gpio_desc **desc_array,
2978
+
int *value_array)
2979
+
{
2980
+
might_sleep_if(extra_checks);
2981
+
if (!desc_array)
2982
+
return -EINVAL;
2983
+
return gpiod_get_array_value_complex(false, true, array_size,
2984
+
desc_array, value_array);
2985
+
}
2986
+
EXPORT_SYMBOL_GPL(gpiod_get_array_value_cansleep);
3157
2987
3158
2988
/**
3159
2989
* gpiod_set_raw_value_cansleep() - assign a gpio's raw value
···
3216
2952
{
3217
2953
might_sleep_if(extra_checks);
3218
2954
VALIDATE_DESC_VOID(desc);
3219
-
_gpiod_set_raw_value(desc, value);
2955
+
gpiod_set_raw_value_commit(desc, value);
3220
2956
}
3221
2957
EXPORT_SYMBOL_GPL(gpiod_set_raw_value_cansleep);
3222
2958
···
3236
2972
VALIDATE_DESC_VOID(desc);
3237
2973
if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
3238
2974
value = !value;
3239
-
_gpiod_set_raw_value(desc, value);
2975
+
gpiod_set_raw_value_commit(desc, value);
3240
2976
}
3241
2977
EXPORT_SYMBOL_GPL(gpiod_set_value_cansleep);
3242
2978
···
3532
3268
set_bit(FLAG_OPEN_DRAIN, &desc->flags);
3533
3269
if (lflags & GPIO_OPEN_SOURCE)
3534
3270
set_bit(FLAG_OPEN_SOURCE, &desc->flags);
3535
-
if (lflags & GPIO_SLEEP_MAY_LOOSE_VALUE)
3536
-
set_bit(FLAG_SLEEP_MAY_LOOSE_VALUE, &desc->flags);
3271
+
if (lflags & GPIO_SLEEP_MAY_LOSE_VALUE)
3272
+
set_bit(FLAG_SLEEP_MAY_LOSE_VALUE, &desc->flags);
3537
3273
3538
3274
/* No particular flag request, return here... */
3539
3275
if (!(dflags & GPIOD_FLAGS_BIT_DIR_SET)) {
+5
-1
drivers/gpio/gpiolib.h
+5
-1
drivers/gpio/gpiolib.h
···
180
180
#endif
181
181
182
182
struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip, u16 hwnum);
183
+
int gpiod_get_array_value_complex(bool raw, bool can_sleep,
184
+
unsigned int array_size,
185
+
struct gpio_desc **desc_array,
186
+
int *value_array);
183
187
void gpiod_set_array_value_complex(bool raw, bool can_sleep,
184
188
unsigned int array_size,
185
189
struct gpio_desc **desc_array,
···
205
201
#define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */
206
202
#define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */
207
203
#define FLAG_IS_HOGGED 11 /* GPIO is hogged */
208
-
#define FLAG_SLEEP_MAY_LOOSE_VALUE 12 /* GPIO may loose value in sleep */
204
+
#define FLAG_SLEEP_MAY_LOSE_VALUE 12 /* GPIO may lose value in sleep */
209
205
210
206
/* Connection label */
211
207
const char *label;
+7
-15
drivers/md/dm-mpath.c
+7
-15
drivers/md/dm-mpath.c
···
641
641
blk_finish_plug(&plug);
642
642
}
643
643
644
-
static void assign_bit(bool value, long nr, unsigned long *addr)
645
-
{
646
-
if (value)
647
-
set_bit(nr, addr);
648
-
else
649
-
clear_bit(nr, addr);
650
-
}
651
-
652
644
/*
653
645
* If we run out of usable paths, should we queue I/O or error it?
654
646
*/
···
650
658
unsigned long flags;
651
659
652
660
spin_lock_irqsave(&m->lock, flags);
653
-
assign_bit((save_old_value && test_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags)) ||
654
-
(!save_old_value && queue_if_no_path),
655
-
MPATHF_SAVED_QUEUE_IF_NO_PATH, &m->flags);
656
-
assign_bit(queue_if_no_path || dm_noflush_suspending(m->ti),
657
-
MPATHF_QUEUE_IF_NO_PATH, &m->flags);
661
+
assign_bit(MPATHF_SAVED_QUEUE_IF_NO_PATH, &m->flags,
662
+
(save_old_value && test_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags)) ||
663
+
(!save_old_value && queue_if_no_path));
664
+
assign_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags,
665
+
queue_if_no_path || dm_noflush_suspending(m->ti));
658
666
spin_unlock_irqrestore(&m->lock, flags);
659
667
660
668
if (!queue_if_no_path) {
···
1580
1588
unsigned long flags;
1581
1589
1582
1590
spin_lock_irqsave(&m->lock, flags);
1583
-
assign_bit(test_bit(MPATHF_SAVED_QUEUE_IF_NO_PATH, &m->flags),
1584
-
MPATHF_QUEUE_IF_NO_PATH, &m->flags);
1591
+
assign_bit(MPATHF_QUEUE_IF_NO_PATH, &m->flags,
1592
+
test_bit(MPATHF_SAVED_QUEUE_IF_NO_PATH, &m->flags));
1585
1593
spin_unlock_irqrestore(&m->lock, flags);
1586
1594
}
1587
1595
+2
-2
drivers/pinctrl/bcm/pinctrl-bcm2835.c
+2
-2
drivers/pinctrl/bcm/pinctrl-bcm2835.c
···
379
379
events &= pc->enabled_irq_map[bank];
380
380
for_each_set_bit(offset, &events, 32) {
381
381
gpio = (32 * bank) + offset;
382
-
generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
382
+
generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
383
383
gpio));
384
384
}
385
385
}
···
661
661
enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
662
662
const char *fname = bcm2835_functions[fsel];
663
663
int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
664
-
int irq = irq_find_mapping(chip->irqdomain, offset);
664
+
int irq = irq_find_mapping(chip->irq.domain, offset);
665
665
666
666
seq_printf(s, "function %s in %s; irq %d (%s)",
667
667
fname, value ? "hi" : "lo",
+1
-1
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+1
-1
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
···
172
172
173
173
for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
174
174
unsigned pin = NGPIOS_PER_BANK * i + bit;
175
-
int child_irq = irq_find_mapping(gc->irqdomain, pin);
175
+
int child_irq = irq_find_mapping(gc->irq.domain, pin);
176
176
177
177
/*
178
178
* Clear the interrupt before invoking the
+3
-3
drivers/pinctrl/intel/pinctrl-baytrail.c
+3
-3
drivers/pinctrl/intel/pinctrl-baytrail.c
···
1627
1627
pending = readl(reg);
1628
1628
raw_spin_unlock(&vg->lock);
1629
1629
for_each_set_bit(pin, &pending, 32) {
1630
-
virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
1630
+
virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1631
1631
generic_handle_irq(virq);
1632
1632
}
1633
1633
}
···
1660
1660
1661
1661
value = readl(reg);
1662
1662
if (value & BYT_DIRECT_IRQ_EN) {
1663
-
clear_bit(i, gc->irq_valid_mask);
1663
+
clear_bit(i, gc->irq.valid_mask);
1664
1664
dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1665
1665
} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1666
1666
byt_gpio_clear_triggering(vg, i);
···
1703
1703
gc->can_sleep = false;
1704
1704
gc->parent = &vg->pdev->dev;
1705
1705
gc->ngpio = vg->soc_data->npins;
1706
-
gc->irq_need_valid_mask = true;
1706
+
gc->irq.need_valid_mask = true;
1707
1707
1708
1708
#ifdef CONFIG_PM_SLEEP
1709
1709
vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
+3
-3
drivers/pinctrl/intel/pinctrl-cherryview.c
+3
-3
drivers/pinctrl/intel/pinctrl-cherryview.c
···
1523
1523
unsigned irq, offset;
1524
1524
1525
1525
offset = pctrl->intr_lines[intr_line];
1526
-
irq = irq_find_mapping(gc->irqdomain, offset);
1526
+
irq = irq_find_mapping(gc->irq.domain, offset);
1527
1527
generic_handle_irq(irq);
1528
1528
}
1529
1529
···
1585
1585
chip->label = dev_name(pctrl->dev);
1586
1586
chip->parent = pctrl->dev;
1587
1587
chip->base = -1;
1588
-
chip->irq_need_valid_mask = need_valid_mask;
1588
+
chip->irq.need_valid_mask = need_valid_mask;
1589
1589
1590
1590
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1591
1591
if (ret) {
···
1617
1617
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1618
1618
1619
1619
if (need_valid_mask && intsel >= pctrl->community->nirqs)
1620
-
clear_bit(i, chip->irq_valid_mask);
1620
+
clear_bit(i, chip->irq.valid_mask);
1621
1621
}
1622
1622
1623
1623
/* Clear all interrupts */
+1
-1
drivers/pinctrl/intel/pinctrl-intel.c
+1
-1
drivers/pinctrl/intel/pinctrl-intel.c
+2
-4
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+2
-4
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
···
592
592
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
593
593
struct irq_chip *chip = irq_desc_get_chip(desc);
594
594
struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
595
-
struct irq_domain *d = gc->irqdomain;
595
+
struct irq_domain *d = gc->irq.domain;
596
596
int i;
597
597
598
598
chained_irq_enter(chip, desc);
···
626
626
627
627
static unsigned int armada_37xx_irq_startup(struct irq_data *d)
628
628
{
629
-
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
630
-
int irq = d->hwirq - chip->irq_base;
631
629
/*
632
630
* The mask field is a "precomputed bitmask for accessing the
633
631
* chip registers" which was introduced for the generic
634
632
* irqchip framework. As we don't use this framework, we can
635
633
* reuse this field for our own usage.
636
634
*/
637
-
d->mask = BIT(irq % GPIO_PER_REG);
635
+
d->mask = BIT(d->hwirq % GPIO_PER_REG);
638
636
639
637
armada_37xx_irq_unmask(d);
640
638
+2
-2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
+2
-2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
···
413
413
u32 falling = nmk_chip->fimsc & BIT(offset);
414
414
u32 rising = nmk_chip->rimsc & BIT(offset);
415
415
int gpio = nmk_chip->chip.base + offset;
416
-
int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);
416
+
int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
417
417
struct irq_data *d = irq_get_irq_data(irq);
418
418
419
419
if (!rising && !falling)
···
815
815
while (status) {
816
816
int bit = __ffs(status);
817
817
818
-
generic_handle_irq(irq_find_mapping(chip->irqdomain, bit));
818
+
generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
819
819
status &= ~BIT(bit);
820
820
}
821
821
+1
-1
drivers/pinctrl/pinctrl-amd.c
+1
-1
drivers/pinctrl/pinctrl-amd.c
+1
-1
drivers/pinctrl/pinctrl-at91.c
+1
-1
drivers/pinctrl/pinctrl-at91.c
+1
-1
drivers/pinctrl/pinctrl-coh901.c
+1
-1
drivers/pinctrl/pinctrl-coh901.c
···
517
517
518
518
for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
519
519
int offset = pinoffset + irqoffset;
520
-
int pin_irq = irq_find_mapping(chip->irqdomain, offset);
520
+
int pin_irq = irq_find_mapping(chip->irq.domain, offset);
521
521
522
522
dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
523
523
pin_irq, offset);
+1
-1
drivers/pinctrl/pinctrl-mcp23s08.c
+1
-1
drivers/pinctrl/pinctrl-mcp23s08.c
···
537
537
((gpio_bit_changed || intcap_changed) &&
538
538
(BIT(i) & mcp->irq_fall) && !gpio_set) ||
539
539
defval_changed) {
540
-
child_irq = irq_find_mapping(mcp->chip.irqdomain, i);
540
+
child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
541
541
handle_nested_irq(child_irq);
542
542
}
543
543
}
+1
-1
drivers/pinctrl/pinctrl-oxnas.c
+1
-1
drivers/pinctrl/pinctrl-oxnas.c
···
1064
1064
stat = readl(bank->reg_base + IRQ_PENDING);
1065
1065
1066
1066
for_each_set_bit(pin, &stat, BITS_PER_LONG)
1067
-
generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
1067
+
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
1068
1068
1069
1069
chained_irq_exit(chip, desc);
1070
1070
}
+1
-1
drivers/pinctrl/pinctrl-pic32.c
+1
-1
drivers/pinctrl/pinctrl-pic32.c
···
2106
2106
pending = pic32_gpio_get_pending(gc, stat);
2107
2107
2108
2108
for_each_set_bit(pin, &pending, BITS_PER_LONG)
2109
-
generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
2109
+
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
2110
2110
2111
2111
chained_irq_exit(chip, desc);
2112
2112
}
+1
-1
drivers/pinctrl/pinctrl-pistachio.c
+1
-1
drivers/pinctrl/pinctrl-pistachio.c
···
1307
1307
pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
1308
1308
gpio_readl(bank, GPIO_INTERRUPT_EN);
1309
1309
for_each_set_bit(pin, &pending, 16)
1310
-
generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
1310
+
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
1311
1311
chained_irq_exit(chip, desc);
1312
1312
}
1313
1313
+1
-1
drivers/pinctrl/pinctrl-st.c
+1
-1
drivers/pinctrl/pinctrl-st.c
+1
-1
drivers/pinctrl/pinctrl-sx150x.c
+1
-1
drivers/pinctrl/pinctrl-sx150x.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm.c
···
795
795
g = &pctrl->soc->groups[i];
796
796
val = readl(pctrl->regs + g->intr_status_reg);
797
797
if (val & BIT(g->intr_status_bit)) {
798
-
irq_pin = irq_find_mapping(gc->irqdomain, i);
798
+
irq_pin = irq_find_mapping(gc->irq.domain, i);
799
799
generic_handle_irq(irq_pin);
800
800
handled++;
801
801
}
+1
-1
drivers/pinctrl/sirf/pinctrl-atlas7.c
+1
-1
drivers/pinctrl/sirf/pinctrl-atlas7.c
+1
-1
drivers/pinctrl/sirf/pinctrl-sirf.c
+1
-1
drivers/pinctrl/sirf/pinctrl-sirf.c
···
587
587
if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
588
588
pr_debug("%s: gpio id %d idx %d happens\n",
589
589
__func__, bank->id, idx);
590
-
generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
590
+
generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
591
591
bank->id * SIRFSOC_GPIO_BANK_SIZE));
592
592
}
593
593
+1
-1
drivers/pinctrl/spear/pinctrl-plgpio.c
+1
-1
drivers/pinctrl/spear/pinctrl-plgpio.c
+3
-3
drivers/platform/x86/intel_int0002_vgpio.c
+3
-3
drivers/platform/x86/intel_int0002_vgpio.c
···
119
119
if (!(gpe_sts_reg & GPE0A_PME_B0_STS_BIT))
120
120
return IRQ_NONE;
121
121
122
-
generic_handle_irq(irq_find_mapping(chip->irqdomain,
122
+
generic_handle_irq(irq_find_mapping(chip->irq.domain,
123
123
GPE0A_PME_B0_VIRT_GPIO_PIN));
124
124
125
125
pm_system_wakeup();
···
165
165
chip->direction_output = int0002_gpio_direction_output;
166
166
chip->base = -1;
167
167
chip->ngpio = GPE0A_PME_B0_VIRT_GPIO_PIN + 1;
168
-
chip->irq_need_valid_mask = true;
168
+
chip->irq.need_valid_mask = true;
169
169
170
170
ret = devm_gpiochip_add_data(&pdev->dev, chip, NULL);
171
171
if (ret) {
···
173
173
return ret;
174
174
}
175
175
176
-
bitmap_clear(chip->irq_valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN);
176
+
bitmap_clear(chip->irq.valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN);
177
177
178
178
/*
179
179
* We manually request the irq here instead of passing a flow-handler
+1
-1
include/dt-bindings/gpio/gpio.h
+1
-1
include/dt-bindings/gpio/gpio.h
+18
include/dt-bindings/gpio/uniphier-gpio.h
+18
include/dt-bindings/gpio/uniphier-gpio.h
···
1
+
/*
2
+
* Copyright (C) 2017 Socionext Inc.
3
+
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H
7
+
#define _DT_BINDINGS_GPIO_UNIPHIER_H
8
+
9
+
#define UNIPHIER_GPIO_LINES_PER_BANK 8
10
+
11
+
#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15)
12
+
13
+
#define UNIPHIER_GPIO_PORT(bank, line) \
14
+
((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))
15
+
16
+
#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n))
17
+
18
+
#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */
+24
include/linux/bitops.h
+24
include/linux/bitops.h
···
228
228
return __ffs((unsigned long)word);
229
229
}
230
230
231
+
/**
232
+
* assign_bit - Assign value to a bit in memory
233
+
* @nr: the bit to set
234
+
* @addr: the address to start counting from
235
+
* @value: the value to assign
236
+
*/
237
+
static __always_inline void assign_bit(long nr, volatile unsigned long *addr,
238
+
bool value)
239
+
{
240
+
if (value)
241
+
set_bit(nr, addr);
242
+
else
243
+
clear_bit(nr, addr);
244
+
}
245
+
246
+
static __always_inline void __assign_bit(long nr, volatile unsigned long *addr,
247
+
bool value)
248
+
{
249
+
if (value)
250
+
__set_bit(nr, addr);
251
+
else
252
+
__clear_bit(nr, addr);
253
+
}
254
+
231
255
#ifdef __KERNEL__
232
256
233
257
#ifndef set_mask_bits
+43
include/linux/gpio/consumer.h
+43
include/linux/gpio/consumer.h
···
100
100
101
101
/* Value get/set from non-sleeping context */
102
102
int gpiod_get_value(const struct gpio_desc *desc);
103
+
int gpiod_get_array_value(unsigned int array_size,
104
+
struct gpio_desc **desc_array, int *value_array);
103
105
void gpiod_set_value(struct gpio_desc *desc, int value);
104
106
void gpiod_set_array_value(unsigned int array_size,
105
107
struct gpio_desc **desc_array, int *value_array);
106
108
int gpiod_get_raw_value(const struct gpio_desc *desc);
109
+
int gpiod_get_raw_array_value(unsigned int array_size,
110
+
struct gpio_desc **desc_array,
111
+
int *value_array);
107
112
void gpiod_set_raw_value(struct gpio_desc *desc, int value);
108
113
void gpiod_set_raw_array_value(unsigned int array_size,
109
114
struct gpio_desc **desc_array,
···
116
111
117
112
/* Value get/set from sleeping context */
118
113
int gpiod_get_value_cansleep(const struct gpio_desc *desc);
114
+
int gpiod_get_array_value_cansleep(unsigned int array_size,
115
+
struct gpio_desc **desc_array,
116
+
int *value_array);
119
117
void gpiod_set_value_cansleep(struct gpio_desc *desc, int value);
120
118
void gpiod_set_array_value_cansleep(unsigned int array_size,
121
119
struct gpio_desc **desc_array,
122
120
int *value_array);
123
121
int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc);
122
+
int gpiod_get_raw_array_value_cansleep(unsigned int array_size,
123
+
struct gpio_desc **desc_array,
124
+
int *value_array);
124
125
void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value);
125
126
void gpiod_set_raw_array_value_cansleep(unsigned int array_size,
126
127
struct gpio_desc **desc_array,
···
317
306
WARN_ON(1);
318
307
return 0;
319
308
}
309
+
static inline int gpiod_get_array_value(unsigned int array_size,
310
+
struct gpio_desc **desc_array,
311
+
int *value_array)
312
+
{
313
+
/* GPIO can never have been requested */
314
+
WARN_ON(1);
315
+
return 0;
316
+
}
320
317
static inline void gpiod_set_value(struct gpio_desc *desc, int value)
321
318
{
322
319
/* GPIO can never have been requested */
···
338
319
WARN_ON(1);
339
320
}
340
321
static inline int gpiod_get_raw_value(const struct gpio_desc *desc)
322
+
{
323
+
/* GPIO can never have been requested */
324
+
WARN_ON(1);
325
+
return 0;
326
+
}
327
+
static inline int gpiod_get_raw_array_value(unsigned int array_size,
328
+
struct gpio_desc **desc_array,
329
+
int *value_array)
341
330
{
342
331
/* GPIO can never have been requested */
343
332
WARN_ON(1);
···
370
343
WARN_ON(1);
371
344
return 0;
372
345
}
346
+
static inline int gpiod_get_array_value_cansleep(unsigned int array_size,
347
+
struct gpio_desc **desc_array,
348
+
int *value_array)
349
+
{
350
+
/* GPIO can never have been requested */
351
+
WARN_ON(1);
352
+
return 0;
353
+
}
373
354
static inline void gpiod_set_value_cansleep(struct gpio_desc *desc, int value)
374
355
{
375
356
/* GPIO can never have been requested */
···
391
356
WARN_ON(1);
392
357
}
393
358
static inline int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)
359
+
{
360
+
/* GPIO can never have been requested */
361
+
WARN_ON(1);
362
+
return 0;
363
+
}
364
+
static inline int gpiod_get_raw_array_value_cansleep(unsigned int array_size,
365
+
struct gpio_desc **desc_array,
366
+
int *value_array)
394
367
{
395
368
/* GPIO can never have been requested */
396
369
WARN_ON(1);
+182
-33
include/linux/gpio/driver.h
+182
-33
include/linux/gpio/driver.h
···
20
20
21
21
#ifdef CONFIG_GPIOLIB
22
22
23
+
#ifdef CONFIG_GPIOLIB_IRQCHIP
24
+
/**
25
+
* struct gpio_irq_chip - GPIO interrupt controller
26
+
*/
27
+
struct gpio_irq_chip {
28
+
/**
29
+
* @chip:
30
+
*
31
+
* GPIO IRQ chip implementation, provided by GPIO driver.
32
+
*/
33
+
struct irq_chip *chip;
34
+
35
+
/**
36
+
* @domain:
37
+
*
38
+
* Interrupt translation domain; responsible for mapping between GPIO
39
+
* hwirq number and Linux IRQ number.
40
+
*/
41
+
struct irq_domain *domain;
42
+
43
+
/**
44
+
* @domain_ops:
45
+
*
46
+
* Table of interrupt domain operations for this IRQ chip.
47
+
*/
48
+
const struct irq_domain_ops *domain_ops;
49
+
50
+
/**
51
+
* @handler:
52
+
*
53
+
* The IRQ handler to use (often a predefined IRQ core function) for
54
+
* GPIO IRQs, provided by GPIO driver.
55
+
*/
56
+
irq_flow_handler_t handler;
57
+
58
+
/**
59
+
* @default_type:
60
+
*
61
+
* Default IRQ triggering type applied during GPIO driver
62
+
* initialization, provided by GPIO driver.
63
+
*/
64
+
unsigned int default_type;
65
+
66
+
/**
67
+
* @lock_key:
68
+
*
69
+
* Per GPIO IRQ chip lockdep class.
70
+
*/
71
+
struct lock_class_key *lock_key;
72
+
73
+
/**
74
+
* @parent_handler:
75
+
*
76
+
* The interrupt handler for the GPIO chip's parent interrupts, may be
77
+
* NULL if the parent interrupts are nested rather than cascaded.
78
+
*/
79
+
irq_flow_handler_t parent_handler;
80
+
81
+
/**
82
+
* @parent_handler_data:
83
+
*
84
+
* Data associated, and passed to, the handler for the parent
85
+
* interrupt.
86
+
*/
87
+
void *parent_handler_data;
88
+
89
+
/**
90
+
* @num_parents:
91
+
*
92
+
* The number of interrupt parents of a GPIO chip.
93
+
*/
94
+
unsigned int num_parents;
95
+
96
+
/**
97
+
* @parents:
98
+
*
99
+
* A list of interrupt parents of a GPIO chip. This is owned by the
100
+
* driver, so the core will only reference this list, not modify it.
101
+
*/
102
+
unsigned int *parents;
103
+
104
+
/**
105
+
* @map:
106
+
*
107
+
* A list of interrupt parents for each line of a GPIO chip.
108
+
*/
109
+
unsigned int *map;
110
+
111
+
/**
112
+
* @threaded:
113
+
*
114
+
* True if set the interrupt handling uses nested threads.
115
+
*/
116
+
bool threaded;
117
+
118
+
/**
119
+
* @need_valid_mask:
120
+
*
121
+
* If set core allocates @valid_mask with all bits set to one.
122
+
*/
123
+
bool need_valid_mask;
124
+
125
+
/**
126
+
* @valid_mask:
127
+
*
128
+
* If not %NULL holds bitmask of GPIOs which are valid to be included
129
+
* in IRQ domain of the chip.
130
+
*/
131
+
unsigned long *valid_mask;
132
+
133
+
/**
134
+
* @first:
135
+
*
136
+
* Required for static IRQ allocation. If set, irq_domain_add_simple()
137
+
* will allocate and map all IRQs during initialization.
138
+
*/
139
+
unsigned int first;
140
+
};
141
+
142
+
static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)
143
+
{
144
+
return container_of(chip, struct gpio_irq_chip, chip);
145
+
}
146
+
#endif
147
+
23
148
/**
24
149
* struct gpio_chip - abstract a GPIO controller
25
150
* @label: a functional name for the GPIO device, such as a part
···
161
36
* @direction_input: configures signal "offset" as input, or returns error
162
37
* @direction_output: configures signal "offset" as output, or returns error
163
38
* @get: returns value for signal "offset", 0=low, 1=high, or negative error
39
+
* @get_multiple: reads values for multiple signals defined by "mask" and
40
+
* stores them in "bits", returns 0 on success or negative error
164
41
* @set: assigns output value for signal "offset"
165
42
* @set_multiple: assigns output values for multiple signals defined by "mask"
166
43
* @set_config: optional hook for all kinds of settings. Uses the same
···
193
66
* registers.
194
67
* @read_reg: reader function for generic GPIO
195
68
* @write_reg: writer function for generic GPIO
196
-
* @pin2mask: some generic GPIO controllers work with the big-endian bits
197
-
* notation, e.g. in a 8-bits register, GPIO7 is the least significant
198
-
* bit. This callback assigns the right bit mask.
69
+
* @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
70
+
* line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
71
+
* generic GPIO core. It is for internal housekeeping only.
199
72
* @reg_dat: data (in) register for generic GPIO
200
73
* @reg_set: output set register (out=high) for generic GPIO
201
74
* @reg_clr: output clear register (out=low) for generic GPIO
···
208
81
* safely.
209
82
* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
210
83
* direction safely.
211
-
* @irqchip: GPIO IRQ chip impl, provided by GPIO driver
212
-
* @irqdomain: Interrupt translation domain; responsible for mapping
213
-
* between GPIO hwirq number and linux irq number
214
-
* @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
215
-
* @irq_handler: the irq handler to use (often a predefined irq core function)
216
-
* for GPIO IRQs, provided by GPIO driver
217
-
* @irq_default_type: default IRQ triggering type applied during GPIO driver
218
-
* initialization, provided by GPIO driver
219
-
* @irq_chained_parent: GPIO IRQ chip parent/bank linux irq number,
220
-
* provided by GPIO driver for chained interrupt (not for nested
221
-
* interrupts).
222
-
* @irq_nested: True if set the interrupt handling is nested.
223
-
* @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
224
-
* bits set to one
225
-
* @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
226
-
* be included in IRQ domain of the chip
227
-
* @lock_key: per GPIO IRQ chip lockdep class
228
84
*
229
85
* A gpio_chip can help platforms abstract various sources of GPIOs so
230
86
* they can all be accessed through a common programing interface.
···
237
127
unsigned offset, int value);
238
128
int (*get)(struct gpio_chip *chip,
239
129
unsigned offset);
130
+
int (*get_multiple)(struct gpio_chip *chip,
131
+
unsigned long *mask,
132
+
unsigned long *bits);
240
133
void (*set)(struct gpio_chip *chip,
241
134
unsigned offset, int value);
242
135
void (*set_multiple)(struct gpio_chip *chip,
···
261
148
#if IS_ENABLED(CONFIG_GPIO_GENERIC)
262
149
unsigned long (*read_reg)(void __iomem *reg);
263
150
void (*write_reg)(void __iomem *reg, unsigned long data);
264
-
unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
151
+
bool be_bits;
265
152
void __iomem *reg_dat;
266
153
void __iomem *reg_set;
267
154
void __iomem *reg_clr;
···
277
164
* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
278
165
* to handle IRQs for most practical cases.
279
166
*/
280
-
struct irq_chip *irqchip;
281
-
struct irq_domain *irqdomain;
282
-
unsigned int irq_base;
283
-
irq_flow_handler_t irq_handler;
284
-
unsigned int irq_default_type;
285
-
unsigned int irq_chained_parent;
286
-
bool irq_nested;
287
-
bool irq_need_valid_mask;
288
-
unsigned long *irq_valid_mask;
289
-
struct lock_class_key *lock_key;
167
+
168
+
/**
169
+
* @irq:
170
+
*
171
+
* Integrates interrupt chip functionality with the GPIO chip. Can be
172
+
* used to handle IRQs for most practical cases.
173
+
*/
174
+
struct gpio_irq_chip irq;
290
175
#endif
291
176
292
177
#if defined(CONFIG_OF_GPIO)
···
322
211
unsigned offset);
323
212
324
213
/* add/remove chips */
325
-
extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
214
+
extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
215
+
struct lock_class_key *lock_key);
216
+
217
+
/**
218
+
* gpiochip_add_data() - register a gpio_chip
219
+
* @chip: the chip to register, with chip->base initialized
220
+
* @data: driver-private data associated with this chip
221
+
*
222
+
* Context: potentially before irqs will work
223
+
*
224
+
* When gpiochip_add_data() is called very early during boot, so that GPIOs
225
+
* can be freely used, the chip->parent device must be registered before
226
+
* the gpio framework's arch_initcall(). Otherwise sysfs initialization
227
+
* for GPIOs will fail rudely.
228
+
*
229
+
* gpiochip_add_data() must only be called after gpiolib initialization,
230
+
* ie after core_initcall().
231
+
*
232
+
* If chip->base is negative, this requests dynamic assignment of
233
+
* a range of valid GPIOs.
234
+
*
235
+
* Returns:
236
+
* A negative errno if the chip can't be registered, such as because the
237
+
* chip->base is invalid or already associated with a different chip.
238
+
* Otherwise it returns zero as a success code.
239
+
*/
240
+
#ifdef CONFIG_LOCKDEP
241
+
#define gpiochip_add_data(chip, data) ({ \
242
+
static struct lock_class_key key; \
243
+
gpiochip_add_data_with_key(chip, data, &key); \
244
+
})
245
+
#else
246
+
#define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL)
247
+
#endif
248
+
326
249
static inline int gpiochip_add(struct gpio_chip *chip)
327
250
{
328
251
return gpiochip_add_data(chip, NULL);
···
410
265
411
266
#ifdef CONFIG_GPIOLIB_IRQCHIP
412
267
268
+
int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
269
+
irq_hw_number_t hwirq);
270
+
void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
271
+
413
272
void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
414
273
struct irq_chip *irqchip,
415
274
unsigned int parent_irq,
···
428
279
unsigned int first_irq,
429
280
irq_flow_handler_t handler,
430
281
unsigned int type,
431
-
bool nested,
282
+
bool threaded,
432
283
struct lock_class_key *lock_key);
433
284
434
285
#ifdef CONFIG_LOCKDEP
+1
-1
include/linux/gpio/machine.h
+1
-1
include/linux/gpio/machine.h
+1
-1
include/linux/of_gpio.h
+1
-1
include/linux/of_gpio.h
+10
-7
tools/gpio/gpio-utils.c
+10
-7
tools/gpio/gpio-utils.c
···
76
76
fd = open(chrdev_name, 0);
77
77
if (fd == -1) {
78
78
ret = -errno;
79
-
fprintf(stderr, "Failed to open %s\n", chrdev_name);
79
+
fprintf(stderr, "Failed to open %s, %s\n",
80
+
chrdev_name, strerror(errno));
80
81
goto exit_close_error;
81
82
}
82
83
···
93
92
ret = ioctl(fd, GPIO_GET_LINEHANDLE_IOCTL, &req);
94
93
if (ret == -1) {
95
94
ret = -errno;
96
-
fprintf(stderr, "Failed to issue GET LINEHANDLE IOCTL (%d)\n",
97
-
ret);
95
+
fprintf(stderr, "Failed to issue %s (%d), %s\n",
96
+
"GPIO_GET_LINEHANDLE_IOCTL", ret, strerror(errno));
98
97
}
99
98
100
99
exit_close_error:
···
119
118
ret = ioctl(fd, GPIOHANDLE_SET_LINE_VALUES_IOCTL, data);
120
119
if (ret == -1) {
121
120
ret = -errno;
122
-
fprintf(stderr, "Failed to issue %s (%d)\n",
123
-
"GPIOHANDLE_SET_LINE_VALUES_IOCTL", ret);
121
+
fprintf(stderr, "Failed to issue %s (%d), %s\n",
122
+
"GPIOHANDLE_SET_LINE_VALUES_IOCTL", ret,
123
+
strerror(errno));
124
124
}
125
125
126
126
return ret;
···
143
141
ret = ioctl(fd, GPIOHANDLE_GET_LINE_VALUES_IOCTL, data);
144
142
if (ret == -1) {
145
143
ret = -errno;
146
-
fprintf(stderr, "Failed to issue %s (%d)\n",
147
-
"GPIOHANDLE_GET_LINE_VALUES_IOCTL", ret);
144
+
fprintf(stderr, "Failed to issue %s (%d), %s\n",
145
+
"GPIOHANDLE_GET_LINE_VALUES_IOCTL", ret,
146
+
strerror(errno));
148
147
}
149
148
150
149
return ret;