Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2019-06-14' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Daniel Vetter:
"Nothing unsettling here, also not aware of anything serious still
pending.
The edid override regression fix took a bit longer since this seems to
be an area with an overabundance of bad options. But the fix we have
now seems like a good path forward.
Next week it should be back to Dave.
Summary:
- fix regression on amdgpu on SI
- fix edid override regression
- driver fixes: amdgpu, i915, mediatek, meson, panfrost
- fix writecombine for vmap in gem-shmem helper (used by panfrost)
- add more panel quirks"
* tag 'drm-fixes-2019-06-14' of git://anongit.freedesktop.org/drm/drm: (25 commits)
drm/amdgpu: return 0 by default in amdgpu_pm_load_smu_firmware
drm/amdgpu: Fix bounds checking in amdgpu_ras_is_supported()
drm: add fallback override/firmware EDID modes workaround
drm/edid: abstract override/firmware EDID retrieval
drm/i915/perf: fix whitelist on Gen10+
drm/i915/sdvo: Implement proper HDMI audio support for SDVO
drm/i915: Fix per-pixel alpha with CCS
drm/i915/dmc: protect against reading random memory
drm/i915/dsi: Use a fuzzy check for burst mode clock check
drm/amdgpu/{uvd,vcn}: fetch ring's read_ptr after alloc
drm/panfrost: Require the simple_ondemand governor
drm/panfrost: make devfreq optional again
drm/gem_shmem: Use a writecombine mapping for ->vaddr
drm: panel-orientation-quirks: Add quirk for GPD MicroPC
drm: panel-orientation-quirks: Add quirk for GPD pocket2
drm/meson: fix G12A primary plane disabling
drm/meson: fix primary plane disabling
drm/meson: fix G12A HDMI PLL settings for 4K60 1000/1001 variations
drm/mediatek: call mtk_dsi_stop() after mtk_drm_crtc_atomic_disable()
drm/mediatek: clear num_pipes when unbind driver
...
+253
-73
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
···
2492
2492
2493
2493
int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
2494
2494
{
2495
-
int r = -EINVAL;
2495
+
int r;
2496
2496
2497
2497
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
2498
2498
r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
···
2502
2502
}
2503
2503
*smu_version = adev->pm.fw_version;
2504
2504
}
2505
-
return r;
2505
+
return 0;
2506
2506
}
2507
2507
2508
2508
int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+3
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+3
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
···
594
594
int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
595
595
{
596
596
struct amdgpu_device *adev = ring->adev;
597
-
uint32_t rptr = amdgpu_ring_get_rptr(ring);
597
+
uint32_t rptr;
598
598
unsigned i;
599
599
int r;
600
600
601
601
r = amdgpu_ring_alloc(ring, 16);
602
602
if (r)
603
603
return r;
604
+
605
+
rptr = amdgpu_ring_get_rptr(ring);
604
606
605
607
amdgpu_ring_write(ring, VCN_ENC_CMD_END);
606
608
amdgpu_ring_commit(ring);
+4
-1
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+4
-1
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
···
170
170
static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
171
171
{
172
172
struct amdgpu_device *adev = ring->adev;
173
-
uint32_t rptr = amdgpu_ring_get_rptr(ring);
173
+
uint32_t rptr;
174
174
unsigned i;
175
175
int r;
176
176
177
177
r = amdgpu_ring_alloc(ring, 16);
178
178
if (r)
179
179
return r;
180
+
181
+
rptr = amdgpu_ring_get_rptr(ring);
182
+
180
183
amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
181
184
amdgpu_ring_commit(ring);
182
185
+4
-1
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+4
-1
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
···
175
175
static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
176
176
{
177
177
struct amdgpu_device *adev = ring->adev;
178
-
uint32_t rptr = amdgpu_ring_get_rptr(ring);
178
+
uint32_t rptr;
179
179
unsigned i;
180
180
int r;
181
181
···
185
185
r = amdgpu_ring_alloc(ring, 16);
186
186
if (r)
187
187
return r;
188
+
189
+
rptr = amdgpu_ring_get_rptr(ring);
190
+
188
191
amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
189
192
amdgpu_ring_commit(ring);
190
193
+47
-8
drivers/gpu/drm/drm_edid.c
+47
-8
drivers/gpu/drm/drm_edid.c
···
1570
1570
}
1571
1571
}
1572
1572
1573
+
/* Get override or firmware EDID */
1574
+
static struct edid *drm_get_override_edid(struct drm_connector *connector)
1575
+
{
1576
+
struct edid *override = NULL;
1577
+
1578
+
if (connector->override_edid)
1579
+
override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1580
+
1581
+
if (!override)
1582
+
override = drm_load_edid_firmware(connector);
1583
+
1584
+
return IS_ERR(override) ? NULL : override;
1585
+
}
1586
+
1587
+
/**
1588
+
* drm_add_override_edid_modes - add modes from override/firmware EDID
1589
+
* @connector: connector we're probing
1590
+
*
1591
+
* Add modes from the override/firmware EDID, if available. Only to be used from
1592
+
* drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1593
+
* failed during drm_get_edid() and caused the override/firmware EDID to be
1594
+
* skipped.
1595
+
*
1596
+
* Return: The number of modes added or 0 if we couldn't find any.
1597
+
*/
1598
+
int drm_add_override_edid_modes(struct drm_connector *connector)
1599
+
{
1600
+
struct edid *override;
1601
+
int num_modes = 0;
1602
+
1603
+
override = drm_get_override_edid(connector);
1604
+
if (override) {
1605
+
drm_connector_update_edid_property(connector, override);
1606
+
num_modes = drm_add_edid_modes(connector, override);
1607
+
kfree(override);
1608
+
1609
+
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1610
+
connector->base.id, connector->name, num_modes);
1611
+
}
1612
+
1613
+
return num_modes;
1614
+
}
1615
+
EXPORT_SYMBOL(drm_add_override_edid_modes);
1616
+
1573
1617
/**
1574
1618
* drm_do_get_edid - get EDID data using a custom EDID block read function
1575
1619
* @connector: connector we're probing
···
1641
1597
{
1642
1598
int i, j = 0, valid_extensions = 0;
1643
1599
u8 *edid, *new;
1644
-
struct edid *override = NULL;
1600
+
struct edid *override;
1645
1601
1646
-
if (connector->override_edid)
1647
-
override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1648
-
1649
-
if (!override)
1650
-
override = drm_load_edid_firmware(connector);
1651
-
1652
-
if (!IS_ERR_OR_NULL(override))
1602
+
override = drm_get_override_edid(connector);
1603
+
if (override)
1653
1604
return override;
1654
1605
1655
1606
if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
+2
-1
drivers/gpu/drm/drm_gem_shmem_helper.c
+2
-1
drivers/gpu/drm/drm_gem_shmem_helper.c
···
255
255
if (obj->import_attach)
256
256
shmem->vaddr = dma_buf_vmap(obj->import_attach->dmabuf);
257
257
else
258
-
shmem->vaddr = vmap(shmem->pages, obj->size >> PAGE_SHIFT, VM_MAP, PAGE_KERNEL);
258
+
shmem->vaddr = vmap(shmem->pages, obj->size >> PAGE_SHIFT,
259
+
VM_MAP, pgprot_writecombine(PAGE_KERNEL));
259
260
260
261
if (!shmem->vaddr) {
261
262
DRM_DEBUG_KMS("Failed to vmap pages\n");
+32
drivers/gpu/drm/drm_panel_orientation_quirks.c
+32
drivers/gpu/drm/drm_panel_orientation_quirks.c
···
42
42
.orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP,
43
43
};
44
44
45
+
static const struct drm_dmi_panel_orientation_data gpd_micropc = {
46
+
.width = 720,
47
+
.height = 1280,
48
+
.bios_dates = (const char * const []){ "04/26/2019",
49
+
NULL },
50
+
.orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
51
+
};
52
+
45
53
static const struct drm_dmi_panel_orientation_data gpd_pocket = {
46
54
.width = 1200,
47
55
.height = 1920,
48
56
.bios_dates = (const char * const []){ "05/26/2017", "06/28/2017",
49
57
"07/05/2017", "08/07/2017", NULL },
58
+
.orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
59
+
};
60
+
61
+
static const struct drm_dmi_panel_orientation_data gpd_pocket2 = {
62
+
.width = 1200,
63
+
.height = 1920,
64
+
.bios_dates = (const char * const []){ "06/28/2018", "08/28/2018",
65
+
"12/07/2018", NULL },
50
66
.orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
51
67
};
52
68
···
115
99
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
116
100
},
117
101
.driver_data = (void *)&asus_t100ha,
102
+
}, { /* GPD MicroPC (generic strings, also match on bios date) */
103
+
.matches = {
104
+
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Default string"),
105
+
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
106
+
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
107
+
DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
108
+
},
109
+
.driver_data = (void *)&gpd_micropc,
118
110
}, { /*
119
111
* GPD Pocket, note that the the DMI data is less generic then
120
112
* it seems, devices with a board-vendor of "AMI Corporation"
···
136
112
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
137
113
},
138
114
.driver_data = (void *)&gpd_pocket,
115
+
}, { /* GPD Pocket 2 (generic strings, also match on bios date) */
116
+
.matches = {
117
+
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Default string"),
118
+
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
119
+
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
120
+
DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
121
+
},
122
+
.driver_data = (void *)&gpd_pocket2,
139
123
}, { /* GPD Win (same note on DMI match as GPD Pocket) */
140
124
.matches = {
141
125
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
+7
drivers/gpu/drm/drm_probe_helper.c
+7
drivers/gpu/drm/drm_probe_helper.c
···
479
479
480
480
count = (*connector_funcs->get_modes)(connector);
481
481
482
+
/*
483
+
* Fallback for when DDC probe failed in drm_get_edid() and thus skipped
484
+
* override/firmware EDID.
485
+
*/
486
+
if (count == 0 && connector->status == connector_status_connected)
487
+
count = drm_add_override_edid_modes(connector);
488
+
482
489
if (count == 0 && connector->status == connector_status_connected)
483
490
count = drm_add_modes_noedid(connector, 1024, 768);
484
491
count += drm_helper_probe_add_cmdline_mode(connector);
+1
drivers/gpu/drm/i915/i915_perf.c
+1
drivers/gpu/drm/i915/i915_perf.c
···
3005
3005
static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
3006
3006
{
3007
3007
return gen8_is_valid_mux_addr(dev_priv, addr) ||
3008
+
addr == i915_mmio_reg_offset(GEN10_NOA_WRITE_HIGH) ||
3008
3009
(addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) &&
3009
3010
addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI));
3010
3011
}
+1
drivers/gpu/drm/i915/i915_reg.h
+1
drivers/gpu/drm/i915/i915_reg.h
+18
drivers/gpu/drm/i915/intel_csr.c
+18
drivers/gpu/drm/i915/intel_csr.c
···
303
303
u32 dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
304
304
u32 i;
305
305
u32 *dmc_payload;
306
+
size_t fsize;
306
307
307
308
if (!fw)
308
309
return NULL;
310
+
311
+
fsize = sizeof(struct intel_css_header) +
312
+
sizeof(struct intel_package_header) +
313
+
sizeof(struct intel_dmc_header);
314
+
if (fsize > fw->size)
315
+
goto error_truncated;
309
316
310
317
/* Extract CSS Header information*/
311
318
css_header = (struct intel_css_header *)fw->data;
···
373
366
/* Convert dmc_offset into number of bytes. By default it is in dwords*/
374
367
dmc_offset *= 4;
375
368
readcount += dmc_offset;
369
+
fsize += dmc_offset;
370
+
if (fsize > fw->size)
371
+
goto error_truncated;
376
372
377
373
/* Extract dmc_header information. */
378
374
dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
···
407
397
408
398
/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
409
399
nbytes = dmc_header->fw_size * 4;
400
+
fsize += nbytes;
401
+
if (fsize > fw->size)
402
+
goto error_truncated;
403
+
410
404
if (nbytes > csr->max_fw_size) {
411
405
DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
412
406
return NULL;
···
424
410
}
425
411
426
412
return memcpy(dmc_payload, &fw->data[readcount], nbytes);
413
+
414
+
error_truncated:
415
+
DRM_ERROR("Truncated DMC firmware, rejecting.\n");
416
+
return NULL;
427
417
}
428
418
429
419
static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
+9
-5
drivers/gpu/drm/i915/intel_display.c
+9
-5
drivers/gpu/drm/i915/intel_display.c
···
2432
2432
* main surface.
2433
2433
*/
2434
2434
static const struct drm_format_info ccs_formats[] = {
2435
-
{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2436
-
{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2437
-
{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2438
-
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2435
+
{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2436
+
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2437
+
{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2438
+
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2439
+
{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2440
+
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2441
+
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2442
+
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2439
2443
};
2440
2444
2441
2445
static const struct drm_format_info *
···
11946
11942
return 0;
11947
11943
}
11948
11944
11949
-
static bool intel_fuzzy_clock_check(int clock1, int clock2)
11945
+
bool intel_fuzzy_clock_check(int clock1, int clock2)
11950
11946
{
11951
11947
int diff;
11952
11948
+1
drivers/gpu/drm/i915/intel_drv.h
+1
drivers/gpu/drm/i915/intel_drv.h
···
1742
1742
const struct dpll *dpll);
1743
1743
void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1744
1744
int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1745
+
bool intel_fuzzy_clock_check(int clock1, int clock2);
1745
1746
1746
1747
/* modesetting asserts */
1747
1748
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
+11
drivers/gpu/drm/i915/intel_dsi_vbt.c
+11
drivers/gpu/drm/i915/intel_dsi_vbt.c
···
853
853
if (mipi_config->target_burst_mode_freq) {
854
854
u32 bitrate = intel_dsi_bitrate(intel_dsi);
855
855
856
+
/*
857
+
* Sometimes the VBT contains a slightly lower clock,
858
+
* then the bitrate we have calculated, in this case
859
+
* just replace it with the calculated bitrate.
860
+
*/
861
+
if (mipi_config->target_burst_mode_freq < bitrate &&
862
+
intel_fuzzy_clock_check(
863
+
mipi_config->target_burst_mode_freq,
864
+
bitrate))
865
+
mipi_config->target_burst_mode_freq = bitrate;
866
+
856
867
if (mipi_config->target_burst_mode_freq < bitrate) {
857
868
DRM_ERROR("Burst mode freq is less than computed\n");
858
869
return false;
+47
-11
drivers/gpu/drm/i915/intel_sdvo.c
+47
-11
drivers/gpu/drm/i915/intel_sdvo.c
···
916
916
return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
917
917
}
918
918
919
+
static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
920
+
u8 audio_state)
921
+
{
922
+
return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
923
+
&audio_state, 1);
924
+
}
925
+
919
926
#if 0
920
927
static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
921
928
{
···
1494
1487
else
1495
1488
sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1496
1489
1497
-
if (crtc_state->has_audio) {
1498
-
WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
1499
-
sdvox |= SDVO_AUDIO_ENABLE;
1500
-
}
1501
-
1502
1490
if (INTEL_GEN(dev_priv) >= 4) {
1503
1491
/* done in crtc_mode_set as the dpll_md reg must be written early */
1504
1492
} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
···
1637
1635
if (sdvox & HDMI_COLOR_RANGE_16_235)
1638
1636
pipe_config->limited_color_range = true;
1639
1637
1640
-
if (sdvox & SDVO_AUDIO_ENABLE)
1641
-
pipe_config->has_audio = true;
1638
+
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1639
+
&val, 1)) {
1640
+
u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT;
1641
+
1642
+
if ((val & mask) == mask)
1643
+
pipe_config->has_audio = true;
1644
+
}
1642
1645
1643
1646
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1644
1647
&val, 1)) {
···
1654
1647
intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
1655
1648
}
1656
1649
1650
+
static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
1651
+
{
1652
+
intel_sdvo_set_audio_state(intel_sdvo, 0);
1653
+
}
1654
+
1655
+
static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
1656
+
const struct intel_crtc_state *crtc_state,
1657
+
const struct drm_connector_state *conn_state)
1658
+
{
1659
+
const struct drm_display_mode *adjusted_mode =
1660
+
&crtc_state->base.adjusted_mode;
1661
+
struct drm_connector *connector = conn_state->connector;
1662
+
u8 *eld = connector->eld;
1663
+
1664
+
eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
1665
+
1666
+
intel_sdvo_set_audio_state(intel_sdvo, 0);
1667
+
1668
+
intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1669
+
SDVO_HBUF_TX_DISABLED,
1670
+
eld, drm_eld_size(eld));
1671
+
1672
+
intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1673
+
SDVO_AUDIO_PRESENCE_DETECT);
1674
+
}
1675
+
1657
1676
static void intel_disable_sdvo(struct intel_encoder *encoder,
1658
1677
const struct intel_crtc_state *old_crtc_state,
1659
1678
const struct drm_connector_state *conn_state)
···
1688
1655
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1689
1656
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1690
1657
u32 temp;
1658
+
1659
+
if (old_crtc_state->has_audio)
1660
+
intel_sdvo_disable_audio(intel_sdvo);
1691
1661
1692
1662
intel_sdvo_set_active_outputs(intel_sdvo, 0);
1693
1663
if (0)
···
1777
1741
intel_sdvo_set_encoder_power_state(intel_sdvo,
1778
1742
DRM_MODE_DPMS_ON);
1779
1743
intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1744
+
1745
+
if (pipe_config->has_audio)
1746
+
intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
1780
1747
}
1781
1748
1782
1749
static enum drm_mode_status
···
2642
2603
intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2643
2604
{
2644
2605
struct drm_encoder *encoder = &intel_sdvo->base.base;
2645
-
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2646
2606
struct drm_connector *connector;
2647
2607
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2648
2608
struct intel_connector *intel_connector;
···
2678
2640
encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2679
2641
connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2680
2642
2681
-
/* gen3 doesn't do the hdmi bits in the SDVO register */
2682
-
if (INTEL_GEN(dev_priv) >= 4 &&
2683
-
intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2643
+
if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2684
2644
connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2685
2645
intel_sdvo_connector->is_hdmi = true;
2686
2646
}
+3
drivers/gpu/drm/i915/intel_sdvo_regs.h
+3
drivers/gpu/drm/i915/intel_sdvo_regs.h
···
707
707
#define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
708
708
#define SDVO_CMD_SET_AUDIO_STAT 0x91
709
709
#define SDVO_CMD_GET_AUDIO_STAT 0x92
710
+
#define SDVO_AUDIO_ELD_VALID (1 << 0)
711
+
#define SDVO_AUDIO_PRESENCE_DETECT (1 << 1)
712
+
#define SDVO_AUDIO_CP_READY (1 << 2)
710
713
#define SDVO_CMD_SET_HBUF_INDEX 0x93
711
714
#define SDVO_HBUF_INDEX_ELD 0
712
715
#define SDVO_HBUF_INDEX_AVI_IF 1
+6
-24
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+6
-24
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
···
90
90
static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
91
91
{
92
92
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
93
-
int i;
94
-
95
-
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
96
-
clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
97
93
98
94
mtk_disp_mutex_put(mtk_crtc->mutex);
99
95
···
182
186
183
187
DRM_DEBUG_DRIVER("%s\n", __func__);
184
188
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
185
-
ret = clk_enable(mtk_crtc->ddp_comp[i]->clk);
189
+
ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk);
186
190
if (ret) {
187
191
DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
188
192
goto err;
···
192
196
return 0;
193
197
err:
194
198
while (--i >= 0)
195
-
clk_disable(mtk_crtc->ddp_comp[i]->clk);
199
+
clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
196
200
return ret;
197
201
}
198
202
···
202
206
203
207
DRM_DEBUG_DRIVER("%s\n", __func__);
204
208
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
205
-
clk_disable(mtk_crtc->ddp_comp[i]->clk);
209
+
clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
206
210
}
207
211
208
212
static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
···
573
577
if (!comp) {
574
578
dev_err(dev, "Component %pOF not initialized\n", node);
575
579
ret = -ENODEV;
576
-
goto unprepare;
577
-
}
578
-
579
-
ret = clk_prepare(comp->clk);
580
-
if (ret) {
581
-
dev_err(dev,
582
-
"Failed to prepare clock for component %pOF: %d\n",
583
-
node, ret);
584
-
goto unprepare;
580
+
return ret;
585
581
}
586
582
587
583
mtk_crtc->ddp_comp[i] = comp;
···
591
603
ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
592
604
BIT(pipe), type);
593
605
if (ret)
594
-
goto unprepare;
606
+
return ret;
595
607
}
596
608
597
609
ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
598
610
mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] :
599
611
NULL, pipe);
600
612
if (ret < 0)
601
-
goto unprepare;
613
+
return ret;
602
614
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
603
615
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
604
616
priv->num_pipes++;
605
617
606
618
return 0;
607
-
608
-
unprepare:
609
-
while (--i >= 0)
610
-
clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
611
-
612
-
return ret;
613
619
}
+3
-5
drivers/gpu/drm/mediatek/mtk_drm_drv.c
+3
-5
drivers/gpu/drm/mediatek/mtk_drm_drv.c
···
303
303
static void mtk_drm_kms_deinit(struct drm_device *drm)
304
304
{
305
305
drm_kms_helper_poll_fini(drm);
306
+
drm_atomic_helper_shutdown(drm);
306
307
307
308
component_unbind_all(drm->dev, drm);
308
309
drm_mode_config_cleanup(drm);
···
390
389
struct mtk_drm_private *private = dev_get_drvdata(dev);
391
390
392
391
drm_dev_unregister(private->drm);
392
+
mtk_drm_kms_deinit(private->drm);
393
393
drm_dev_put(private->drm);
394
+
private->num_pipes = 0;
394
395
private->drm = NULL;
395
396
}
396
397
···
563
560
static int mtk_drm_remove(struct platform_device *pdev)
564
561
{
565
562
struct mtk_drm_private *private = platform_get_drvdata(pdev);
566
-
struct drm_device *drm = private->drm;
567
563
int i;
568
-
569
-
drm_dev_unregister(drm);
570
-
mtk_drm_kms_deinit(drm);
571
-
drm_dev_put(drm);
572
564
573
565
component_master_del(&pdev->dev, &mtk_drm_ops);
574
566
pm_runtime_disable(&pdev->dev);
+6
-1
drivers/gpu/drm/mediatek/mtk_drm_gem.c
+6
-1
drivers/gpu/drm/mediatek/mtk_drm_gem.c
···
136
136
* VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().
137
137
*/
138
138
vma->vm_flags &= ~VM_PFNMAP;
139
-
vma->vm_pgoff = 0;
140
139
141
140
ret = dma_mmap_attrs(priv->dma_dev, vma, mtk_gem->cookie,
142
141
mtk_gem->dma_addr, obj->size, mtk_gem->dma_attrs);
···
166
167
return ret;
167
168
168
169
obj = vma->vm_private_data;
170
+
171
+
/*
172
+
* Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
173
+
* whole buffer from the start.
174
+
*/
175
+
vma->vm_pgoff = 0;
169
176
170
177
return mtk_drm_gem_object_mmap(obj, vma);
171
178
}
+11
-1
drivers/gpu/drm/mediatek/mtk_dsi.c
+11
-1
drivers/gpu/drm/mediatek/mtk_dsi.c
···
622
622
if (--dsi->refcount != 0)
623
623
return;
624
624
625
+
/*
626
+
* mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
627
+
* mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
628
+
* which needs irq for vblank, and mtk_dsi_stop() will disable irq.
629
+
* mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
630
+
* after dsi is fully set.
631
+
*/
632
+
mtk_dsi_stop(dsi);
633
+
625
634
if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
626
635
if (dsi->panel) {
627
636
if (drm_panel_unprepare(dsi->panel)) {
···
697
688
}
698
689
}
699
690
700
-
mtk_dsi_stop(dsi);
701
691
mtk_dsi_poweroff(dsi);
702
692
703
693
dsi->enabled = false;
···
844
836
/* Skip connector cleanup if creation was delegated to the bridge */
845
837
if (dsi->conn.dev)
846
838
drm_connector_cleanup(&dsi->conn);
839
+
if (dsi->panel)
840
+
drm_panel_detach(dsi->panel);
847
841
}
848
842
849
843
static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
+2
-4
drivers/gpu/drm/meson/meson_crtc.c
+2
-4
drivers/gpu/drm/meson/meson_crtc.c
···
107
107
priv->io_base + _REG(VPP_OUT_H_V_SIZE));
108
108
109
109
drm_crtc_vblank_on(crtc);
110
-
111
-
priv->viu.osd1_enabled = true;
112
110
}
113
111
114
112
static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
···
135
137
priv->io_base + _REG(VPP_MISC));
136
138
137
139
drm_crtc_vblank_on(crtc);
138
-
139
-
priv->viu.osd1_enabled = true;
140
140
}
141
141
142
142
static void meson_g12a_crtc_atomic_disable(struct drm_crtc *crtc,
···
252
256
writel_relaxed(priv->viu.osb_blend1_size,
253
257
priv->io_base +
254
258
_REG(VIU_OSD_BLEND_BLEND1_SIZE));
259
+
writel_bits_relaxed(3 << 8, 3 << 8,
260
+
priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
255
261
}
256
262
257
263
static void meson_crtc_enable_vd1(struct meson_drm *priv)
+5
-3
drivers/gpu/drm/meson/meson_plane.c
+5
-3
drivers/gpu/drm/meson/meson_plane.c
···
305
305
meson_plane->enabled = true;
306
306
}
307
307
308
+
priv->viu.osd1_enabled = true;
309
+
308
310
spin_unlock_irqrestore(&priv->drm->event_lock, flags);
309
311
}
310
312
···
318
316
319
317
/* Disable OSD1 */
320
318
if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
321
-
writel_bits_relaxed(BIT(0) | BIT(21), 0,
322
-
priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
319
+
writel_bits_relaxed(3 << 8, 0,
320
+
priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
323
321
else
324
322
writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
325
323
priv->io_base + _REG(VPP_MISC));
326
324
327
325
meson_plane->enabled = false;
328
-
326
+
priv->viu.osd1_enabled = false;
329
327
}
330
328
331
329
static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
+11
-2
drivers/gpu/drm/meson/meson_vclk.c
+11
-2
drivers/gpu/drm/meson/meson_vclk.c
···
503
503
504
504
/* G12A HDMI PLL Needs specific parameters for 5.4GHz */
505
505
if (m >= 0xf7) {
506
-
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0xea68dc00);
507
-
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
506
+
if (frac < 0x10000) {
507
+
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
508
+
0x6a685c00);
509
+
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
510
+
0x11551293);
511
+
} else {
512
+
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
513
+
0xea68dc00);
514
+
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
515
+
0x65771290);
516
+
}
508
517
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
509
518
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
510
519
} else {
+1
-2
drivers/gpu/drm/meson/meson_viu.c
+1
-2
drivers/gpu/drm/meson/meson_viu.c
+1
drivers/gpu/drm/panfrost/Kconfig
+1
drivers/gpu/drm/panfrost/Kconfig
+12
-1
drivers/gpu/drm/panfrost/panfrost_devfreq.c
+12
-1
drivers/gpu/drm/panfrost/panfrost_devfreq.c
···
140
140
return 0;
141
141
142
142
ret = dev_pm_opp_of_add_table(&pfdev->pdev->dev);
143
-
if (ret)
143
+
if (ret == -ENODEV) /* Optional, continue without devfreq */
144
+
return 0;
145
+
else if (ret)
144
146
return ret;
145
147
146
148
panfrost_devfreq_reset(pfdev);
···
172
170
{
173
171
int i;
174
172
173
+
if (!pfdev->devfreq.devfreq)
174
+
return;
175
+
175
176
panfrost_devfreq_reset(pfdev);
176
177
for (i = 0; i < NUM_JOB_SLOTS; i++)
177
178
pfdev->devfreq.slot[i].busy = false;
···
184
179
185
180
void panfrost_devfreq_suspend(struct panfrost_device *pfdev)
186
181
{
182
+
if (!pfdev->devfreq.devfreq)
183
+
return;
184
+
187
185
devfreq_suspend_device(pfdev->devfreq.devfreq);
188
186
}
189
187
···
195
187
struct panfrost_devfreq_slot *devfreq_slot = &pfdev->devfreq.slot[slot];
196
188
ktime_t now;
197
189
ktime_t last;
190
+
191
+
if (!pfdev->devfreq.devfreq)
192
+
return;
198
193
199
194
now = ktime_get();
200
195
last = pfdev->devfreq.slot[slot].time_last_update;
+1
include/drm/drm_edid.h
+1
include/drm/drm_edid.h
···
471
471
struct i2c_adapter *adapter);
472
472
struct edid *drm_edid_duplicate(const struct edid *edid);
473
473
int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
474
+
int drm_add_override_edid_modes(struct drm_connector *connector);
474
475
475
476
u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
476
477
enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);