Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: lynx-28g: restructure protocol configuration register accesses
Eliminate the need to calculate a lane_offset manually, and generate
some macros which access the protocol converter corresponding to the
correct lane in the PCC* registers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20251125114847.804961-10-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Vladimir Oltean
and committed by
Vinod Koul
6af3b6d3
90d985a0
+32
-21
+32
-21
drivers/phy/freescale/phy-fsl-lynx-28g.c
+32
-21
drivers/phy/freescale/phy-fsl-lynx-28g.c
···
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#define LYNX_28G_NUM_LANE 8
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#define LYNX_28G_NUM_PLL 2
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+
#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
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+
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/* General registers per SerDes block */
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#define PCC8 0x10a0
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-
#define PCC8_SGMII 0x1
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#define PCC8_SGMII_DIS 0x0
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#define PCC8_SGMIInCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
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#define PCC8_SGMIInCFG_EN(lane) PCC8_SGMIInCFG(lane, 1)
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#define PCC8_SGMIInCFG_MSK(lane) PCC8_SGMIInCFG(lane, GENMASK(2, 0))
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#define PCC8_SGMIIn_KX(lane, x) ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
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#define PCC8_SGMIIn_KX_MSK(lane) PCC8_SGMIIn_KX(lane, 1)
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#define PCC8_MSK(lane) PCC8_SGMIInCFG_MSK(lane) | \
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PCC8_SGMIIn_KX_MSK(lane)
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#define PCCC 0x10b0
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#define PCCC_10GBASER 0x9
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#define PCCC_USXGMII 0x1
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#define PCCC_SXGMII_DIS 0x0
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#define PCCC_SXGMIInCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
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#define PCCC_SXGMIInCFG_EN(lane) PCCC_SXGMIInCFG(lane, 1)
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#define PCCC_SXGMIInCFG_MSK(lane) PCCC_SXGMIInCFG(lane, GENMASK(2, 0))
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#define PCCC_SXGMIInCFG_XFI(lane, x) ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
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#define PCCC_SXGMIInCFG_XFI_MSK(lane) PCCC_SXGMIInCFG_XFI(lane, 1)
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#define PCCC_MSK(lane) PCCC_SXGMIInCFG_MSK(lane) | \
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PCCC_SXGMIInCFG_XFI_MSK(lane)
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#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
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#define PCCD 0x10b4
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#define PCCD_E25GnCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCCD_OFFSET(lane))
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#define PCCD_E25GnCFG_EN(lane) PCCD_E25GnCFG(lane, 1)
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#define PCCD_E25GnCFG_MSK(lane) PCCD_E25GnCFG(lane, GENMASK(2, 0))
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#define PCCD_MSK(lane) PCCD_E25GnCFG_MSK(lane)
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/* Per PLL registers */
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#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
···
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static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
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{
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struct lynx_28g_priv *priv = lane->priv;
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-
u32 lane_offset = LNa_PCC_OFFSET(lane);
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/* Cleanup the protocol configuration registers of the current protocol */
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switch (lane->interface) {
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case PHY_INTERFACE_MODE_10GBASER:
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lynx_28g_rmw(priv, PCCC,
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PCCC_SXGMII_DIS << lane_offset,
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GENMASK(3, 0) << lane_offset);
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/* Cleanup the protocol configuration registers */
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lynx_28g_rmw(priv, PCCC, 0, PCCC_MSK(lane));
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break;
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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lynx_28g_rmw(priv, PCC8,
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PCC8_SGMII_DIS << lane_offset,
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GENMASK(3, 0) << lane_offset);
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/* Cleanup the protocol configuration registers */
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lynx_28g_rmw(priv, PCC8, 0, PCC8_MSK(lane));
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/* Disable the SGMII PCS */
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lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
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break;
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default:
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break;
···
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static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
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{
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u32 lane_offset = LNa_PCC_OFFSET(lane);
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struct lynx_28g_priv *priv = lane->priv;
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struct lynx_28g_pll *pll;
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lynx_28g_cleanup_lane(lane);
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/* Setup the lane to run in SGMII */
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lynx_28g_rmw(priv, PCC8,
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PCC8_SGMII << lane_offset,
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GENMASK(3, 0) << lane_offset);
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lynx_28g_rmw(priv, PCC8, PCC8_SGMIInCFG_EN(lane), PCC8_MSK(lane));
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/* Setup the protocol select and SerDes parallel interface width */
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lynx_28g_lane_rmw(lane, LNaGCR0,
···
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static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
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{
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struct lynx_28g_priv *priv = lane->priv;
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u32 lane_offset = LNa_PCC_OFFSET(lane);
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struct lynx_28g_pll *pll;
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lynx_28g_cleanup_lane(lane);
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/* Enable the SXGMII lane */
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lynx_28g_rmw(priv, PCCC,
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PCCC_10GBASER << lane_offset,
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GENMASK(3, 0) << lane_offset);
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lynx_28g_rmw(priv, PCCC, PCCC_SXGMIInCFG_EN(lane) |
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PCCC_SXGMIInCFG_XFI(lane, 1), PCCC_MSK(lane));
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/* Setup the protocol select and SerDes parallel interface width */
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lynx_28g_lane_rmw(lane, LNaGCR0,