Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'mlx5-misc-patches'
Tariq Toukan says:
====================
mlx5 misc patches
This patchset includes small features and misc code enhancements for the
mlx5 core and EN drivers.
Patches 1-4 by Gal improves the mlx5e ethtool stats implementation, for
example by using standard helpers ethtool_sprintf/puts.
Patch 5 by me adds a reset option for the FW command interface debugfs
stats entries. This allows explicit FW command interface stats reset
between different runs of a test case.
Patches 6 and 7 are simple cleanups.
Patch 8 by Gal adds driver support for 800Gbps link modes.
Patch 9 by Jianbo enhances the L4 steering abilities.
Patches 10-11 by Jianbo save redundant operations.
====================
Link: https://lore.kernel.org/r/20240402133043.56322-1-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+595
-407
+17
-5
drivers/net/ethernet/mellanox/mlx5/core/debugfs.c
+17
-5
drivers/net/ethernet/mellanox/mlx5/core/debugfs.c
···
143
143
return simple_read_from_buffer(buf, count, pos, tbuf, ret);
144
144
}
145
145
146
-
static ssize_t average_write(struct file *filp, const char __user *buf,
147
-
size_t count, loff_t *pos)
146
+
static ssize_t reset_write(struct file *filp, const char __user *buf,
147
+
size_t count, loff_t *pos)
148
148
{
149
149
struct mlx5_cmd_stats *stats;
150
150
···
152
152
spin_lock_irq(&stats->lock);
153
153
stats->sum = 0;
154
154
stats->n = 0;
155
+
stats->failed = 0;
156
+
stats->failed_mbox_status = 0;
157
+
stats->last_failed_errno = 0;
158
+
stats->last_failed_mbox_status = 0;
159
+
stats->last_failed_syndrome = 0;
155
160
spin_unlock_irq(&stats->lock);
156
161
157
162
*pos += count;
···
164
159
return count;
165
160
}
166
161
167
-
static const struct file_operations stats_fops = {
162
+
static const struct file_operations reset_fops = {
163
+
.owner = THIS_MODULE,
164
+
.open = simple_open,
165
+
.write = reset_write,
166
+
};
167
+
168
+
static const struct file_operations average_fops = {
168
169
.owner = THIS_MODULE,
169
170
.open = simple_open,
170
171
.read = average_read,
171
-
.write = average_write,
172
172
};
173
173
174
174
static ssize_t slots_read(struct file *filp, char __user *buf, size_t count,
···
238
228
continue;
239
229
stats->root = debugfs_create_dir(namep, *cmd);
240
230
231
+
debugfs_create_file("reset", 0200, stats->root, stats,
232
+
&reset_fops);
241
233
debugfs_create_file("average", 0400, stats->root, stats,
242
-
&stats_fops);
234
+
&average_fops);
243
235
debugfs_create_u64("n", 0400, stats->root, &stats->n);
244
236
debugfs_create_u64("failed", 0400, stats->root, &stats->failed);
245
237
debugfs_create_u64("failed_mbox_status", 0400, stats->root,
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en.h
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en.h
···
1160
1160
void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1161
1161
struct ethtool_drvinfo *drvinfo);
1162
1162
void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1163
-
uint32_t stringset, uint8_t *data);
1163
+
u32 stringset, u8 *data);
1164
1164
int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1165
1165
void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1166
1166
struct ethtool_stats *stats, u64 *data);
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
···
565
565
linear = !!(dma_len - inline_hdr_sz);
566
566
ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + linear + !!inline_hdr_sz;
567
567
568
-
/* check_result must be 0 if sinfo is passed. */
568
+
/* check_result must be 0 if xdptxd->has_frags is true. */
569
569
if (!check_result) {
570
570
int stop_room = 1;
571
571
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_accel/fs_tcp.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_accel/fs_tcp.c
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/en_accel/fs_tcp.h
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/en_accel/fs_tcp.h
···
11
11
void mlx5e_accel_fs_tcp_destroy(struct mlx5e_flow_steering *fs);
12
12
struct mlx5_flow_handle *mlx5e_accel_fs_add_sk(struct mlx5e_flow_steering *fs,
13
13
struct sock *sk, u32 tirn,
14
-
uint32_t flow_tag);
14
+
u32 flow_tag);
15
15
void mlx5e_accel_fs_del_sk(struct mlx5_flow_handle *rule);
16
16
#else
17
17
static inline int mlx5e_accel_fs_tcp_create(struct mlx5e_flow_steering *fs) { return 0; }
18
18
static inline void mlx5e_accel_fs_tcp_destroy(struct mlx5e_flow_steering *fs) {}
19
19
static inline struct mlx5_flow_handle *mlx5e_accel_fs_add_sk(struct mlx5e_flow_steering *fs,
20
20
struct sock *sk, u32 tirn,
21
-
uint32_t flow_tag)
21
+
u32 flow_tag)
22
22
{ return ERR_PTR(-EOPNOTSUPP); }
23
23
static inline void mlx5e_accel_fs_del_sk(struct mlx5_flow_handle *rule) {}
24
24
#endif
+12
-16
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_stats.c
+12
-16
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_stats.c
···
78
78
unsigned int i;
79
79
80
80
if (!priv->ipsec)
81
-
return idx;
81
+
return;
82
82
83
83
for (i = 0; i < NUM_IPSEC_HW_COUNTERS; i++)
84
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
85
-
mlx5e_ipsec_hw_stats_desc[i].format);
86
-
87
-
return idx;
84
+
ethtool_puts(data, mlx5e_ipsec_hw_stats_desc[i].format);
88
85
}
89
86
90
87
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(ipsec_hw)
···
89
92
int i;
90
93
91
94
if (!priv->ipsec)
92
-
return idx;
95
+
return;
93
96
94
97
mlx5e_accel_ipsec_fs_read_stats(priv, &priv->ipsec->hw_stats);
95
98
for (i = 0; i < NUM_IPSEC_HW_COUNTERS; i++)
96
-
data[idx++] = MLX5E_READ_CTR_ATOMIC64(&priv->ipsec->hw_stats,
97
-
mlx5e_ipsec_hw_stats_desc, i);
98
-
99
-
return idx;
99
+
mlx5e_ethtool_put_stat(
100
+
data,
101
+
MLX5E_READ_CTR_ATOMIC64(&priv->ipsec->hw_stats,
102
+
mlx5e_ipsec_hw_stats_desc, i));
100
103
}
101
104
102
105
static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(ipsec_sw)
···
112
115
113
116
if (priv->ipsec)
114
117
for (i = 0; i < NUM_IPSEC_SW_COUNTERS; i++)
115
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
116
-
mlx5e_ipsec_sw_stats_desc[i].format);
117
-
return idx;
118
+
ethtool_puts(data, mlx5e_ipsec_sw_stats_desc[i].format);
118
119
}
119
120
120
121
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(ipsec_sw)
···
121
126
122
127
if (priv->ipsec)
123
128
for (i = 0; i < NUM_IPSEC_SW_COUNTERS; i++)
124
-
data[idx++] = MLX5E_READ_CTR_ATOMIC64(&priv->ipsec->sw_stats,
125
-
mlx5e_ipsec_sw_stats_desc, i);
126
-
return idx;
129
+
mlx5e_ethtool_put_stat(
130
+
data, MLX5E_READ_CTR_ATOMIC64(
131
+
&priv->ipsec->sw_stats,
132
+
mlx5e_ipsec_sw_stats_desc, i));
127
133
}
128
134
129
135
MLX5E_DEFINE_STATS_GRP(ipsec_hw, 0);
+4
-10
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.h
+4
-10
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.h
···
95
95
void mlx5e_ktls_cleanup(struct mlx5e_priv *priv);
96
96
97
97
int mlx5e_ktls_get_count(struct mlx5e_priv *priv);
98
-
int mlx5e_ktls_get_strings(struct mlx5e_priv *priv, uint8_t *data);
99
-
int mlx5e_ktls_get_stats(struct mlx5e_priv *priv, u64 *data);
98
+
void mlx5e_ktls_get_strings(struct mlx5e_priv *priv, u8 **data);
99
+
void mlx5e_ktls_get_stats(struct mlx5e_priv *priv, u64 **data);
100
100
101
101
#else
102
102
static inline void mlx5e_ktls_build_netdev(struct mlx5e_priv *priv)
···
144
144
static inline int mlx5e_ktls_init(struct mlx5e_priv *priv) { return 0; }
145
145
static inline void mlx5e_ktls_cleanup(struct mlx5e_priv *priv) { }
146
146
static inline int mlx5e_ktls_get_count(struct mlx5e_priv *priv) { return 0; }
147
-
static inline int mlx5e_ktls_get_strings(struct mlx5e_priv *priv, uint8_t *data)
148
-
{
149
-
return 0;
150
-
}
147
+
static inline void mlx5e_ktls_get_strings(struct mlx5e_priv *priv, u8 **data) { }
151
148
152
-
static inline int mlx5e_ktls_get_stats(struct mlx5e_priv *priv, u64 *data)
153
-
{
154
-
return 0;
155
-
}
149
+
static inline void mlx5e_ktls_get_stats(struct mlx5e_priv *priv, u64 **data) { }
156
150
#endif
157
151
158
152
#endif /* __MLX5E_TLS_H__ */
+11
-15
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_stats.c
+11
-15
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_stats.c
···
58
58
return ARRAY_SIZE(mlx5e_ktls_sw_stats_desc);
59
59
}
60
60
61
-
int mlx5e_ktls_get_strings(struct mlx5e_priv *priv, uint8_t *data)
61
+
void mlx5e_ktls_get_strings(struct mlx5e_priv *priv, u8 **data)
62
62
{
63
-
unsigned int i, n, idx = 0;
63
+
unsigned int i, n;
64
64
65
65
if (!priv->tls)
66
-
return 0;
66
+
return;
67
67
68
68
n = mlx5e_ktls_get_count(priv);
69
69
70
70
for (i = 0; i < n; i++)
71
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
72
-
mlx5e_ktls_sw_stats_desc[i].format);
73
-
74
-
return n;
71
+
ethtool_puts(data, mlx5e_ktls_sw_stats_desc[i].format);
75
72
}
76
73
77
-
int mlx5e_ktls_get_stats(struct mlx5e_priv *priv, u64 *data)
74
+
void mlx5e_ktls_get_stats(struct mlx5e_priv *priv, u64 **data)
78
75
{
79
-
unsigned int i, n, idx = 0;
76
+
unsigned int i, n;
80
77
81
78
if (!priv->tls)
82
-
return 0;
79
+
return;
83
80
84
81
n = mlx5e_ktls_get_count(priv);
85
82
86
83
for (i = 0; i < n; i++)
87
-
data[idx++] = MLX5E_READ_CTR_ATOMIC64(&priv->tls->sw_stats,
88
-
mlx5e_ktls_sw_stats_desc,
89
-
i);
90
-
91
-
return n;
84
+
mlx5e_ethtool_put_stat(
85
+
data,
86
+
MLX5E_READ_CTR_ATOMIC64(&priv->tls->sw_stats,
87
+
mlx5e_ktls_sw_stats_desc, i));
92
88
}
+9
-13
drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec_stats.c
+9
-13
drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec_stats.c
···
38
38
unsigned int i;
39
39
40
40
if (!priv->macsec)
41
-
return idx;
41
+
return;
42
42
43
43
if (!mlx5e_is_macsec_device(priv->mdev))
44
-
return idx;
44
+
return;
45
45
46
46
for (i = 0; i < NUM_MACSEC_HW_COUNTERS; i++)
47
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
48
-
mlx5e_macsec_hw_stats_desc[i].format);
49
-
50
-
return idx;
47
+
ethtool_puts(data, mlx5e_macsec_hw_stats_desc[i].format);
51
48
}
52
49
53
50
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(macsec_hw)
···
53
56
int i;
54
57
55
58
if (!priv->macsec)
56
-
return idx;
59
+
return;
57
60
58
61
if (!mlx5e_is_macsec_device(priv->mdev))
59
-
return idx;
62
+
return;
60
63
61
64
macsec_fs = priv->mdev->macsec_fs;
62
65
mlx5_macsec_fs_get_stats_fill(macsec_fs, mlx5_macsec_fs_get_stats(macsec_fs));
63
66
for (i = 0; i < NUM_MACSEC_HW_COUNTERS; i++)
64
-
data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_macsec_fs_get_stats(macsec_fs),
65
-
mlx5e_macsec_hw_stats_desc,
66
-
i);
67
-
68
-
return idx;
67
+
mlx5e_ethtool_put_stat(
68
+
data, MLX5E_READ_CTR64_CPU(
69
+
mlx5_macsec_fs_get_stats(macsec_fs),
70
+
mlx5e_macsec_hw_stats_desc, i));
69
71
}
70
72
71
73
MLX5E_DEFINE_STATS_GRP(macsec_hw, 0);
+8
-2
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+8
-2
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
···
219
219
ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
220
220
ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
221
221
ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
222
+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_8_800GBASE_CR8_KR8, ext,
223
+
ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT,
224
+
ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT,
225
+
ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT,
226
+
ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,
227
+
ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,
228
+
ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT);
222
229
}
223
230
224
231
static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
···
276
269
switch (stringset) {
277
270
case ETH_SS_PRIV_FLAGS:
278
271
for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
279
-
strcpy(data + i * ETH_GSTRING_LEN,
280
-
mlx5e_priv_flags[i].name);
272
+
ethtool_puts(&data, mlx5e_priv_flags[i].name);
281
273
break;
282
274
283
275
case ETH_SS_TEST:
+2
-4
drivers/net/ethernet/mellanox/mlx5/core/en_fs.c
+2
-4
drivers/net/ethernet/mellanox/mlx5/core/en_fs.c
···
896
896
int tt;
897
897
898
898
memset(ttc_params, 0, sizeof(*ttc_params));
899
-
ttc_params->ns = mlx5_get_flow_namespace(fs->mdev,
900
-
MLX5_FLOW_NAMESPACE_KERNEL);
899
+
ttc_params->ns_type = MLX5_FLOW_NAMESPACE_KERNEL;
901
900
ft_attr->level = MLX5E_INNER_TTC_FT_LEVEL;
902
901
ft_attr->prio = MLX5E_NIC_PRIO;
903
902
···
919
920
int tt;
920
921
921
922
memset(ttc_params, 0, sizeof(*ttc_params));
922
-
ttc_params->ns = mlx5_get_flow_namespace(fs->mdev,
923
-
MLX5_FLOW_NAMESPACE_KERNEL);
923
+
ttc_params->ns_type = MLX5_FLOW_NAMESPACE_KERNEL;
924
924
ft_attr->level = MLX5E_TTC_FT_LEVEL;
925
925
ft_attr->prio = MLX5E_NIC_PRIO;
926
926
+14
-16
drivers/net/ethernet/mellanox/mlx5/core/en_rep.c
+14
-16
drivers/net/ethernet/mellanox/mlx5/core/en_rep.c
···
135
135
int i;
136
136
137
137
for (i = 0; i < NUM_VPORT_REP_SW_COUNTERS; i++)
138
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
139
-
sw_rep_stats_desc[i].format);
140
-
return idx;
138
+
ethtool_puts(data, sw_rep_stats_desc[i].format);
141
139
}
142
140
143
141
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(sw_rep)
···
143
145
int i;
144
146
145
147
for (i = 0; i < NUM_VPORT_REP_SW_COUNTERS; i++)
146
-
data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
147
-
sw_rep_stats_desc, i);
148
-
return idx;
148
+
mlx5e_ethtool_put_stat(
149
+
data, MLX5E_READ_CTR64_CPU(&priv->stats.sw,
150
+
sw_rep_stats_desc, i));
149
151
}
150
152
151
153
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(sw_rep)
···
174
176
int i;
175
177
176
178
for (i = 0; i < NUM_VPORT_REP_HW_COUNTERS; i++)
177
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_rep_stats_desc[i].format);
179
+
ethtool_puts(data, vport_rep_stats_desc[i].format);
178
180
for (i = 0; i < NUM_VPORT_REP_LOOPBACK_COUNTERS(priv->mdev); i++)
179
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
180
-
vport_rep_loopback_stats_desc[i].format);
181
-
return idx;
181
+
ethtool_puts(data, vport_rep_loopback_stats_desc[i].format);
182
182
}
183
183
184
184
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vport_rep)
···
184
188
int i;
185
189
186
190
for (i = 0; i < NUM_VPORT_REP_HW_COUNTERS; i++)
187
-
data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.rep_stats,
188
-
vport_rep_stats_desc, i);
191
+
mlx5e_ethtool_put_stat(
192
+
data, MLX5E_READ_CTR64_CPU(&priv->stats.rep_stats,
193
+
vport_rep_stats_desc, i));
189
194
for (i = 0; i < NUM_VPORT_REP_LOOPBACK_COUNTERS(priv->mdev); i++)
190
-
data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.rep_stats,
191
-
vport_rep_loopback_stats_desc, i);
192
-
return idx;
195
+
mlx5e_ethtool_put_stat(
196
+
data,
197
+
MLX5E_READ_CTR64_CPU(&priv->stats.rep_stats,
198
+
vport_rep_loopback_stats_desc, i));
193
199
}
194
200
195
201
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vport_rep)
···
274
276
}
275
277
276
278
static void mlx5e_rep_get_strings(struct net_device *dev,
277
-
u32 stringset, uint8_t *data)
279
+
u32 stringset, u8 *data)
278
280
{
279
281
struct mlx5e_priv *priv = netdev_priv(dev);
280
282
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c
+245
-246
drivers/net/ethernet/mellanox/mlx5/core/en_stats.c
+245
-246
drivers/net/ethernet/mellanox/mlx5/core/en_stats.c
···
41
41
#include <net/page_pool/helpers.h>
42
42
#endif
43
43
44
+
void mlx5e_ethtool_put_stat(u64 **data, u64 val)
45
+
{
46
+
*(*data)++ = val;
47
+
}
48
+
44
49
static unsigned int stats_grps_num(struct mlx5e_priv *priv)
45
50
{
46
51
return !priv->profile->stats_grps_num ? 0 :
···
95
90
int i;
96
91
97
92
for (i = 0; i < num_stats_grps; i++)
98
-
idx = stats_grps[i]->fill_stats(priv, data, idx);
93
+
stats_grps[i]->fill_stats(priv, &data);
99
94
}
100
95
101
96
void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data)
102
97
{
103
98
mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
104
99
const unsigned int num_stats_grps = stats_grps_num(priv);
105
-
int i, idx = 0;
100
+
int i;
106
101
107
102
for (i = 0; i < num_stats_grps; i++)
108
-
idx = stats_grps[i]->fill_strings(priv, data, idx);
103
+
stats_grps[i]->fill_strings(priv, &data);
109
104
}
110
105
111
106
/* Concrete NIC Stats */
···
262
257
int i;
263
258
264
259
for (i = 0; i < NUM_SW_COUNTERS; i++)
265
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
266
-
return idx;
260
+
ethtool_puts(data, sw_stats_desc[i].format);
267
261
}
268
262
269
263
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(sw)
···
270
266
int i;
271
267
272
268
for (i = 0; i < NUM_SW_COUNTERS; i++)
273
-
data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
274
-
return idx;
269
+
mlx5e_ethtool_put_stat(data,
270
+
MLX5E_READ_CTR64_CPU(&priv->stats.sw,
271
+
sw_stats_desc, i));
275
272
}
276
273
277
274
static void mlx5e_stats_grp_sw_update_stats_xdp_red(struct mlx5e_sw_stats *s,
···
596
591
int i;
597
592
598
593
for (i = 0; i < NUM_Q_COUNTERS && q_counter_any(priv); i++)
599
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
600
-
q_stats_desc[i].format);
594
+
ethtool_puts(data, q_stats_desc[i].format);
601
595
602
596
for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
603
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
604
-
drop_rq_stats_desc[i].format);
605
-
606
-
return idx;
597
+
ethtool_puts(data, drop_rq_stats_desc[i].format);
607
598
}
608
599
609
600
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qcnt)
···
607
606
int i;
608
607
609
608
for (i = 0; i < NUM_Q_COUNTERS && q_counter_any(priv); i++)
610
-
data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
611
-
q_stats_desc, i);
609
+
mlx5e_ethtool_put_stat(data,
610
+
MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
611
+
q_stats_desc, i));
612
612
for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
613
-
data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
614
-
drop_rq_stats_desc, i);
615
-
return idx;
613
+
mlx5e_ethtool_put_stat(
614
+
data, MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
615
+
drop_rq_stats_desc, i));
616
616
}
617
617
618
618
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qcnt)
···
687
685
int i;
688
686
689
687
for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++)
690
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
691
-
vnic_env_stats_steer_desc[i].format);
688
+
ethtool_puts(data, vnic_env_stats_steer_desc[i].format);
692
689
693
690
for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++)
694
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
695
-
vnic_env_stats_dev_oob_desc[i].format);
691
+
ethtool_puts(data, vnic_env_stats_dev_oob_desc[i].format);
696
692
697
693
for (i = 0; i < NUM_VNIC_ENV_DROP_COUNTERS(priv->mdev); i++)
698
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
699
-
vnic_env_stats_drop_desc[i].format);
700
-
701
-
return idx;
694
+
ethtool_puts(data, vnic_env_stats_drop_desc[i].format);
702
695
}
703
696
704
697
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vnic_env)
···
701
704
int i;
702
705
703
706
for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++)
704
-
data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
705
-
vnic_env_stats_steer_desc, i);
707
+
mlx5e_ethtool_put_stat(
708
+
data,
709
+
MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
710
+
vnic_env_stats_steer_desc, i));
706
711
707
712
for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++)
708
-
data[idx++] = MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
709
-
vnic_env_stats_dev_oob_desc, i);
713
+
mlx5e_ethtool_put_stat(
714
+
data,
715
+
MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
716
+
vnic_env_stats_dev_oob_desc, i));
710
717
711
718
for (i = 0; i < NUM_VNIC_ENV_DROP_COUNTERS(priv->mdev); i++)
712
-
data[idx++] = MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
713
-
vnic_env_stats_drop_desc, i);
714
-
715
-
return idx;
719
+
mlx5e_ethtool_put_stat(
720
+
data,
721
+
MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
722
+
vnic_env_stats_drop_desc, i));
716
723
}
717
724
718
725
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vnic_env)
···
799
798
int i;
800
799
801
800
for (i = 0; i < NUM_VPORT_COUNTERS; i++)
802
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
801
+
ethtool_puts(data, vport_stats_desc[i].format);
803
802
804
803
for (i = 0; i < NUM_VPORT_LOOPBACK_COUNTERS(priv->mdev); i++)
805
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
806
-
vport_loopback_stats_desc[i].format);
807
-
808
-
return idx;
804
+
ethtool_puts(data, vport_loopback_stats_desc[i].format);
809
805
}
810
806
811
807
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vport)
···
810
812
int i;
811
813
812
814
for (i = 0; i < NUM_VPORT_COUNTERS; i++)
813
-
data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
814
-
vport_stats_desc, i);
815
+
mlx5e_ethtool_put_stat(
816
+
data,
817
+
MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
818
+
vport_stats_desc, i));
815
819
816
820
for (i = 0; i < NUM_VPORT_LOOPBACK_COUNTERS(priv->mdev); i++)
817
-
data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
818
-
vport_loopback_stats_desc, i);
819
-
820
-
return idx;
821
+
mlx5e_ethtool_put_stat(
822
+
data,
823
+
MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
824
+
vport_loopback_stats_desc, i));
821
825
}
822
826
823
827
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vport)
···
868
868
int i;
869
869
870
870
for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
871
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
872
-
return idx;
871
+
ethtool_puts(data, pport_802_3_stats_desc[i].format);
873
872
}
874
873
875
874
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(802_3)
···
876
877
int i;
877
878
878
879
for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
879
-
data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
880
-
pport_802_3_stats_desc, i);
881
-
return idx;
880
+
mlx5e_ethtool_put_stat(
881
+
data, MLX5E_READ_CTR64_BE(
882
+
&priv->stats.pport.IEEE_802_3_counters,
883
+
pport_802_3_stats_desc, i));
882
884
}
883
885
884
886
#define MLX5_BASIC_PPCNT_SUPPORTED(mdev) \
···
1029
1029
int i;
1030
1030
1031
1031
for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
1032
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
1033
-
return idx;
1032
+
ethtool_puts(data, pport_2863_stats_desc[i].format);
1034
1033
}
1035
1034
1036
1035
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2863)
···
1037
1038
int i;
1038
1039
1039
1040
for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
1040
-
data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
1041
-
pport_2863_stats_desc, i);
1042
-
return idx;
1041
+
mlx5e_ethtool_put_stat(
1042
+
data, MLX5E_READ_CTR64_BE(
1043
+
&priv->stats.pport.RFC_2863_counters,
1044
+
pport_2863_stats_desc, i));
1043
1045
}
1044
1046
1045
1047
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2863)
···
1088
1088
int i;
1089
1089
1090
1090
for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
1091
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
1092
-
return idx;
1091
+
ethtool_puts(data, pport_2819_stats_desc[i].format);
1093
1092
}
1094
1093
1095
1094
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2819)
···
1096
1097
int i;
1097
1098
1098
1099
for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
1099
-
data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
1100
-
pport_2819_stats_desc, i);
1101
-
return idx;
1100
+
mlx5e_ethtool_put_stat(
1101
+
data, MLX5E_READ_CTR64_BE(
1102
+
&priv->stats.pport.RFC_2819_counters,
1103
+
pport_2819_stats_desc, i));
1102
1104
}
1103
1105
1104
1106
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2819)
···
1215
1215
struct mlx5_core_dev *mdev = priv->mdev;
1216
1216
int i;
1217
1217
1218
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
1218
+
ethtool_puts(data, "link_down_events_phy");
1219
1219
1220
1220
if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
1221
-
return idx;
1221
+
return;
1222
1222
1223
1223
for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
1224
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
1225
-
pport_phy_statistical_stats_desc[i].format);
1224
+
ethtool_puts(data, pport_phy_statistical_stats_desc[i].format);
1226
1225
1227
1226
if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters))
1228
1227
for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++)
1229
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
1230
-
pport_phy_statistical_err_lanes_stats_desc[i].format);
1231
-
1232
-
return idx;
1228
+
ethtool_puts(data,
1229
+
pport_phy_statistical_err_lanes_stats_desc[i].format);
1233
1230
}
1234
1231
1235
1232
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy)
···
1235
1238
int i;
1236
1239
1237
1240
/* link_down_events_phy has special handling since it is not stored in __be64 format */
1238
-
data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
1239
-
counter_set.phys_layer_cntrs.link_down_events);
1241
+
mlx5e_ethtool_put_stat(
1242
+
data, MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
1243
+
counter_set.phys_layer_cntrs.link_down_events));
1240
1244
1241
1245
if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
1242
-
return idx;
1246
+
return;
1243
1247
1244
1248
for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
1245
-
data[idx++] =
1246
-
MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
1247
-
pport_phy_statistical_stats_desc, i);
1249
+
mlx5e_ethtool_put_stat(
1250
+
data,
1251
+
MLX5E_READ_CTR64_BE(
1252
+
&priv->stats.pport.phy_statistical_counters,
1253
+
pport_phy_statistical_stats_desc, i));
1248
1254
1249
1255
if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters))
1250
1256
for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++)
1251
-
data[idx++] =
1252
-
MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
1253
-
pport_phy_statistical_err_lanes_stats_desc,
1254
-
i);
1255
-
return idx;
1257
+
mlx5e_ethtool_put_stat(
1258
+
data,
1259
+
MLX5E_READ_CTR64_BE(
1260
+
&priv->stats.pport
1261
+
.phy_statistical_counters,
1262
+
pport_phy_statistical_err_lanes_stats_desc,
1263
+
i));
1256
1264
}
1257
1265
1258
1266
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy)
···
1438
1436
1439
1437
if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
1440
1438
for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
1441
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
1442
-
pport_eth_ext_stats_desc[i].format);
1443
-
return idx;
1439
+
ethtool_puts(data, pport_eth_ext_stats_desc[i].format);
1444
1440
}
1445
1441
1446
1442
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(eth_ext)
···
1447
1447
1448
1448
if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
1449
1449
for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
1450
-
data[idx++] =
1451
-
MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
1452
-
pport_eth_ext_stats_desc, i);
1453
-
return idx;
1450
+
mlx5e_ethtool_put_stat(
1451
+
data,
1452
+
MLX5E_READ_CTR64_BE(
1453
+
&priv->stats.pport.eth_ext_counters,
1454
+
pport_eth_ext_stats_desc, i));
1454
1455
}
1455
1456
1456
1457
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(eth_ext)
···
1517
1516
1518
1517
if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1519
1518
for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
1520
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
1521
-
pcie_perf_stats_desc[i].format);
1519
+
ethtool_puts(data, pcie_perf_stats_desc[i].format);
1522
1520
1523
1521
if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1524
1522
for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
1525
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
1526
-
pcie_perf_stats_desc64[i].format);
1523
+
ethtool_puts(data, pcie_perf_stats_desc64[i].format);
1527
1524
1528
1525
if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1529
1526
for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
1530
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
1531
-
pcie_perf_stall_stats_desc[i].format);
1532
-
return idx;
1527
+
ethtool_puts(data,
1528
+
pcie_perf_stall_stats_desc[i].format);
1533
1529
}
1534
1530
1535
1531
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pcie)
···
1535
1537
1536
1538
if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1537
1539
for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
1538
-
data[idx++] =
1539
-
MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
1540
-
pcie_perf_stats_desc, i);
1540
+
mlx5e_ethtool_put_stat(
1541
+
data,
1542
+
MLX5E_READ_CTR32_BE(
1543
+
&priv->stats.pcie.pcie_perf_counters,
1544
+
pcie_perf_stats_desc, i));
1541
1545
1542
1546
if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1543
1547
for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
1544
-
data[idx++] =
1545
-
MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
1546
-
pcie_perf_stats_desc64, i);
1548
+
mlx5e_ethtool_put_stat(
1549
+
data,
1550
+
MLX5E_READ_CTR64_BE(
1551
+
&priv->stats.pcie.pcie_perf_counters,
1552
+
pcie_perf_stats_desc64, i));
1547
1553
1548
1554
if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1549
1555
for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
1550
-
data[idx++] =
1551
-
MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
1552
-
pcie_perf_stall_stats_desc, i);
1553
-
return idx;
1556
+
mlx5e_ethtool_put_stat(
1557
+
data,
1558
+
MLX5E_READ_CTR32_BE(
1559
+
&priv->stats.pcie.pcie_perf_counters,
1560
+
pcie_perf_stall_stats_desc, i));
1554
1561
}
1555
1562
1556
1563
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pcie)
···
1612
1609
int i, prio;
1613
1610
1614
1611
if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1615
-
return idx;
1612
+
return;
1616
1613
1617
1614
for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1618
1615
for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
1619
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
1620
-
pport_per_tc_prio_stats_desc[i].format, prio);
1616
+
ethtool_sprintf(data,
1617
+
pport_per_tc_prio_stats_desc[i].format,
1618
+
prio);
1621
1619
for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS; i++)
1622
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
1623
-
pport_per_tc_congest_prio_stats_desc[i].format, prio);
1620
+
ethtool_sprintf(data,
1621
+
pport_per_tc_congest_prio_stats_desc[i].format,
1622
+
prio);
1624
1623
}
1625
-
1626
-
return idx;
1627
1624
}
1628
1625
1629
1626
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_port_buff_congest)
···
1633
1630
int i, prio;
1634
1631
1635
1632
if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1636
-
return idx;
1633
+
return;
1637
1634
1638
1635
for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1639
1636
for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
1640
-
data[idx++] =
1641
-
MLX5E_READ_CTR64_BE(&pport->per_tc_prio_counters[prio],
1642
-
pport_per_tc_prio_stats_desc, i);
1637
+
mlx5e_ethtool_put_stat(
1638
+
data,
1639
+
MLX5E_READ_CTR64_BE(
1640
+
&pport->per_tc_prio_counters[prio],
1641
+
pport_per_tc_prio_stats_desc, i));
1643
1642
for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS ; i++)
1644
-
data[idx++] =
1645
-
MLX5E_READ_CTR64_BE(&pport->per_tc_congest_prio_counters[prio],
1646
-
pport_per_tc_congest_prio_stats_desc, i);
1643
+
mlx5e_ethtool_put_stat(
1644
+
data,
1645
+
MLX5E_READ_CTR64_BE(
1646
+
&pport->per_tc_congest_prio_counters
1647
+
[prio],
1648
+
pport_per_tc_congest_prio_stats_desc,
1649
+
i));
1647
1650
}
1648
-
1649
-
return idx;
1650
1651
}
1651
1652
1652
1653
static void mlx5e_grp_per_tc_prio_update_stats(struct mlx5e_priv *priv)
···
1735
1728
return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
1736
1729
}
1737
1730
1738
-
static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
1739
-
u8 *data,
1740
-
int idx)
1731
+
static void mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
1732
+
u8 **data)
1741
1733
{
1742
1734
int i, prio;
1743
1735
1744
1736
for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1745
1737
for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
1746
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
1747
-
pport_per_prio_traffic_stats_desc[i].format, prio);
1738
+
ethtool_sprintf(data,
1739
+
pport_per_prio_traffic_stats_desc[i].format,
1740
+
prio);
1748
1741
}
1749
-
1750
-
return idx;
1751
1742
}
1752
1743
1753
-
static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
1754
-
u64 *data,
1755
-
int idx)
1744
+
static void mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
1745
+
u64 **data)
1756
1746
{
1757
1747
int i, prio;
1758
1748
1759
1749
for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1760
1750
for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
1761
-
data[idx++] =
1762
-
MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
1763
-
pport_per_prio_traffic_stats_desc, i);
1751
+
mlx5e_ethtool_put_stat(
1752
+
data,
1753
+
MLX5E_READ_CTR64_BE(
1754
+
&priv->stats.pport
1755
+
.per_prio_counters[prio],
1756
+
pport_per_prio_traffic_stats_desc, i));
1764
1757
}
1765
-
1766
-
return idx;
1767
1758
}
1768
1759
1769
1760
static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
···
1821
1816
NUM_PPORT_PFC_STALL_COUNTERS(priv);
1822
1817
}
1823
1818
1824
-
static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
1825
-
u8 *data,
1826
-
int idx)
1819
+
static void mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
1820
+
u8 **data)
1827
1821
{
1828
1822
unsigned long pfc_combined;
1829
1823
int i, prio;
···
1833
1829
char pfc_string[ETH_GSTRING_LEN];
1834
1830
1835
1831
snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
1836
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
1837
-
pport_per_prio_pfc_stats_desc[i].format, pfc_string);
1832
+
ethtool_sprintf(data,
1833
+
pport_per_prio_pfc_stats_desc[i].format,
1834
+
pfc_string);
1838
1835
}
1839
1836
}
1840
1837
1841
1838
if (mlx5e_query_global_pause_combined(priv)) {
1842
1839
for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1843
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
1844
-
pport_per_prio_pfc_stats_desc[i].format, "global");
1840
+
ethtool_sprintf(data,
1841
+
pport_per_prio_pfc_stats_desc[i].format,
1842
+
"global");
1845
1843
}
1846
1844
}
1847
1845
1848
1846
for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
1849
-
strcpy(data + (idx++) * ETH_GSTRING_LEN,
1850
-
pport_pfc_stall_stats_desc[i].format);
1851
-
1852
-
return idx;
1847
+
ethtool_puts(data, pport_pfc_stall_stats_desc[i].format);
1853
1848
}
1854
1849
1855
-
static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
1856
-
u64 *data,
1857
-
int idx)
1850
+
static void mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
1851
+
u64 **data)
1858
1852
{
1859
1853
unsigned long pfc_combined;
1860
1854
int i, prio;
···
1860
1858
pfc_combined = mlx5e_query_pfc_combined(priv);
1861
1859
for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
1862
1860
for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1863
-
data[idx++] =
1864
-
MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
1865
-
pport_per_prio_pfc_stats_desc, i);
1861
+
mlx5e_ethtool_put_stat(
1862
+
data,
1863
+
MLX5E_READ_CTR64_BE(
1864
+
&priv->stats.pport
1865
+
.per_prio_counters[prio],
1866
+
pport_per_prio_pfc_stats_desc, i));
1866
1867
}
1867
1868
}
1868
1869
1869
1870
if (mlx5e_query_global_pause_combined(priv)) {
1870
1871
for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1871
-
data[idx++] =
1872
-
MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1873
-
pport_per_prio_pfc_stats_desc, i);
1872
+
mlx5e_ethtool_put_stat(
1873
+
data,
1874
+
MLX5E_READ_CTR64_BE(
1875
+
&priv->stats.pport.per_prio_counters[0],
1876
+
pport_per_prio_pfc_stats_desc, i));
1874
1877
}
1875
1878
}
1876
1879
1877
1880
for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
1878
-
data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1879
-
pport_pfc_stall_stats_desc, i);
1880
-
1881
-
return idx;
1881
+
mlx5e_ethtool_put_stat(
1882
+
data, MLX5E_READ_CTR64_BE(
1883
+
&priv->stats.pport.per_prio_counters[0],
1884
+
pport_pfc_stall_stats_desc, i));
1882
1885
}
1883
1886
1884
1887
static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_prio)
···
1894
1887
1895
1888
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_prio)
1896
1889
{
1897
-
idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
1898
-
idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
1899
-
return idx;
1890
+
mlx5e_grp_per_prio_traffic_fill_strings(priv, data);
1891
+
mlx5e_grp_per_prio_pfc_fill_strings(priv, data);
1900
1892
}
1901
1893
1902
1894
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_prio)
1903
1895
{
1904
-
idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
1905
-
idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
1906
-
return idx;
1896
+
mlx5e_grp_per_prio_traffic_fill_stats(priv, data);
1897
+
mlx5e_grp_per_prio_pfc_fill_stats(priv, data);
1907
1898
}
1908
1899
1909
1900
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_prio)
···
1949
1944
int i;
1950
1945
1951
1946
for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1952
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1947
+
ethtool_puts(data, mlx5e_pme_status_desc[i].format);
1953
1948
1954
1949
for (i = 0; i < NUM_PME_ERR_STATS; i++)
1955
-
strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1956
-
1957
-
return idx;
1950
+
ethtool_puts(data, mlx5e_pme_error_desc[i].format);
1958
1951
}
1959
1952
1960
1953
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pme)
···
1963
1960
mlx5_get_pme_stats(priv->mdev, &pme_stats);
1964
1961
1965
1962
for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1966
-
data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.status_counters,
1967
-
mlx5e_pme_status_desc, i);
1963
+
mlx5e_ethtool_put_stat(
1964
+
data, MLX5E_READ_CTR64_CPU(pme_stats.status_counters,
1965
+
mlx5e_pme_status_desc, i));
1968
1966
1969
1967
for (i = 0; i < NUM_PME_ERR_STATS; i++)
1970
-
data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.error_counters,
1971
-
mlx5e_pme_error_desc, i);
1972
-
1973
-
return idx;
1968
+
mlx5e_ethtool_put_stat(
1969
+
data, MLX5E_READ_CTR64_CPU(pme_stats.error_counters,
1970
+
mlx5e_pme_error_desc, i));
1974
1971
}
1975
1972
1976
1973
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pme) { return; }
···
1982
1979
1983
1980
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(tls)
1984
1981
{
1985
-
return idx + mlx5e_ktls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1982
+
mlx5e_ktls_get_strings(priv, data);
1986
1983
}
1987
1984
1988
1985
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(tls)
1989
1986
{
1990
-
return idx + mlx5e_ktls_get_stats(priv, data + idx);
1987
+
mlx5e_ktls_get_stats(priv, data);
1991
1988
}
1992
1989
1993
1990
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(tls) { return; }
···
2267
2264
2268
2265
for (qid = 0; qid < max_qos_sqs; qid++)
2269
2266
for (i = 0; i < NUM_QOS_SQ_STATS; i++)
2270
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2271
-
qos_sq_stats_desc[i].format, qid);
2272
-
2273
-
return idx;
2267
+
ethtool_sprintf(data, qos_sq_stats_desc[i].format, qid);
2274
2268
}
2275
2269
2276
2270
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qos)
···
2284
2284
struct mlx5e_sq_stats *s = READ_ONCE(stats[qid]);
2285
2285
2286
2286
for (i = 0; i < NUM_QOS_SQ_STATS; i++)
2287
-
data[idx++] = MLX5E_READ_CTR64_CPU(s, qos_sq_stats_desc, i);
2287
+
mlx5e_ethtool_put_stat(
2288
+
data,
2289
+
MLX5E_READ_CTR64_CPU(s, qos_sq_stats_desc, i));
2288
2290
}
2289
-
2290
-
return idx;
2291
2291
}
2292
2292
2293
2293
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qos) { return; }
···
2312
2312
int i, tc;
2313
2313
2314
2314
if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
2315
-
return idx;
2315
+
return;
2316
2316
2317
2317
for (i = 0; i < NUM_PTP_CH_STATS; i++)
2318
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2319
-
"%s", ptp_ch_stats_desc[i].format);
2318
+
ethtool_puts(data, ptp_ch_stats_desc[i].format);
2320
2319
2321
2320
if (priv->tx_ptp_opened) {
2322
2321
for (tc = 0; tc < priv->max_opened_tc; tc++)
2323
2322
for (i = 0; i < NUM_PTP_SQ_STATS; i++)
2324
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2325
-
ptp_sq_stats_desc[i].format, tc);
2323
+
ethtool_sprintf(data,
2324
+
ptp_sq_stats_desc[i].format,
2325
+
tc);
2326
2326
2327
2327
for (tc = 0; tc < priv->max_opened_tc; tc++)
2328
2328
for (i = 0; i < NUM_PTP_CQ_STATS; i++)
2329
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2330
-
ptp_cq_stats_desc[i].format, tc);
2329
+
ethtool_sprintf(data,
2330
+
ptp_cq_stats_desc[i].format,
2331
+
tc);
2331
2332
}
2332
2333
if (priv->rx_ptp_opened) {
2333
2334
for (i = 0; i < NUM_PTP_RQ_STATS; i++)
2334
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2335
-
ptp_rq_stats_desc[i].format, MLX5E_PTP_CHANNEL_IX);
2335
+
ethtool_sprintf(data, ptp_rq_stats_desc[i].format,
2336
+
MLX5E_PTP_CHANNEL_IX);
2336
2337
}
2337
-
return idx;
2338
2338
}
2339
2339
2340
2340
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(ptp)
···
2342
2342
int i, tc;
2343
2343
2344
2344
if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
2345
-
return idx;
2345
+
return;
2346
2346
2347
2347
for (i = 0; i < NUM_PTP_CH_STATS; i++)
2348
-
data[idx++] =
2349
-
MLX5E_READ_CTR64_CPU(&priv->ptp_stats.ch,
2350
-
ptp_ch_stats_desc, i);
2348
+
mlx5e_ethtool_put_stat(
2349
+
data, MLX5E_READ_CTR64_CPU(&priv->ptp_stats.ch,
2350
+
ptp_ch_stats_desc, i));
2351
2351
2352
2352
if (priv->tx_ptp_opened) {
2353
2353
for (tc = 0; tc < priv->max_opened_tc; tc++)
2354
2354
for (i = 0; i < NUM_PTP_SQ_STATS; i++)
2355
-
data[idx++] =
2356
-
MLX5E_READ_CTR64_CPU(&priv->ptp_stats.sq[tc],
2357
-
ptp_sq_stats_desc, i);
2355
+
mlx5e_ethtool_put_stat(
2356
+
data, MLX5E_READ_CTR64_CPU(
2357
+
&priv->ptp_stats.sq[tc],
2358
+
ptp_sq_stats_desc, i));
2358
2359
2359
2360
for (tc = 0; tc < priv->max_opened_tc; tc++)
2360
2361
for (i = 0; i < NUM_PTP_CQ_STATS; i++)
2361
-
data[idx++] =
2362
-
MLX5E_READ_CTR64_CPU(&priv->ptp_stats.cq[tc],
2363
-
ptp_cq_stats_desc, i);
2362
+
mlx5e_ethtool_put_stat(
2363
+
data, MLX5E_READ_CTR64_CPU(
2364
+
&priv->ptp_stats.cq[tc],
2365
+
ptp_cq_stats_desc, i));
2364
2366
}
2365
2367
if (priv->rx_ptp_opened) {
2366
2368
for (i = 0; i < NUM_PTP_RQ_STATS; i++)
2367
-
data[idx++] =
2369
+
mlx5e_ethtool_put_stat(
2370
+
data,
2368
2371
MLX5E_READ_CTR64_CPU(&priv->ptp_stats.rq,
2369
-
ptp_rq_stats_desc, i);
2372
+
ptp_rq_stats_desc, i));
2370
2373
}
2371
-
return idx;
2372
2374
}
2373
2375
2374
2376
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(ptp) { return; }
···
2396
2394
2397
2395
for (i = 0; i < max_nch; i++)
2398
2396
for (j = 0; j < NUM_CH_STATS; j++)
2399
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2400
-
ch_stats_desc[j].format, i);
2397
+
ethtool_sprintf(data, ch_stats_desc[j].format, i);
2401
2398
2402
2399
for (i = 0; i < max_nch; i++) {
2403
2400
for (j = 0; j < NUM_RQ_STATS; j++)
2404
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2405
-
rq_stats_desc[j].format, i);
2401
+
ethtool_sprintf(data, rq_stats_desc[j].format, i);
2406
2402
for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++)
2407
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2408
-
xskrq_stats_desc[j].format, i);
2403
+
ethtool_sprintf(data, xskrq_stats_desc[j].format, i);
2409
2404
for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
2410
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2411
-
rq_xdpsq_stats_desc[j].format, i);
2405
+
ethtool_sprintf(data, rq_xdpsq_stats_desc[j].format, i);
2412
2406
}
2413
2407
2414
2408
for (tc = 0; tc < priv->max_opened_tc; tc++)
2415
2409
for (i = 0; i < max_nch; i++)
2416
2410
for (j = 0; j < NUM_SQ_STATS; j++)
2417
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2418
-
sq_stats_desc[j].format,
2419
-
i + tc * max_nch);
2411
+
ethtool_sprintf(data, sq_stats_desc[j].format,
2412
+
i + tc * max_nch);
2420
2413
2421
2414
for (i = 0; i < max_nch; i++) {
2422
2415
for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++)
2423
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2424
-
xsksq_stats_desc[j].format, i);
2416
+
ethtool_sprintf(data, xsksq_stats_desc[j].format, i);
2425
2417
for (j = 0; j < NUM_XDPSQ_STATS; j++)
2426
-
sprintf(data + (idx++) * ETH_GSTRING_LEN,
2427
-
xdpsq_stats_desc[j].format, i);
2418
+
ethtool_sprintf(data, xdpsq_stats_desc[j].format, i);
2428
2419
}
2429
-
2430
-
return idx;
2431
2420
}
2432
2421
2433
2422
static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(channels)
···
2429
2436
2430
2437
for (i = 0; i < max_nch; i++)
2431
2438
for (j = 0; j < NUM_CH_STATS; j++)
2432
-
data[idx++] =
2433
-
MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->ch,
2434
-
ch_stats_desc, j);
2439
+
mlx5e_ethtool_put_stat(
2440
+
data, MLX5E_READ_CTR64_CPU(
2441
+
&priv->channel_stats[i]->ch,
2442
+
ch_stats_desc, j));
2435
2443
2436
2444
for (i = 0; i < max_nch; i++) {
2437
2445
for (j = 0; j < NUM_RQ_STATS; j++)
2438
-
data[idx++] =
2439
-
MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->rq,
2440
-
rq_stats_desc, j);
2446
+
mlx5e_ethtool_put_stat(
2447
+
data, MLX5E_READ_CTR64_CPU(
2448
+
&priv->channel_stats[i]->rq,
2449
+
rq_stats_desc, j));
2441
2450
for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++)
2442
-
data[idx++] =
2443
-
MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->xskrq,
2444
-
xskrq_stats_desc, j);
2451
+
mlx5e_ethtool_put_stat(
2452
+
data, MLX5E_READ_CTR64_CPU(
2453
+
&priv->channel_stats[i]->xskrq,
2454
+
xskrq_stats_desc, j));
2445
2455
for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
2446
-
data[idx++] =
2447
-
MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->rq_xdpsq,
2448
-
rq_xdpsq_stats_desc, j);
2456
+
mlx5e_ethtool_put_stat(
2457
+
data, MLX5E_READ_CTR64_CPU(
2458
+
&priv->channel_stats[i]->rq_xdpsq,
2459
+
rq_xdpsq_stats_desc, j));
2449
2460
}
2450
2461
2451
2462
for (tc = 0; tc < priv->max_opened_tc; tc++)
2452
2463
for (i = 0; i < max_nch; i++)
2453
2464
for (j = 0; j < NUM_SQ_STATS; j++)
2454
-
data[idx++] =
2455
-
MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->sq[tc],
2456
-
sq_stats_desc, j);
2465
+
mlx5e_ethtool_put_stat(
2466
+
data,
2467
+
MLX5E_READ_CTR64_CPU(
2468
+
&priv->channel_stats[i]->sq[tc],
2469
+
sq_stats_desc, j));
2457
2470
2458
2471
for (i = 0; i < max_nch; i++) {
2459
2472
for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++)
2460
-
data[idx++] =
2461
-
MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->xsksq,
2462
-
xsksq_stats_desc, j);
2473
+
mlx5e_ethtool_put_stat(
2474
+
data, MLX5E_READ_CTR64_CPU(
2475
+
&priv->channel_stats[i]->xsksq,
2476
+
xsksq_stats_desc, j));
2463
2477
for (j = 0; j < NUM_XDPSQ_STATS; j++)
2464
-
data[idx++] =
2465
-
MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->xdpsq,
2466
-
xdpsq_stats_desc, j);
2478
+
mlx5e_ethtool_put_stat(
2479
+
data, MLX5E_READ_CTR64_CPU(
2480
+
&priv->channel_stats[i]->xdpsq,
2481
+
xdpsq_stats_desc, j));
2467
2482
}
2468
-
2469
-
return idx;
2470
2483
}
2471
2484
2472
2485
static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(channels) { return; }
+6
-4
drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
+6
-4
drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
···
71
71
struct mlx5e_stats_grp {
72
72
u16 update_stats_mask;
73
73
int (*get_num_stats)(struct mlx5e_priv *priv);
74
-
int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
75
-
int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
74
+
void (*fill_strings)(struct mlx5e_priv *priv, u8 **data);
75
+
void (*fill_stats)(struct mlx5e_priv *priv, u64 **data);
76
76
void (*update_stats)(struct mlx5e_priv *priv);
77
77
};
78
+
79
+
void mlx5e_ethtool_put_stat(u64 **data, u64 val);
78
80
79
81
typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
80
82
···
89
87
void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
90
88
91
89
#define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
92
-
int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx)
90
+
void MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 **data)
93
91
94
92
#define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
95
-
int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx)
93
+
void MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 **data)
96
94
97
95
#define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
98
96
+1
-2
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+1
-2
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
···
835
835
836
836
memset(ttc_params, 0, sizeof(*ttc_params));
837
837
838
-
ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
839
-
MLX5_FLOW_NAMESPACE_KERNEL);
838
+
ttc_params->ns_type = MLX5_FLOW_NAMESPACE_KERNEL;
840
839
for (tt = 0; tt < MLX5_NUM_TT; tt++) {
841
840
ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
842
841
ttc_params->dests[tt].tir_num =
+8
-1
drivers/net/ethernet/mellanox/mlx5/core/eq.c
+8
-1
drivers/net/ethernet/mellanox/mlx5/core/eq.c
···
688
688
if (err)
689
689
goto err2;
690
690
691
+
/* Skip page eq creation when the device does not request for page requests */
692
+
if (MLX5_CAP_GEN(dev, page_request_disable)) {
693
+
mlx5_core_dbg(dev, "Skip page EQ creation\n");
694
+
return 0;
695
+
}
696
+
691
697
param = (struct mlx5_eq_param) {
692
698
.irq = table->ctrl_irq,
693
699
.nent = /* TODO: sriov max_vf + */ 1,
···
722
716
{
723
717
struct mlx5_eq_table *table = dev->priv.eq_table;
724
718
725
-
cleanup_async_eq(dev, &table->pages_eq, "pages");
719
+
if (!MLX5_CAP_GEN(dev, page_request_disable))
720
+
cleanup_async_eq(dev, &table->pages_eq, "pages");
726
721
cleanup_async_eq(dev, &table->async_eq, "async");
727
722
mlx5_cmd_allowed_opcode(dev, MLX5_CMD_OP_DESTROY_EQ);
728
723
mlx5_cmd_use_polling(dev);
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/fw.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/fw.c
+2
-6
drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
+2
-6
drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
···
449
449
static void mlx5_lag_set_inner_ttc_params(struct mlx5_lag *ldev,
450
450
struct ttc_params *ttc_params)
451
451
{
452
-
struct mlx5_core_dev *dev = ldev->pf[MLX5_LAG_P1].dev;
453
452
struct mlx5_lag_port_sel *port_sel = &ldev->port_sel;
454
453
struct mlx5_flow_table_attr *ft_attr;
455
454
int tt;
456
455
457
-
ttc_params->ns = mlx5_get_flow_namespace(dev,
458
-
MLX5_FLOW_NAMESPACE_PORT_SEL);
456
+
ttc_params->ns_type = MLX5_FLOW_NAMESPACE_PORT_SEL;
459
457
ft_attr = &ttc_params->ft_attr;
460
458
ft_attr->level = MLX5_LAG_FT_LEVEL_INNER_TTC;
461
459
···
468
470
static void mlx5_lag_set_outer_ttc_params(struct mlx5_lag *ldev,
469
471
struct ttc_params *ttc_params)
470
472
{
471
-
struct mlx5_core_dev *dev = ldev->pf[MLX5_LAG_P1].dev;
472
473
struct mlx5_lag_port_sel *port_sel = &ldev->port_sel;
473
474
struct mlx5_flow_table_attr *ft_attr;
474
475
int tt;
475
476
476
-
ttc_params->ns = mlx5_get_flow_namespace(dev,
477
-
MLX5_FLOW_NAMESPACE_PORT_SEL);
477
+
ttc_params->ns_type = MLX5_FLOW_NAMESPACE_PORT_SEL;
478
478
ft_attr = &ttc_params->ft_attr;
479
479
ft_attr->level = MLX5_LAG_FT_LEVEL_TTC;
480
480
+204
-48
drivers/net/ethernet/mellanox/mlx5/core/lib/fs_ttc.c
+204
-48
drivers/net/ethernet/mellanox/mlx5/core/lib/fs_ttc.c
···
9
9
#include "mlx5_core.h"
10
10
#include "lib/fs_ttc.h"
11
11
12
-
#define MLX5_TTC_NUM_GROUPS 3
13
-
#define MLX5_TTC_GROUP1_SIZE (BIT(3) + MLX5_NUM_TUNNEL_TT)
14
-
#define MLX5_TTC_GROUP2_SIZE BIT(1)
15
-
#define MLX5_TTC_GROUP3_SIZE BIT(0)
16
-
#define MLX5_TTC_TABLE_SIZE (MLX5_TTC_GROUP1_SIZE +\
17
-
MLX5_TTC_GROUP2_SIZE +\
18
-
MLX5_TTC_GROUP3_SIZE)
12
+
#define MLX5_TTC_MAX_NUM_GROUPS 4
13
+
#define MLX5_TTC_GROUP_TCPUDP_SIZE (MLX5_TT_IPV6_UDP + 1)
19
14
20
-
#define MLX5_INNER_TTC_NUM_GROUPS 3
21
-
#define MLX5_INNER_TTC_GROUP1_SIZE BIT(3)
22
-
#define MLX5_INNER_TTC_GROUP2_SIZE BIT(1)
23
-
#define MLX5_INNER_TTC_GROUP3_SIZE BIT(0)
24
-
#define MLX5_INNER_TTC_TABLE_SIZE (MLX5_INNER_TTC_GROUP1_SIZE +\
25
-
MLX5_INNER_TTC_GROUP2_SIZE +\
26
-
MLX5_INNER_TTC_GROUP3_SIZE)
15
+
struct mlx5_fs_ttc_groups {
16
+
bool use_l4_type;
17
+
int num_groups;
18
+
int group_size[MLX5_TTC_MAX_NUM_GROUPS];
19
+
};
20
+
21
+
static int mlx5_fs_ttc_table_size(const struct mlx5_fs_ttc_groups *groups)
22
+
{
23
+
int i, sz = 0;
24
+
25
+
for (i = 0; i < groups->num_groups; i++)
26
+
sz += groups->group_size[i];
27
+
28
+
return sz;
29
+
}
27
30
28
31
/* L3/L4 traffic type classifier */
29
32
struct mlx5_ttc_table {
···
141
138
142
139
};
143
140
141
+
enum TTC_GROUP_TYPE {
142
+
TTC_GROUPS_DEFAULT = 0,
143
+
TTC_GROUPS_USE_L4_TYPE = 1,
144
+
};
145
+
146
+
static const struct mlx5_fs_ttc_groups ttc_groups[] = {
147
+
[TTC_GROUPS_DEFAULT] = {
148
+
.num_groups = 3,
149
+
.group_size = {
150
+
BIT(3) + MLX5_NUM_TUNNEL_TT,
151
+
BIT(1),
152
+
BIT(0),
153
+
},
154
+
},
155
+
[TTC_GROUPS_USE_L4_TYPE] = {
156
+
.use_l4_type = true,
157
+
.num_groups = 4,
158
+
.group_size = {
159
+
MLX5_TTC_GROUP_TCPUDP_SIZE,
160
+
BIT(3) + MLX5_NUM_TUNNEL_TT - MLX5_TTC_GROUP_TCPUDP_SIZE,
161
+
BIT(1),
162
+
BIT(0),
163
+
},
164
+
},
165
+
};
166
+
167
+
static const struct mlx5_fs_ttc_groups inner_ttc_groups[] = {
168
+
[TTC_GROUPS_DEFAULT] = {
169
+
.num_groups = 3,
170
+
.group_size = {
171
+
BIT(3),
172
+
BIT(1),
173
+
BIT(0),
174
+
},
175
+
},
176
+
[TTC_GROUPS_USE_L4_TYPE] = {
177
+
.use_l4_type = true,
178
+
.num_groups = 4,
179
+
.group_size = {
180
+
MLX5_TTC_GROUP_TCPUDP_SIZE,
181
+
BIT(3) - MLX5_TTC_GROUP_TCPUDP_SIZE,
182
+
BIT(1),
183
+
BIT(0),
184
+
},
185
+
},
186
+
};
187
+
144
188
u8 mlx5_get_proto_by_tunnel_type(enum mlx5_tunnel_types tt)
145
189
{
146
190
return ttc_tunnel_rules[tt].proto;
···
238
188
return 0;
239
189
}
240
190
191
+
static void mlx5_fs_ttc_set_match_proto(void *headers_c, void *headers_v,
192
+
u8 proto, bool use_l4_type)
193
+
{
194
+
int l4_type;
195
+
196
+
if (use_l4_type && (proto == IPPROTO_TCP || proto == IPPROTO_UDP)) {
197
+
if (proto == IPPROTO_TCP)
198
+
l4_type = MLX5_PACKET_L4_TYPE_TCP;
199
+
else
200
+
l4_type = MLX5_PACKET_L4_TYPE_UDP;
201
+
202
+
MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, l4_type);
203
+
MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_type, l4_type);
204
+
} else {
205
+
MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
206
+
MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, proto);
207
+
}
208
+
}
209
+
241
210
static struct mlx5_flow_handle *
242
211
mlx5_generate_ttc_rule(struct mlx5_core_dev *dev, struct mlx5_flow_table *ft,
243
-
struct mlx5_flow_destination *dest, u16 etype, u8 proto)
212
+
struct mlx5_flow_destination *dest, u16 etype, u8 proto,
213
+
bool use_l4_type)
244
214
{
245
215
int match_ipv_outer =
246
216
MLX5_CAP_FLOWTABLE_NIC_RX(dev,
···
277
207
278
208
if (proto) {
279
209
spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
280
-
MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.ip_protocol);
281
-
MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, proto);
210
+
mlx5_fs_ttc_set_match_proto(MLX5_ADDR_OF(fte_match_param,
211
+
spec->match_criteria,
212
+
outer_headers),
213
+
MLX5_ADDR_OF(fte_match_param,
214
+
spec->match_value,
215
+
outer_headers),
216
+
proto, use_l4_type);
282
217
}
283
218
284
219
ipv = mlx5_etype_to_ipv(etype);
···
309
234
310
235
static int mlx5_generate_ttc_table_rules(struct mlx5_core_dev *dev,
311
236
struct ttc_params *params,
312
-
struct mlx5_ttc_table *ttc)
237
+
struct mlx5_ttc_table *ttc,
238
+
bool use_l4_type)
313
239
{
314
240
struct mlx5_flow_handle **trules;
315
241
struct mlx5_ttc_rule *rules;
···
327
251
continue;
328
252
rule->rule = mlx5_generate_ttc_rule(dev, ft, ¶ms->dests[tt],
329
253
ttc_rules[tt].etype,
330
-
ttc_rules[tt].proto);
254
+
ttc_rules[tt].proto,
255
+
use_l4_type);
331
256
if (IS_ERR(rule->rule)) {
332
257
err = PTR_ERR(rule->rule);
333
258
rule->rule = NULL;
···
350
273
trules[tt] = mlx5_generate_ttc_rule(dev, ft,
351
274
¶ms->tunnel_dests[tt],
352
275
ttc_tunnel_rules[tt].etype,
353
-
ttc_tunnel_rules[tt].proto);
276
+
ttc_tunnel_rules[tt].proto,
277
+
use_l4_type);
354
278
if (IS_ERR(trules[tt])) {
355
279
err = PTR_ERR(trules[tt]);
356
280
trules[tt] = NULL;
···
367
289
}
368
290
369
291
static int mlx5_create_ttc_table_groups(struct mlx5_ttc_table *ttc,
370
-
bool use_ipv)
292
+
bool use_ipv,
293
+
const struct mlx5_fs_ttc_groups *groups)
371
294
{
372
295
int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
373
296
int ix = 0;
···
376
297
int err;
377
298
u8 *mc;
378
299
379
-
ttc->g = kcalloc(MLX5_TTC_NUM_GROUPS, sizeof(*ttc->g), GFP_KERNEL);
300
+
ttc->g = kcalloc(groups->num_groups, sizeof(*ttc->g), GFP_KERNEL);
380
301
if (!ttc->g)
381
302
return -ENOMEM;
382
303
in = kvzalloc(inlen, GFP_KERNEL);
···
386
307
return -ENOMEM;
387
308
}
388
309
389
-
/* L4 Group */
390
310
mc = MLX5_ADDR_OF(create_flow_group_in, in, match_criteria);
391
-
MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ip_protocol);
392
311
if (use_ipv)
393
312
MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ip_version);
394
313
else
395
314
MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
396
315
MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
316
+
317
+
/* TCP UDP group */
318
+
if (groups->use_l4_type) {
319
+
MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.l4_type);
320
+
MLX5_SET_CFG(in, start_flow_index, ix);
321
+
ix += groups->group_size[ttc->num_groups];
322
+
MLX5_SET_CFG(in, end_flow_index, ix - 1);
323
+
ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in);
324
+
if (IS_ERR(ttc->g[ttc->num_groups]))
325
+
goto err;
326
+
ttc->num_groups++;
327
+
328
+
MLX5_SET(fte_match_param, mc, outer_headers.l4_type, 0);
329
+
}
330
+
331
+
/* L4 Group */
332
+
MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ip_protocol);
397
333
MLX5_SET_CFG(in, start_flow_index, ix);
398
-
ix += MLX5_TTC_GROUP1_SIZE;
334
+
ix += groups->group_size[ttc->num_groups];
399
335
MLX5_SET_CFG(in, end_flow_index, ix - 1);
400
336
ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in);
401
337
if (IS_ERR(ttc->g[ttc->num_groups]))
···
420
326
/* L3 Group */
421
327
MLX5_SET(fte_match_param, mc, outer_headers.ip_protocol, 0);
422
328
MLX5_SET_CFG(in, start_flow_index, ix);
423
-
ix += MLX5_TTC_GROUP2_SIZE;
329
+
ix += groups->group_size[ttc->num_groups];
424
330
MLX5_SET_CFG(in, end_flow_index, ix - 1);
425
331
ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in);
426
332
if (IS_ERR(ttc->g[ttc->num_groups]))
···
430
336
/* Any Group */
431
337
memset(in, 0, inlen);
432
338
MLX5_SET_CFG(in, start_flow_index, ix);
433
-
ix += MLX5_TTC_GROUP3_SIZE;
339
+
ix += groups->group_size[ttc->num_groups];
434
340
MLX5_SET_CFG(in, end_flow_index, ix - 1);
435
341
ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in);
436
342
if (IS_ERR(ttc->g[ttc->num_groups]))
···
452
358
mlx5_generate_inner_ttc_rule(struct mlx5_core_dev *dev,
453
359
struct mlx5_flow_table *ft,
454
360
struct mlx5_flow_destination *dest,
455
-
u16 etype, u8 proto)
361
+
u16 etype, u8 proto, bool use_l4_type)
456
362
{
457
363
MLX5_DECLARE_FLOW_ACT(flow_act);
458
364
struct mlx5_flow_handle *rule;
···
473
379
474
380
if (proto) {
475
381
spec->match_criteria_enable = MLX5_MATCH_INNER_HEADERS;
476
-
MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, inner_headers.ip_protocol);
477
-
MLX5_SET(fte_match_param, spec->match_value, inner_headers.ip_protocol, proto);
382
+
mlx5_fs_ttc_set_match_proto(MLX5_ADDR_OF(fte_match_param,
383
+
spec->match_criteria,
384
+
inner_headers),
385
+
MLX5_ADDR_OF(fte_match_param,
386
+
spec->match_value,
387
+
inner_headers),
388
+
proto, use_l4_type);
478
389
}
479
390
480
391
rule = mlx5_add_flow_rules(ft, spec, &flow_act, dest, 1);
···
494
395
495
396
static int mlx5_generate_inner_ttc_table_rules(struct mlx5_core_dev *dev,
496
397
struct ttc_params *params,
497
-
struct mlx5_ttc_table *ttc)
398
+
struct mlx5_ttc_table *ttc,
399
+
bool use_l4_type)
498
400
{
499
401
struct mlx5_ttc_rule *rules;
500
402
struct mlx5_flow_table *ft;
···
513
413
rule->rule = mlx5_generate_inner_ttc_rule(dev, ft,
514
414
¶ms->dests[tt],
515
415
ttc_rules[tt].etype,
516
-
ttc_rules[tt].proto);
416
+
ttc_rules[tt].proto,
417
+
use_l4_type);
517
418
if (IS_ERR(rule->rule)) {
518
419
err = PTR_ERR(rule->rule);
519
420
rule->rule = NULL;
···
531
430
return err;
532
431
}
533
432
534
-
static int mlx5_create_inner_ttc_table_groups(struct mlx5_ttc_table *ttc)
433
+
static int mlx5_create_inner_ttc_table_groups(struct mlx5_ttc_table *ttc,
434
+
const struct mlx5_fs_ttc_groups *groups)
535
435
{
536
436
int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
537
437
int ix = 0;
···
540
438
int err;
541
439
u8 *mc;
542
440
543
-
ttc->g = kcalloc(MLX5_INNER_TTC_NUM_GROUPS, sizeof(*ttc->g),
544
-
GFP_KERNEL);
441
+
ttc->g = kcalloc(groups->num_groups, sizeof(*ttc->g), GFP_KERNEL);
545
442
if (!ttc->g)
546
443
return -ENOMEM;
547
444
in = kvzalloc(inlen, GFP_KERNEL);
···
550
449
return -ENOMEM;
551
450
}
552
451
553
-
/* L4 Group */
554
452
mc = MLX5_ADDR_OF(create_flow_group_in, in, match_criteria);
555
-
MLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.ip_protocol);
556
453
MLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.ip_version);
557
454
MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_INNER_HEADERS);
455
+
456
+
/* TCP UDP group */
457
+
if (groups->use_l4_type) {
458
+
MLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.l4_type);
459
+
MLX5_SET_CFG(in, start_flow_index, ix);
460
+
ix += groups->group_size[ttc->num_groups];
461
+
MLX5_SET_CFG(in, end_flow_index, ix - 1);
462
+
ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in);
463
+
if (IS_ERR(ttc->g[ttc->num_groups]))
464
+
goto err;
465
+
ttc->num_groups++;
466
+
467
+
MLX5_SET(fte_match_param, mc, inner_headers.l4_type, 0);
468
+
}
469
+
470
+
/* L4 Group */
471
+
MLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.ip_protocol);
558
472
MLX5_SET_CFG(in, start_flow_index, ix);
559
-
ix += MLX5_INNER_TTC_GROUP1_SIZE;
473
+
ix += groups->group_size[ttc->num_groups];
560
474
MLX5_SET_CFG(in, end_flow_index, ix - 1);
561
475
ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in);
562
476
if (IS_ERR(ttc->g[ttc->num_groups]))
···
581
465
/* L3 Group */
582
466
MLX5_SET(fte_match_param, mc, inner_headers.ip_protocol, 0);
583
467
MLX5_SET_CFG(in, start_flow_index, ix);
584
-
ix += MLX5_INNER_TTC_GROUP2_SIZE;
468
+
ix += groups->group_size[ttc->num_groups];
585
469
MLX5_SET_CFG(in, end_flow_index, ix - 1);
586
470
ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in);
587
471
if (IS_ERR(ttc->g[ttc->num_groups]))
···
591
475
/* Any Group */
592
476
memset(in, 0, inlen);
593
477
MLX5_SET_CFG(in, start_flow_index, ix);
594
-
ix += MLX5_INNER_TTC_GROUP3_SIZE;
478
+
ix += groups->group_size[ttc->num_groups];
595
479
MLX5_SET_CFG(in, end_flow_index, ix - 1);
596
480
ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in);
597
481
if (IS_ERR(ttc->g[ttc->num_groups]))
···
612
496
struct mlx5_ttc_table *mlx5_create_inner_ttc_table(struct mlx5_core_dev *dev,
613
497
struct ttc_params *params)
614
498
{
499
+
const struct mlx5_fs_ttc_groups *groups;
500
+
struct mlx5_flow_namespace *ns;
615
501
struct mlx5_ttc_table *ttc;
502
+
bool use_l4_type;
616
503
int err;
617
504
618
505
ttc = kvzalloc(sizeof(*ttc), GFP_KERNEL);
619
506
if (!ttc)
620
507
return ERR_PTR(-ENOMEM);
621
508
509
+
switch (params->ns_type) {
510
+
case MLX5_FLOW_NAMESPACE_PORT_SEL:
511
+
use_l4_type = MLX5_CAP_GEN_2(dev, pcc_ifa2) &&
512
+
MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(dev, inner_l4_type);
513
+
break;
514
+
case MLX5_FLOW_NAMESPACE_KERNEL:
515
+
use_l4_type = MLX5_CAP_GEN_2(dev, pcc_ifa2) &&
516
+
MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(dev, inner_l4_type);
517
+
break;
518
+
default:
519
+
return ERR_PTR(-EINVAL);
520
+
}
521
+
522
+
ns = mlx5_get_flow_namespace(dev, params->ns_type);
523
+
groups = use_l4_type ? &inner_ttc_groups[TTC_GROUPS_USE_L4_TYPE] :
524
+
&inner_ttc_groups[TTC_GROUPS_DEFAULT];
525
+
622
526
WARN_ON_ONCE(params->ft_attr.max_fte);
623
-
params->ft_attr.max_fte = MLX5_INNER_TTC_TABLE_SIZE;
624
-
ttc->t = mlx5_create_flow_table(params->ns, ¶ms->ft_attr);
527
+
params->ft_attr.max_fte = mlx5_fs_ttc_table_size(groups);
528
+
ttc->t = mlx5_create_flow_table(ns, ¶ms->ft_attr);
625
529
if (IS_ERR(ttc->t)) {
626
530
err = PTR_ERR(ttc->t);
627
531
kvfree(ttc);
628
532
return ERR_PTR(err);
629
533
}
630
534
631
-
err = mlx5_create_inner_ttc_table_groups(ttc);
535
+
err = mlx5_create_inner_ttc_table_groups(ttc, groups);
632
536
if (err)
633
537
goto destroy_ft;
634
538
635
-
err = mlx5_generate_inner_ttc_table_rules(dev, params, ttc);
539
+
err = mlx5_generate_inner_ttc_table_rules(dev, params, ttc, use_l4_type);
636
540
if (err)
637
541
goto destroy_ft;
638
542
···
685
549
bool match_ipv_outer =
686
550
MLX5_CAP_FLOWTABLE_NIC_RX(dev,
687
551
ft_field_support.outer_ip_version);
552
+
const struct mlx5_fs_ttc_groups *groups;
553
+
struct mlx5_flow_namespace *ns;
688
554
struct mlx5_ttc_table *ttc;
555
+
bool use_l4_type;
689
556
int err;
690
557
691
558
ttc = kvzalloc(sizeof(*ttc), GFP_KERNEL);
692
559
if (!ttc)
693
560
return ERR_PTR(-ENOMEM);
694
561
562
+
switch (params->ns_type) {
563
+
case MLX5_FLOW_NAMESPACE_PORT_SEL:
564
+
use_l4_type = MLX5_CAP_GEN_2(dev, pcc_ifa2) &&
565
+
MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(dev, outer_l4_type);
566
+
break;
567
+
case MLX5_FLOW_NAMESPACE_KERNEL:
568
+
use_l4_type = MLX5_CAP_GEN_2(dev, pcc_ifa2) &&
569
+
MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(dev, outer_l4_type);
570
+
break;
571
+
default:
572
+
return ERR_PTR(-EINVAL);
573
+
}
574
+
575
+
ns = mlx5_get_flow_namespace(dev, params->ns_type);
576
+
groups = use_l4_type ? &ttc_groups[TTC_GROUPS_USE_L4_TYPE] :
577
+
&ttc_groups[TTC_GROUPS_DEFAULT];
578
+
695
579
WARN_ON_ONCE(params->ft_attr.max_fte);
696
-
params->ft_attr.max_fte = MLX5_TTC_TABLE_SIZE;
697
-
ttc->t = mlx5_create_flow_table(params->ns, ¶ms->ft_attr);
580
+
params->ft_attr.max_fte = mlx5_fs_ttc_table_size(groups);
581
+
ttc->t = mlx5_create_flow_table(ns, ¶ms->ft_attr);
698
582
if (IS_ERR(ttc->t)) {
699
583
err = PTR_ERR(ttc->t);
700
584
kvfree(ttc);
701
585
return ERR_PTR(err);
702
586
}
703
587
704
-
err = mlx5_create_ttc_table_groups(ttc, match_ipv_outer);
588
+
err = mlx5_create_ttc_table_groups(ttc, match_ipv_outer, groups);
705
589
if (err)
706
590
goto destroy_ft;
707
591
708
-
err = mlx5_generate_ttc_table_rules(dev, params, ttc);
592
+
err = mlx5_generate_ttc_table_rules(dev, params, ttc, use_l4_type);
709
593
if (err)
710
594
goto destroy_ft;
711
595
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/lib/fs_ttc.h
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/lib/fs_ttc.h
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
···
205
205
void mlx5_cmd_disable(struct mlx5_core_dev *dev);
206
206
void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
207
207
enum mlx5_cmdif_state cmdif_state);
208
-
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
208
+
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, u32 *sw_owner_id);
209
209
int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
210
210
int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
211
211
int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
+3
drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c
+3
drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
···
1897
1897
1898
1898
static int dr_ste_v1_build_tnl_header_0_1_tag(struct mlx5dr_match_param *value,
1899
1899
struct mlx5dr_ste_build *sb,
1900
-
uint8_t *tag)
1900
+
u8 *tag)
1901
1901
{
1902
1902
struct mlx5dr_match_misc5 *misc5 = &value->misc5;
1903
1903
···
2129
2129
static int
2130
2130
dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_tag(struct mlx5dr_match_param *value,
2131
2131
struct mlx5dr_ste_build *sb,
2132
-
uint8_t *tag)
2132
+
u8 *tag)
2133
2133
{
2134
2134
u8 parser_id = sb->caps->flex_parser_id_geneve_tlv_option_0;
2135
2135
struct mlx5dr_match_misc *misc = &value->misc;
+7
-1
include/linux/mlx5/device.h
+7
-1
include/linux/mlx5/device.h
···
68
68
#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
69
69
#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
70
70
#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
71
-
#define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
71
+
#define MLX5_ADDR_OF(typ, p, fld) ((void *)((u8 *)(p) + MLX5_BYTE_OFF(typ, fld)))
72
72
73
73
/* insert a value to a struct */
74
74
#define MLX5_SET(typ, p, fld, v) do { \
···
1336
1336
#define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \
1337
1337
MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1338
1338
1339
+
#define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \
1340
+
MLX5_CAP_FLOWTABLE(mdev, ft_field_support_2_nic_receive.cap)
1341
+
1339
1342
#define MLX5_CAP_ESW(mdev, cap) \
1340
1343
MLX5_GET(e_switch_cap, \
1341
1344
mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
···
1361
1358
1362
1359
#define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
1363
1360
MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1361
+
1362
+
#define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \
1363
+
MLX5_CAP_PORT_SELECTION(mdev, ft_field_support_2_port_selection.cap)
1364
1364
1365
1365
#define MLX5_CAP_ODP(mdev, cap)\
1366
1366
MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
+30
-6
include/linux/mlx5/mlx5_ifc.h
+30
-6
include/linux/mlx5/mlx5_ifc.h
···
416
416
417
417
/* Table 2170 - Flow Table Fields Supported 2 Format */
418
418
struct mlx5_ifc_flow_table_fields_supported_2_bits {
419
-
u8 reserved_at_0[0xe];
419
+
u8 reserved_at_0[0x2];
420
+
u8 inner_l4_type[0x1];
421
+
u8 outer_l4_type[0x1];
422
+
u8 reserved_at_4[0xa];
420
423
u8 bth_opcode[0x1];
421
424
u8 reserved_at_f[0x1];
422
425
u8 tunnel_header_0_1[0x1];
···
528
525
u8 reserved_at_0[0x80];
529
526
};
530
527
528
+
enum {
529
+
MLX5_PACKET_L4_TYPE_NONE,
530
+
MLX5_PACKET_L4_TYPE_TCP,
531
+
MLX5_PACKET_L4_TYPE_UDP,
532
+
};
533
+
531
534
struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
532
535
u8 smac_47_16[0x20];
533
536
···
559
550
u8 tcp_sport[0x10];
560
551
u8 tcp_dport[0x10];
561
552
562
-
u8 reserved_at_c0[0x10];
553
+
u8 l4_type[0x2];
554
+
u8 reserved_at_c2[0xe];
563
555
u8 ipv4_ihl[0x4];
564
556
u8 reserved_at_c4[0x4];
565
557
···
856
846
857
847
struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
858
848
859
-
u8 reserved_at_e00[0x700];
849
+
u8 reserved_at_e00[0x600];
850
+
851
+
struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
852
+
853
+
u8 reserved_at_1480[0x80];
860
854
861
855
struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
862
856
···
890
876
891
877
struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
892
878
893
-
u8 reserved_at_400[0x7c00];
879
+
struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
880
+
881
+
u8 reserved_at_480[0x7b80];
894
882
};
895
883
896
884
enum {
···
1485
1469
};
1486
1470
1487
1471
struct mlx5_ifc_cmd_hca_cap_bits {
1488
-
u8 reserved_at_0[0x10];
1472
+
u8 reserved_at_0[0x6];
1473
+
u8 page_request_disable[0x1];
1474
+
u8 reserved_at_7[0x9];
1489
1475
u8 shared_object_to_user_object_allowed[0x1];
1490
1476
u8 reserved_at_13[0xe];
1491
1477
u8 vhca_resource_manager[0x1];
···
2022
2004
u8 reserved_at_3a0[0x10];
2023
2005
u8 max_rqt_vhca_id[0x10];
2024
2006
2025
-
u8 reserved_at_3c0[0x440];
2007
+
u8 reserved_at_3c0[0x20];
2008
+
2009
+
u8 reserved_at_3e0[0x10];
2010
+
u8 pcc_ifa2[0x1];
2011
+
u8 reserved_at_3f1[0xf];
2012
+
2013
+
u8 reserved_at_400[0x400];
2026
2014
};
2027
2015
2028
2016
enum mlx5_ifc_flow_destination_type {