Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Enable dcn42 DC
Add support for DCN 4.2 in Display Core
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Roman Li
and committed by
Alex Deucher
6b2dd7d3
083a1638
+568
-36
+1
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+1
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+10
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+10
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
···
1
1
#
2
-
# Copyright 2017 Advanced Micro Devices, Inc.
2
+
# Copyright 2017-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
176
176
AMD_DAL_CLK_MGR_DCN401 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn401/,$(CLK_MGR_DCN401))
177
177
178
178
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN401)
179
+
180
+
###############################################################################
181
+
# DCN42
182
+
###############################################################################
183
+
CLK_MGR_DCN42 = dcn42_smu.o dcn42_clk_mgr.o
184
+
185
+
AMD_DAL_CLK_MGR_DCN42 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn42/,$(CLK_MGR_DCN42))
186
+
187
+
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN42)
179
188
endif
+38
-1
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+38
-1
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
···
1
1
/*
2
-
* Copyright 2015 Advanced Micro Devices, Inc.
2
+
* Copyright 2015-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
846
846
block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
847
847
(*num_steps)++;
848
848
}
849
+
if (current_mpc_pipe->plane_state->update_flags.bits.cm_hist_change) {
850
+
block_sequence[*num_steps].params.control_cm_hist_params.dpp
851
+
= current_mpc_pipe->plane_res.dpp;
852
+
block_sequence[*num_steps].params.control_cm_hist_params.cm_hist_control
853
+
= current_mpc_pipe->plane_state->cm_hist_control;
854
+
block_sequence[*num_steps].params.control_cm_hist_params.color_space
855
+
= current_mpc_pipe->plane_state->color_space;
856
+
block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST;
857
+
(*num_steps)++;
858
+
}
849
859
}
850
860
if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
851
861
block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
···
1038
1028
break;
1039
1029
case HUBP_PROGRAM_MCACHE_ID:
1040
1030
hwss_program_mcache_id_and_split_coordinate(params);
1031
+
break;
1032
+
case DPP_PROGRAM_CM_HIST:
1033
+
hwss_program_cm_hist(params);
1041
1034
break;
1042
1035
case PROGRAM_CURSOR_UPDATE_NOW:
1043
1036
dc->hwss.program_cursor_offload_now(
···
2065
2052
2066
2053
hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs);
2067
2054
2055
+
}
2056
+
2057
+
void hwss_program_cm_hist(union block_sequence_params *params)
2058
+
{
2059
+
struct dpp *dpp = params->control_cm_hist_params.dpp;
2060
+
2061
+
if (dpp && dpp->funcs->dpp_cm_hist_control)
2062
+
dpp->funcs->dpp_cm_hist_control(dpp,
2063
+
params->control_cm_hist_params.cm_hist_control,
2064
+
params->control_cm_hist_params.color_space);
2068
2065
}
2069
2066
2070
2067
void get_surface_tile_visual_confirm_color(
···
3389
3366
seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.opp = opp;
3390
3367
seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.use_default_params = use_default_params;
3391
3368
seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx;
3369
+
(*seq_state->num_steps)++;
3370
+
}
3371
+
}
3372
+
3373
+
void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state,
3374
+
struct dpp *dpp,
3375
+
struct cm_hist_control cm_hist_control,
3376
+
enum dc_color_space color_space)
3377
+
{
3378
+
if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3379
+
seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_CM_HIST;
3380
+
seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp;
3381
+
seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.cm_hist_control = cm_hist_control;
3382
+
seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.color_space = color_space;
3392
3383
(*seq_state->num_steps)++;
3393
3384
}
3394
3385
}
+7
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+7
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
···
78
78
#include "dcn351/dcn351_resource.h"
79
79
#include "dcn36/dcn36_resource.h"
80
80
#include "dcn401/dcn401_resource.h"
81
+
#include "dcn42/dcn42_resource.h"
81
82
#if defined(CONFIG_DRM_AMD_DC_FP)
82
83
#include "dc_spl_translate.h"
83
84
#endif
···
253
252
ASICREV_IS_GC_12_0_0_A0(asic_id.hw_internal_rev))
254
253
dc_version = DCN_VERSION_4_01;
255
254
break;
255
+
case AMDGPU_FAMILY_GC_11_5_4:
256
+
dc_version = DCN_VERSION_4_2;
257
+
break;
256
258
default:
257
259
dc_version = DCE_VERSION_UNKNOWN;
258
260
break;
···
371
367
break;
372
368
case DCN_VERSION_4_01:
373
369
res_pool = dcn401_create_resource_pool(init_data, dc);
370
+
break;
371
+
case DCN_VERSION_4_2:
372
+
res_pool = dcn42_create_resource_pool(init_data, dc);
374
373
break;
375
374
#endif /* CONFIG_DRM_AMD_DC_FP */
376
375
default:
+9
-1
drivers/gpu/drm/amd/display/dc/dc.h
+9
-1
drivers/gpu/drm/amd/display/dc/dc.h
···
1
1
/*
2
-
* Copyright 2012-2023 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
733
733
struct {
734
734
uint8_t base_efficiency; //LP1
735
735
uint8_t low_power_efficiency; //LP2
736
+
uint8_t z8_stutter_efficiency;
737
+
int z8_stutter_period;
736
738
} stutter_efficiency;
737
739
};
738
740
···
1213
1211
unsigned int num_fast_flips_to_steady_state_override;
1214
1212
bool enable_dmu_recovery;
1215
1213
unsigned int force_vmin_threshold;
1214
+
bool enable_otg_frame_sync_pwa;
1216
1215
};
1217
1216
1218
1217
···
1422
1419
struct dc_plane_address current_address;
1423
1420
bool is_flip_pending;
1424
1421
bool is_right_eye;
1422
+
struct cm_hist cm_hist;
1425
1423
};
1426
1424
1427
1425
union surface_update_flags {
···
1459
1455
uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */
1460
1456
uint32_t full_update:1;
1461
1457
uint32_t sdr_white_level_nits:1;
1458
+
uint32_t cm_hist_change:1;
1462
1459
} bits;
1463
1460
1464
1461
uint32_t raw;
···
1544
1539
int sharpness_level;
1545
1540
enum linear_light_scaling linear_light_scaling;
1546
1541
unsigned int sdr_white_level_nits;
1542
+
struct cm_hist_control cm_hist_control;
1547
1543
struct spl_sharpness_range sharpness_range;
1548
1544
enum sharpness_range_source sharpness_source;
1549
1545
};
···
1853
1847
struct dc_transfer_func *out_transfer_func;
1854
1848
struct dc_csc_transform *output_csc_transform;
1855
1849
const struct dc_csc_transform *cursor_csc_color_matrix;
1850
+
struct cm_hist_control *cm_hist_control;
1856
1851
};
1857
1852
1858
1853
struct dc_surface_update {
···
1886
1879
const struct dc_csc_transform *cursor_csc_color_matrix;
1887
1880
unsigned int sdr_white_level_nits;
1888
1881
struct dc_bias_and_scale bias_and_scale;
1882
+
struct cm_hist_control *cm_hist_control;
1889
1883
};
1890
1884
1891
1885
struct dc_underflow_debug_data {
+2
drivers/gpu/drm/amd/display/dc/dc_helper.c
+2
drivers/gpu/drm/amd/display/dc/dc_helper.c
+73
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+73
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
···
271
271
DC_SURF_TILE_SPLIT_1KB = 0x4,
272
272
};
273
273
274
+
enum otg_pwa_sync_mode {
275
+
DC_OTG_PWA_FRAME_SYNC_MODE_VSYNC = 0x0,
276
+
DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP = 0x1,
277
+
};
278
+
struct otc_pwa_frame_sync {
279
+
enum otg_pwa_sync_mode pwa_sync_mode;
280
+
uint32_t pwa_frame_sync_line_offset;
281
+
};
282
+
274
283
/* TODO: These values come from hardware spec. We need to readdress this
275
284
* if they ever change.
276
285
*/
···
1146
1137
unsigned int warmup_pitch;
1147
1138
unsigned int swlock;
1148
1139
unsigned int p_vmid;
1140
+
uint8_t tmz_id;
1149
1141
};
1150
1142
1151
1143
···
1172
1162
enum symclk_state symclk_state;
1173
1163
};
1174
1164
1165
+
enum cm_hist_tap_point {
1166
+
CM_HIST_TAP_POINT_1,
1167
+
CM_HIST_TAP_POINT_2,
1168
+
CM_HIST_TAP_POINT_3,
1169
+
CM_HIST_TAP_POINT_4,
1170
+
};
1171
+
1172
+
enum cm_hist_src {
1173
+
CM_HIST_SRC1,
1174
+
CM_HIST_SRC2,
1175
+
CM_HIST_SRC3,
1176
+
};
1177
+
1178
+
enum cm_hist_format {
1179
+
CM_HIST_FORMAT_FIXED_POINT,
1180
+
CM_HIST_FORMAT_FP16_POS,
1181
+
CM_HIST_FORMAT_FP16_POS_AND_NEG,
1182
+
};
1183
+
1184
+
enum cm_hist_read_channel_mask {
1185
+
CM_HIST_READ_DISABLED,
1186
+
CM_HIST_READ_CH1,
1187
+
CM_HIST_READ_CH2,
1188
+
CM_HIST_READ_CH1_CH2,
1189
+
CM_HIST_READ_CH3,
1190
+
CM_HIST_READ_CH1_CH3,
1191
+
CM_HIST_READ_CH2_CH3,
1192
+
CM_HIST_READ_ALL,
1193
+
};
1194
+
1195
+
enum cm_hist_src1_mode {
1196
+
CM_HIST_SRC1_MODE_R_OR_CR,
1197
+
CM_HIST_SRC1_MODE_MAX_RGB,
1198
+
};
1199
+
1200
+
enum cm_hist_src2_mode {
1201
+
CM_HIST_SRC2_MODE_G_OR_Y,
1202
+
CM_HIST_SRC2_MODE_RGB_TO_Y,
1203
+
};
1204
+
1205
+
enum cm_hist_src3_mode {
1206
+
CM_HIST_SRC3_MODE_B_OR_CB,
1207
+
CM_HIST_SRC3_MODE_MIN_RGB,
1208
+
};
1209
+
1210
+
struct cm_hist_control {
1211
+
enum cm_hist_tap_point tap_point;
1212
+
uint32_t channels_enabled;
1213
+
enum cm_hist_src1_mode src_1_select;
1214
+
enum cm_hist_src2_mode src_2_select;
1215
+
enum cm_hist_src3_mode src_3_select;
1216
+
enum cm_hist_src ch1_src;
1217
+
enum cm_hist_src ch2_src;
1218
+
enum cm_hist_src ch3_src;
1219
+
enum cm_hist_format format;
1220
+
enum cm_hist_read_channel_mask read_channel_mask;
1221
+
};
1222
+
1223
+
struct cm_hist {
1224
+
uint32_t ch1[256];
1225
+
uint32_t ch2[256];
1226
+
uint32_t ch3[256];
1227
+
};
1175
1228
#endif /* DC_HW_TYPES_H */
1176
1229
+5
-1
drivers/gpu/drm/amd/display/dc/dc_types.h
+5
-1
drivers/gpu/drm/amd/display/dc/dc_types.h
···
1
1
/*
2
-
* Copyright 2012-15 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
1346
1346
1347
1347
enum dc_cm2_gpu_mem_pixel_component_order {
1348
1348
DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA,
1349
+
DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA
1349
1350
};
1350
1351
1351
1352
enum dc_cm2_gpu_mem_format {
···
1368
1367
1369
1368
enum dc_cm2_gpu_mem_size {
1370
1369
DC_CM2_GPU_MEM_SIZE_171717,
1370
+
DC_CM2_GPU_MEM_SIZE_333333,
1371
+
DC_CM2_GPU_MEM_SIZE_454545,
1372
+
DC_CM2_GPU_MEM_SIZE_656565,
1371
1373
DC_CM2_GPU_MEM_SIZE_TRANSFORMED,
1372
1374
};
1373
1375
+10
-1
drivers/gpu/drm/amd/display/dc/dccg/Makefile
+10
-1
drivers/gpu/drm/amd/display/dc/dccg/Makefile
···
1
1
2
-
# Copyright 2022 Advanced Micro Devices, Inc.
2
+
# Copyright 2022-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
100
100
AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401))
101
101
102
102
AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN401)
103
+
104
+
###############################################################################
105
+
# DCN42
106
+
###############################################################################
107
+
DCCG_DCN42 = dcn42_dccg.o
108
+
109
+
AMD_DAL_DCCG_DCN42 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn42/,$(DCCG_DCN42))
110
+
111
+
AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN42)
103
112
endif
+14
-1
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
+14
-1
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
···
1
1
/*
2
-
* Copyright 2018 Advanced Micro Devices, Inc.
2
+
* Copyright 2018-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
362
362
type SYMCLK32_LE3_EN;\
363
363
type DP_DTO_ENABLE[MAX_PIPES];
364
364
365
+
#define DCCG42_REG_FIELD_LIST(type) \
366
+
type OTG0_ADD_PIXEL;\
367
+
type OTG1_ADD_PIXEL;\
368
+
type OTG2_ADD_PIXEL;\
369
+
type OTG0_DROP_PIXEL;\
370
+
type OTG1_DROP_PIXEL;\
371
+
type OTG2_DROP_PIXEL;\
372
+
type OTG3_ADD_PIXEL;\
373
+
type OTG3_DROP_PIXEL;
374
+
365
375
struct dccg_shift {
366
376
DCCG_REG_FIELD_LIST(uint8_t)
367
377
DCCG3_REG_FIELD_LIST(uint8_t)
···
380
370
DCCG32_REG_FIELD_LIST(uint8_t)
381
371
DCCG35_REG_FIELD_LIST(uint8_t)
382
372
DCCG401_REG_FIELD_LIST(uint8_t)
373
+
DCCG42_REG_FIELD_LIST(uint8_t)
383
374
};
384
375
385
376
struct dccg_mask {
···
391
380
DCCG32_REG_FIELD_LIST(uint32_t)
392
381
DCCG35_REG_FIELD_LIST(uint32_t)
393
382
DCCG401_REG_FIELD_LIST(uint32_t)
383
+
DCCG42_REG_FIELD_LIST(uint32_t)
394
384
};
395
385
396
386
#define DCCG_REG_VARIABLE_LIST \
···
505
493
506
494
struct dccg_registers {
507
495
DCCG_REG_VARIABLE_LIST;
496
+
uint32_t OTG_ADD_DROP_PIXEL_CNTL;
508
497
};
509
498
510
499
struct dcn_dccg {
+59
-1
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+59
-1
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
···
1
1
/*
2
-
* Copyright 2012-16 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
285
285
ABM1_ACE_THRES_DATA_1, mask_sh), \
286
286
ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \
287
287
ABM1_ACE_THRES_DATA_2, mask_sh), \
288
+
ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \
289
+
ABM1_HG_RESULT_DATA, mask_sh), \
290
+
ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \
291
+
ABM1_HG_RESULT_INDEX, mask_sh), \
292
+
ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \
293
+
ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \
294
+
ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \
295
+
ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \
296
+
ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \
297
+
ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \
298
+
ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \
299
+
ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \
300
+
ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \
301
+
ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh)
302
+
303
+
#define ABM_MASK_SH_LIST_DCN42(mask_sh) \
304
+
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
305
+
ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
306
+
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
307
+
ABM1_HG_VMAX_SEL, mask_sh), \
308
+
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
309
+
ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
310
+
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
311
+
ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
312
+
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
313
+
ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
314
+
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
315
+
ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
316
+
ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
317
+
BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
318
+
ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
319
+
BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
320
+
ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
321
+
BL1_PWM_USER_LEVEL, mask_sh), \
322
+
ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
323
+
ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
324
+
ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
325
+
ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
326
+
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
327
+
ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
328
+
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
329
+
ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
330
+
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
331
+
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
332
+
ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
333
+
ABM1_ACE_SLOPE_DATA, mask_sh), \
334
+
ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
335
+
ABM1_ACE_OFFSET_DATA, mask_sh), \
336
+
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
337
+
ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \
338
+
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
339
+
ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \
340
+
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
341
+
ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \
342
+
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
343
+
ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \
344
+
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
345
+
ABM1_ACE_LOCK, mask_sh), \
288
346
ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \
289
347
ABM1_HG_RESULT_DATA, mask_sh), \
290
348
ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \
+10
-1
drivers/gpu/drm/amd/display/dc/dio/Makefile
+10
-1
drivers/gpu/drm/amd/display/dc/dio/Makefile
···
1
1
#
2
-
# Copyright 2020 Advanced Micro Devices, Inc.
2
+
# Copyright 2020-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
123
123
AMD_DAL_DIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/dio/dcn401/,$(DIO_DCN401))
124
124
125
125
AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN401)
126
+
127
+
###############################################################################
128
+
# DCN42
129
+
###############################################################################
130
+
DIO_DCN42 = dcn42_dio_link_encoder.o dcn42_dio_stream_encoder.o
131
+
132
+
AMD_DAL_DIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/dio/dcn42/,$(DIO_DCN42))
133
+
134
+
AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN42)
126
135
endif
+9
-1
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
+9
-1
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
···
1
1
/*
2
-
* Copyright 2012-15 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
190
190
uint32_t DIG_FE_CLK_CNTL;
191
191
uint32_t DIG_FE_EN_CNTL;
192
192
uint32_t STREAM_MAPPER_CONTROL;
193
+
uint32_t DIG_FE_AUDIO_CNTL;
193
194
};
194
195
195
196
···
599
598
type DP_VID_N_INTERVAL;\
600
599
type DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE;\
601
600
type DP_STEER_FIFO_ENABLE
601
+
602
+
#define SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(type) \
603
+
type DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\
604
+
type APG_CLOCK_ENABLE
605
+
602
606
struct dcn10_stream_encoder_shift {
603
607
SE_REG_FIELD_LIST_DCN1_0(uint8_t);
604
608
uint8_t HDMI_ACP_SEND;
···
612
606
SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t);
613
607
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);
614
608
SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);
609
+
SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t);
615
610
};
616
611
617
612
struct dcn10_stream_encoder_mask {
···
623
616
SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t);
624
617
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);
625
618
SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);
619
+
SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t);
626
620
};
627
621
628
622
struct dcn10_stream_encoder {
+9
-1
drivers/gpu/drm/amd/display/dc/dpp/Makefile
+9
-1
drivers/gpu/drm/amd/display/dc/dpp/Makefile
···
1
1
2
-
# Copyright 2022 Advanced Micro Devices, Inc.
2
+
# Copyright 2022-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
80
80
81
81
AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN401)
82
82
83
+
###############################################################################
84
+
# DCN42
85
+
###############################################################################
86
+
DPP_DCN42 = dcn42_dpp.o
87
+
88
+
AMD_DAL_DPP_DCN42 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn42/,$(DPP_DCN42))
89
+
90
+
AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN42)
83
91
endif
+4
-1
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
+4
-1
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
···
1
-
/* Copyright 2023 Advanced Micro Devices, Inc.
1
+
/* SPDX-License-Identifier: MIT */
2
+
/* Copyright 2023-2026 Advanced Micro Devices, Inc.
2
3
*
3
4
* Permission is hereby granted, free of charge, to any person obtaining a
4
5
* copy of this software and associated documentation files (the "Software"),
···
654
653
655
654
struct dcn401_dpp_registers {
656
655
DPP_REG_VARIABLE_LIST_DCN401;
656
+
uint32_t ALPHA_2BIT_LUT01;
657
+
uint32_t ALPHA_2BIT_LUT23;
657
658
};
658
659
659
660
struct dcn401_dpp_shift {
+12
-1
drivers/gpu/drm/amd/display/dc/gpio/Makefile
+12
-1
drivers/gpu/drm/amd/display/dc/gpio/Makefile
···
1
1
#
2
-
# Copyright 2017 Advanced Micro Devices, Inc.
2
+
# Copyright 2017-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
131
131
AMD_DAL_GPIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn401/,$(GPIO_DCN401))
132
132
133
133
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN401)
134
+
135
+
###############################################################################
136
+
# DCN 4.2
137
+
###############################################################################
138
+
139
+
GPIO_DCN42 = hw_translate_dcn42.o hw_factory_dcn42.o
140
+
141
+
AMD_DAL_GPIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn42/,$(GPIO_DCN42))
142
+
143
+
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN42)
144
+
134
145
+4
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+4
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
···
53
53
#include "dcn315/hw_factory_dcn315.h"
54
54
#include "dcn32/hw_factory_dcn32.h"
55
55
#include "dcn401/hw_factory_dcn401.h"
56
+
#include "dcn42/hw_factory_dcn42.h"
56
57
57
58
bool dal_hw_factory_init(
58
59
struct hw_factory *factory,
···
118
117
return true;
119
118
case DCN_VERSION_4_01:
120
119
dal_hw_factory_dcn401_init(factory);
120
+
return true;
121
+
case DCN_VERSION_4_2:
122
+
dal_hw_factory_dcn42_init(factory);
121
123
return true;
122
124
default:
123
125
ASSERT_CRITICAL(false);
+4
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+4
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
···
53
53
#include "dcn315/hw_translate_dcn315.h"
54
54
#include "dcn32/hw_translate_dcn32.h"
55
55
#include "dcn401/hw_translate_dcn401.h"
56
+
#include "dcn42/hw_translate_dcn42.h"
56
57
57
58
/*
58
59
* This unit
···
119
118
return true;
120
119
case DCN_VERSION_4_01:
121
120
dal_hw_translate_dcn401_init(translate);
121
+
return true;
122
+
case DCN_VERSION_4_2:
123
+
dal_hw_translate_dcn42_init(translate);
122
124
return true;
123
125
default:
124
126
BREAK_TO_DEBUGGER();
+10
-1
drivers/gpu/drm/amd/display/dc/hpo/Makefile
+10
-1
drivers/gpu/drm/amd/display/dc/hpo/Makefile
···
1
1
#
2
-
# Copyright 2020 Advanced Micro Devices, Inc.
2
+
# Copyright 2020-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
47
47
AMD_DAL_HPO_DCN32 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn32/,$(HPO_DCN32))
48
48
49
49
AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN32)
50
+
51
+
###############################################################################
52
+
# DCN42
53
+
###############################################################################
54
+
HPO_DCN42 = dcn42_hpo_dp_link_encoder.o
55
+
56
+
AMD_DAL_HPO_DCN42 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn42/,$(HPO_DCN42))
57
+
58
+
AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN42)
50
59
endif
+8
-2
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
+8
-2
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
···
1
1
/*
2
-
* Copyright 2019 Advanced Micro Devices, Inc.
2
+
* Copyright 2019-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
208
208
type CRC_CONT_MODE_ENABLE;\
209
209
type HBLANK_MINIMUM_SYMBOL_WIDTH
210
210
211
+
#define DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
212
+
type DP_STREAM_ENC_APG_CLOCK_EN
211
213
214
+
#define DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\
215
+
DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh),\
216
+
SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_APG_CLOCK_EN, mask_sh)
212
217
struct dcn31_hpo_dp_stream_encoder_registers {
213
218
DCN3_1_HPO_DP_STREAM_ENC_REGS;
214
219
};
215
220
216
221
struct dcn31_hpo_dp_stream_encoder_shift {
217
222
DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
223
+
DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
218
224
};
219
225
220
226
struct dcn31_hpo_dp_stream_encoder_mask {
221
227
DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
228
+
DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
222
229
};
223
230
224
231
struct dcn31_hpo_dp_stream_encoder {
···
247
240
const struct dcn31_hpo_dp_stream_encoder_registers *regs,
248
241
const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,
249
242
const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask);
250
-
251
243
252
244
#endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__
+9
-1
drivers/gpu/drm/amd/display/dc/hubbub/Makefile
+9
-1
drivers/gpu/drm/amd/display/dc/hubbub/Makefile
···
1
1
2
-
# Copyright 2022 Advanced Micro Devices, Inc.
2
+
# Copyright 2022-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
101
101
AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN401)
102
102
103
103
###############################################################################
104
+
# DCN42
105
+
###############################################################################
106
+
HUBBUB_DCN42 = dcn42_hubbub.o
107
+
108
+
AMD_DAL_HUBBUB_DCN42 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn42/,$(HUBBUB_DCN42))
109
+
110
+
AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN42)
111
+
104
112
endif
+5
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
+5
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
···
1
1
/*
2
-
* Copyright 2016 Advanced Micro Devices, Inc.
2
+
* Copyright 2016-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
441
441
type DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE;\
442
442
type DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE
443
443
444
+
#define HUBBUB_REG_FIELD_LIST_DCN4_2(type) \
445
+
type URGENT_ZERO_SIZE_REQ_EN
444
446
struct dcn_hubbub_shift {
445
447
DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
446
448
HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
···
451
449
HUBBUB_REG_FIELD_LIST_DCN32(uint8_t);
452
450
HUBBUB_REG_FIELD_LIST_DCN35(uint8_t);
453
451
HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t);
452
+
HUBBUB_REG_FIELD_LIST_DCN4_2(uint8_t);
454
453
455
454
};
456
455
···
463
460
HUBBUB_REG_FIELD_LIST_DCN32(uint32_t);
464
461
HUBBUB_REG_FIELD_LIST_DCN35(uint32_t);
465
462
HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t);
463
+
HUBBUB_REG_FIELD_LIST_DCN4_2(uint8_t);
466
464
467
465
};
468
466
+9
-1
drivers/gpu/drm/amd/display/dc/hubp/Makefile
+9
-1
drivers/gpu/drm/amd/display/dc/hubp/Makefile
···
1
1
2
-
# Copyright 2022 Advanced Micro Devices, Inc.
2
+
# Copyright 2022-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
93
93
AMD_DAL_HUBP_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn401/,$(HUBP_DCN401))
94
94
95
95
AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN401)
96
+
97
+
###############################################################################
98
+
99
+
HUBP_DCN42 = dcn42_hubp.o
100
+
101
+
AMD_DAL_HUBP_DCN42 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn42/,$(HUBP_DCN42))
102
+
103
+
AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN42)
96
104
97
105
endif
+7
-1
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
+7
-1
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
···
1
1
/*
2
-
* Copyright 2012-17 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
288
288
type MCACHEID_MALL_PREF_2H_P1;\
289
289
type HUBP_FGCG_REP_DIS
290
290
291
+
#define DCN42_HUBP_REG_FIELD_VARIABLE_LIST(type) \
292
+
type HUBP_3DLUT_CROSSBAR_SEL_G;\
293
+
type HUBP_3DLUT_CROSSBAR_SEL_B;\
294
+
type HUBP_3DLUT_CROSSBAR_SEL_R
291
295
struct dcn_hubp2_registers {
292
296
DCN401_HUBP_REG_COMMON_VARIABLE_LIST;
293
297
};
294
298
295
299
struct dcn_hubp2_shift {
296
300
DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
301
+
DCN42_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
297
302
};
298
303
299
304
struct dcn_hubp2_mask {
300
305
DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
306
+
DCN42_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
301
307
};
302
308
303
309
struct dcn20_hubp {
+10
-2
drivers/gpu/drm/amd/display/dc/hwss/Makefile
+10
-2
drivers/gpu/drm/amd/display/dc/hwss/Makefile
···
1
-
2
-
# Copyright 2022 Advanced Micro Devices, Inc.
1
+
# Copyright 2022-2026 Advanced Micro Devices, Inc.
3
2
#
4
3
# Permission is hereby granted, free of charge, to any person obtaining a
5
4
# copy of this software and associated documentation files (the "Software"),
···
198
199
AMD_DAL_HWSS_DCN401 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn401/,$(HWSS_DCN401))
199
200
200
201
AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN401)
202
+
203
+
###############################################################################
204
+
205
+
HWSS_DCN42 = dcn42_hwseq.o dcn42_init.o
206
+
207
+
AMD_DAL_HWSS_DCN42 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn42/,$(HWSS_DCN42))
208
+
209
+
AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN42)
210
+
201
211
endif
+12
-1
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
+12
-1
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
···
1
1
/*
2
-
* Copyright 2016 Advanced Micro Devices, Inc.
2
+
* Copyright 2016, 2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
700
700
uint32_t DOMAIN23_PG_STATUS;
701
701
uint32_t DOMAIN24_PG_STATUS;
702
702
uint32_t DOMAIN25_PG_STATUS;
703
+
uint32_t DOMAIN26_PG_CONFIG;
704
+
uint32_t DOMAIN26_PG_STATUS;
703
705
};
704
706
/* set field name */
705
707
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
···
1247
1245
type DOMAIN25_PGFSM_PWR_STATUS; \
1248
1246
type DOMAIN_DESIRED_PWR_STATE;
1249
1247
1248
+
#define HWSEQ_DCN42_REG_FIELD_LIST(type) \
1249
+
type DPIASYMCLK4_GATE_DISABLE;\
1250
+
type DPIASYMCLK5_GATE_DISABLE;\
1251
+
type DOMAIN26_POWER_FORCEON; \
1252
+
type DOMAIN26_POWER_GATE; \
1253
+
type DOMAIN26_PGFSM_PWR_STATUS;
1254
+
1250
1255
struct dce_hwseq_shift {
1251
1256
HWSEQ_REG_FIELD_LIST(uint8_t)
1252
1257
HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
···
1262
1253
HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
1263
1254
HWSEQ_DCN35_REG_FIELD_LIST(uint8_t)
1264
1255
HWSEQ_DCN401_REG_FIELD_LIST(uint8_t)
1256
+
HWSEQ_DCN42_REG_FIELD_LIST(uint8_t)
1265
1257
};
1266
1258
1267
1259
struct dce_hwseq_mask {
···
1273
1263
HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
1274
1264
HWSEQ_DCN35_REG_FIELD_LIST(uint32_t)
1275
1265
HWSEQ_DCN401_REG_FIELD_LIST(uint32_t)
1266
+
HWSEQ_DCN42_REG_FIELD_LIST(uint32_t)
1276
1267
};
1277
1268
1278
1269
+16
-1
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+16
-1
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
···
1
1
/*
2
-
* Copyright 2015 Advanced Micro Devices, Inc.
2
+
* Copyright 2015-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
172
172
struct program_mcache_id_and_split_coordinate {
173
173
struct hubp *hubp;
174
174
struct dml2_hubp_pipe_mcache_regs *mcache_regs;
175
+
};
176
+
177
+
struct control_cm_hist_params {
178
+
struct dpp *dpp;
179
+
struct cm_hist_control cm_hist_control;
180
+
enum dc_color_space color_space;
175
181
};
176
182
177
183
struct program_cursor_update_now_params {
···
761
755
struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params;
762
756
struct program_surface_config_params program_surface_config_params;
763
757
struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate;
758
+
struct control_cm_hist_params control_cm_hist_params;
764
759
struct program_cursor_update_now_params program_cursor_update_now_params;
765
760
struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params;
766
761
struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params;
···
886
879
DMUB_HW_CONTROL_LOCK_FAST,
887
880
HUBP_PROGRAM_SURFACE_CONFIG,
888
881
HUBP_PROGRAM_MCACHE_ID,
882
+
DPP_PROGRAM_CM_HIST,
889
883
PROGRAM_CURSOR_UPDATE_NOW,
890
884
HUBP_WAIT_PIPE_READ_START,
891
885
HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM,
···
1423
1415
1424
1416
void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params);
1425
1417
1418
+
void hwss_program_cm_hist(union block_sequence_params *params);
1419
+
1426
1420
void hwss_set_odm_combine(union block_sequence_params *params);
1427
1421
1428
1422
void hwss_set_odm_bypass(union block_sequence_params *params);
···
1774
1764
struct output_pixel_processor *opp,
1775
1765
bool use_default_params,
1776
1766
struct pipe_ctx *pipe_ctx);
1767
+
1768
+
void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state,
1769
+
struct dpp *dpp,
1770
+
struct cm_hist_control cm_hist_control,
1771
+
enum dc_color_space color_space);
1777
1772
1778
1773
void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,
1779
1774
struct dc *dc,
+4
-1
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
+4
-1
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
···
1
1
/*
2
-
* Copyright 2015 Advanced Micro Devices, Inc.
2
+
* Copyright 2015-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
222
222
void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);
223
223
void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);
224
224
void (*dc_ip_request_cntl)(struct dc *dc, bool enable);
225
+
void (*program_cm_hist)(struct dc *dc,
226
+
struct pipe_ctx *pipe_ctx,
227
+
const struct dc_plane_state *plane_state);
225
228
};
226
229
227
230
struct dce_hwseq {
+23
-1
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+23
-1
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
···
1
+
/* SPDX-License-Identifier: MIT */
1
2
/*
2
-
* Copyright 2012-16 Advanced Micro Devices, Inc.
3
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
4
*
4
5
* Permission is hereby granted, free of charge, to any person obtaining a
5
6
* copy of this software and associated documentation files (the "Software"),
···
94
93
uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
95
94
uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
96
95
uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
96
+
};
97
+
98
+
struct dcn42_clk_internal {
99
+
int dummy;
100
+
uint32_t CLK8_CLK0_CURRENT_CNT; //dispclk
101
+
uint32_t CLK8_CLK1_CURRENT_CNT; //dppclk
102
+
uint32_t CLK8_CLK2_CURRENT_CNT; //dprefclk
103
+
uint32_t CLK8_CLK3_CURRENT_CNT; //dcfclk
104
+
uint32_t CLK8_CLK4_CURRENT_CNT; //dtbclk
105
+
uint32_t CLK8_CLK0_DS_CNTL; //dispclk deep_sleep_divider
106
+
uint32_t CLK8_CLK1_DS_CNTL; //dppclk deep_sleep_divider
107
+
uint32_t CLK8_CLK2_DS_CNTL; //dprefclk deep_sleep_divider
108
+
uint32_t CLK8_CLK3_DS_CNTL; //dcfclk deep_sleep_divider
109
+
uint32_t CLK8_CLK4_DS_CNTL; //dtbclk deep_sleep_divider
110
+
uint32_t CLK8_CLK0_BYPASS_CNTL; //dispclk bypass
111
+
uint32_t CLK8_CLK1_BYPASS_CNTL; //dppclk bypass
112
+
uint32_t CLK8_CLK2_BYPASS_CNTL; //dprefclk bypass
113
+
uint32_t CLK8_CLK3_BYPASS_CNTL; //dcfclk bypass
114
+
uint32_t CLK8_CLK4_BYPASS_CNTL; //dtbclk bypass
115
+
uint32_t CLK8_CLK_TICK_CNT__TIMER_THRESHOLD;
97
116
};
98
117
99
118
/* Will these bw structures be ASIC specific? */
···
215
194
uint32_t dcfclk_bypass;
216
195
uint32_t dprefclk_bypass;
217
196
uint32_t dispclk_bypass;
197
+
uint32_t timer_threhold;
218
198
};
219
199
220
200
struct rv1_clk_internal {
+41
-1
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+41
-1
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
···
1
+
/* SPDX-License-Identifier: MIT */
1
2
/*
2
-
* Copyright 2018 Advanced Micro Devices, Inc.
3
+
* Copyright 2018-2026 Advanced Micro Devices, Inc.
3
4
*
4
5
* Permission is hereby granted, free of charge, to any person obtaining a
5
6
* copy of this software and associated documentation files (the "Software"),
···
224
223
#define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \
225
224
CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh)
226
225
226
+
#define CLK_REG_LIST_DCN42() \
227
+
SR(DENTIST_DISPCLK_CNTL), \
228
+
CLK_SR_DCN42(CLK8_CLK_TICK_CNT_CONFIG_REG), \
229
+
CLK_SR_DCN42(CLK8_CLK0_CURRENT_CNT), \
230
+
CLK_SR_DCN42(CLK8_CLK1_CURRENT_CNT), \
231
+
CLK_SR_DCN42(CLK8_CLK2_CURRENT_CNT), \
232
+
CLK_SR_DCN42(CLK8_CLK3_CURRENT_CNT), \
233
+
CLK_SR_DCN42(CLK8_CLK4_CURRENT_CNT), \
234
+
CLK_SR_DCN42(CLK8_CLK0_BYPASS_CNTL), \
235
+
CLK_SR_DCN42(CLK8_CLK1_BYPASS_CNTL), \
236
+
CLK_SR_DCN42(CLK8_CLK2_BYPASS_CNTL), \
237
+
CLK_SR_DCN42(CLK8_CLK3_BYPASS_CNTL), \
238
+
CLK_SR_DCN42(CLK8_CLK4_BYPASS_CNTL), \
239
+
CLK_SR_DCN42(CLK8_CLK0_DS_CNTL), \
240
+
CLK_SR_DCN42(CLK8_CLK1_DS_CNTL), \
241
+
CLK_SR_DCN42(CLK8_CLK2_DS_CNTL), \
242
+
CLK_SR_DCN42(CLK8_CLK3_DS_CNTL), \
243
+
CLK_SR_DCN42(CLK8_CLK4_DS_CNTL)
244
+
245
+
#define CLK_COMMON_MASK_SH_LIST_DCN42(mask_sh) 0
246
+
247
+
248
+
227
249
#define CLK_REG_FIELD_LIST(type) \
228
250
type DPREFCLK_SRC_SEL; \
229
251
type DENTIST_DPREFCLK_WDIVIDER; \
···
322
298
uint32_t CLK1_CLK5_ALLOW_DS;
323
299
uint32_t CLK5_spll_field_8;
324
300
uint32_t CLK6_spll_field_8;
301
+
uint32_t CLK8_CLK0_CURRENT_CNT;
302
+
uint32_t CLK8_CLK1_CURRENT_CNT;
303
+
uint32_t CLK8_CLK2_CURRENT_CNT;
304
+
uint32_t CLK8_CLK3_CURRENT_CNT;
305
+
uint32_t CLK8_CLK4_CURRENT_CNT;
306
+
uint32_t CLK8_CLK0_DS_CNTL;
307
+
uint32_t CLK8_CLK1_DS_CNTL;
308
+
uint32_t CLK8_CLK2_DS_CNTL;
309
+
uint32_t CLK8_CLK3_DS_CNTL;
310
+
uint32_t CLK8_CLK4_DS_CNTL;
311
+
uint32_t CLK8_CLK0_BYPASS_CNTL;
312
+
uint32_t CLK8_CLK1_BYPASS_CNTL;
313
+
uint32_t CLK8_CLK2_BYPASS_CNTL;
314
+
uint32_t CLK8_CLK3_BYPASS_CNTL;
315
+
uint32_t CLK8_CLK4_BYPASS_CNTL;
316
+
uint32_t CLK8_CLK_TICK_CNT_CONFIG_REG;
325
317
};
326
318
327
319
struct clk_mgr_shift {
+9
-1
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+9
-1
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
···
1
1
/*
2
-
* Copyright 2012-15 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
367
367
368
368
void (*dpp_force_disable_cursor)(struct dpp *dpp_base);
369
369
370
+
void (*dpp_cm_hist_control)(
371
+
struct dpp *dpp_base,
372
+
struct cm_hist_control cm_hist_control,
373
+
enum dc_color_space color_space);
374
+
375
+
bool (*dpp_cm_hist_read)(
376
+
struct dpp *dpp_base,
377
+
struct cm_hist *cm_hist);
370
378
};
371
379
372
380
+19
-1
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+19
-1
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
···
1
1
/*
2
-
* Copyright 2012-15 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
1041
1041
*/
1042
1042
1043
1043
void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);
1044
+
1045
+
/**
1046
+
* @get_3dlut_fast_load_status:
1047
+
*
1048
+
* Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers.
1049
+
*
1050
+
* Parameters:
1051
+
* - [in/out] mpc - MPC context.
1052
+
* - [in] mpcc_id
1053
+
* - [in/out] done
1054
+
* - [in/out] soft_underflow
1055
+
* - [in/out] hard_underflow
1056
+
*
1057
+
* Return:
1058
+
*
1059
+
* void
1060
+
*/
1061
+
void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow);
1044
1062
1045
1063
/**
1046
1064
* @populate_lut:
+3
-1
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+3
-1
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
···
1
1
/*
2
-
* Copyright 2012-15 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
518
518
bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked);
519
519
void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s);
520
520
void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state);
521
+
void (*enable_otg_pwa)(struct timing_generator *tg, struct otc_pwa_frame_sync *pwa_param);
522
+
void (*disable_otg_pwa)(struct timing_generator *tg);
521
523
};
522
524
523
525
#endif
+9
drivers/gpu/drm/amd/display/dc/irq/Makefile
+9
drivers/gpu/drm/amd/display/dc/irq/Makefile
···
198
198
AMD_DAL_IRQ_DCN401= $(addprefix $(AMDDALPATH)/dc/irq/dcn401/,$(IRQ_DCN401))
199
199
200
200
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN401)
201
+
202
+
###############################################################################
203
+
# DCN 42
204
+
###############################################################################
205
+
IRQ_DCN42 = irq_service_dcn42.o
206
+
207
+
AMD_DAL_IRQ_DCN42= $(addprefix $(AMDDALPATH)/dc/irq/dcn42/,$(IRQ_DCN42))
208
+
209
+
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN42)
+9
-1
drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile
+9
-1
drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile
···
1
1
#
2
-
# Copyright 2020 Advanced Micro Devices, Inc.
2
+
# Copyright 2020-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
52
52
AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN35)
53
53
endif
54
54
55
+
###############################################################################
56
+
# DCN42
57
+
###############################################################################
58
+
MMHUBBUB_DCN42 = dcn42_mmhubbub.o
59
+
60
+
AMD_DAL_MMHUBBUB_DCN42 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn42/,$(MMHUBBUB_DCN42))
61
+
62
+
AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN42)
+9
-1
drivers/gpu/drm/amd/display/dc/mpc/Makefile
+9
-1
drivers/gpu/drm/amd/display/dc/mpc/Makefile
···
1
1
#
2
-
# Copyright 2020 Advanced Micro Devices, Inc.
2
+
# Copyright 2020-2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
69
69
70
70
AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN401)
71
71
72
+
###############################################################################
73
+
# DCN42
74
+
###############################################################################
75
+
MPC_DCN42 = dcn42_mpc.o
76
+
77
+
AMD_DAL_MPC_DCN42 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn42/,$(MPC_DCN42))
78
+
79
+
AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN42)
72
80
endif
+12
-1
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
+12
-1
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
···
1
1
/*
2
-
* Copyright 2023 Advanced Micro Devices, Inc.
2
+
* Copyright 2023-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
45
45
struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
46
46
47
47
REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, MPCC_MCM_3DLUT_FL_SEL, hubp_idx);
48
+
}
49
+
50
+
void mpc401_get_3dlut_fast_load_status(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow)
51
+
{
52
+
struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
53
+
54
+
REG_GET_3(MPCC_MCM_3DLUT_FAST_LOAD_STATUS[mpcc_id],
55
+
MPCC_MCM_3DLUT_FL_DONE, done,
56
+
MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, soft_underflow,
57
+
MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, hard_underflow);
48
58
}
49
59
50
60
void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id)
···
612
602
.set_bg_color = mpc1_set_bg_color,
613
603
.set_movable_cm_location = mpc401_set_movable_cm_location,
614
604
.update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select,
605
+
.get_3dlut_fast_load_status = mpc401_get_3dlut_fast_load_status,
615
606
.populate_lut = mpc401_populate_lut,
616
607
.program_lut_read_write_control = mpc401_program_lut_read_write_control,
617
608
.program_lut_mode = mpc401_program_lut_mode,
+9
-1
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
+9
-1
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
···
1
1
/*
2
-
* Copyright 2023 Advanced Micro Devices, Inc.
2
+
* Copyright 2023-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
184
184
185
185
struct dcn401_mpc_registers {
186
186
MPC_REG_VARIABLE_LIST_DCN4_01
187
+
uint32_t MPCC_CONTROL2[MAX_MPCC];
187
188
};
188
189
189
190
struct dcn401_mpc {
···
249
248
uint16_t *regval,
250
249
enum mpcc_gamut_remap_id gamut_remap_block_id,
251
250
uint32_t *mode_select);
251
+
252
+
void mpc401_get_3dlut_fast_load_status(
253
+
struct mpc *mpc,
254
+
int mpcc_id,
255
+
uint32_t *done,
256
+
uint32_t *soft_underflow,
257
+
uint32_t *hard_underflow);
252
258
253
259
void mpc401_update_3dlut_fast_load_select(
254
260
struct mpc *mpc,
+9
-1
drivers/gpu/drm/amd/display/dc/optc/Makefile
+9
-1
drivers/gpu/drm/amd/display/dc/optc/Makefile
···
104
104
105
105
###############################################################################
106
106
107
-
###############################################################################
108
107
OPTC_DCN401 = dcn401_optc.o
109
108
110
109
AMD_DAL_OPTC_DCN401 = $(addprefix $(AMDDALPATH)/dc/optc/dcn401/,$(OPTC_DCN401))
111
110
112
111
AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN401)
112
+
113
+
###############################################################################
114
+
115
+
OPTC_DCN42 = dcn42_optc.o
116
+
117
+
AMD_DAL_OPTC_DCN42 = $(addprefix $(AMDDALPATH)/dc/optc/dcn42/,$(OPTC_DCN42))
118
+
119
+
AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN42)
120
+
113
121
endif
114
122
+19
-1
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
+19
-1
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
···
1
1
/*
2
-
* Copyright 2012-15 Advanced Micro Devices, Inc.
2
+
* Copyright 2012-2026 Advanced Micro Devices, Inc.
3
3
*
4
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
5
* copy of this software and associated documentation files (the "Software"),
···
253
253
uint32_t OTG_CRC1_DATA_B32
254
254
255
255
256
+
#define OPTC_REG_VARIABLE_LIST_DCN42 \
257
+
uint32_t OTG_PWA_FRAME_SYNC_CONTROL; \
258
+
uint32_t OTG_CRC0_DATA_R; \
259
+
uint32_t OTG_CRC1_DATA_R; \
260
+
uint32_t OTG_CRC2_DATA_R; \
261
+
uint32_t OTG_CRC3_DATA_R; \
262
+
uint32_t OTG_CRC0_DATA_G; \
263
+
uint32_t OTG_CRC1_DATA_G; \
264
+
uint32_t OTG_CRC2_DATA_G; \
265
+
uint32_t OTG_CRC3_DATA_G
266
+
256
267
struct dcn_optc_registers {
257
268
OPTC_REG_VARIABLE_LIST_DCN;
269
+
OPTC_REG_VARIABLE_LIST_DCN42;
258
270
};
259
271
260
272
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
···
691
679
type OTG_UNBLANK;\
692
680
type OTG_PSTATE_ALLOW_WIDTH_MIN;
693
681
682
+
#define TG_REG_FIELD_LIST_DCN42(type) \
683
+
type OTG_PWA_FRAME_SYNC_EN;\
684
+
type OTG_PWA_FRAME_SYNC_VCOUNT_MODE;\
685
+
type OTG_PWA_FRAME_SYNC_LINE;
694
686
695
687
struct dcn_optc_shift {
696
688
TG_REG_FIELD_LIST(uint8_t)
···
703
687
TG_REG_FIELD_LIST_DCN3_5(uint8_t)
704
688
TG_REG_FIELD_LIST_DCN3_6(uint8_t)
705
689
TG_REG_FIELD_LIST_DCN401(uint8_t)
690
+
TG_REG_FIELD_LIST_DCN42(uint8_t)
706
691
};
707
692
708
693
struct dcn_optc_mask {
···
713
696
TG_REG_FIELD_LIST_DCN3_5(uint32_t)
714
697
TG_REG_FIELD_LIST_DCN3_6(uint32_t)
715
698
TG_REG_FIELD_LIST_DCN401(uint32_t)
699
+
TG_REG_FIELD_LIST_DCN42(uint32_t)
716
700
};
717
701
718
702
void dcn10_timing_generator_init(struct optc *optc);
+9
-1
drivers/gpu/drm/amd/display/dc/pg/Makefile
+9
-1
drivers/gpu/drm/amd/display/dc/pg/Makefile
···
1
1
#
2
-
# Copyright 2020 Advanced Micro Devices, Inc.
2
+
# Copyright 2020, 2026 Advanced Micro Devices, Inc.
3
3
#
4
4
# Permission is hereby granted, free of charge, to any person obtaining a
5
5
# copy of this software and associated documentation files (the "Software"),
···
32
32
AMD_DAL_PG_DCN35 = $(addprefix $(AMDDALPATH)/dc/pg/dcn35/,$(PG_DCN35))
33
33
34
34
AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN35)
35
+
###############################################################################
36
+
# DCN42
37
+
###############################################################################
38
+
PG_DCN42 = dcn42_pg_cntl.o
39
+
40
+
AMD_DAL_PG_DCN42 = $(addprefix $(AMDDALPATH)/dc/pg/dcn42/,$(PG_DCN42))
41
+
42
+
AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN42)
35
43
endif
+18
drivers/gpu/drm/amd/display/dc/resource/Makefile
+18
drivers/gpu/drm/amd/display/dc/resource/Makefile
···
222
222
223
223
AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN401)
224
224
225
+
###############################################################################
226
+
# DCN42
227
+
###############################################################################
228
+
RESOURCE_DCN42 = dcn42_resource.o dcn42_resource_fpu.o
229
+
230
+
AMD_DAL_RESOURCE_DCN42 = $(addprefix $(AMDDALPATH)/dc/resource/dcn42/,$(RESOURCE_DCN42))
231
+
232
+
AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN42)
233
+
234
+
# FPU Compile Flags for FPU files
235
+
resource_ccflags := $(CC_FLAGS_FPU)
236
+
resource_rcflags := $(CC_FLAGS_NO_FPU)
237
+
238
+
CFLAGS_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_ccflags)
239
+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_rcflags)
240
+
241
+
###############################################################################
225
242
endif
243
+