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dt-bindings: riscv: convert pwm bindings to json-schema
Convert device tree bindings for SiFive's PWM controller to YAML
format.
Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
Link: https://lore.kernel.org/r/1601393531-2402-4-git-send-email-sagar.kadam@sifive.com
Signed-off-by: Rob Herring <robh@kernel.org>
authored by
Sagar Kadam
and committed by
Rob Herring
6b49329a
c825a081
+69
-33
-33
Documentation/devicetree/bindings/pwm/pwm-sifive.txt
-33
Documentation/devicetree/bindings/pwm/pwm-sifive.txt
···
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SiFive PWM controller
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Unlike most other PWM controllers, the SiFive PWM controller currently only
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supports one period for all channels in the PWM. All PWMs need to run at
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the same period. The period also has significant restrictions on the values
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it can achieve, which the driver rounds to the nearest achievable period.
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PWM RTL that corresponds to the IP block version numbers can be found
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here:
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
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Required properties:
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- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
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Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
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PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
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SiFive PWM v0 IP block with no chip integration tweaks.
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Please refer to sifive-blocks-ip-versioning.txt for details.
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- reg: physical base address and length of the controller's registers
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- clocks: Should contain a clock identifier for the PWM's parent clock.
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- #pwm-cells: Should be 3. See pwm.yaml in this directory
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for a description of the cell format.
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- interrupts: one interrupt per PWM channel
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Examples:
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pwm: pwm@10020000 {
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compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
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reg = <0x0 0x10020000 0x0 0x1000>;
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clocks = <&tlclk>;
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interrupt-parent = <&plic>;
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interrupts = <42 43 44 45>;
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#pwm-cells = <3>;
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};
+69
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
+69
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 SiFive, Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive PWM controller
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maintainers:
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- Yash Shah <yash.shah@sifive.com>
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- Sagar Kadam <sagar.kadam@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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description:
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Unlike most other PWM controllers, the SiFive PWM controller currently
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only supports one period for all channels in the PWM. All PWMs need to
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run at the same period. The period also has significant restrictions on
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the values it can achieve, which the driver rounds to the nearest
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achievable period. PWM RTL that corresponds to the IP block version
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numbers can be found here -
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
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properties:
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compatible:
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items:
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- const: sifive,fu540-c000-pwm
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- const: sifive,pwm0
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description:
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Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
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compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
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as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
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SiFive PWM v0 IP block with no chip integration tweaks.
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Please refer to sifive-blocks-ip-versioning.txt for details.
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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"#pwm-cells":
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const: 3
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interrupts:
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maxItems: 4
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description:
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Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
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required:
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- compatible
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- reg
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- clocks
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- "#pwm-cells"
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- interrupts
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additionalProperties: false
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examples:
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- |
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pwm: pwm@10020000 {
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compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
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reg = <0x10020000 0x1000>;
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clocks = <&tlclk>;
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interrupt-parent = <&plic>;
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interrupts = <42>, <43>, <44>, <45>;
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#pwm-cells = <3>;
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};