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ASoC: renesas: msiof: Convert to <linux/spi/sh_msiof.h>

Convert the MSIOF I2S driver to reuse the MSIOF register and register
bit definitions in the header file shared by the MSIOF SPI driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://patch.msgid.link/754ed54057e54effd06143e71d6cd305c3334eca.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Geert Uytterhoeven and committed by
Mark Brown
6ba68e5a 0779c0ad

+28 -66
+28 -66
sound/soc/renesas/rcar/msiof.c
··· 30 30 #include <linux/of_graph.h> 31 31 #include <linux/platform_device.h> 32 32 #include <linux/pm_runtime.h> 33 + #include <linux/spi/sh_msiof.h> 33 34 #include <sound/dmaengine_pcm.h> 34 35 #include <sound/soc.h> 35 36 36 - /* register */ 37 - #define SITMDR1 0x00 38 - #define SITMDR2 0x04 39 - #define SITMDR3 0x08 40 - #define SIRMDR1 0x10 41 - #define SIRMDR2 0x14 42 - #define SIRMDR3 0x18 43 - #define SICTR 0x28 44 - #define SISTR 0x40 45 - #define SIIER 0x44 46 - #define SITFDR 0x50 47 - #define SIRFDR 0x60 48 - 49 - /* SITMDR1/ SIRMDR1 */ 50 - #define PCON (1 << 30) /* Transfer Signal Connection */ 51 - #define SYNCMD_LR (3 << 28) /* L/R mode */ 52 - #define SYNCAC (1 << 25) /* Sync Polarity (Active-low) */ 53 - #define DTDL_1 (1 << 20) /* 1-clock-cycle delay */ 54 - #define TXSTP (1 << 0) /* Transmission/Reception Stop on FIFO */ 55 - 56 - /* SITMDR2 and SIRMDR2 */ 57 - #define BITLEN1(x) (((x) - 1) << 24) /* Data Size (8-32 bits) */ 58 - #define GRP (1 << 30) /* Group count */ 59 - 60 - /* SICTR */ 61 - #define TEDG (1 << 27) /* Transmit Timing (1 = falling edge) */ 62 - #define REDG (1 << 26) /* Receive Timing (1 = rising edge) */ 63 - #define TXE (1 << 9) /* Transmit Enable */ 64 - #define RXE (1 << 8) /* Receive Enable */ 65 - 66 37 /* SISTR */ 67 - #define TFSERR (1 << 21) /* Transmit Frame Synchronization Error */ 68 - #define TFOVF (1 << 20) /* Transmit FIFO Overflow */ 69 - #define TFUDF (1 << 19) /* Transmit FIFO Underflow */ 70 - #define RFSERR (1 << 5) /* Receive Frame Synchronization Error */ 71 - #define RFUDF (1 << 4) /* Receive FIFO Underflow */ 72 - #define RFOVF (1 << 3) /* Receive FIFO Overflow */ 73 - #define SISTR_ERR_TX (TFSERR | TFOVF | TFUDF) 74 - #define SISTR_ERR_RX (RFSERR | RFOVF | RFUDF) 38 + #define SISTR_ERR_TX (SISTR_TFSERR | SISTR_TFOVF | SISTR_TFUDF) 39 + #define SISTR_ERR_RX (SISTR_RFSERR | SISTR_RFOVF | SISTR_RFUDF) 75 40 #define SISTR_ERR (SISTR_ERR_TX | SISTR_ERR_RX) 76 - 77 - /* SIIER */ 78 - #define TDMAE (1 << 31) /* Transmit Data DMA Transfer Req. Enable */ 79 - #define TDREQE (1 << 28) /* Transmit Data Transfer Request Enable */ 80 - #define RDMAE (1 << 15) /* Receive Data DMA Transfer Req. Enable */ 81 - #define RDREQE (1 << 12) /* Receive Data Transfer Request Enable */ 82 41 83 42 /* 84 43 * The data on memory in 24bit case is located at <right> side ··· 133 174 134 175 /* SITMDRx */ 135 176 if (is_play) { 136 - val = PCON | SYNCMD_LR | SYNCAC | TXSTP; 177 + val = SITMDR1_PCON | 178 + FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_LR) | 179 + SIMDR1_SYNCAC | SIMDR1_XXSTP; 137 180 if (msiof_flag_has(priv, MSIOF_FLAGS_NEED_DELAY)) 138 - val |= DTDL_1; 181 + val |= FIELD_PREP(SIMDR1_DTDL, 1); 139 182 140 183 msiof_write(priv, SITMDR1, val); 141 184 142 - val = BITLEN1(width); 143 - msiof_write(priv, SITMDR2, val | GRP); 185 + val = FIELD_PREP(SIMDR2_BITLEN1, width - 1); 186 + msiof_write(priv, SITMDR2, val | FIELD_PREP(SIMDR2_GRP, 1)); 144 187 msiof_write(priv, SITMDR3, val); 145 188 146 189 } 147 190 /* SIRMDRx */ 148 191 else { 149 - val = SYNCMD_LR | SYNCAC; 192 + val = FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_LR) | 193 + SIMDR1_SYNCAC; 150 194 if (msiof_flag_has(priv, MSIOF_FLAGS_NEED_DELAY)) 151 - val |= DTDL_1; 195 + val |= FIELD_PREP(SIMDR1_DTDL, 1); 152 196 153 197 msiof_write(priv, SIRMDR1, val); 154 198 155 - val = BITLEN1(width); 156 - msiof_write(priv, SIRMDR2, val | GRP); 199 + val = FIELD_PREP(SIMDR2_BITLEN1, width - 1); 200 + msiof_write(priv, SIRMDR2, val | FIELD_PREP(SIMDR2_GRP, 1)); 157 201 msiof_write(priv, SIRMDR3, val); 158 202 } 159 203 160 204 /* SIIER */ 161 205 if (is_play) 162 - val = TDREQE | TDMAE | SISTR_ERR_TX; 206 + val = SIIER_TDREQE | SIIER_TDMAE | SISTR_ERR_TX; 163 207 else 164 - val = RDREQE | RDMAE | SISTR_ERR_RX; 208 + val = SIIER_RDREQE | SIIER_RDMAE | SISTR_ERR_RX; 165 209 msiof_update(priv, SIIER, val, val); 166 210 167 211 /* SICTR */ 168 212 if (is_play) 169 - val = TXE | TEDG; 213 + val = SICTR_TXE | SICTR_TEDG; 170 214 else 171 - val = RXE | REDG; 215 + val = SICTR_RXE | SICTR_REDG; 172 216 msiof_update_and_wait(priv, SICTR, val, val, val); 173 217 174 218 msiof_status_clear(priv); ··· 192 230 193 231 /* SIIER */ 194 232 if (is_play) 195 - val = TDREQE | TDMAE | SISTR_ERR_TX; 233 + val = SIIER_TDREQE | SIIER_TDMAE | SISTR_ERR_TX; 196 234 else 197 - val = RDREQE | RDMAE | SISTR_ERR_RX; 235 + val = SIIER_RDREQE | SIIER_RDMAE | SISTR_ERR_RX; 198 236 msiof_update(priv, SIIER, val, 0); 199 237 200 238 /* Stop DMAC */ ··· 202 240 203 241 /* SICTR */ 204 242 if (is_play) 205 - val = TXE; 243 + val = SICTR_TXE; 206 244 else 207 - val = RXE; 245 + val = SICTR_RXE; 208 246 msiof_update_and_wait(priv, SICTR, val, 0, 0); 209 247 210 248 /* indicate error status if exist */ ··· 440 478 substream = priv->substream[SNDRV_PCM_STREAM_PLAYBACK]; 441 479 if (substream && (sistr & SISTR_ERR_TX)) { 442 480 // snd_pcm_stop_xrun(substream); 443 - if (sistr & TFSERR) 481 + if (sistr & SISTR_TFSERR) 444 482 priv->err_syc[SNDRV_PCM_STREAM_PLAYBACK]++; 445 - if (sistr & TFOVF) 483 + if (sistr & SISTR_TFOVF) 446 484 priv->err_ovf[SNDRV_PCM_STREAM_PLAYBACK]++; 447 - if (sistr & TFUDF) 485 + if (sistr & SISTR_TFUDF) 448 486 priv->err_udf[SNDRV_PCM_STREAM_PLAYBACK]++; 449 487 } 450 488 451 489 substream = priv->substream[SNDRV_PCM_STREAM_CAPTURE]; 452 490 if (substream && (sistr & SISTR_ERR_RX)) { 453 491 // snd_pcm_stop_xrun(substream); 454 - if (sistr & RFSERR) 492 + if (sistr & SISTR_RFSERR) 455 493 priv->err_syc[SNDRV_PCM_STREAM_CAPTURE]++; 456 - if (sistr & RFOVF) 494 + if (sistr & SISTR_RFOVF) 457 495 priv->err_ovf[SNDRV_PCM_STREAM_CAPTURE]++; 458 - if (sistr & RFUDF) 496 + if (sistr & SISTR_RFUDF) 459 497 priv->err_udf[SNDRV_PCM_STREAM_CAPTURE]++; 460 498 } 461 499